Digital System Controller FEATURES Fully Configurable Multi-

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UCD9240
Digital System Controller
FEATURES
Fully Configurable Multi-Output Multi-Phase Non-Isolated DC/DC Controller Controls Four Voltage Rails Eight Phases Supports Switching Frequencies 2MHz With Duty-Cycle Resolution Closed Loop Resolution Hardware-Accelerated, 3-Pole/3-Zero Compensator With Non-Linear Gain Improved Transient Performance Supports Multiple Soft-Start Soft-Stop Configurations Including Prebias Start-up Supports Voltage Tracking, Margining Sequencing Supports Current Temperature Balancing Multi-Phase Power Stages Supports Phase Adding/Shedding Multi-Phase Power Stages Sync /Out Pins Align DPWM Clocks Between Multiple UCD9240 Devices Monitoring Control 12-Bit Digital Monitoring Power Supply Parameters Including: Input Current Voltage Output Current Voltage Temperature Each Power Stage Multiple Levels Overcurrent Fault Protection: External Current Fault Inputs Analog Comparators Monitor Current Sense Voltage Current Continually Digitally Monitored Over Undervoltage Fault Protection Overtemperature Fault Protection Enhanced Nonvolatile Memory With Error Correction Code (ECC) Device Operates From Single Supply With Internal Regulator Controller That Allows Operation Over Wide Supply Voltage Range
Supported Fusion Digital PowerDesigner, Full Featured Based Design Tool Simulate, Configure, Monitor Power Supply Performance.
APPLICATIONS
Industrial/ATE Networking Equipment Telecommunications Equipment Servers Storage Systems FPGA, Memory Power
DESCRIPTION
UCD9240 multi-rail, multi-phase synchronous buck digital controller designed non-isolated DC/DC power applications. This device integrates dedicated circuitry DC/DC loop management with flash memory serial interface support configurability, monitoring management. UCD9240 designed provide wide variety desirable features non-isolated DC/DC converter applications while minimizing total system component count reducing external circuits. solution integrates multi-loop management with sequencing, margining, tracking intelligent phase management optimize total system efficiency. Additionally, loop compensation calibration supported without need external components. facilitate configuring device, Texas Instruments Fusion Digital PowerDesigner provided. This based Graphical User Interface offers intuitive interface device. This tool allows design engineer configure system operating parameters application, store configuration on-chip non-volatile memory observe both frequency domain time domain simulations each power stage outputs. also developed multiple complementary power stage solutions from discrete drives UCD7k family fully tested power train modules family. These solutions have been developed complement UCD9k family system power controllers.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. Fusion Digital Power, Auto-ID trademarks Texas Instruments.
Copyright 2008, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
UCD9240
SLUS766C JULY 2008 REVISED NOVEMBER 2008. www.ti.com
These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
ORDERING INFORMATION
OPERATING TEMPERATURE RANGE, ORDERABLE PART NUMBER UCD9240PFCR UCD9240PFC UCD9240RGCR UCD9240RGCT COUNT 80-pin 80-pin 64-pin 64-pin SUPPLY Reel 1000 Tray Reel 2000 Reel PACKAGE SIDE MARKING UCD9240 UCD9240 UCD9240 UCD9240
most current package ordering information, Package Option Addendum this document, site www.ti.com.
ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS
VALUE Voltage applied V33D DVSS Voltage applied V33A AVSS Voltage applied
UNIT
-0.3 -0.3 -0.3
Storage temperature (TSTG)
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. voltages referenced VSS.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
Supply voltage during operation, V33D, V33DIO, V33A Operating free-air temperature range Junction temperature UNIT
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UCD9240
ELECTRICAL CHARACTERISTICS
PARAMETER SUPPLY CURRENT IV33A IV33DIO IV33D IV33D Supply current VV33A VV33DIO VV33D VV33D storing configuration parameters flash memory 3.3-V linear regulator 3.3-V linear regulator feedback Series pass base drive Series pass device VVIN Emitter transistor 3.25 TEST CONDITIONS UNIT
INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS VV33 V33FB IV33FB Beta VV33D, VV33DION VV33A VDIFF VERROR EAP-EAN IOFFSET IBIAS VADDR_OPEN VADDR_SHORT VADC_RANGE VOC_THRS VOC_RES ADCREF Tempinternal Ilkg 3.35
EXTERNALLY SUPPLIED POWER Digital 3.3-V power Analog 3.3-V power Common mode voltage each Differential Voltage Range Internal error Voltage range Error voltage digital resolution Input Impedance Input offset current Bias current PMBus Addr pins Voltage indicating open Voltage indicating shorted Measurment range voltage monitoring Overcurrent comparator threshold voltage range Overcurrent comparator threshold voltage range External Reference input Int. temperature sense accuracy integral nonlinearity Input leakage current Input impedance Current Sense Input capacitance UCD92xx PMBus Command Reference description AFE_GAIN field CLA_GAINS command. applied Ground reference AddrSens open AddrSense short ground Inputs: VIn, Vtrack, Vtemp CS-1A, CS-1B, CS-2A, CS-2B CS-3A, CS-3B, CS-4A, CS-4B Inputs: CS-1A, CS-2A, CS-3A, CS-4A Inputs: CS-1A, CS-2A, CS-3A, CS-4A (80-pin package) Over range from 100°C -2.5 AFE_GAIN field CLA_GAINS AFE_GAIN field CLA_Gains Ground reference source impedence 2.47 0.179 3.13 3.13 -0.15 -0.256 -256 3.47 3.47 1.848 1.998
ERROR AMPLIFIER INPUTS EAPn, EANn
ANALOG INPUTS Vin, TEMP, PMBusADDR
0.032 31.25
V33A
Copyright 2008, Texas Instruments Incorporated
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UCD9240
SLUS766C JULY 2008 REVISED NOVEMBER 2008. www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
PARAMETER DIGITAL INPUTS/OUTPUTS TPWM_PERIOD DUTYPWM DUTYRES TachRANGE TachRES tMIN Low-level output voltage High-level output voltage High-level input voltage Low-level input voltage FAN-PWM period FAN-PWM duty cycle range Duty cycle resolution FAN-TACH range FAN-TACH resolution FAN-TACH minimum pulse width Tach pulse revolution. pulse/rev, divide that value Tach pulse revolution Either positive negative polarity Vref commanded AFEgain input EAP/N measured output EADC AFEgain compared AFEgain 300k (2), VV33DIO (3), VV33DIO VV33DIO VV33DIO 100% V33DIO -0.6V Dgnd +0.25 TEST CONDITIONS UNIT
CONTROL INPUTS/OUTPUTS
SYSTEM PERFORMANCE VRef Setpoint Reference Accuracy Setpoint Reference Accuracy over temeprature VDiffOffset tDelay Duty VDDSlew tretention Write_Cycles Differential offset between gain setetings Digital Compensator Delay Switching Frequency Duty Cycle Minimum slew rate Retention configuration parameters Number nonvolatile erase/write cycles Configured PMBus slew rate between 2.3V 2.9V 15.260 0.25 2000 100% V/ms Years cycles
maximum IOL, outputs combined, should exceed hold maximum voltage drop specified. maximum IOH, outputs combined, should exceed hold maximum voltage drop specified. With default device caliibration. PMBus calibration used improve regulation tolerance. Time from close error sample window time when digitally calculated control effort (duty cycle) available. This delay must accounted when calculating system dynamic response. PMBus command: EADC_SAMPLE_TRIGGER defines start 32ns sample window. minimum EAD_SAMPLE_TRIGGER time
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UCD9240
MONITORING INTERVALS RESPONSE TIMES
operates continuous conversion sequence that measures each rail's output voltage, each power stage's ouput current, plus four other variables (external temperature, Internal temperature, input voltage current, tracking input voltage). length sequence determined number output rails (NumRails) total output power stages (NumPhases) configured use. time complete monitoring sampling sequence give formula:
tADC_SEQ tADC (NumRAILS NumPHASE
PARAMETER tADC tADC_SEQ single-sample time sequencer interval Rail Phase samples Rails Phases samples 23.04 TEST CONDITIONS 3.84 61.44 UNIT
most recent conversion results periodically converted into proper measurement units (volts, amperes, degrees), each measurement compared corresponding fault warning limits. monitoring operates asynchronously ADC, intervals shown table below.
PARAMETER tVout tIout tVin tIin tTEMP tIbal tFanTach Output voltage monitoring interval Output current monitoring interval Input voltage monitoring interval Input current monitoring interval Temeprature monitoring interval Output current balancing interval speed monitoring interval TEST CONDITIONS NRails 1000 UNIT
Because sequencer monitoring comparisons asynchronous each other, response time fault condition depends where event occurs within monitoring interval within sequence interval. Once fault condition detected, some additional time required determine correct action based FAULT_RESPONSE code, then perform appropriate response. following table lists worse-case fault response times.
PARAMETER tOVF, tUVF tOVF, tUVF tOVF, tUVF tOCF, tUCF Over/under voltage fault response time during normal operation TEST CONDITIONS Normal regulation, PMBus activity, stages enabled TIME
UNIT
Over/under voltage fault response time, during data During data logging nonvolatile logging memory Over/under voltage fault response time, when tracking sequencing enable Over/under current fault response time during normal operation During tracking soft-start ramp. Normal regulation, PMBus activity, stages enabled 125% current step
(600 NRails)
tOCF, tUCF tOCF, tUCF tOTF
During data logging nonvolatile Over/under current fault response time, during data memory logging 125% current step Over/under current fault response time, when tracking sequencing enable Overtemperature fault response time During tracking soft start ramp 125% current step Temperature rise °C/sec, threshold
(600 NRails) (600 NRails)
During STORE_DEFAULT_ALL command, which stores entire configuration nonvolatile memory, fault detection latency Because current measurement averaged with smoothing filter, response time Overcurrent condition depends combination time constant from Table recent measurement history, much measured value exceeds overcurrent limit.
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UCD9240
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HARDWARE FAULT DETECTION LATENCY
controller contains hardware fault detection circuits that independent monitoring sequencer.
PARAMETER tFAULT tCLF-A tCLF-B Time disable DPWM output base active FAULT signal Time disable DPWM output based internal analog comparator Time disable remaining DPWM outputs configured drive voltage rail after CLF-A event occurs TEST CONDITIONS High level FAULT Step change voltage from 2.5V Step change voltage from 2.5V TIME NumPhases NumPhases UNIT Switch Cycles
PMBUS/SMBUS/I2C
timing characteristics timing diagram communications interface that supports I2C, SMBus PMBus shown below.
I2C/SMBus/PMBus Timing Characteristics
-40°C 85°C, 3.6V, typical values 25°C (Unless otherwise noted)
PARAMETER fSMB fI2C t(BUF) t(HD:STA) t(SU:STA) t(SU:STO) t(HD:DAT) t(SU:DAT) t(TIMEOUT) t(LOW) t(HIGH) t(LOW:SEXT) tFALL tRISE SMBus/PMBus operating frequency operating frequency free time between start stop Hold time after (repeated) start Repeated start setup timed Stop setup time Data hold time Data setup time Error signal/detect Clock period Clock high period Cumulative clock slave extend time Clock/data fall time Clock/data rise time
TEST CONDITIONS Slave mode; SMBC duty cycle Slave mode; duty cycle
0.26 0.26 0.26
1000 1000
UNIT
Receive mode
0.26
UCD9240 times when clock exceeds t(TIMEOUT). t(HIGH), max, minimum idle time. SMBC SMBD causes reset transaction involving UCD9240 that progress. This specification valid when NC_SMB control remains default cleared state (CLK[0]=0). t(LOW:SEXT) cumulative time slave device allowed extend clock cycles message from initial start stop. Rise time tRISE VVILMAX 0.15) (VVIHMIN 0.15) Fall time tFALL (VILMAX 0.15)
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UCD9240
coefficients filter sections generated through modeling power stage load Power+ Designer tool. Several banks filter coefficients downloaded device that automatically switch them based power stage operation.
Figure I2C/SMBus/PMBus Timing Extended Mode Diagram
Copyright 2008, Texas Instruments Incorporated
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UCD9240
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FUNCTIONAL BLOCK DIAGRAM
Fusion Power Peripheral
EAp4 EAn4
Analog Front (AFE)
Compensator 3P/3Z
Digital High
DPWM-4A DPWM-4B FAULT-4A FAULT-4B
Fusion Power Peripheral
EAp3 EAn3
Analog Front (AFE)
Compensator 3P/3Z
Digital High
DPWM-3A DPWM-3B FAULT-3A FAULT-3B
Fusion Power Peripheral
EAp2 EAn2
Analog Front (AFE)
Compensator 3P/3Z
Digital High
DPWM-2A DPWM-2B FAULT-2A FAULT-2B
Fusion Power Peripheral Analog Front
EAp1 EAn1 Diff
Compensator 3P/3Z Coeff. Regs Digital High
DPWM-1A DPWM-1B FAULT-1A FAULT-1B SYNC-IN (TDI) SYNC -OUT (TDO)
V33x xGnd BPCap 3.3V reg. controller 1.8V regulator
Analog Comparators
PWM-1A
ARM-7 core
Control
AddrSens0 AddrSens1 CS-1A CS-1B CS-2A CS-2B CS-3A CS-3B CS-4A CS-4B Vin/Iin Vtrack Temp ADCref
PWM-2A
SRE-4B SRE-4A SRE-3B SRE-3A SRE-2B SRE-2A SRE-1B SRE-1A TMUX0 TMUX1 TMUX2 FAN-TACH (TCK) FAN-PWM PMBus-Clk PMBus-Data PMBus-Alert PMBus-Cntl PowerGood (TMS) /RESET
12-bit ksps
PWM-3A
Flash Memory with POR/BOR
Control Control
PWM-4A
PMBus
Internal Temp Sense
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UCD9240
UCD9240-64pin
DPWM-1A DPWM-1B DPWM-2A DPWM-2B DPWM-3A DPWM-4A FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-4A SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-4A EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4
UCD9240-80pin
DPWM-1A DPWM-1B DPWM-2A DPWM-2B DPWM-3A DPWM-3B DPWM-4A DPWM-4B FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-3B FAULT-4A FAULT-4B SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-3B SRE-4A SRE-4B SYNC-IN SYNC-OUT FAN-PWM FAN-TACH Diag /TRST TRCK
V33FB V33A V33D V33DIO-1 V33DIO-2 BPCap
EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4
AddrSens0 AddrSens1 CS-1A (COMP1) CS-2A (COMP2) CS-3A (COMP3) CS-4A (COMP4) CS-1B CS-2B Vin/Iin Vtrack Temp
AVSS-1 AVSS-2
DVSS-1 DVSS-2 DVSS-3
AVSS-3
TMUX-0 TMUX-1 PMBus-Clk TMUX-2 PMBus-Data PMBus-Alert FAN-PWM PMBus-Ctrl FAN-TACH (TCK) PowerGood (TMS) SYNC-IN (TDI) SYNC-OUT (TDO) /RESET /TRST TRCK
AddrSen0 AddrSen1 CS-1A (COMP1) CS-2A (COMP2) CS-3A (COMP3) CS-4A (COMP4) CS-1B CS-2B CS-3B CS-4B Vin/Iin Vtrack Temp Aux-in Aux-in ADCref
TMUX-0 TMUX-1 TMUX-2 PMBus-Clk PMBus-Data PMBus-Alert PMBus-Ctrl PowerGood
/RESET
Figure UCD9240 Assignment UCD9240 available plastic 64-pin package (RGC) 80-pin TQFP package (PFC).
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AVSS-1 AVSS-2 AVSS-3 DVSS-1 DVSS-2 DVSS-3
V33FB V33A V33D V33DIO-1 V33DIO-2 BPCap
UCD9240
SLUS766C JULY 2008 REVISED NOVEMBER 2008. www.ti.com
TYPICAL APPLICATION SCHEMATIC
Figure shows UCD9240 power supply controller part system that provides regulation four independent power supplies. loop each power supply created respective voltage outputs feeding into differential voltage error (EADC) inputs, completed DPWM outputs feeding into gate drivers each power stage. ±Vsenserail signals must routed EAp/EAn input that matches number lowest DPWM configured part rail. (See more detail page "Flexible Rail/Power Stage Configuration".)
FCX491A +3.3 82.5
FAULT VBIAS UCD7230 Driver Commutation
Temp-rail1A PTD08A020W
TEMP Temp Sensor
+3.3
Logic
CS-rail1A
IOUT
V33D
V33DIO-
V33DIO-2
BPCap
V33FB
V33A
+Vsens-rail1 -Vsens-rail1 +Vsens-rail2 -Vsens-rail2 +Vsens-rail3 -Vsens-rail3 +Vsens-rail4 -Vsens-rail4
DPWM-1A DPWM-1B DPWM-2A DPWM-2B DPWM-3A DPWM-4A FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-4A SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-4A TMUX-0 TMUX-1 TMUX-2 FAN-PWM FAN-TACH SYNC-IN FAULT FAN-PWM FAN-Tach SyncIn SyncOut Temp-rail3A CS-rail2B VBIAS TEMP VOUT CS-rail2A Temp-rail2B FAULT VBIAS TEMP VOUT Temp-rail2A CS-rail1B +Vsens-rail1 -Vsens-rail1 FAULT VBIAS TEMP VOUT Temp-rail1B
EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4
PTD08A020W
IOUT
AddrSens0 AddrSens1 CS-1A(COMP1) CS-2A(COMP2) CS-3A(COMP3) CS-4A(COMP4) CS-1B CS-2B Vin/Iin Vtrack Temp PMBus-Clk PMBus-Data PMBus-Alert PMBus-Ctrl PowerGood (TMS)
CS-rail1A CS-rail2A CS-rail3A CS-rail4A CS-rail1B CS-rail2B
PTD08A010W
IOUT
UCD9240RGC
PTD08A010W
IOUT +Vsens-rail2 -Vsens-rail2
Agnd-1 Agnd-2 Dgnd-
SYNC-OUT
Dgnd-2 Dgnd-3 Agnd-3
+3.3
RESET
TRST
FAULT CS-rail3A
VBIAS
TEMP VOUT
PTD08A010W
IOUT +Vsens-rail3 -Vsens-rail3 Temp-rail4A
Temp-rail1A Temp-rail1B Temp-rail2A Temp-rail2B Temp-rail3A Temp-rail4A
CD74HC4051
+3.3
FAULT CS-rail4A
VBIAS
TEMP VOUT +Vsens-rail4 -Vsens-rail4 UDG-08035
PTD08A010W
IOUT
Figure Typical Application Schematic
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UCD9240
DESCRIPTIONS
64-PIN PACKAGE SIGNAL EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAN4 80-PIN PACKAGE SIGNAL EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4 DESCRIPTION Error Amplifier Differential Analog Inputs Error analog, differential voltage. Positive channel input. Error analog, differential voltage. Negative channel input. Error analog, differential voltage. Positive channel input. Error analog, differential voltage. Negative channel input. Error analog, differential voltage. Positive channel input. Error analog, differential voltage. Negative channel input. Error analog, differential voltage. Positive channel input. Error analog, differential voltage. Negative channel input. Analog Inputs AddrSens0 AddrSens1 CS-1A CS-2A CS-3A CS-4A CS-1B CS-2B CS-3B CS-4B Vin/ VTRACK Temp Aux-in (AD13) Aux-in (AD14) ADCref AddrSens0 AddrSens1 CS-1A CS-2A CS-3A CS-4A CS-1B CS-2B CS-3B CS-4B Vin/ VTRACK Temp Aux-in (AD13) Aux-in (AD14) ADCref PMBus address sense. Least significant address bits PMBus address sense. Most significant address bits Power stage current sense input. Analog comparator Power stage current sense input. Analog comparator Power stage current sense input. Analog comparator Power stage current sense input. Analog comparator Power stage current sense input Power stage current sense input Power stage current sense input Power stage current sense input Input supply sense, alternates between Voltage tracking Temperature sense input Unused analog input ground with resistor Unused analog input ground with reisistor Decoupling Capacitor ground Digital Outputs dPWM-1A dPWM-1B dPWM-2A dPWM-2B dPWM-3A dPWM-4A dPWM-1A dPWM-1B dPWM-2A dPWM-2B dPWM-3A dPWM-3B dPWM-4A dPWM-4B DPWM output DPWM output DPWM output DPWM output DPWM output DPWM output DPWM output DPWM output External Fault Inputs FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-4A FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-3B FAULT-4A FAULT-4B External fault input External fault input External fault input External fault input External fault input External fault input External fault input External fault input Submit Documentation Feedback Product Folder Link(s): UCD9240
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UCD9240
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DESCRIPTIONS (continued)
64-PIN PACKAGE SIGNAL 80-PIN PACKAGE SIGNAL DESCRIPTION Synchronous Rectification Enable Outputs SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-4A SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-3B SRE-4A SRE-4B Synchronous rectifier enable Synchronous rectifier enable Synchronous rectifier enable Synchronous rectifier enable Synchronous rectifier enable Synchronous rectifier enable Synchronous rectifier enable Synchronous rectifier enable Miscellaneous Digital TMUX-0 RESET TMUX-1 TMUX-2 FAN-PWM PowerGood FAN-Tach Sync_Out Sync_In TMUX-0 RESET TMUX-1 TMUX-2 FAN-PWM PowerGood FAN-Tach Sync_Out Sync_In diag Temperature multiplexer select Active device reset input Temperature multiplexer select Temperature multiplexer select control output Power good signal (multiplexed with 64-pin package) tachometer input (multiplexed with 64-pin package) Synchronization output from DPWM (multiplexed with 64-pin package) Synchronization input DPWM (multiplexed with 64-pin package) Diagnostic PMBus Communications Interface PMBus_Clk PMBus_Data PMBus_Alert PMBus_Cntrl PMBus_Clk PMBus_Data PMBus_Alert PMBus_Cntrl PMBus (Must have pullup PMBus Data (Must have pullup PMBUS Alert PMBUS Cntl JTAG TRCK TRST TRCK TRST Test return clock Test clock (multiplexed with FAN-Tach (TCK) 64-pin package) Test data (multiplexed with Sync_Out (TDO) 64-pin package) Test data with resistor (multiplexed with Sync_In (TDI) 64-pin package) Test mode select with resistor (multiplexed with PowerGood (TMS) 64-pin package) Test reset ground with resistor Input Power Grounds V33FB V33A V33D V33DIO V33DIO BPCap AVSS AVSS AVSS V33FB V33A V33D V33DIO V33DIO BPCap AVSS AVSS AVSS 3.3-V linear regulator Feedback connection Analog 3.3-V supply Digital core 3.3-V supply Digital 3.3-V supply Digital 3.3-V supply 1.8-V bypass capacitor connection Analog ground Analog ground Analog ground
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DESCRIPTIONS (continued)
64-PIN PACKAGE Power SIGNAL DVSS DVSS DVSS Connect 80-PIN PACKAGE SIGNAL DVSS DVSS DVSS DESCRIPTION Digital ground Digital ground Digital ground recommended that this connected analog ground. (64-pin package only)
FUNCTIONAL OVERVIEW
UCD9240 contains four fusion power peripherals (FPP). Each configured regulated four DC/DC converter outputs. There eight outputs that assigned drive coverter outputs. Each configured drive from eight power stages. Each consists differential input error voltage amplifier. 10-bit used output regulation reference voltage. fast with programmable input gain digitally measure error voltage. dedicated 3-pole/3-zero digital filter compensate error voltage. digital (DPWM) engine that generates pulse width based compensator output. Each controller configured through PMBus serial interface.
PMBus Interface
PMBus serial interface specifically designed support power management. based SMBus interface that built physical specification. UCD9240 supports revision PMBus standard. Wherever possible, standard PMBus commands used support function device. unique features UCD9240, MFR_SPECIFIC commands defined configure activate those features. These commands defined UCD92xx PMBUS Command Reference. UCD9240 PMBus compliant, accordance with "Compliance" section PMBus specification. firmware also compliant with SMBus specification, including support SMBus ALERT function. hardware support either kHz, kHz, PMBus operation.
Resistor Programmed PMBus Address Decode
pins allocated decode PMBus address. power-up, device applies bias current each address detect pin, voltage that captured internal 12-bit ADC. PMBus address calculated follows:
PMBus Address bin(VAD01) bin(VAD00)
Where bin(VAD0x) address address shown Table
AddrSens0, AddrSens1 pins
IBIAS
UCD9240
On/Off Control
Resistor PMBus Address
-bit
Figure PMBus Address Detection Method address bins defined that each constant ratio previous bin. This method maintains width each relative tolerance standard resistors. ratio betweens bins 1.30.
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Table PMBus Address Bins
PMBus ADDRESS open short VPMBus PMBus VOLTAGE RANGE 2.226 1.746 1.342 1.030 0.792 0.609 0.468 0.359 0.276 0.212 0.162 0.125 0.098 3.300 2.255 1.746 1.341 1.030 0.792 0.608 0.467 0.358 0.275 0.211 0.162 0.124 0.097 RPMBus PMBus RESISTANCE 84.5 63.4 47.5 36.5 27.4 21.5 16.9 13.0 10.2
impedance (short) either address that produces voltage below minimum voltage causes PMBus address default address 126. high impedance (open) either address that produces voltage above maximum voltage also causes PMBus address default address 126. PMBus address value ranging from 126, except address Address used because SMBus General Call address; address reserved PMBus alert response. Also, recommended that address used this device other device that shares PMBus with since used manufacturing program device. Further, address cannot used this device other device that shares PMBus with since address reserved this device device manufacturing test. Finally, recommended that address used devices PMBus, since this address that UCD9240 defaults address lines shorted ground left open. other UCD9240 short open address lines, then address would conflict with (programmed) address 126.
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Table PMBus Address Assignment Rules
ADDRESS 1-10 13-125 STATUS Prohibited Avaliable Avoid Prohibited Avaliable Avoid Prohibited Default value; cause conflicts with other devices. Used manufacturing device tests. Causes confilcts with other devices during program flash updates. PMBus alert response protocol SMBus generall address call REASON
JTAG Interface
JTAG interface provide alternate interface programming device. disabled default order enable fan, sync, power good status pins with which multiplexed. There three conditions under which JTAG interface enabled: When ROM_MODE PMBus command issued. power-up Data Flash blank. This allows JTAG used writing configuration parameters programmed device with PMBus interaction. When invalid address detected power-up. shorting address pins ground, invalid address generated that enables JTAG.
Bias Supply Generator (Series Regulator Controller)
Internally, circuits UCD92XX require 3.3V operate. This provided directly V33x pins, generated from power supply input voltage using internal series regulator external transistor. requirements external transistor that device with beta least Figure shows typical application using external series pass transistor. base transistor driven resistor transconduction amplifier whose output VD33FB pin. emitter becomes supply chip requires bypass capacitor Some circuits device require 1.8V that generated internally from 3.3V supply. This voltage requires bypass capacitor from BPCap ground.
FCX491A Power Stage +3.3V
10k0
4.7u
+1.8V
0.1u
0.1u
Figure Series-Pass 3.3V Regulator Controller
Power Reset
UCD9240 integrated power-on reset (POR) circuit that monitors supply voltage. power-up, circuit detects V33D rise. When V33D greater than VRESET, device initiates UVLO startup-delay sequence. delay sequence, device begins normal operation, defined downloaded device PMBus configuration.
V33FB V33A V33D V33DIO-1 V33DIO-2 BPCap
UCD9240
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External Reset
device forced into reset state external circuit connected RESET pin. logic voltage this holds device reset. avoid erroneous trigger caused noise, pull resistor 3.3V recommended.
Output Voltage Adjustment
nominal output voltage programmed combination PMBus commands: VOUT_COMMAND, VOUT_CAL_OFFSET, VOUT_MAX. Their relationship shown Figure Output voltage margining configured VOUT_MARGIN_HIGH VOUT_MARGIN_LOW commands. OPERATION command selects between nominal output voltage either margin voltages. OPERATION command also includes option suppress certain voltage faults warnings while operating margin settings.
OPERATION Command VOUT_MAX VOUT_MARGIN_HIGH VOUT_COMMAND VOUT_MARGIN_LOW
Limiter
VOUT_ SCALE_ LOOP
"Reference Voltage Equivalent"
VOUT_CAL_OFFSET
Figure PMBus Voltage Adjustment Methods complete description commands supported UCD9240 UCD92xx PMBUS Command Reference. Each these commands also issued from Texas Instruments Fusion Digital PowerDesigner program. This Graphical User Interface (GUI) program issues appropriate commands configure UCD9240 device.
Analog Front (AFE)
EApx EAnx
GAFE
Vead
6-bit result
eADC
eADC 8mV/LSB Vref Vref 1.563 mV/LSB
PMBus
Figure Analog Front Block Diagram UCD9240 senses power supply output voltage differentially through pins. error amplifier utilizes switched capacitor topology that provides wide common mode range output voltage sense signals. fully differential nature error amplifier also ensures offset performance. output voltage sampled programmable time (set EADC_SAMPLE_TRIGGER PMBus
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command). When differential input voltage sampled, voltage captured internal capacitors then transferred error amplifier where value subtracted from set-point reference which generated Vref shown Figure resulting error voltage then amplified programmable gain circuit before error voltage converted digital value flash ADC. This programmable gain configured through PMBus affects dynamic range resolution sensed error voltage shown Table Table Analog Front Resolution
GAIN AFE_GAIN PMBus COMMAND EFFECTIVE RESOLUTION (mV) DIGITAL ERROR VOLTAGE DYNAMIC RANGE (mV) -256 -128
variable gain compensation coefficients that stored when device configured issuing CLA_GAINS PMBus command. Compensator coefficients arranged several banks: bank start/stop ramp tracking, bank normal regulation mode bank light load mode. This allows user trade-off resolution dynamic range each operational mode. EADC, which samples error voltage, high accuracy, high resolution, fast conversion time. However, range limited shown Table output voltage different from reference more than this, EADC reports saturated value LSBs LSBs. UCD9240 overcomes this limitation adjusting setpoint down order bring error voltage saturation. this way, effective range extended. When EADC saturates, setpoint slewed rate 0.156 V/ms, referred differential inputs.
VOUT
IOFF
Figure Input Offset Equivalent Circuit obtain best possible accuracy, input resistance offset current device should considered when calculating gain voltage divider between output voltage sense inputs UCD9240. input resistance input offset current specified parametric tables this datasheet.
VOUT IOFF
effect offset current reduced making resistance divider network low. should between Then lower divider resistor, calculated R1VEA VOUT R1IOFF
Digital Compensator
Each voltage rail controller UCD9240 includes digital compensator. compensator consists nonlinear gain stage, followed digital filter consisting second order infinite impulse response (IIR) filter section cascaded with first order filter section.
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Texas Instruments Fusion Digital PowerDesigner development tool used assist defining compensator coefficients. design tool allows compensator described terms pole frequencies, zero frequencies gain desired control loop. addition, Fusion Digital PowerDesigner used characterize power stage that compensator coefficients chosen based total loop gain each feedback system. coefficients filter sections generated through modeling power stage load. Additionally, UCD9240 three banks filter coefficients: Bank-0 used during soft start/stop ramp tracking; Bank-1 used while regulation mode; Bank-2 used when measured output current below configured light load threshold. compensator also allows minimum maximum duty cycle programmed. This again done issuing PMBus command device.
Limit Limit Limit Limit
Threshold logic
Gain Gain Gain Gain Gain
Clamp
Nonlinear Gain Block Order Filter Section eADC
Duty
Clamp
Order Filter Section
Figure Digital Compensator nonlinear gain block allows different gain applied system when error voltage deviates from zero. Typically Limit Limit would configured with negative values between Limit Limit would configured with positive values between However, gain thresholds have symmetric. example, four limit registers could positive values causing Gain value gain negative errors nonlinear gain profile would applied only positive error voltages. cascaded order filter section used generated third zero third pole.
DPWM Engine
output compensator feeds high resolution DPWM engine. DPWM engine produces pulse width modulated gate drive output from device. operation, compensator calculates necessary duty cycle digital number representing value from This duty cycle value multiplied configured period generate comparator threshold value. This threshold compared against high speed switching period counter generate desired DPWM pulse width. This shown Figure resolution duty period nominally picoseconds. Each DPWM engine synchronized another DPWM engine external sync signal SYNC_IN SYNC_OUT pins. Configuration synchronization function done through MFR_SPECIFIC PMBus command. DPWM Synchronization section more details.
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DPWM Engine
SysClk SyncIn high reset ramp counter
Switch period Current balance Compensator output
gate drive output
(calculated duty cycle)
EADC trigger
EADC trigger threshold
SyncOut
Figure DPWM Engine switching frequency issuing FREQUENCY_SWITCH PMBus command.
Flexible Rail/Power Stage Configuration
UCD9240 control four rails, each which comprise programmable number power stages. Constraints mapping power stages rails described detail UCD92xx PMBus Command Reference under PHASE_INFO command. While there significant flexibility terms mapping power stages output rails, differential voltage feedback signals (EAP/EAN) cannot re-mapped through commands, therefore, must connected proper input circuit board. Because EADC sample trigger given front stage derived from ramp timer first (lowest numbered) DPWM rail, system must ensure that number EADC number first DPWM match. example, consider rail configuration which power stages (1A, assigned first rail power stages second. first DPWM first rail voltage feedback must through EAP1/EAN1. first DPWM second rail voltage feedback must through EAP3/EAN3. this configuration EAP2/EAN2 EAP4/EAN4 unused disabled reduce unnecessary power consumption.)
DPWM Phase Distribution
number voltage rails configured using PHASE_INFO PMBus command. UCD9240 automatically synchronizes first power stage each voltage rail. phase time) each power stage shifted amount order minimize input current ripple. amount that each power stage shifted rail-rail spread
Where period rail with fastest switching frequency.
ratio 3/13 chosen because close 1/4, prime ratio. This should ensure that configuration rails power stages should have leading edge DPWM signal aligned. PHASE_INFO PMBus command also used configure number power stages driving each voltage rail. When multiple power stages configured drive voltage rail, UCD9240 automatically distributes phase each DPWM output minimize ripple. This accomplished setting rising edge each DPWM pulse separated
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phase-phase spread
NPhases
Where switching period NPhases number power stages driving voltage rail.
DPWM Synchronization
DPWM synchronization provides method link timing between rails distinct devices switching rate; i.e., rails different devices configured same frequency sync forcing them drift from each other. (Note that within single device, because rails driven common clock there need internal sync because rails wont drift.) PMBus SYNC_IN_OUT command sets which rails any) should follow sync input, which rail any) should drive sync output. rails that following sync input, DPWM ramp timer that output reset when sync input goes high. This allows slave device sync inputs that either faster slower than fast side, there limit much faster input compared defined frequency rail; when pulse comes timer reset frequencies locked. This standard mode operation setting slave slower, letting sync speed slave rail running fast, sync pulse resets counter after DPWM output already been turned Resetting counter this point results larger duty cycle that period. Because system closed loop; however, controller reacts decreasing commanded control effort, with result being regulated rail synchronized slower master. Synchronizing slower master does have limit however. master slow enough that DPWM output sufficient time output entire command pulse before sync input arrives, result double pulse. This likely undesirable mode operation. Sync Input Output Configuration Word PMBus command consists bytes. upper byte (sync_out) controls which rail drives sync output signal (0=DWPM1, 1=DPWM2, 2=DPWM3, 3=DPWM4. other value disables sync_out). lower byte (sync_in) determines which rail(s) respond sync input signal (each represents rail note that multiple rails synchronized input). DPWM period aligned sync input. more information, UCD92xx PMBUS Command Reference. Note that once rail synchronized external source, rail-to-rail spacing that attempts minimize input current ripple lost. Rail-to-rail spacing only restored power cycling issuing SOFT_RESET command.
Phase Shedding Light Current Load
issuing LIGHT_LOAD_LIMIT_LOW, LIGHT_LOAD_LIMIT_HIGH, LIGHT_LOAD_CONFIG commands, UCD9240 configured shed (disable) power stages when light load. When this feature enabled, device disables configured number power stages when average current drops below specified LIGHT_LOAD_LIMIT_LOW. addition, separate compensation coefficients loaded into digital compensator when entering light load condition.
Phase Adding Normal Current Load
After shedding phases, current load increased past LIGHT_LOAD_LIMIT_HIGH threshold, phases re-enabled. compensator configured light load, normal load coefficients restored well. UCD92xx PMBUS Command Reference more information.
Output Current Measurment
Pins CS-1A, CS-1B, CS-2A, CS-2B, CS-3A, CS-3B, CS-4A, CS-4B used measure either output current inductor current each controlled power stages. PMBus commands IOUT_CAL_GAIN IOUT_CAL_OFFSET used calibrate each measurement. UCD92xx PMBus Command Reference specifics configuring this voltage current conversion. When measured current outside range either overcurrent undercurrent threshold, FAULT
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declared UCD9240 performs PMBus configured fault recovery. current measurements digitally averaged before they compared against FAULT threshold. output current measured rate output rail microseconds. current measurements then passed through smoothing filter reduce noise signal prevent false errors. output smoothing filter asymptotically approaches input value with time constant that approximately times sampling interval. Table Output Current Filter Times Constants
NUMBER OUTPUT RAILS OUTPUT CURRENT SAMPLING INTERVALS (µs) FILTER TIME CONSTANTS (ms)
example, with single rail, filter transfer function characteristics (Figure that shows signal magnitude output averaging filter sine wave input range frequencies. This plot includes analog pass network, with corner frequency kHz, current sense inputs. This averaged current measurement used output current fault detection; "Overcurrent Detection," below. response PMBus request current reading, device returns average current value. When UCD9240 configured drive multi-phase power converter, device adds average current measurement each power stages tied power rail.
1.0k freq 100k
Figure Averaging filter Current Monitoring Figure Averaging Filter current monitoring
Output Current Balancing
When UCD9240 configured drive multiple power stage circuits from compensator, current balancing implemented adjusting each gate drive output pulse width correct current imbalance between connected power stage sections. UCD9240 balances current monitoring current analog input each power stage then adding current balance adjustment value DPWM ramp threshold value each power stage. When there more than power stage connected voltage rail, device continually determines which stage highest measured current which stage lowest measured current. balance currents while maintaining constant total current, adjustment value power stage with lowest current increased same amount adjustment value power stage with highest current decreased. slight modification this algorithm made keep adjustment values positive order ensure that positive DPWM duty cycle commanded under conditions.
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Overcurrent Detection
Several mechanisms provided sense output current fault conditions. This allows design power systems with multiple layers protection. logic high signal FAULT input causes hardware interrupt internal CPU. then determines which DPWM outputs configured associated with voltage rail that contained fault disables those DPWM outputs. This process takes about microseconds. integrated gate driver such UCD7230 used generate FAULT signal. UCD7230 monitors voltage drop across high side exceeds resistor/voltage programmed threshold, UCD7230 activates fault output. FAULT input disabled reconfiguring FAULT sequencing pin. Inputs CS-1A, CS-2A, CS-3A CS-4A each drive internal analog comparator. These comparators used detect voltage output current sense circuit. Each comparator separate PMBus configurable threshold. This threshold issuing FAST_OC_FAULT_LIMIT command. Though command specified amperes, hardware threshold programmed with value between 31mV steps. conversion from amperes volts accomplished issuing IOUT_CAL_GAIN command. When current sense voltage exceeds configured threshold corresponding DPWM outputs driven voltage rail with fault. Each Current Sense input UCD9240 also monitored 12-bit ADC. Each measured value scaled using IOUT_CAL_GAIN IOUT_CAL_OFFSET commands. currents each power stage configured part voltage rail summed compared limit IOUT_OC_FAULT_LIMIT command. action taken when fault detected defined IOUT_OC_FAULT_RESPONSE command. Because current measurement averaged with smoothing filter, response time Overcurrent condition depends combination time constant from Table recent measurement history, much measured value exceeds overcurrent limit. When current steps from current (I1) that less than limit higher current (I2) that greater than limit, output smoothing filter Ismoothed point when Ismoothed exceeds limit, smoothing filter lags time, tlag
tlag Ilimit
worst case response time overcurrent condition sampling interval (Table smoothing filter lag, tlag from equation above.
Current Foldback Mode
When measured output current exceeds value specified IOUT_OC_FAULT_LIMIT command, UCD9240 attempts continue operate reducing output voltage order maintain output current value IOUT_OC_FAULT_LIMIT. This continues indefinitely long output voltage remains above minimum value specified IOUT_OC_LV_FAULT_LIMIT. output voltage pulled down less than that value, device shuts down, programmed IOUT_OC_LV_FAULT_RESPONSE command.
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Input Voltage Current Monitoring
Vin/Iin UCD9240 monitors input voltage current. measure both input voltage input current, external multiplexer required. measurement only input voltage, input current, desired, then multiplexer needed, Figure multiplexer switched between voltage current using TMUX-0 signal. (This signal temperature select signals, TMUX-0 signal connected both temperature multiplexer well voltage/current multiplexer). Vin/Iin monitored using internal 12-bit dynamic range 2.5V. fault thresholds input voltage using VIN_OV_FAULT_LIMIT VIN_UV_FAULT_LIMIT commands. scaling using VIN_SCALE_MONITOR command, scaling using IIN_SCALE_MONITOR command.
Temperature Monitoring
Both internal device temperature eight external temperatures monitored UCD9240. controller supports multiple PMBus commands related temperature, including READ_TEMPERATURE_1, which reads internal temperature, READ_TEMPERATURE_2, which reads external power stage temperatures, OT_FAULT_LIMIT, which sets over temperature fault limit, OT_FAULT_RESPONSE, which defines action take when configured limit exceeded. more than external temperature measured, UCD9240 provides analog multiplexer select pins (TMUX0-2) allow external temperatures measured. output multiplexer routed Temp pin. controller cycles through each power stage temperature measurement signals. signal from external temperature sensor expected linear voltage proportional temperature. PMBus commands TEMPERATURE_CAL_GAIN TEMPERATURE_CAL_OFFSET used scale measured temperature-dependent voltage inputs multiplexer mapped order that outputs assigned PHASE_INFO PMBus command. example, only power stage wired each DPWM, four temperature signals should wired first four multiplexer input. UCD9240 monitors temperature using 12-bit monitor ADC, sampling each temperature turn with sample period. These measurements smoothed digital filter, similar that used smooth output current measurements. filter time constant 15.5 times sample interval, 12.4 (15.5 12.4 seconds). This filtering reduces probability false fault detections.
+3.3V
Temp-rail1A Temp-rail1B Temp-rail2A Temp-rail2B Temp-rail3A Temp-rail4A
CD74HC4051
Temp TMUX2 TMUX1 TMUX0
Figure Temperature (4-rail, 6-phase Example) Below example system with output voltage rails, where each output driven power stages. first output voltage rail driven with PWM-1A, -1B, PWM-3A. second output voltage rail driven with PWM-2A, PWM-2B, PWM-4A. order which temperature multiplexer inputs assigned shown Table Table Temperature Sensor Mapping
TEMPERATURE INPUT POWER STAGE PWM-1A PWM-1B PWM-3A PWM-2A RAIL Rail-1A Rail-1B Rail-1C Rail-2A
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Table Temperature Sensor Mapping (continued)
TEMPERATURE INPUT POWER STAGE PWM-2B PWM-4A RAIL Rail-2B Rail-2C
Temperature Balancing
Temperature balancing between phases performed adjusting current such that cooler phases draw larger share current. Temperature balancing occurs slowly (the loop runs rate), only when phase currents exceeds PMBus settable TEMP_BALANCE_IMIN. This minimum current threshold prevents controller from "winding forcing phase carry current under low-load condition, when total current insufficient significantly affect phase temperatures.
Soft Start, Soft Stop Ramp Sequence
UCD9240 performs soft start soft stop ramps under closed loop control. Performing start stop ramp tracking considered separate operational mode. other operational modes normal regulation light load regulation. Each operational mode configured have independent loop gain compensation. Each loop gain coefficients called "bank" configured using CLA_GAINS PMBus command. Start ramps performed waiting configured start delay TON_DELAY then ramping internal reference toward commanded reference voltage rate specified TON_DELAY time. DPWM outputs enabled when internal ramp reference equals preexisting voltage (pre-bias) output calculated DPWM pulse width exceeds pulse width specified DRIVER_MIN_PULSE. This ensures that constant ramp rate maintained, that ramp completed same time would there pre-bias condition. operation soft-stop ramps depends voltage rail configured. PAGE_ISOLATED through PAGE_ISOLATED PMBus command, controller assumes that only device driving voltage rail, soft-stop ramp performed with enabled until voltage associated with configured minimum supported pulse width reached. PAGE_ISOLATED controller assumes that multiple power stages supplying voltage rail disabled beginning soft-stop ramp. Figure shows operation soft-start ramps soft-stop ramps.
Soft-Start Soft-Stop
Bridged, 0.45-V bias
Start into -bias
Volts
begins here with pre-bias
Volts
Unbridged 0.45-V bias
Start from zero
begins here from output voltage
Unbridged bias
-0.2 Time
-0.2 Time
Figure Start Stop Ramps
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When voltage rail idle state, DPWM outputs disabled, differential voltage EAP/EAN pins monitored controller. During idle setpoint adjusted minimize error voltage. there pre-bias (that non-zero voltage regulated output), then device begin start ramp from that voltage with minimum disturbance. This done calculating duty cycle that required match measured voltage rail. Nominally this calculated Vout; however, allow losses offsets system, PREBIAS_GAIN PREBIAS_OFFSET used fine tuning. pre-bias voltage output requires smaller pulse width than driver deliver, defined DRIVER_MIN_PULSE PMBus command, then start ramp delayed until internal ramp reference voltage increased point where required duty cycle exceeds specified minimum duty. Once soft start/stop ramp begun, output controlled adjusting setpoint fixed rate allowing digital compensator control engine generate duty cycle based error. setpoint adjustments made rate based TON_RISE TOFF_FALL PMBus configuration parameters. Although presence pre-bias voltage specified minimum DPWM pulse width affects time when DPWM signals become active, time from when controller starts processing turn-on command time when reaches regulation TON_DELAY plus TON_RISE, regardless pre-bias minimum duty cycle. During normal ramp (i.e. tracking, current limiting events EADC saturation), setpoint slews pre-calculated rate based commanded output voltage TON_RISE. Under closed loop control, compensator follows this ramp regulation point. Because EADC controller limited range, saturate large transient during start/stop ramp. this occurs, controller overrides calculated setpoint ramp value, adjusts reference direction minimize error. continues step reference this direction until EADC comes saturation. Once saturation, start ramp continues, from this setpoint voltage; therefore, impact ramp time.
Input Lockout
normal operation supply lock-out voltage thresholds configured with VIN_ON VIN_OFF commands. When input supply voltage drops below value VIN_OFF, device starts normal soft stop ramp. When input supply voltage drops below voltage VIN_UV_FAULT_LIMIT, device performs configuration using VIN_UV_FAULT_RESPONSE command. example, when bias supply controller derived from another source, response code "Continue" "Continue with delay," controller attempts finish soft stop ramp. bias voltages controller gate driver uncertain below some voltage, user fault limit that voltage specify response code "shut down immediately" disabling DPWM outputs. VIN_OFF sets voltage which output voltage soft-stop ramp initiated, VIN_UV_FAULT_LIMIT sets voltage where power conversion stopped.
Voltage Tracking
Each voltage rail configured operate tracking mode. When voltage rail configured track another voltage rail, adjusts setpoint follow master, which either another internal rail external Vtrack pin. standard non-tracking mode, target Vout still specified voltage rail. tracking input exceeds this target, tracking voltage rail stops following master signal, switch regulation gains, regulate target voltage. When tracking input drops back below target (with hysteresis), tracking gains re-loaded, voltage rail follows tracking reference. Note that target above range tracking input, forcing voltage rail always remain tracking mode. During tracking, setpoint permitted change only fast possible without inducing EADC saturate. This limit reached master ramps extremely fast rate, master significantly different voltage when rail turned normal regulation, current limit (current foldback) detection EADC saturating forces rail temporarily deviate from tracking reference. PMBus command TRACKING_SOURCE available enable tracking mode select master track. tracking mode individually each rail, allowing each rail have different master, multiple rails share master, some rails track while others remain independent. Additionally, TRACKING_SCALE_MONITOR permits tracking voltage with fixed ratio master voltage. example, ratio causes rail regulate half master's voltage.
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Sequencing
There three methods squence voltage rails controlled UCD9240 that allow variety system sequencing configurations. Each these options configurable GUI. These methods include: PMBus soft start/stop parameters each rail. Multiple start/stop sequences triggered simultaneously. Each voltage rail performs sequencing open-loop manner. rail fails complete sequence, other rails unaffected. Daisy-chain Power Good output signal from controller PMBus-CTRL input another. GPIO_SEQ_CONFIG command assign dependencies between rails, configure unused pins sequencing control inputs sequencing status outputs. Method Each rail programmable delay times, TON_DELAY TOFF_DELAY, before beginning soft start ramp soft stop ramp, programmable ramp times, TON_RISE TOFF_FALL determine long ramp takes. These PMBus commands defined UCD92xx PMBUS Command Reference. parameters also configured using Fusion Digital PowerDesigner (see configurable times used program time based sequence each voltage rail. Using this method each rail ramps independently completes ramp regardless success other rails. start/stop sequence initiated single rail PMBus-CTRL PMBus using OPERATION ON_OFF_CONTROL commands. start/stop sequence initiated simultaneously multiple rails within same controller configuring each rail respond PMBus-CTRL pin. Alternatively, after setting PMBus PAGE variable 255, subsequent OPERATION ON_OFF_CONTROL commands applies rails same time. simultaneously initiate start/stop sequences multiple controllers, common PMBus-CTRL signal into each controller. Alternatively, PMBus Group Command Protocol used send separate commands multiple controllers. commands sent continuous transmission wait final STOP signal order start executing their commands simultaneously. Method Power Good used coordinate multiple controllers running Power Good output from controller PMBus-CTRL input another. This imposes master/slave relationship between multiple devices. During startup, slave controllers initiates their start sequences after master completes start sequence reaches regulation voltage. During shut-down, soon master starts shut-down sequence, shut-down signals slaves. Unlike Method shut-down more rails master initiate shut-downs slave devices. master shut-downs initiate intentionally fault condition. PMBus specification implies that Power Good signal active when rails controller above their power-good "on" threshold setting. UCD9240 allows Power Good reprogrammed using GPIO_SEQ_CONFIG command that responds desired subset rails. This method works coordinate multiple controllers, does enforce interdependency between rails within single controller. Method Using GPIO_SEQ_CONFIG command, several sequencing options configured using undedicated pins input/output. many four pins configured inputs, many eight outputs. outputs open-drain actively driven with selectable polarity. Each rail configured respond combination power-good status other internal rails and/or state sequencing input pins. output pins configured reflect power-good status combination rails, several status indicators including power-good, Overcurrent warning, "open-drain outputs valid" signal. When using output signals sequencing, they routed sequencing control inputs PMBus-CTRL inputs other controllers. Once each rail's input dependencies configured, rail responds those input pins internal rails. Like method shut-downs rail controller initiate shut-downs other rails controllers. Unlike method GPIO_SEQ_CONFIG offers much more flexibility assigning relationships between multiple rails within single controller between multiple controllers. possible each controller both master slave another controller.
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GPIO_SEQ_CONFIG allows configuration fault relationships such that fault rail result shut down selection rails addition rail fault. These fault interactions constrained single master/slave relationship; example, system configured such that fault rail shuts down rails. fault response failing rail shut down immediately, dependent rails follow suit shuts down immediately regardless their programmed response code. Each rail optionally configured monitor sequencing input specified period time after turns reaches power good threshold. programmable timeout reached before input state matches defined logic level, rail shut down, status error posted. This feature could used, example, ensure that board turn when main system voltage came Each rail enabled independently other rails unique timeout value; single input used timeout source. setup GPIO_SEQ_CONFIG command aided Fusion Digital PowerDesigner, which graphically displays relationships between rails provides intuitive controls allocate configure available resources. following pins available GPIO sequencing control, provided they being used their primary purpose:
NAME DPWM-1A DPWM-1B DPWM-2A DPWM-2B DPWM-3A DPWM-3B DPWM-4A DPWM-4B FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-3B FAULT-4A FAULT-4B SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-3B SRE-4A SRE-4B POWER_GOOD FAN_TACH FAN_PWM DIAG_LED 80-PIN IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT
64-PIN IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT
FAN_PWM Diag_LED pins outputs when configured their primary purpose. When configured sequencing, they used only inputs.
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Control
UCD9240 control defined PMBus standard. When enabled, FAN-PWM control output provides digital signal, with duty cycle that based FAN_COMMAND_1 PMBus command. duty cycle from 100% with resolution. FAN-TACH input counts number transitions tachometer output from each second interval. speed read issuing READ_FAN_SPEED_1 command. speed returned RPMs. Different fans output from four tachometer pulses revolution. FAN_CONFIG_1_2 command used number tachometer pulses revolution. same command used indicate whether attached. UCD9240 report speed faults when speed slow consecutive seconds. speed fault limit FAN_SPEED_FAULT_LIMIT command. status checked issuing STATUS_FAN_1_2 command. UCD92xx PMBUS Command Reference complete description each command.
33k2
FAN-PWM FAN-TACH
0.1u
3.3V
TS321 TIP31A
10k0
Figure Example Control Circuit
Non-volatile Memory Error Correction Coding
UCD9240 uses Error Correcting Code (ECC) improve data integrity provide high reliability storage Data Flash contents. uses dedicated hardware generate extra check bits user data written into Flash memory. This adds additional bits each 32-bit memory word stored into Flash array. These extra check bits, along with hardware algorithm, allow single error detected corrected when Data Flash read.
APPLICATION INFORMATION Calculation Open Loop Gain Using UCD9240
When designing power supply necessary determine stability closed loop system. usual this determine open loop gain versus frequency from open loop gain determine gain margin phase margin. Figure shows block diagram complete control loop using UDC9240. Each component loop gain that function frequency labeled "Gx". Constant gain components labeled "Kx".
CONSTANT GAIN COMPONENTS Gplant Gdiv KAFE KEADC DESCRIPTION Transfer function power stage circuit consisting switches, output filter load. Transfer function VOUT sense divider capacitive filter network. Analog fron-end amplifier gain. Gain 6-bit EADC units LSBs/V
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CONSTANT GAIN COMPONENTS Gdelay Knonlinear GCLA2 GCLA1 KPWM
DESCRIPTION Phase shift delays control loop. Nonlinear function gain. Gain limit interval that contains zero error. Transfer function second order filter section compensator. Transfer function first order filter section compensator. Accounts resolution input DPWM
Gplant(f) Gdiv(f) Vout
Power Stage PMBus
divider
KPWM GCLA1 GCLA2
UCD9240
Gdelay
VrefDAC KEADC KAFE
Knonlinear
Figure Loop Gain Contributions Several gain blocks programmable. They configured issuing CLA_GAINS command over PMBus. syntax this command shown UCD92xx PMBUS Command Reference. These gains also configured using Fusion Digital PowerDesigner program.
Automatic System Identification (Auto-IDTM)
using digital circuits create control function switch-mode power supply, additional features implemented. those features measurement open loop gain stability margin power supply without external test equipment. This capability called automatic system identification Auto-IDTM. identify frequency response, UCD9240 internally synthesizes sine wave signal injects into loop point DAC. This signal excites system, closed-loop response that excitation measured another point loop. UCD9240 measures response excitation output digital compensator. From closed-loop response, open-loop transfer function calculated. open-loop transfer function calculated from closed-loop response. Note that since compensator DPWM digital, their transfer functions known exactly divided measured open-loop gain. this UCD9240 accurately measure power stage/load plant transfer function situ place), factory floor equipment application send measurement data back host through PMBus interface without need external test equipment. Details Auto-IDPMBus measurement commands found UCD92xx PMBus Command Reference.
EAp/EAn Voltage Sense Filtering
Conditioning should provided signals. Figure shows divider network between output voltage voltage sense input controller. resistor divider used bring output voltage within dynamic range controller. When attenuation needed, left open signal conditioned low-pass filter formed
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divider
Vout
Power Stage
Figure EAp/EAn Input Network with power supply system, maximize accuracy output voltage sensing voltage directly across output capacitor, route positive negative differential sense signals balanced pair traces twisted pair cable back controller. divider network close controller. This ensures that there impedance driving differential voltage sense signal from voltage rail output back controller. resistance divider network trade-off between power loss minimizing interference susceptibility. parallel resistance good compromise.
where VOUT
recommended that capacitor placed across lower resistor divider network. This acts additional pole compensation anti-alias filter EADC. effective anti-alias filter, corner frequency should switching frequency. Then capacitor calculated 0.35
Current Sense Input FIltering
Each power stage current monitored device pins. There channel pins channel pins package). channels monitor current with 12-bit samples each current sense voltage turn. channels monitor current with same12-bit also monitor current with digitally programmable analog comparator. Because current sense signal digitally sampled, should conditioned with network acting anti-alias filter. Since sample rate inputs TIout, good cutoff frequency network from kHz.
Output Voltage Margining
UCD9240 supports Voltage Margining using PMBus VOUT_MARGIN_HIGH VOUT_MARGIN_LOW commands conjunction with OPERATION command. margin voltages configured device configuration saved into Data Flash. output commanded switch between Margin High, Nominal, Margin using bits [3:2] OPERATION command.
Calibration
optimize operation UCD9240, PMBus commands supplied enable fine calibration output voltage, output current, temperature measurements. supported commands related calibration formulas found UCD92xx PMBUS Command Reference.
Data Logging
UCD9240 maintains data non-volatile memory. This tracks peak internal external temperature measurements, peak current measurements, fault history. PMBus commands data format data logging found UCD92xx PMBUS Command Reference (SLUU337)
Submit Documentation Feedback Product Folder Link(s): UCD9240
Copyright 2008, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
13-Nov-2008
PACKAGING INFORMATION
Orderable Device UCD9240PFC UCD9240PFCG4 UCD9240PFCR UCD9240PFCRG4 UCD9240RGCR UCD9240RGCT
Status ACTIVE ACTIVE ACTIVE ACTIVE PREVIEW PREVIEW
Package Type TQFP TQFP TQFP TQFP VQFN VQFN
Package Drawing
Pins Package Plan Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU Call Call
Peak Temp Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Call Call
1000 Green (RoHS Sb/Br) 1000 Green (RoHS Sb/Br) 2000
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Oct-2008
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing TQFP
Reel Reel Diameter Width (mm) (mm) 330.0 24.4
(mm)
(mm)
(mm)
(mm) 20.0
Pin1 (mm) Quadrant 24.0
UCD9240PFCR
1000
15.0
15.0
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Oct-2008
*All dimensions nominal
Device UCD9240PFCR
Package Type TQFP
Package Drawing
Pins
1000
Length (mm) 346.0
Width (mm) 346.0
Height (mm) 41.0
Pack Materials-Page
MECHANICAL DATA
MTQF009A OCTOBER 1994 REVISED DECEMBER 1996
(S-PQFP-G80)
0,27 0,17
PLASTIC QUAD FLATPACK
0,50
0,08
0,13
9,50 12,20 11,80 14,20 13,80 1,05 0,95
Gage Plane 0,25 0,05 0,75 0,45 Seating Plane
1,20
0,08 4073177 11/96
NOTES: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026
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