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20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH FEATURES Audi


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TAS5707
20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH
FEATURES
Audio Input/Output 20-W Into Load From 18-V Supply Wide PVDD Range, From Efficient Class-D Operation Eliminates Need Heatsinks Requires Only PVDD Serial Audio Input (Two Audio Channels) Supports 8-kHz 48-kHz Sample Rate (LJ/RJ/I2S) Audio/PWM Processing Independent Channel Volume Controls With 24-dB Mute Soft Mute (50% Duty Cycle) Programmable Dynamic Range Control Programmable Biquads Speaker Other Audio Processing Features Programmable Coefficients Filters Blocking Filters General Features Serial Control Interface Operational Without MCLK Factory-Trimmed Internal Oscillator automatic rate detection Surface Mount, 48-PIN, 7-mm 7-mm HTQFP Package Thermal Short-Circuit Protection Benefits Speaker Equalization Improves Audio Performance DRC: Dynamic Range Compression. Used Power Limiter. Enables Speaker Protection, Easy Listening, Night-Mode Listening. Autobank Switching: Preload Coefficients Different Sample Rates. Need Write Coefficients Part When Sample Rate Changes. Autodetect: Automatically Detects Sample-Rate Changes. Need External Microprocessor Intervention
DESCRIPTION
TAS5707 20-W, efficient, digital audio power amplifier driving stereo bridge-tied speakers. serial data input allows processing discrete audio channels seamless integration most digital audio processors MPEG decoders. device accepts wide range input data data rates. fully programmable data path routes these channels internal speaker drivers. TAS5707 slave-only device receiving clocks from external sources. TAS5707 operates with carrier between 384-kHz switching rate 352-KHz switching rate depending input sample rate. Oversampling combined with fourth-order noise shaper provides flat noise floor excellent dynamic range from kHz.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
SIMPLIFIED APPLICATION DIAGRAM
V-24
AVDD/DVDD
PVDD
OUT_A LRCLK Digital Audio Source SCLK MCLK SDIN BST_B BST_A Left
OUT_B
Control
OUT_C
BST_C Control Inputs RESET OUT_D BST_D Right
PLL_FLTP
Loop Filter* PLL_FLB0264-03
*Refer user's guide Loop Filter details.
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TAS5707
FUNCTIONAL VIEW
Serial Audio Port
Order Noise Shaper
OUT_A OUT_B
SDIN
OUT_C OUT_D
mDAP Protection Logic MCLK SCLK LRCLK Sample Rate Autodetect Microcontroller Based System Control Click Control
Serial Control
Terminal Control
B0262-02
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FAULT FAULT Undervoltage Protection
Protection Logic
Power Reset
AGND
Temp. Sense VALID Overcurrent Protection Isense
OC_ADJ
BST_D PVDD_D PWM_D Ctrl Timing Gate Drive
Pulldown Resistor
OUT_D
Controller
GVDD_CD Regulator
PGND_CD GVDD_CD BST_C PVDD_C
PWM_C
Ctrl
Timing
Gate Drive
Pulldown Resistor
OUT_C
PGND_CD
BST_B PVDD_B PWM_B Ctrl Timing Gate Drive
Pulldown Resistor
OUT_B
GVDD_AB Regulator
PGND_AB GVDD_AB BST_A PVDD_A
PWM_A
Ctrl
Timing
Gate Drive
Pulldown Resistor
OUT_A
PGND_AB
B0034-05
Figure Power Stage Functional Block Diagram
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TAS5707
Process Structure
B0341-0
3B-3C
numbers refer subaddresses [Di] subaddress
Energy MAXMUX
ealpha
Attack DRC1 Decay
46[D0]
ealpha
29-2F
Input Muxing
50[D7]
30-36
Vol2
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48-TERMINAL, HTQFP PACKAGE (TOP VIEW)
Package (Top View)
PGND_CD
PVDD_C
OUT_A PVDD_A PVDD_A BST_A GVDD_OUT SSTIMER OC_ADJ TAS5707 OUT_D PVDD_D PVDD_D BST_D GVDD_OUT VREG AGND DVSS DVDD STEST RESET
AVSS PLL_FLPLL_FLTP
VR_ANA
LRCLK
FAULT MCLK
VR_DIG
SDIN
OSC_RES
DVSSO
AVDD
SCLK
PGND_CD
PGND_AB
PGND_AB
PVDD_B
PVDD_C
PVDD_B
OUT_B
OUT_C
BST_C
BST_B
P0075-0
FUNCTIONS
NAME AGND AVDD AVSS BST_A BST_B BST_C BST_D DVDD DVSSO DVSS GVDD_OUT LRCLK MCLK TYPE
TOLERANT
TERMINATION
DESCRIPTION Analog ground power stage 3.3-V analog power supply Analog 3.3-V supply ground High-side bootstrap supply half-bridge High-side bootstrap supply half-bridge High-side bootstrap supply half-bridge High-side bootstrap supply half-bridge 3.3-V digital power supply Oscillator ground Digital ground Analog ground power stage Gate drive internal regulator output
Pulldown Pulldown
Input serial audio data left/right clock (sample rate clock) Master clock input
TYPE: analog; 3.3-V digital; power/ground/decoupling; input; output pullups weak pullups pulldowns weak pulldowns. pullups pulldowns included assure proper input logic levels pins left unconnected (pullups logic input; pulldowns logic input). Submit Documentation Feedback Product Folder Link(s): TAS5707
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TAS5707
FUNCTIONS (continued)
NAME OC_ADJ OSC_RES OUT_A OUT_B OUT_C OUT_D TYPE
TOLERANT
TERMINATION
DESCRIPTION connection Analog overcurrent programming. Requires resistor ground. Oscillator trim resistor. Connect 18.2-k resistor DVSSO. Output, half-bridge Output, half-bridge Output, half-bridge Output, half-bridge
Pullup
Power down, active-low. prepares device loss power supplies shutting down Noise Shaper initiating stop sequence. Power ground half-bridges Power ground half-bridges negative loop filter terminal positive loop filter terminal Power supply input half-bridge output Power supply input half-bridge output Power supply input half-bridge output Power supply input half-bridge output
PGND_AB PGND_CD PLL_FLPLL_FLTP PVDD_A PVDD_B PVDD_C PVDD_D RESET
Pullup
Reset, active-low. system reset generated applying logic this pin. RESET asynchronous control signal that restores default conditions, places hard mute state (tristated). serial control clock input Serial audio data clock (shift clock). SCLK serial audio port input data clock. serial control data interface input/output Serial audio data input. SDIN supports three discrete (stereo) data formats. Controls ramp time OUT_X minimize pop. Leave this floating mode. Requires capacitor mode. capacitor determines ramp time. Factory test pin. Connect directly DVSS. Backend error indicator. Asserted over temperature, over current, over voltage, under voltage error conditions. De-asserted upon recovery from error condition. Internally regulated 1.8-V analog supply voltage. This must used power external devices. Internally regulated 1.8-V digital supply voltage. This must used power external devices. Digital regulator output. used powering external circuitry.
SCLK SDIN SSTIMER
Pulldown Pulldown
STEST FAULT
VR_ANA VR_DIG VREG
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
DVDD, AVDD PVDD_X OC_ADJ Input voltage 3.3-V digital input tolerant digital input (except MCLK) tolerant MCLK input OUT_x PGND_X BST_x PGND_X Input clamp current, Output clamp current, Operating free-air temperature Operating junction temperature range Storage temperature range, Tstg
VALUE Supply voltage -0.3 -0.3 -0.3 -0.5 DVDD -0.5 DVDD -0.5 AVDD
UNIT
Stresses beyond those listed under absolute ratings cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under recommended operation conditions implied. Exposure absolute-maximum conditions extended periods affect device reliability. tolerant inputs PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, SCL. Maximum voltage should exceed 6.0Vele voltage peak waveform measured should below allowed limit conditions.
DISSIPATION RATINGS
PACKAGE 7-mm 7-mm HTQFP DERATING FACTOR ABOVE 25°C mW/°C 25°C POWER RATING 45°C POWER RATING 70°C POWER RATING
This data taken using trace copper that soldered directly JEDEC standard high-k PCB. thermal must soldered thermal land printed-circuit board. Technical Briefs SLMA002 more information about using HTQFP thermal
RECOMMENDED OPERATING CONDITIONS
Digital/analog supply voltage Half-bridge supply voltage
UNIT
DVDD, AVDD PVDD_X tolerant tolerant
High-level input voltage Low-level input voltage Operating ambient temperature range Operating junction temperature range Load impedance Output-filter inductance
(BTL) (BTL)
Output filter: Minimum output inductance under short-circuit condition
Continuous operation above recommended junction temperature result reduced reliability and/or lifetime device.
OPERATION RECOMMENDED OPERATING CONDITIONS
PARAMETER Output sample rate TEST CONDITIONS 11.025/22.05/44.1-kHz data rate 48/24/12/8/16/32-kHz data rate VALUE 352.8 UNIT
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INPUT PARAMETERS EXTERNAL FILTER COMPONENTS
PARAMETER fMCLKI tf(MCLK) MCLK Frequency MCLK duty cycle Rise/fall time MCLK LRCLK allowable drift before LRCLK reset External filter capacitor External filter capacitor External filter resistor 0603 0603 0603, metal film TEST CONDITIONS 2.8224 24.576 MCLKs UNIT
ELECTRICAL CHARACTERISTICS Characteristics
25°, PVCC_X 18V, DVDD AVDD 3.3V, Mode, 48KHz (unless otherwise noted)
PARAMETER High-level output voltage Low-level output voltage Low-level input current High-level input current supply voltage (DVDD, AVDD) FAULTZ FAULTZ TEST CONDITIONS DVDD DVDD DVDD AVDD 3.6V DVDD AVDD 3.6V Normal Mode Reset (RESET low, high) Normal Mode IPVDD Half-bridge supply current load (PVDD_X) Reset (RESET low, high) UNIT
supply current
Drain-to-source resistance, 25°C, includes metallization resistance rDS(on) Drain-to-source resistance, Undervoltage protection limit Undervoltage protection limit Overtemperature error Extra temperature drop required recover from error Overload protection counter Overcurrent limit protection Overcurrent response time programming resistor range Internal pulldown resistor output each half-bridge Resistor tolerance typical value; minimum resistance should less than Connected when drivers tristated provide bootstrap capacitor charge. fPWM Resistor-programmable, max. current, ROCP 25°C, includes metallization resistance
Protection Vuvp Vuvp,hyst OTEHYST OLPC IOCT ROCP PVDD falling PVDD rising 1.25
This does include bond-wire resistance. Specified design
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Characteristics (BTL)
PVDD_X mode, KHz, ROCP CBST audio frequency kHz, AES17 filter, fPWM kHz, 25°C (unless otherwise noted). performance accordance with recommended operating conditions, unless otherwise specified.
PARAMETER TEST CONDITIONS PVDD V,10% THD, 1-kHz input signal PVDD THD, 1-kHz input signal Power output channel PVDD THD, 1-kHz input signal PVDD THD, 1-kHz input signal PVDD THD, 1-kHz input signal PVDD THD, 1-kHz input signal PVDD= THD+N Total harmonic distortion noise Output integrated noise (rms) Crosstalk Signal-to-noise ratio
20.6 19.5 0.06% 0.13% 0.2%
UNIT
PVDD= PVDD= A-weighted 0.25 1kHz Mode) 0.25 1kHz Mode) A-weighted, kHz, maximum power
calculated relative 0-dBFS input level.
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SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
PARAMETER fSCLKIN tsu1 tsu2 Frequency, SCLK Setup time, LRCLK SCLK rising edge Hold time, LRCLK from SCLK rising edge Setup time, SDIN SCLK rising edge Hold time, SDIN from SCLK rising edge LRCLK frequency SCLK duty cycle LRCLK duty cycle SCLK rising edges between LRCLK rising edges t(edge) tf(SCLK/LRCLK) LRCLK clock edge with respect falling edge SCLK Rise/fall time SCLK/LRCLK
SCLK (Input) t(edge) tsu1 LRCLK (Input) tsu2 SDIN
T0026-04
TEST CONDITIONS
1.024 -1/4
12.288
UNIT
SCLK edges SCLK period
Figure Slave Mode Serial Data Interface Timing
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SERIAL CONTROL PORT OPERATION
Timing characteristics Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER fSCL tw(H) tw(L) tsu1 t(buf) tsu2 tsu3 Frequency, Pulse duration, high Pulse duration, Rise time, Fall time, Setup time, Hold time, free time between stop start condition Setup time, start condition Hold time, start condition Setup time, stop condition Load capacitance each line
tw(H) tw(L)
TEST CONDITIONS wait states
UNIT
tsu1
T0027-0
Figure Timing
tsu2 tsu3
t(buf)
Start Condition
Stop Condition
T0028-0
Figure Start Stop Conditions Timing
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RESET TIMING (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer Recommended Model section usage terminals.
PARAMETER tw(RESET) td(I2C_ready) Pulse duration, RESET active Time enable 13.5 UNIT
RESET
tw(RESET)
Active td(I2C_ready)
Active
System Initialization. Enable
T0421-0
NOTE: power recommended that TAS5707 RESET held least after DVDD reached NOTE: RESET asserted while LOW, then RESET must continue held least after deasserted (HIGH).
Figure Reset Timing
TYPICAL CHARACTERISTICS, CONFIGURATION
TOTAL HARMONIC DISTORTION NOISE FREQUENCY
TOTAL HARMONIC DISTORTION NOISE FREQUENCY
THD+N Total Harmonic Distortion Noise PVDD
THD+N Total Harmonic Distortion Noise
PVDD P=5W
P=1W
0.001
Frequency
0.001
Frequency
G002
Figure
Figure
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TYPICAL CHARACTERISTICS, CONFIGURATION (continued)
TOTAL HARMONIC DISTORTION NOISE FREQUENCY
THD+N Total Harmonic Distortion Noise PVDD THD+N Total Harmonic Distortion Noise PVDD
TOTAL HARMONIC DISTORTION NOISE OUTPUT POWER
P=1W
0.001 0.01
G004
0.001
Frequency
G003
Output Power
Figure TOTAL HARMONIC DISTORTION NOISE OUTPUT POWER
THD+N Total Harmonic Distortion Noise PVDD THD+N Total Harmonic Distortion Noise PVDD
Figure TOTAL HARMONIC DISTORTION NOISE OUTPUT POWER
0.001 0.01
G005
0.001
G006
Output Power
Output Power
Figure
Figure
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TYPICAL CHARACTERISTICS, CONFIGURATION (continued)
OUTPUT POWER SUPPLY VOLTAGE
Output Power THD+N
G010
EFFICIENCY OUTPUT POWER
PVDD THD+N Efficiency
G012
PVDD PVDD
PVDD Supply Voltage
Output Power (Per Channel)
Figure CROSSTALK FREQUENCY
Crosstalk Right Left Left Right -100 -100 Crosstalk 0.25 PVDD 0.25 PVDD
Figure CROSSTALK FREQUENCY
Right Left
Left Right
Frequency
G013
Frequency
G014
Figure
Figure
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TYPICAL CHARACTERISTICS, CONFIGURATION (continued)
CROSSTALK FREQUENCY
Crosstalk Left Right -100 Right Left 0.25 PVDD
Frequency
G015
Figure
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TAS5707
DETAILED DESCRIPTION POWER SUPPLY
facilitate system design, TAS5707 needs only 3.3-V supply addition (typical) 18-V power-stage supply. internal voltage regulator provides suitable voltage levels gate drive circuitry. Additionally, circuitry requiring floating voltage supply, e.g., high-side gate drive, accommodated built-in bootstrap circuitry requiring only external capacitors. order provide good electrical acoustical characteristics, signal path output stage designed identical, independent half-bridges. this reason, each half-bridge separate bootstrap pins (BST_X), power-stage supply pins (PVDD_X). gate drive voltages (GVDD_AB GVDD_CD) derived from PVDD voltage. Special attention should paid placing decoupling capacitors close their associated pins possible. general, inductance between power-supply pins decoupling capacitors must avoided. properly functioning bootstrap circuit, small ceramic capacitor must connected from each bootstrap (BST_X) power-stage output (OUT_X). When power-stage output low, bootstrap capacitor charged through internal diode connected between gate-drive regulator output (GVDD_X) bootstrap pin. When power-stage output high, bootstrap capacitor potential shifted above output potential thus provides suitable voltage supply high-side gate driver. application with switching frequencies range from kHz, recommended 33-nF ceramic capacitors, size 0603 0805, bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal duty cycles, keep high-side power stage (LDMOS) fully turned during remaining part cycle. Special attention should paid power-stage power supply; this includes component selection, placement, routing. indicated, each half-bridge independent power-stage supply pins (PVDD_X). optimal electrical performance, compliance, system reliability, important that each PVDD_X decoupled with 100-nF ceramic capacitor placed close possible each supply pin. TAS5707 fully protected against erroneous power-stage turnon parasitic gate charging.
ERROR REPORTING
fault resulting device shutdown signaled FAULT going (see Table sticky version this available register 0X02. Table FAULT Output States
FAULT DESCRIPTION Overcurrent (OC) undervoltage (UVP) error overtemperature error (OTE) over voltage ERROR faults (normal operation)
DEVICE PROTECTION SYSTEM
Overcurrent (OC) Protection With Current Limiting device independent, fast-reacting current detectors high-side low-side power-stage FETs. detector outputs closely monitored protection systems. first protection system controls power stage order prevent output current further increasing, i.e., performs cycle-by-cycle current-limiting function, rather than prematurely shutting down during combinations high-level music transients extreme speaker load impedance drops. high-current condition situation persists, i.e., power stage being overloaded, second protection system triggers latching shutdown, resulting power stage being high-impedance (Hi-Z) state. device returns normal operation once fault condition (i.e., short circuit output) removed. Current limiting overcurrent protection independent half-bridges. That bridge-tied load between half-bridges causes overcurrent fault, half-bridges shut down.
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Overtemperature Protection TAS5707 over temperature-protection system. device junction temperature exceeds 150°C (nominal), device into thermal shutdown, resulting half-bridge outputs being high-impedance (Hi-Z) state FAULT being asserted low. TAS5707 recovers automatically once temperature drops approximately 30°. Undervoltage Protection (UVP) Power-On Reset (POR) circuits TAS5707 fully protect device power-up/down brownout situation. While powering circuit resets overload circuit (OLP) ensures that circuits fully operational when PVDD AVDD supply voltages reach respectively. Although PVDD AVDD independently monitored, supply voltage drop below threshold AVDD either PVDD results half-bridge outputs immediately being high-impedance (Hi-Z) state FAULT being asserted low.
SSTIMER FUNCTIONALITY
SSTIMER uses capacitor connected between this ground control output duty cycle when exiting all-channel shutdown. capacitor SSTIMER slowly charged through internal current source, charge time determines rate which output transitions from near zero duty cycle desired duty cycle. This allows smooth transition that minimizes audible pops clicks. When part shutdown drivers tristated transition slowly down through resistor, similarly minimizing pops clicks. shutdown transition time independent SSTIMER capacitance. Larger capacitors will increase start-up time, while capacitors smaller than will decrease start-up time. SSTIMER should left floating modulation.
CLOCK, AUTO DETECTION,
TAS5707 slave device. accepts MCLK, SCLK, LRCLK. digital audio processor (DAP) supports sample rates MCLK rates that defined clock control register. TAS5707 checks verify that SCLK specific value only supports LRCLK. timing relationship these clocks SDIN shown subsequent sections. clock section uses MCLK internal oscillator clock (when MCLK unstable, range, absent) produce internal clock (DCLK) running time switching frequency. autodetect internal clock control logic appropriate settings supported clock rates defined clock control register. TAS5707 robust clock error handling that uses bulit-in trimmed oscillator clock quickly detect changes/errors. Once system detects clock change/error, will mute audio (through single step mute) then force limp using internal oscillator reference clock. Once clocks stable, system will auto detect rate revert normal operation. During this process, default volume will restored single step (also called hard unmute). ramp process programmed ramp back slowly (also called soft unmute) defined volume register (0X0E).
SERIAL DATA INTERFACE
Serial data input SDIN. outputs derived from SDIN. TAS5707 accepts serial data 16-, 20-, 24-bit left-justified, right-justified, serial data formats.
Section
TAS5707 device uses noise-shaping sophisticated non-linear correction algorithms achieve high power efficiency high-performance digital audio reproduction. uses fourth-order noise shaper increase dynamic range audio band. section accepts 24-bit data from outputs audio output channels. section individual channel blocking filters that enabled disabled. filter cutoff frequency less than Individual channel de-emphasis filters 44.1- 48-kHz included enabled disabled.
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Finally, section adjustable maximum modulation limit 93.8% 99.2%. detailed description using audio processing features like please refer User's Guide TAS570X software development tool documentation. Also refer software development tool device data path.
COMPATIBLE SERIAL CONTROL INTERFACE
TAS5707 serial control slave interface receive commands from system controller. serial control interface supports both normal-speed (100-kHz) high-speed (400-kHz) operations without wait states. added feature, this interface operates even MCLK absent. serial control interface supports both single-byte multi-byte read write operations status registers general control registers associated with PWM.
SERIAL INTERFACE CONTROL TIMING
Timing timing uses LRCLK define when data being transmitted left channel when right channel. LRCLK left channel high right channel. clock running used clock data. There delay clock from time LRCLK signal changes state first data data lines. data written first valid rising edge clock. masks unused trailing data positions.
2-Channel (Philips Format) Stereo Input Clks Clks
LRCLK (Note Reversed Phase)
Left Channel
Right Channel
SCLK
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0034-0
NOTE: data presented 2s-complement form with first.
Figure 64-fS Format
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2-Channel (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size) Clks Clks
LRCLK
Left Channel
Right Channel
SCLK
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0092-0
NOTE: data presented 2s-complement form with first.
Figure 48-fS Format
2-Channel (Philips Format) Stereo Input Clks Clks
LRCLK
Left Channel
Right Channel
SCLK
SCLK
16-Bit Mode
T0266-0
NOTE: data presented 2s-complement form with first.
Figure 32-fS Format
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Left-Justified Left-justified (LJ) timing uses LRCLK define when data being transmitted left channel when right channel. LRCLK high left channel right channel. clock running used clock data. first data appears data lines same time LRCLK toggles. data written first valid rising edge clock. masks unused trailing data positions.
2-Channel Left-Justified Stereo Input Clks LRCLK Left Channel Right Channel Clks
SCLK
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0034-02
NOTE: data presented 2s-complement form with first.
Figure Left-Justified 64-fS Format
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2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size) Clks LRCLK Left Channel Right Channel Clks
SCLK
SCLK
24-Bit Mode
20-Bit Mode 16-Bit Mode
T0092-02
NOTE: data presented 2s-complement form with first.
Figure Left-Justified 48-fS Format
2-Channel Left-Justified Stereo Input Clks LRCLK Left Channel Right Channel Clks
SCLK
SCLK
16-Bit Mode
T0266-02
NOTE: data presented 2s-complement form with first.
Figure Left-Justified 32-fS Format
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Right-Justified Right-justified (RJ) timing uses LRCLK define when data being transmitted left channel when right channel. LRCLK high left channel right channel. clock running used clock data. first data appears data bit-clock periods (for 24-bit data) after LRCLK toggles. mode data always clocked last clock before LRCLK transitions. data written first valid rising edge clock. masks unused leading data positions.
2-Channel Right-Justified (Sony Format) Stereo Input Clks LRCLK Left Channel Right Channel Clks
SCLK
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0034-03
Figure Right Justified 64-fS Format
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2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size) Clks LRCLK Left Channel Right Channel Clks
SCLK
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0092-03
Figure Right Justified 48-fS Format
Figure Right Justified 32-fS Format
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SERIAL CONTROL INTERFACE
TAS5707 bidirectional interface that compatible with (Inter protocol supports both 100-kHz 400-kHz data transfer rates single multiple byte write read operations. This slave only device that does support multimaster environment wait state insertion. control interface used program registers device read device status. supports standard-mode operation (100 maximum) fast operation (400 maximum). performs operations without wait cycles. General Operation employs signals; (data) (clock), communicate between integrated circuits system. Data transferred serially time. address data transferred byte (8-bit) format, with most significant (MSB) transferred first. addition, each byte transferred acknowledged receiving device with acknowledge bit. Each transfer operation begins with master device driving start condition ends with master device driving stop condition bus. uses transitions data (SDA) while clock high indicate start stop conditions. high-to-low transition indicates start low-to-high transition indicates stop. Normal data transitions must occur within time clock period. These conditions shown Figure master generates 7-bit slave address read/write (R/W) open communication with another device then waits acknowledge condition. TAS5707 holds during acknowledge clock period indicate acknowledgment. When this occurs, master transmits next byte sequence. Each device addressed unique 7-bit slave address plus byte). compatible devices share same signals bidirectional using wired-AND connection. external pullup resistor must used signals high level bus.
8-Bit Register Data Address 8-Bit Register Data Address
7-Bit Slave Address
8-Bit Register Address
Start
Stop
T0035-0
Figure Typical Sequence There limit number bytes that transmitted between start stop conditions. When last word transfers, master generates stop condition release bus. generic data transfer sequence shown Figure 7-bit address TAS5707 0011 (0x36). TAS5707 address changed from 0X36 0X38 writing 0x38 device address register 0XF9. Single- Multiple-Byte Transfers serial control interface supports both single-byte multiple-byte read/write operations subaddresses 0x00 0x1F. However, subaddresses 0x20 0xFF, serial control interface supports only multiple-byte read/write operations multiples bytes). During multiple-byte read operations, responds with data, byte time, starting subaddress assigned, long master device continues respond with acknowledges. particular subaddress does contain bits, unused bits read logic During multiple-byte write operations, compares number bytes transmitted number bytes that required each specific subaddress. example, write command received biquad subaddress, expects receive five 32-bit words. fewer than five 32-bit data words have been received when stop command another start command) received, data received discarded.
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Supplying subaddress each subaddress transaction referred random addressing. TAS5707 also supports sequential addressing. write transactions, subaddress issued followed data that subaddress subaddresses that follow, sequential write transaction taken place, data subaddresses successfully received TAS5707. sequential write transactions, subaddress then serves start address, amount data subsequently transmitted, before stop start transmitted, determines many subaddresses written. true random addressing, sequential addressing requires that complete data transmitted. only partial data written last subaddress, data last subaddress discarded. However, other data written accepted; only incomplete data discarded. Single-Byte Write shown Figure single-byte data write transfer begins with master device transmitting start condition followed device address read/write bit. read/write determines direction data transfer. write data transfer, read/write will After receiving correct device address read/write bit, responds with acknowledge bit. Next, master transmits address byte bytes corresponding TAS5707 internal memory address being accessed. After receiving address byte, TAS5707 again responds with acknowledge bit. Next, master device transmits data byte written memory address being accessed. After receiving data byte, TAS5707 again responds with acknowledge bit. Finally, master device transmits stop condition complete single-byte data write transfer.
Start Condition Acknowledge Acknowledge Acknowledge
Device Address Read/Write
Subaddress
Data Byte
Stop Condition
T0036-0
Figure Single-Byte Write Transfer Multiple-Byte Write multiple-byte data write transfer identical single-byte data write transfer except that multiple data bytes transmitted master device shown Figure After receiving each data byte, TAS5707 responds with acknowledge bit.
Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
Device Address Read/Write
Subaddress
First Data Byte
Other Data Bytes
Last Data Byte
Stop Condition
T0036-02
Figure Multiple-Byte Write Transfer
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TAS5707
Single-Byte Read shown Figure single-byte data read transfer begins with master device transmitting start condition followed device address read/write bit. data read transfer, both write followed read actually done. Initially, write done transfer address byte bytes internal memory address read. result, read/write becomes After receiving TAS5707 address read/write bit, TAS5707 responds with acknowledge bit. addition, after sending internal memory address byte bytes, master device transmits another start condition followed TAS5707 address read/write again. This time read/write becomes indicating read transfer. After receiving address read/write bit, TAS5707 again responds with acknowledge bit. Next, TAS5707 transmits data byte from memory address being read. After receiving data byte, master device transmits acknowledge followed stop condition complete single byte data read transfer.
Start Condition Repeat Start Condition Acknowledge Acknowledge Acknowledge Acknowledge
Device Address Read/Write
Subaddress
Device Address Read/Write
Data Byte
Stop Condition
T0036-03
Figure Single-Byte Read Transfer Multiple-Byte Read multiple-byte data read transfer identical single-byte data read transfer except that multiple data bytes transmitted TAS5707 master device shown Figure Except last data byte, master device responds with acknowledge after receiving each data byte.
Start Condition Repeat Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
Device Address Read/Write
Subaddress
Device Address Read/Write
First Data Byte
Other Data Bytes
Last Data Byte
Stop Condition
T0036-04
Figure Multiple Byte Read Transfer
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Dynamic Range Control (DRC)
scheme single threshold, offset, slope (all programmable). There ganged left/right channels. input/output diagram shown Figure
Output Level (dB)
Transfer Function Implemented Transfer Function
Input Level (dB)
M0091-02
Professional-quality dynamic range compression automatically adjusts volume flatten volume level. left/right adjustable threshold, offset, compression levels Programmable energy, attack, decay time constants Transparent compression: compressors attack fast enough avoid apparent clipping before engaging, decay times slow enough avoid pumping.
Figure Dynamic Range Control
Audio Input
Energy Filter
Compression Control
Attack Decay Filters
Coefficient
0x3A
0x40, 0x41, 0x42
0x3B 0x3C
Alpha Filter Structure
NOTE: w=1-a
B0265-0
Figure Structure
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TAS5707
BANK SWITCHING
TAS5707 uses approach called bank switching together with automatic sample-rate detection. processing features that must changed different sample rates stored internally three banks. user program which sample rates each bank. default, bank used 32kHz mode, bank used 44.1/48 mode, bank used other rates. Combined with clock-rate autodetection feature, bank switching allows TAS5707 detect automatically change input sample rate switch appropriate bank without intervention. external controller configures bankable locations (0x29-0x36 0x3A-0x3C) three banks during initialization sequence. auto bank switching enabled (register 0x50, bits 2:0) then TAS5707 automatically swaps coefficients subsequent sample rate changes, avoiding need external controller intervention sample rate change. default, bits have value 000; indicating that bank switching disabled. that state, updates bankable locations take immediate effect. write register 0x50 with bits being 001, 010, brings system into coefficient-bank-update state update bank1, update bank2, update bank3, respectively. subsequent write bankable locations updates coefficient banks stored outside DAP. After updating three banks, system controller should issue write register 0x50 with bits being 100; this changes system state automatic bank switching mode. automatic bank switching mode, TAS5707 automatically swaps banks based sample rate.
Command sequences updating coefficients summarized follows: Bank switching disabled (default): coefficient writes take immediate effect influenced subsequent sample rate changes. Bank switching enabled: Update bank-1 mode: Write "001" bits 0x50. Load coefficients. Update bank-2 mode: Write "010" bits 0x50. Load coefficients. Update bank-3 mode: Write "011" bits 0x50. Load other coefficients. Enable automatic bank switching writing "100" bits 0x50.
26-Bit 3.23 Number Format
mixer gain coefficients 26-bit coefficients using 3.23 number format. Numbers formatted 3.23 numbers means that there bits left decimal point bits right decimal point. This shown Figure
Sign
M0125-0
Figure 3.23 Format
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decimal value 3.23 format number found following weighting shown Figure most significant logic number positive number, weighting shown yields correct number. most significant logic then number negative number. this case every must inverted, added result, then weighting shown Figure applied obtain magnitude negative number.
M0126-0
Figure Conversion Weighting Factors-3.23 Format Floating Point Gain coefficients, entered bus, must entered 32-bit binary numbers. format 32-bit number (4-byte 8-digit hexadecimal number) shown Figure
Sign Fraction Digit Fraction Digit Fraction Digit Fraction Digit Fraction Digit Fraction Digit
Integer Digit
Coefficient Digit
Coefficient Digit
Coefficient Digit
Coefficient Digit
Coefficient Digit
Coefficient Digit
Coefficient Digit
Coefficient Digit
unused don't care bits Digit hexadecimal digit
M0127-0
Figure Alignment 3.23 Coefficient 32-Bit Word Sample calculation 3.23 format
Linear 1.77 0.56 10(X/20) Decimal 8388608 14917288 4717260 8388608 (3.23 Format) 800000 00E39EA8 0047FACC dec2hex
Sample calculation 9.17 format
Linear 1.77 0.56 10(X/20) Decimal 131072 231997 73400 131072 (9.17 Format) 20000 38A3D 11EB8 dec2hex
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Initialization Shutdown
Normal Operation
Powerdown
Recommended Model
AVDD/DVDD
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tPLL tstart Stable Valid Clocks Clock Changes/Errors
MCLK LRCLK SCLK SDIN
Stable Valid Clocks
Trim
tstart
Exit
Config Other Config
Volume Mute Commands
Enter tstop
13.5
Figure Recommended Command Sequence
tPLL
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RESET
PVDD
tPLL greater than tstart. This constraint only applies first trim command following AVDD/DVDD power-up. does apply trim commands following subsequent resets. tstart/tstop start/stop time defined register 0X1A
T0419-0
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AVDD/DVDD
RESET PVDD
T0420-0
Figure Power Loss Sequence Recommended Command Sequences groups commands. configuration intended only during initialization. other built-in click protection used during normal operation while audio streaming. following supported command sequences illustrate initialize, operate, shutdown device. Initialization Sequence following sequence power-up initialize device: Hold digital inputs ramp AVDD/DVDD least Initialize digital inputs PVDD supply follows: Drive RESETZ=0, PDNZ=1, other digital inputs their desired state while ensuring that never more than 2.5V above AVDD/DVDD. Provide stable valid clocks (MCLK, LRCLK, SCLK). Wait least 100us, drive RESETZ=1, wait least another 13.5ms. Ramp PVDD least while ensuring that remains below least 100us after AVDD/DVDD reaches Then wait least another 10us.
Trim oscillator (write 0x00 register 0x1B) wait least 50ms. Configure (see Users's Guide typical values): Biquads (0x29-36) parameters (0x3A-3C, 0x40-42, 0x46) Bank select (0x50)
Configure remaining registers Exit shutdown (sequence defined below).
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TAS5707
Normal Operation following only events supported during normal operation: Writes master/channel volume registers Writes soft mute register Enter exit shutdown (sequence defined below) Clock errors rate changes Note: Events supported 240ms+1.3*Tstart after trim following AVDD/DVDD powerup ramp (where Tstart specified register 0x1A). Shutdown Sequence Enter: Exit: Ensure clocks have been stable valid least 50ms. Write 0x00 register 0x05 (exit shutdown command serviced much 240ms after trim following AVDD/DVDD powerup ramp). Wait least 1ms+1.3*Tstart (where Tstart specified register 0x1A). Proceed with normal operation. Ensure clocks have been stable valid least 50ms. Write 0x40 register 0x05. Wait least 1ms+1.3*Tstop (where Tstop specified register 0x1A). Once shutdown, stable clocks required while device remains idle. desired, reconfigure ensuring that clocks have been stable valid least 50ms before returning step initialization sequence.
Powerdown Sequence following sequence powerdown device supplies: time permits, enter shutdown (sequence defined above); else, case sudden power loss, assert PDNZ=0 wait least 2ms. Assert RESETZ=0. Drive digital inputs ramp down PVDD supply follows: Drive digital inputs after RESETZ been least 2us. Ramp down PVDD while ensuring that remains above until RESETZ been least 2us.
Ramp down AVDD/DVDD while ensuring that remains above until PVDD below that never more than 2.5V below digital inputs.
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Table Serial Control Interface Register Summary
SUBADDRESS REGISTER NAME BYTES Volume configuration register Modulation limit register delay channel delay channel delay channel delay channel Start/stop period register Oscillator trim register BKND_ERR register Input register register ch1_bq[0] CONTENTS indicates unused bits. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0X0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15-0x19 0x1A 0x1B 0x1C 0x1D-0x1F 0x20 0x21-0X24 0x25 0x26-0x28 0x29 Clock control register Device register Error status register System control register Serial data interface register System control register Soft mute register Master volume Channel Channel Fine master volume Description shown subsequent section Description shown subsequent section Description shown subsequent section Description shown subsequent section Description shown subsequent section Description shown subsequent section Description shown subsequent section Description shown subsequent section Description shown subsequent section Description shown subsequent section Description shown subsequent section Reserved
INITIALIZATION VALUE 0x6C 0x70 0x00 0xA0 0x05 0x40 0x00 0xFF (mute) 0x30 0x30 0x00
Description shown subsequent section Reserved Description shown subsequent section Description shown subsequent section Description shown subsequent section Description shown subsequent section Description shown subsequent section Reserved Description shown subsequent section Description shown subsequent section Description shown subsequent section Reserved Description shown subsequent section Reserved Description shown subsequent section Reserved
0x02 0xAC 0x54 0xAC 0x54 0x0F 0x82 0x02 0x0001 7772 0x0102 1345 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000
u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0]
0x2A
ch1_bq[1]
u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0]
0x2B
ch1_bq[2]
u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0]
Reserved registers should accessed. Submit Documentation Feedback Product Folder Link(s): TAS5707
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TAS5707
Table Serial Control Interface Register Summary (continued)
SUBADDRESS 0x2C REGISTER NAME ch1_bq[3] BYTES u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] 0x2D ch1_bq[4] u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] 0x2E ch1_bq[5] u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] 0x2F ch1_bq[6] u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] 0x30 ch2_bq[0] u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] 0x31 ch2_bq[1] u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] 0x32 ch2_bq[2] u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] 0x33 ch2_bq[3] u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] 0x34 ch2_bq[4] u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] CONTENTS INITIALIZATION VALUE 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000
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Table Serial Control Interface Register Summary (continued)
SUBADDRESS 0x35 REGISTER NAME ch2_bq[5] BYTES u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] 0x36 ch2_bq[6] u[31:26], b0[25:0] u[31:26], b1[25:0] u[31:26], b2[25:0] u[31:26], a1[25:0] u[31:26], a2[25:0] 0x37 0x39 0x3A 0x3B 0x3C 0x3D-0x3F 0x40 0x41 0x42 0x43-0x45 0x46 0x47-0x4F 0x50 0x51-0xF8 0xF9 0xFA-0xFF Update device address register Bank switch control control DRC-T DRC-K DRC-O Reserved u[31:26], ae[25:0] u[31:26], ae)[25:0] u[31:26], aa[25:0] u[31:26], aa)[25:0] u[31:26], ad[25:0] u[31:26], ad)[25:0] Reserved(2) T[31:0] (9.23 format) u[31:26], K[25:0] u[31:26], O[25:0] Reserved(2) Description shown subsequent section Reserved(2) Description shown subsequent section Reserved
CONTENTS
INITIALIZATION VALUE 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0080 0000 0x0000 0000 0x0080 0000 0x0000 0000 0xFDA2 1490 0x0384 2109 0x0008 4210 0x0000 0000 0x0F70 8000 0x00000036
u[31:8],New Id[7:0] (New 0x38) Reserved(2)
Reserved registers should accessed. "ae" stands energy filter, "aa" stands attack filter "ad" stands decay filter
coefficients 3.23 format unless specified otherwise.
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TAS5707
CLOCK CONTROL REGISTER (0x00)
clocks data rates automatically determined TAS5707. clock control register contains auto-detected clock status. Bits D7-D5 reflect sample rate. Bits D4-D2 reflect MCLK frequency. Table Clock Control Register (0x00)
32-kHz sample rate Reserved Reserved 44.1/48-kHz sample rate 16-kHz sample rate 22.05/24 -kHz sample rate 8-kHz sample rate 11.025/12 -kHz sample rate MCLK frequency MCLK frequency MCLK frequency MCLK frequency MCLK frequency Reserved Reserved Reserved Reserved
FUNCTION
MCLK frequency
Reserved registers should accessed. Default values bold. Only available 44.1 rates. Rate only available 32/44.1/48 sample rates available
DEVICE REGISTER (0x01)
device register contains code firmware revision. Table General Status Register (0x01)
Reserved Identification code FUNCTION
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ERROR STATUS REGISTER (0x02)
error bits sticky cleared hardware. This means that software must clear register (write zeroes) then read them determine they persistent errors. Error Definitions: MCLK Error MCLK frequency changing. number MCLKs LRCLK changing. SCLK Error: number SCLKs LRCLK changing. LRCLK Error: LRCLK frequency changing. Frame Slip: LRCLK phase drifting with respect internal Frame Sync. Table Error Status Register (0x02)
MCLK error autolock error SCLK error LRCLK error Frame slip Over current, Over Temperature, Over voltage Under voltage errors. Overtemperature warning (sets around 145°) errors
FUNCTION
Default values bold.
SYSTEM CONTROL REGISTER (0x03)
system control register several functions: dc-blocking filter each channel disabled. dc-blocking filter cutoff each channel enabled (default). soft unmute recovery from clock error. This slow recovery. Unmute takes same time volume ramp defined 0X0E. hard unmute recovery from clock error (default). This fast recovery, single step volume ramp
Bits D1-D0: Select de-emphasis Table System Control Register (0x03)
FUNCTION high-pass blocking) disabled high-pass blocking) enabled Reserved
Soft unmute recovery from clock error Hard unmute recovery from clock error Reserved Reserved Reserved Reserved De-emphasis 44.1 De-emphasis
de-emphasis
Default values bold.
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TAS5707
SERIAL DATA INTERFACE REGISTER (0x04)
shown Table TAS5707 supports serial data modes. default 24-bit, mode, Table Serial Data Interface Control Register (0x04) Format
RECEIVE SERIAL DATA INTERFACE FORMAT Right-justified Right-justified Right-justified
WORD LENGTH
D7-D4 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Left-justified Left-justified Left-justified Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default values bold.
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SYSTEM CONTROL REGISTER (0x05)
When low, system exits channel shutdown starts playing audio; otherwise, outputs shut down(hard mute). Table System Control Register (0x05)
Reserved
FUNCTION Enter channel shut down (hard mute). channel shutdown (normal operation) Reserved
Default values bold.
SOFT MUTE REGISTER (0x06)
Writing following bits sets output respective channel duty cycle (soft mute). Table Soft Mute Register (0x06)
Soft mute channel Soft unmute channel Soft mute channel Soft unmute channel Reserved FUNCTION
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TAS5707
VOLUME REGISTERS (0x07, 0x08, 0x09)
Step size Master volume Channel-1 volume Channel-2 volume 0x07 (default mute) 0x08 (default 0x09 (default Table Volume Registers (0x07, 0x08, 0x09)
(default individual channel volume) -78.5 -79.0 Values between 0xCF 0xFE Reserved MUTE (default master volume)
FUNCTION
Default values bold.
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MASTER FINE VOLUME REGISTER (0x0A)
This register used provide precision tuning master volume. Table Master Fine Volume Register (0x0A)
FUNCTION 0.125 0.25 0.375 Write enable Ignore Write register 0X0A
Default values bold.
VOLUME CONFIGURATION REGISTER (0x0E)
Bits D2-D0: Volume slew rate (Used control volume change MUTE ramp rates). These bits control number steps volume ramp.Volume steps occur rate that depends sample rate data follows Sample Rate (KHz) 8/16/32 11.025/22.05/44.1 12/24/48 Approximate Ramp Rate us/step 90.7 us/step 83.3 us/step Table Volume Control Register (0x0E)
Reserved
FUNCTION Volume slew steps volume ramp time 48kHz) Volume slew 1024 steps volume ramp time 48kHz) Volume slew 2048 steps (171 volume ramp time 48kHz) Volume slew steps (21ms volume ramp time 48kHz) Reserved
Default values bold.
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TAS5707
MODULATION LIMIT REGISTER (0x10)
Table Modulation Limit Register (0x10)
MODULATION LIMIT 99.2% 98.4% 97.7% 96.9% 96.1% 95.3% 94.5% 93.8% RESERVED
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, 0x14)
Internal Channels mapped into registers 0x11, 0x12, 0x13, 0x14. Table Channel Interchannel Delay Register Format
BITS DEFINITION SUBADDRESS 0x11 0x12 0x13 0x14 FUNCTION Minimum absolute delay, DCLK cycles Maximum positive delay, DCLK cycles Maximum negative delay, DCLK cycles RESERVED Delay (value) DCLKs Default value channel Default value channel Default value channel Default value channel
Default values bold.
settings have high impact audio performance (eg: Dynamic Range, THD, Cross talk etc.) Therefore, appropriate settings must used. default device settings mode.If used mode, then update these registers before coming channel shutdown.
MODE 0x11 0x12 0x13 0x14 MODE MODE
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START/STOP PERIOD REGISTER (0x1A)
This register used control soft-start soft-stop period following enter/exit channel shut down command change state. This helps reduce pops clicks start-up shutdown.The times only approximate vary depending device activity level clock stability. Table Start/Stop Period Register (0x1A)
Reserved duty cycle start/stop period 16.5-ms duty cycle start/stop period 23.9-ms duty cycle start/stop period 31.4-ms duty cycle start/stop period 40.4-ms duty cycle start/stop period 53.9-ms duty cycle start/stop period 70.3-ms duty cycle start/stop period 94.2-ms duty cycle start/stop period 125.7-ms duty cycle start/stop period 164.6-ms duty cycle start/stop period 239.4-ms duty cycle start/stop period 314.2-ms duty cycle start/stop period 403.9-ms duty cycle start/stop period 538.6-ms duty cycle start/stop period 703.1-ms duty cycle start/stop period 942.5-ms duty cycle start/stop period 1256.6-ms duty cycle start/stop period 1728.1-ms duty cycle start/stop period 2513.6-ms duty cycle start/stop period 3299.1-ms duty cycle start/stop period 4241.7-ms duty cycle start/stop period 5655.6-ms duty cycle start/stop period 7383.7-ms duty cycle start/stop period 9897.3-ms duty cycle start/stop period 13,196.4-ms duty cycle start/stop period FUNCTION
Default values bold.
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TAS5707
OSCILLATOR TRIM REGISTER (0x1B)
TAS5707 processor contains internal oscillator support autodetect clock rates. This reduces system cost because external reference required. Currently, recommends reference resistor value 18.2 (1%). This should connected between OSC_RES DVSSO. Writing 0X00 0X1B enables trim that programmed factory. Note that trim must always following reset device. Table Oscillator Trim Register (0x1B)
Reserved
FUNCTION Oscillator trim done (read-only) Oscillator trim done (read only) Reserved
Select factory trim (Write select factory trim; default Factory trim disabled Reserved
Default values bold.
BKND_ERR REGISTER (0x1C)
When back-end error signal received from internal power stage, power stage reset stopping activity. Subsequently, modulator waits approximately time listed Table before attempting re-start power stage. Table BKND_ERR Register (0x1C)
Reserved back-end reset period back-end reset period back-end reset period back-end reset period back-end reset period back-end reset period 1047 back-end reset period 1197 back-end reset period 1346 back-end reset period 1496 back-end reset period 1496
FUNCTION
This register written only with "non-Reserved" value. Also this register written once after reset. Default values bold.
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INPUT MULTIPLEXER REGISTER (0x20)
This register controls modulation scheme mode) well routing audio internal channels. Table Input Multiplexer Register (0x20)
Reserved
FUNCTION Reserved
FUNCTION Channel-1 mode Channel-1 mode SDIN-L channel SDIN-R channel Reserved Reserved Reserved Reserved Ground channel Reserved Channel mode Channel mode SDIN-L channel SDIN-R channel Reserved Reserved Reserved Reserved Ground channel Reserved FUNCTION Reserved
FUNCTION
Default values bold.
OUTPUT REGISTER (0x25)
This output selects which internal channel output external pins. channel output external output pin. Bits D21-D20: Bits D17-D16: Bits D13-D12: Bits D09-D08: Selects which channel output OUT_A Selects which channel output OUT_B Selects which channel output OUT_C Selects which channel output OUT_D
Note that channels enclosed that channel 0x00, channel 0x01, channet 0x02, channel 0x03.
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TAS5707
Table Output Register (0x25)
RESERVED Reserved
FUNCTION Reserved
FUNCTION Reserved Multiplex channel OUT_A Multiplex channel OUT_A Multiplex channel OUT_A Multiplex channel OUT_A Reserved
Multiplex channel OUT_B Multiplex channel OUT_B Multiplex channel OUT_B Multiplex channel OUT_B FUNCTION Multiplex channel OUT_C Multiplex channel OUT_C Multiplex channel OUT_C Multiplex channel OUT_C Reserved
Multiplex channel OUT_D Multiplex channel OUT_D Multiplex channel OUT_D Multiplex channel OUT_D
FUNCTION
Default values bold.
CONTROL (0x46)
turned turned Reserved
FUNCTION Reserved
FUNCTION Reserved
FUNCTION Reserved
FUNCTION
Default values bold.
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback Product Folder Link(s): TAS5707
TAS5707
SLOS556 NOVEMBER 2008. www.ti.com
BANK SWITCH CONTROL (0x50)
Table Bank Switching Command
kHz, does bank kHz, uses bank Reserved Reserved 44.1/48 kHz, does bank 44.1/48 kHz, uses bank kHz, does bank kHz, uses bank 22.025/24 kHz, does bank 22.025/24 kHz, uses bank kHz, does bank kHz, uses bank 11.025/12 kHz, does bank 11.025/12 kHz, uses bank
FUNCTION kHz, does bank kHz, uses bank Reserved Reserved 44.1/48 kHz, does bank 44.1/48 kHz, uses bank kHz, does bank kHz, uses bank
22.025/24 kHz, does bank 22.025/24 kHz, uses bank kHz, does bank kHz, uses bank
11.025 kHz/12, does bank 11.025/12 kHz, uses bank
FUNCTION kHz, does bank kHz, uses bank Reserved Reserved
44.1/48 kHz, does bank 44.1/48 kHz, uses bank kHz, uses bank 22.025/24 kHz, does bank 22.025/24 kHz, uses bank kHz, does bank kHz, uses bank 11.025/12 kHz, does bank 11.025/12 kHz, uses bank FUNCTION
kHz, does bank
Default values bold. Submit Documentation Feedback Product Folder Link(s): TAS5707
Copyright 2008, Texas Instruments Incorporated
TAS5707
Table Bank Switching Command (continued)
(bypass channels Reserved
FUNCTION
Ignore bank-mapping bits D31-D8.Use default mapping. bank-mapping bits D31-D8. written independently.
ganged biquads; write Left channel also written Right channel (0X29-2F ganged 0X30-0X36). Reserved
bank switching. updates Configure bank default) Configure bank (44.1/48 default)
Configure bank (other sample rates default) Automatic bank selection Reserved Reserved
Default values bold.
Copyright 2008, Texas Instruments Incorporated
Submit Documentation Feedback Product Folder Link(s): TAS5707
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Nov-2008
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing HTQFP
Reel Reel Diameter Width (mm) (mm) 330.0 16.4
(mm)
(mm)
(mm)
(mm) 12.0
Pin1 (mm) Quadrant 16.0
TAS5707PHPR
1000
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Nov-2008
*All dimensions nominal
Device TAS5707PHPR
Package Type HTQFP
Package Drawing
Pins
1000
Length (mm) 346.0
Width (mm) 346.0
Height (mm) 33.0
Pack Materials-Page
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