ASSP (USB2.0 Dual Function Controller) REJ03F0119-0100Z 1.00 2006
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M66596FP/WG
ASSP (USB2.0 Dual Function Controller)
REJ03F0119-0100Z 1.00 2006.3.14
1.The M66596 (Universal Serial Bus) Rev. host peripheral controller that supports Hi-Speed Full-Speed transfers. This controller built-in transceiver supports transfer types defined specification. M66596 compact package compatible with peripheral controller M66592. M66596 built-in buffer memory data transfers enables eight pipes. pipes endpoint numbers assigned, based user's system. controller connected using either separate multiplex bus. Moreover, split interface (dedicated external interface) provided independent interface, making this ideal choice systems that require transfer large volumes data high speed.
Features
1.2.1
Built Hi-Speed host peripheral controller
Hi-Speed host peripheral controllers built chip. Both Hi-Speed transfer (480Mbps) Full-Speed transfer (12Mbps) supported possible change host peripheral mode register setup. Built-in Hi-Speed Full-Speed transceiver
1.2.2
Reduced power consumption
core power supply, selectable interface power supply 3.3V 1.8V. power consumption makes this ideal mobile devices Low-power mode (power-saving sleep state) supported reduce power consumption during suspended operation
1.2.3
Small package
Compact 64-pin package used compatible with Renesas Technology Hi-Speed peripheral controller M66596. external elements used, less space required mounting VBUS signal connected directly controller Built-in pull-up resistor(Peripheral mode) Built-in pull-down resistor(Host mode) Built-in terminating resistors (for Hi-Speed operation) Built-in output resistors (for Full-Speed operation)
1.2.4
Isochronous transfer supported
types transfers supported Control transfers Bulk transfers Interrupt transfers (High-Bandwidth transfers supported) Isochronous transfers (High-Bandwidth transfers supported)
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1.2.5
interfaces
user select either interface power supply 16-bit interface 16-bit separate 16-bit multiplex supported 16-bit interface (slave function) supported 8-bit split (dedicated external interface) supported Built-in interface channels transfer enables high-speed access MB/sec.
1.2.6
Pipe configuration
Built-in buffer memory communication pipes(endpoints) selected (including default control pipe endpoint Programmable pipe configuration point numbers assigned pipe 1-7. Transfer conditions that each pipes Pipe Control transfer, continuous transfer mode, 256-byte fixed single buffer Pipe Bulk transfer isochronous transfer, continuous transfer mode, programmable buffer size double buffer selected) Pipe Bulk transfer, continuous transfer mode, programmable buffer size double buffer selected) Pipe Interrupt transfer, 64-byte fixed single buffer
1.2.7
Feature host mode
Capable Hi-Speed transfer peripheral device. Automatic schedule send transaction. Automatic schedule interval isochronous trenasfer interrupt transfer.
1.2.8
Feature peripheral mode
Control transfer stage control function Device state control function Auto response function SET_ADDRESS request response assignment function (NRDY)
1.2.9
Other functions
Automatic recognition Hi-Speed operation Full-Speed operation based automatic response reset handshake Byte endian swap function when using 16-bit data transfers Transfer termination function when using transaction count function. transfer termination function using external trigger (DEND pin) interpolation function pulse output function Three types input clocks built into available selection Input clocks selected Zero-Length packet addition function (DEZPM) when ending transfers using DEND BRDY interrupt event notification timing change function (BFRE) Function that automatically clears buffer memory after data pipe specified DxFIFO port been read (DCLRM) Function automatically supply clock from low-power sleep state (ATCKM) setting function response generated transfer (SHTNAK)
1.2.10 Applications
PDA, recorder, box, Digital Printer audio devce, Digital video camera, Digital still camera, external storage device, Hi-Speed devices
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layout diagram
Figure Figure show layout diagram (top view) controller.
DGND
INT_N SOF_N RD_N WR0_N WR1_N CS_N DREQ0_N DACK0_N DEND0_N DREQ1_N DACK1_N/DSTB0_N DEND1_N RST_N
D6/AD6 D5/AD5 D4/AD4 D3/AD3 D2/AD2 D1/AD1 MPBUS
M66596FP
(Top view)
AFED33V
VBUS
AFEA15V
AFEA33V
AFED15V
AFEA15G
AFED33G
AFEA33G
XOUT
*The "_N" signal name indicates that signal active state.
package M66596FP 64P6X 64pinLQFP(0.5mm pitch)
Figure layout diagram M66596FP
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AFED15G
REFRIN
TEST
M66596FP/WG
M66596WG(TOP VIEW)
DGND
RD_N
SOF_N
INT_N
D6/AD6
D5/AD5
CS_N
WR1_N
WR0_N
D2/AD2
D1/AD1
D4/AD4
D3/AD3
DEND0_N DREQ1_N DREQ0_N DACK0_N
A6/ALE
DACK1_N /DSTB0_N RST_N
DEND1_N AFEA15V AFEA33G AFEA33V
AFED33V
VBUS
AFEA15G
XOUT
AFED15G
TEST
AFED33G
REFRIN
AFED15V
MPBUS
*The "_N" signal name indicates that signal active state.
Package M66596WG 64FHX 64pin FBGA (0.8mm pitch)
Figure layout diagram M66956WG
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Description pins
Table describes controller pins. Table describes used pins.
Table descriptions
Category name Name Function count
(Pin no.s.)
State
RST_ N="L" RST_ goes PCUT
interface
D15-0 AD6-1
Data Multiplex Address
A6-1
Address
CS_N RD_N WR0_N WR1_N MPBUS
Address Latch Enable Chip Select Read Strobe D7-0 Byte Write Strobe D15-8 Byte Write Strobe Mode Selection
Split interface interface
SD7-0 DREQ0_N*1) DREQ1_N*1) DACK0_N*1) DACK1_N*1) DSTB0_N*2)
Split Data Request
Acknowledge Data Strobe
DEND0_N*1) DEND1_N*1)
Transfer
Interrupt/ output
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INT_N
Interrupt
This 16-bit data bus. When multiplex specified, this group pins used time-shared basis some data buses (D6-D1), bits address (A6-A1). This 6-bit address bus. Because data consists bits, there When multiplex specified, used signal. Setting this level selects this controller. Setting this level reads data from controller registers. rising edge, D7-D0 written registers controller. rising edge, D15-D8 written registers controller. Setting this level selects separate bus. Setting this level selects multiplex bus. This should fixed either level. split selected, this functions data split bus. This notifies system D0FIFO port D1FIFO port transfer request. Input Acknowledge signal D0FIFO D1FIFO port. This functions data strobe signal D0FIFO port. Because also used Acknowledge signal D1FIFO port, DSTB0_N function cannot used DACK1_N function being used. FIFO port access writing direction> This receives Transfer signal from another peripheral chip input signal. FIFO port access reading direction> This indicates transfer data output signal. active state, this notifies system various types interrupts relating communication.
(24-39)
Input (Hi-z)
(18-23)
Input Input
Input Input Input Input Input Input Input
Input (Hi-z) Input Input Input Input Input Input
(56) (53) (54) (55) (17)
Input Input Input Input Input
(43-50) (57, (58,
Input (Hi-z)
Input (Hi-z)
Input (Hi-z) Input
Input
Input
(59,
Input (Hi-z)
Input (Hi-z)
Input (Hi-z)
(51)
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Category
name
Name
Function
count
(Pin no.s.)
State
RST_ N="L" RST_ goes PCUT
SOF_N Clock XOUT
pulse output Oscillation input Oscillation output Reset signal Test signal data data VBUS input
System control interface
RST_N TEST
When detected active state, pulse output. crystal oscillator should connected between XOUT. When using external clock input, external clock signal should connected XIN, XOUT should open. level, controller initialized. This should fixed open. This should connected bus. This should connected bus. This should connected directly Vbus bus. connected disconnected state Vbus detected. this connected with Vbus bus, connect case host controller, please too. *This can't supply vbus. This should connected AFEA33G through kOhm resistance. This should connected
(52) (10) (11) (63) (16)
Input Input (Hi-z) Input (Hi-z) Input (Hi-z)
Input Input (Hi-z) Input (Hi-z) Input (Hi-z)
Input Input (Hi-z) Input (Hi-z) Input (Hi-z)
VBUS monitor input
VBUS
Reference resistance
REFRIN AFEA33V
Power supply
AFEA33G
AFED33V
AFED33G
AFEA15V
AFEA15G
AFED15V
AFED15G
DGND
Reference input Transceiver unit analog power supply Transceiver unit analog Transceiver unit digital power supply Transceiver unit digital Transceiver unit analog power supply Transceiver unit analog Transceiver unit digital power supply Transceiver unit digital Core power supply power supply Digital
(12)
This should connected
This should connected
This should connected
(13)
(14)
This should connected This should connected
(40) (15, (41)
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M66596FP/WG active active states these pins selected using control program user system. "_N" indicates that active state default state. DSTB0_N DACK1_N assigned same pin, functions other valid. input level MPBUS needs established just before reset. Also, this should switched during operation. When CS_N RD_N "L", These pins output "L". MPBUS "H", these pins made open. CS_N, WR0_N, WR1_N should kept during RST_N="L" (from RST_N goes right after RST_N goes "H"). CS_N="H" WR0_N="H" WR1_N="H" Description "State pin" Input Pins Hi-z state. Please make "open" board. Input(Hi-z) Pins Hi-z state. Pins "open" board. Output states shown. These pins inactive state.
Table example used pins
Category SPLIT interface interface name SD7-0 DREQ0_N DREQ1_N DACK0_N DACK1_N/DSTB0_N DEND0_N DEND1_N SOF_N TEST VBUS Description "Open" "Open" "Open" "H"*1) "H"*1) "Open" "Open" "Open" "Open"
output System control VBUS monitor input
When DACKn_N used, please DACKA DMAnCFG register (n=0,1). When DENDx_N used, please DENDA DMAnCFG register (n=0,1). this connected with Vbus bus,
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function configuration
Figure shows diagram function configuration controller.
interface D15-7,D6-1(/AD6-1),D0 A6/ALE,A5-1 CS_N RD_N WR0_N WR1_N MPBUS Interrupt output INT_N SOF_N
M66596
interface DREQ0_N DACK0_N DEND0_N DREQ1_N DACK1_N/DSTB0_N DEND1_N Split SD7-0 System control RST_N TEST
Clock XOUT VBUS monitor input VBUS
interface Reference resistance REFRIN
Figure function configuration diagram
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Block diagram
controller consists analog front unit (AFE), protocol engine unit (Prtcl_Eng) that includes SIE, pipe control unit (Pipe_Ctrl), transaction schedule control unit(Schedule Ctrl), FIFO port unit (FIFO_Port), buffer memory unit (Buf_Mem), interrupt control unit (Int_Ctrl), interface unit (BIU), interface register unit (CPU_IF_Reg). Figure shows block diagram controller. When data being sent received between M66596 peripheral(or host) controller connected bus, buffer memory assigned each pipes used. Two-way communication possible controller changing data stored buffer memory into data packets outputting them using serial output, inputting data packets which then stored buffer memory.
power supply
Core power supply
power supply AFEA33V, AFED33V AFEA15V, AFED15V
Interrupt output INT_N, SOF_N
Int_Ctrl
interface A6(/ALE), A5-1, D15-7, D6-1(/AD6-1), CS_N, RD_N, WR0_N,WR1_N MPBUS
CPU_IF_Reg
Schedule _Ctrl Clock XIN, XOUT Prctl_Eng VBUS monitor VBUS Buf_Mem
Split SD7-0 System control RST_N, TEST
FIFO_Port
interface DREQ0_N, DREQ1_N DACK0_N, DACK1_N/DSTB0_N, DEND0_N, DEND1_N
Pipe_Ctrl
interface Reference resistance REFRIN
Ground DGND
ground AFEA33G,AFED33G AFEA15G,AFED15G
Figure Block diagram
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overview functions
1.7.1 function selection
controller change host function peripheral function register setup. When which Host function Peripheral function chosen, hardware recognizes Hi-Speed Full-Speed automatically.
1.7.2
interfaces
controller supports interfaces noted below.
1.7.2.1 External interface
controller uses interface access control registers. interface with supports access methods noted below. Chip Select (CS_N) three strobe pins (RD_N, WR0_N WR1_N) should used access. (16-bit separate address buses (A6-1) data buses (D15-0) used. 16-bit multiplex (ALE) data buses (D15-0) used. data buses used addresses data time-shared basis. separate multiplex selected based MPBUS signal level when reset canceled.
1.7.2.2 Accessing buffer memory
controller supports methods described below access data transfer buffer memory. access Addresses control signals should used write data buffer memory read from buffer memory. access Data should written buffer memory controller, read from buffer memory, from DMAC dedicated DMAC. data communication done using Little Endian. There byte Endian swap function FIFO port access, when using 16-bit access, Endian switched using register settings.
1.7.2.3 access methods
When using access access buffer memory, access methods noted below selected. Method using shared with Method using dedicated (split bus)
1.7.3
events
controller notifies user's system operation events means interrupts. Moreover, with pipe which interface been selected, system notified that buffer memory controller accessed asserting DREQ signal. There types interrupts causes interrupts being generated. user select whether interrupt notification permitted each type each cause, using settings control program user system.
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1.7.4
data transfers
controller capable types transfers: communication control transfers, bulk transfers, interrupt transfers, well isochronous data transfers. pipes noted below used with data transfers various types communication. Dedicated control transfer pipe(Default Control Pipe(DCP)) dedicated interrupt transfer pipes(Pipe6,7) Three dedicated bulk transfer pipes(Pipe3, pipes which bulk transfers isochronous transfers selected(Pipe1, settings necessary transfers, such transfer type, point number, maximum packet size, should each pipe, conjunction with user system. Also, controller built-in buffer memory. dedicated bulk transfer pipe pipes which bulk transfers isochronous transfers selected, settings such buffer memory assignment buffer operation mode which based user system should entered. buffer operation mode setting enable high-speed data transfers with interrupts, using double-buffer configuration data packet continuous transfer function. Access buffer memory from control user's system controller done through three FIFO port registers.
1.7.5
interface
(Direct Memory Access) interface consists data transfers between user system controller using DxFIFO port, type data transfer which involved. controller equipped with 2-channel interface following functions. transfer notification function using Transfer signal (DEND signal) auto-clear function activated when Zero-Length packet received "send addition" function used send Zero-Length packet based input Transfer signal (DEND signal) transfer function using transaction counter function controller supports types interfaces noted below. Cycle steal transfer With this type transfer, DREQ repeatedly asserted negated each time data transfer byte word) carried out. Burst transfer With this type transfer, DREQ remains asserted pipe buffer area assigned pertinent FIFO port, until transfer ended DEND signal, without ever being negated.
Also, following selected interface handshake signal (pin): CS_N, RD_N, WR_N, DACK_N. With transfers using split bus, high-speed transfers possible changing data setup timing, operating OBUS DMAxCFG register.
1.7.6
pulse output function
pulse output function provided that notifies system timing which packets transmited received. Host mode, when controller transmits packet, controller outputs pulses SOF_N pin. Peripheral mode, when controller recives packet, controller outputs pulse. controller outputs pulses fairly regular intervals, using interpolation timer, even packet damaged. Peripheral mode, also possible output pulse only when packet damaged.
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1.7.7
External elements integration
controller following external elements built into Also, because VBUS withstand user system input VBUS signal directly controller. Resistors necessary line control Resistance D-line built pull up-registor(Peripheral mode) pull-down registor(Host mode) terminating resistors (for Hi-Speed operation) output resistors (for Full-Speed operation) three external clocks MHz) selected Hi-Speed Full-Speed operation carried out.
1.7.8
Low-power sleep state function
controller equipped with low-power sleep state that reduces current consumption. low-power sleep state functions effectively under following circumstances. When there host peripheral controller connected When device state shifted suspended state, data transfer necessary system returned from low-power sleep state normal operating state using designated interrupt, dummy writing controller.
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Registers
Reading table registers
Status after reset Each register connected 16-bit internal bus. Odd-numbered addresses will even-numbered addresses This indicates default state register immediately after reset operation, after recovering from low-power sleep state. Reset default state when external reset signal been input from RST_N pin. Reset default state when user system carried operation using USBE bit. Reset default state when controller detected reset. Low-power Sleep default state when controller recovered from low-power sleep state. Items that require particular attention during reset operation noted under Notes". indicates state which there operation controller, user setting retained. indicates that value undecided.
Access Condition This condition effect softwear accessing register. Access Condition This condition effect controller accessing register during operation other than reset. Read Only Write Only Read Write R(0) "0"Read Only W(1) "1"Write Only Note Name Function Description This number detailed explanations number notes. This indicates symbol name. This describes active items notes.
Nothing placed shaded sections. These should fixed "0".
<Example table notation> number symbol reset reset reset
Low-power sleep state
Name Function Nothing placed here. should fixed "0". Operation disabled enabled Operation enabled "L"output operation "H"output control
R(0)/ W(1)
Note 2.3.1 2.3.2 2.3.2
<<Note>> being accessed succession writing, access cycle necessary.
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Table registers
Table shows controller registers.
Table Registers
Address
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Symbol SYSCFG SYSSTS DVSTCTR TESTMODE PINCFG DMA0CFG DMA1CFG CFIFO D0FIFO D1FIFO
Name System configuration control register System configuration status register Device state control register Test mode register Data configuration register DMA0 configuration register DMA1 configuration register CFIFO port register D0FIFO port register D1FIFO port register
Index
CFIFOSEL CFIFOCTR CFIFOSIE D0FIFOSEL D0FIFOCTR D0FIFOTRN D1FIFOSEL D1FIFOCTR D1FIFOTRN INTENB0 INTENB1 BRDYENB NRDYENB BEMPENB SOFCFG INTSTS0 INTSTS1 BRDYSTS NRDYSTS BEMPSTS FRMNUM UFRMNUM RECOVER USBREQ USBVAL USBINDX USBLENG
CFIFO port selection register CFIFO port control register CFIFO port register D0FIFO port selection register D0FIFO port control register transaction counter register D1FIFO port selection register D1FIFO port control register transaction counter register Interrupt enable register Interrupt enable register BRDY interrupt enable register NRDY interrupt enable register BEMP interrupt enable register configuration register Interrupt status register Interrupt status register BRDY interrupt status register NRDY interrupt status register BEMP interrupt status register Frame number register Micro frame number register address low-power status recovery register request type register request value register request index register request length register
2.10 2.10 2.11 2.12 2.12 2.12 2.12
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Address
Symbol DCPCFG DCPMAXP DCPCTR PIPESEL PIPECFG PIPEBUF PIPEMAXP PIPEPERI PIPE1CTR PIPE2CTR PIPE3CTR PIPE4CTR PIPE5CTR PIPE6CTR PIPE7CTR
Name configuration register maximum packet size register control register Pipe window selection register Pipe configuration register Pipe buffer setting register Pipe maximum packet size register Pipe period control register Pipe control register Pipe control register Pipe control register Pipe control register Pipe control register Pipe control register Pipe control register
Index 2.13 2.13 2.13 2.14 2.14 2.14 2.14 2.14 2.14 2.14 2.14 2.14 2.14 2.14 2.14
Nothing placed addresses that shaded. These addresses should accessed.
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Table symbols
Table shows controller symbols.
Table symbols
Addr Register name
XTAL
Odd-numbered addresses
XCKE RCKE PLLC SCKE
ATCKM
Even-numbered addresses
FSRPC
PCUT LNST
USBE
SYSCFG SYSSTS DVSTCTR TESTMODE PINCFG DMA0CFG DMA1CFG CFIFO D0FIFO D1FIFO CFIFOSEL CFIFOCTR CFIFOSIE D0FIFOSEL
DCFM DMRPD DPRPU
WKUP RWUPE USBRST RESUME UACT UTST LDRV DREQA BURST DREQA BURST DACKA DACKA BIGEND DFORM DFORM CFPORT D0FPORT D1FIPORT DENDA PKDENDA PKDENDE DENDE OBUS OBUS
RHST
RCNT BVAL RCNT
BCLR SCLR BCLR BCLR RSME BCHGE FRDY SBUSY DCLRM DREQE FRDY
ISEL DTLN
CURPIPE
TRENB TRCLR DEZPM DTLN TRNCNT
CURPIPE
D0FIFOCTR BVAL D0FIFOTRN D1FIFOSEL RCNT D1FIFOCTR BVAL D1FIFOTRN INTENB0 INTENB1 BRDYENB NRDYENB BEMPENB SOFCFG INTSTS0 INTSTS1 BRDYSTS NRDYSTS BEMPSTS FRMNUM UFRMNUM RECOVER USBREQ USBVAL USBINDX USBLENG DCPCFG DCPMAXP OVRN VBINT VBSE
DCLRM DREQE FRDY
TRENB TRCLR DEZPM DTLN TRNCNT
CURPIPE
SOFE
DVSE DTCHE
CTRE
BEMPE NRDYE BRDYE
URST
SADR
SCFG
SUSP
WDST
RDST BRDYM
CMPL INTL
SERR PCSE
SIGNE SACKE PIPEBRDYE PIPENRDYE PIPEBEMPE
SOFM RESM BCHG SOFR SOFR DVST DTCH CTRT BEMP BEMP NRDY NRDY BRDY BRDY VBSTS DVSQ SIGN SACK PIPEBRDY PIPENRDY PIPEBEMP CRCE SOFRM STSRECOV bRequest wValue wIndex wLength CNTMD DEVSEL MXPS FRNM UFRNM USBADDR bmRequestType VALID CTSQ
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Addr
Register name
BSTS
SUREQ
Odd-numbered addresses
Even-numbered addresses
CCPL
PIPESEL
DCPCTR PIPESEL PIPECFG PIPEBUF PIPEMAXP PIPEPERI PIPE1CTR PIPE2CTR PIPE3CTR PIPE4CTR PIPE5CTR PIPE6CTR PIPE7CTR
SQCLR SQSET SQMON
TYPE BUFSIZE DEVSEL IFIS BSTS INBUFM BSTS INBUFM BSTS INBUFM BSTS INBUFM BSTS INBUFM BSTS BSTS
BFRE
DBLB
CNTMD SHTNAK MXPS
BUFNMB
EPNUM
IITV ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON ACLRM SQCLR SQSET SQMON
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System control
System configuration control register [SYSCFG]
XTAL XCKE RCKE PLLC SCKE ATCKM
<Address 00H>
DCFM DMRPD DPRPU FSRPC PCUT USBE
15-14 XTAL Clock selection
Name input input input Reserved
Function
Note 3.1.6
XCKE Oscillation buffer operation disabled Oscillation buffer enabled Oscillation buffer operation enabled RCKE Reference clock supply stopped Reference clock enabled Reference clock supply enabled PLLC operation disabled operation enabled operation enabled SCKE Internal clock supply stopped Internal clock enabled Internal clock supply enabled Nothing placed here. should fixed "0". ATCKM clock supplied from low-power sleep Auto clock supply function enabled state clock stop state. Auto clock supply function disabled Auto clock supply function enabled This enables Hi-Speed operation. Hi-Speed operation enabled Hi-Speed operation disabled (Full-Speed) Hi-Speed operation enabled (detected controller) DCFM Peripheral Controller Host Controller detailed information, refer Chapter 2.3.4 DMRPD D+,D- line resistance control DPRPU D+,D- line resistance control Nothing placed here. These should fixed "0". FSRPC Full-Speed receiver controled Full-Speed receiver enable Full-Speed receiver enabled PCUT Normal operation state Low-power sleep state enabled Low-power sleep state USBE block operation disabled (S/W Reset) block operation enabled block operation enabled
3.1.6 3.1.6 3.1.6 3.1.6
3.1.7
2.3.1 3.1.4 2.3.1 2.3.4 2.3.4
2.3.3 2.3.2 3.1.4
Notes Hi-Speed operation enabled (HSE) Device Controller function (DCFM) should before internal clock supplied .setup DPRPU DPRPD bit. When system returns from low-power sleep state normal operation state, controller sets "XCKE
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System configuration status register [SYSSTS]
<Address: 02H>
LNST
Name
Function
Note 2.3.3
15-2 Nothing placed here. These should fixed "0". LNST Please detailed explanation concerning data line status this item. <<Notes>> None particular
2.3.1
Selection function
DCFM SYSCFG register should used select function controller. controller function selection table shown Table 2.3.
Table controller function selection
DCFM Speed Full Full Full Full RHSP Reset Handshake Protocol Function Peripheral Host Peripheral Host Note Full-Speed communication only. Full-Speed communication only. communication speed based result RHSP. communication speed based result RHSP.
2.3.2
block operation enabled
USBE SYSCFG register should used enable block operation. same used carry reset controller. When software "USBE=0", controller resets register targeted reset initialization default setting value. long "USBE=0" set, data written software targeted reset initialization. "USBE=1" should following reset enable controller operation.
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2.3.3
Line status monitor
Table 2.4Table shows data line statuses controller. controller monitors line status line line) data using LNST SYSSTS register. LNST configured bits. meaning each bits, please refer table below. line status checked with Full-Speed receiver inside M66596. This controller controls Full-Speed receiver automatically when internal clock supplied. FSRPC SYSCFG register enabled setting FSRPC SYSCFG register when internal clock supplied. After reset, checking state before supplying internal clock, please FSRPC Once supplying internal clock, necessary S/W. low-power sleep state, line status cannot monitored.
Table data line statuses
LNST LNST During Full-Speed operation During Hi-Speed operation During chirp operation
Squelch Squelch State Squelch Chirp State Invalid Chirp Invalid Invalid Chirp: reset handshake protocol being executed Hi-Speed operation enabled state (HSE "1"). Squelch: Idle state Squelch: Hi-Speed state Hi-Speed state Chirp Chirp state Chirp Chirp state
2.3.4
data register control
setup about resistance data shown Table 2.5. data line resistors controled DMRPD DPRPU SYSCFG register.
Table Resistance control data
DMRPD DPRPU DOpen Open Pull-Down Pull-Down Open Pull-Up Pull-Down Pull-Up note Peripheral Controller Host Controller
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signal control
Device state control register [DVSTCTR]
<Address: 04H>
WKUP RWUPE USBRST RESUME UACT RHST
Name
Function
Note
15-9 Nothing placed here. These should fixed "0". WKUP Non-output Wakeup output (Peripheral mode) Remote wakeup signal output RWUPE Remote wakeup disabled Remote wakeup enable Remote wakeup enabled (Host mode) USBRST Non-output reset output (Host mode) reset output RESUME Non-output Resume output (Host mode) Resume signal output UACT Disable Communication enable Enable Nothing placed here. These should fixed "0". RHST Communication speed decided Reset handshake Reset handshake being processed Full-Speed operation established Hi-Speed operation established
R/W(1) R/W(0) 2.4.1 *1),*2) 2.4.1 *2),*3)
2.4.1 *3)*3 R/W(1) 2.4.1 2.4.1 2.4.2
<<Notes>> should never written WKUP unless "Suspended" device state ("DVSQ 1xx") remote wakeup from host enabled. WKUP RWUPE 1,don' stop Internal clock supply. controller peripheral mode ,set "RWUPE=0, USBRST=0, RESUME=0, UACT=0". Test mode register [TESTMODE]
<Address: 06H>
UTST
Name
Function
Note 2.4.3
15-4 Nothing placed here. These should fixed "0". UTST Please detailed explanation concerning Test mode this item.
<<Note>> UTST valid only during Hi-Speed operation. Check make sure "RHST=11" before using reset required after test UTST operation.
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2.4.1
data control
Each DVSTCTR register used control confirm state data based user system. Remote wakeup (Peripheral mode) WKUP handles control remote wakeup signal output bus. controller controls output time remote wakeup signals. after software WKUP bit, M66596 outputs "K-State" then transfers state idle. When state transferred idle state, controller sets "WKUP=0". According specification, idle state must kept longer than 5ms. Thus software "WKUP=1" right after detection Suspend state, controller will assert "K-State" after 2ms.
Remote wakeup, Resume (Host mode) resume signal output setting RESUME Moreover, when RWUPE remote wakeup signal detected, resume signal outputted down port. this time, controller sets "RESUME" bit. both cases manage output time resume signal S/W. output resume signal stopped "RWUP=0" "RESUME=0" writing S/W. Communication enable (Host mode) uSOF) packet transmitted UACT bit. controller manages packet interval. When UACT bitthe packet sent out. When UACT bit, after sending next SOF, controller made into idle state.
reset (Host mode) reset signal outputted setting USBRST Software should manage reset time. Please "USBRST=0" after waiting reset time.
2.4.2
Communication speed discrimination
SYSCFG register time transmission reception reset, this controller execute reset handshake automatically determine transmission speed. Softwear able confirm speed, using RHST bit. Hi-Speed operation been disabled state ("HSE=0") softwere, controller immediately establishes Full-Speed operation ("RHST=10"), without executing reset handshake protocol. Host mode, following timing that result reflected RHST after reset desabled. Software needs wait connected peripheral Full-Speed device. Full-Speed device When changes from State State with reset. Hi-Speed device When termination resistance changed Hi-Speed mode reset handshake. decides during reset) After reset (after URST=0 setup), when RHST decided after sufficient waiting time, cable disconnect during reset. such case, please check state LNST bit.
2.4.3
Test mode
Table shows test mode operation controller. UTST TESTMODE register controls test signal output during Hi-Speed operation.
Table Test mode operation
UTST setting Test mode Normal operation Test_J Test_K Test_SE0_NAK Test_Packet Reserved
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Peripheral mode 0000 0001 0010 0011 0100 0101-0111
Host mode 0000 1001 1010 1011 1100 1101-0111
M66596FP/WG
External input/output control
Data configuration register [PINCFG]
LDRV
BIGEND
<Address: 0AH>
Name
Function
Note 2.5.1 2.5.2
LDRV When VIF=1.6-2.0 Output pins drive current control When VIF=2.7-3.6 14-9 Nothing placed here. These should fixed "0". BIGEND Little Endian FIFO port Endian Endian Nothing placed here. These should fixed "0".
<<Note>> BIGEND common FIFO ports available FIFO ports only. BIGEND doesn't affects register access.
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DMA0CFG register controls input/output pins used DMA0 interface D0FIFO port, DMA1CFG register controls input/output pins used DMA1 interface D1FIFO port. DMA0 configuration register [DMA0CFG] DMA1 configuration register [DMA1CFG]
DREQA BURST DACKA DFORM
<Address: 0CH> <Address: 0EH>
DENDA PKDENDE OBUS
Name
Function
Note
Nothing placed here. This should fixed "0". DREQA This specifies active state DREQx_N DREQx_N signal polarity selection pin. active High active BURST Cycle steal transfer Burst mode Burst transfer 12-11 Nothing placed here. These should fixed "0". DACKA This specifies active state DACKx_N DACKx_N signal polarity selection pin. active High active DFORM 011: Only DACKx_N signal used (CPU transfer signal selection bus). 000: Address signal RD_N/WRx_ signals used (CPU bus). 010: DACKx_N RD_N/WRx_N signals used (CPU bus). 100: DACKx_N signal used (split bus). 110: DACK0_N DSTB0_N signal used (split bus). 001, 101, 111: Reserved DENDA This specifies active state DENDx_N DEND0_N signal polarity selection pin. active High active PK0: DENDx_N signal asserted transfer Packet mode units. DENDx_N signal asserted each time amount data corresponding buffer size transferred. DENDE DENDx_N signal disabled DENDx_N signal enabled (Hi-Z output). DENDx_N signal enabled. Nothing placed here. should fixed "0". OBUS OBUS mode enabled. OBUS operation disabled OBUS mode disabled. Nothing placed here. These should fixed "0".
2.5.3
3.4.3
2.5.3 3.4.3.4
2.5.3 3.4.3.4
<<Notes>> PKbit valid only when data receiving direction (reading from buffer memory) set. DxFIFO port being used data writing direction, "PKTM=0" should set. "DFORM=110" setting valid only when channel set. Also, following should set: "DFORM=001","DFORM=101" and"DFORM=111".
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2.5.1
Output pins drive current control
output pins drive capability should using LDRV PINCFG register, match power supply. output pins SD7-0, D15-0, INT_N, DREQx_N, DENDx_N, SOF_N pins.
2.5.2
FIFO port access Endian
Table Table show byte Endian operation controller. (The controller uses Little Endian.) When user-system Big-endian, software should BIGEND PINCFG register.
Table Endian operation when using 16-bit access
BIGEND Odd-numbered addresses Even-numbered addresses Even-numbered addresses Odd-numbered addresses
Table Endian operation when using 8-bit access
BIGEND Writing: invalid Reading: invalid Writing: valid Reading: valid Writing: valid Reading: valid Writing: invalid Reading: invalid
2.5.3
signal control
When transferring data using interface, operations (assertion negation DREQx_N DENDx_N signals, transfer mode) should specified match user system, using BURST, PKTM, DENDE, OBUS bits DMAxCFG register. signals valid selected pipe(s) long transfers enabled using DREQE DxFIFOSEL register, which will explained later. DREQx_N asserted when buffer memory pipe Buffer Ready (BRDY) state.
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FIFO ports
transmission reception buffer memory controller uses FIFO. FIFO port registers should used access buffer memory. There three FIFO ports: CFIFO port, D0FIFO port, D1FIFO port. Each FIFO port configured port register that handles reading data from buffer memory writing data memory, selection register used select pipe assigned FIFO port, control register, registers used specifically port functions register used exclusively CFIFO port, transaction counter register used exclusively DxFIFO port). Notes noted below apply each FIFO ports. buffer memory only accessed through CFIFO port. Accessing buffer memory using transfer done only through DxFIFO port. Accessing DxFIFO port using done conjunction with functions restrictions DxFIFO port.(Using transaction counter, etc.) When using functions specific FIFO port, selected pipe cannot changed. (Using transaction counter, signal input/output through DMA-related pins, etc.) Registers corresponding FIFO port never affect other FIFO ports. same pipe should assigned more separate FIFO ports. There sorts buffer memory states; when access right side side. When buffer memory access right side, memory cannot properly accessed from CPU. pipe configuration,i.e. PIPECFG, PIPEBUF, PIPEMAXP, PIPEPERI, PIPE1CTR registers pipe selected CURPIPE should changed. CFIFO port register [CFIFO] D0FIFO port register [D0FIFO] D1FIFO port register [D1FIFO]
FIFOPORT
<Address: 10H> <Address: 14H> <Address: 18H>
15-0 FIFOPORT FIFO port
Name
Function
Note
This handles reading received data from buffer memory, writing sent data buffer memory.
<<Note>> Only CFIFO port used access buffer memory. Accessing buffer memory using transfers only done through D0FIFO D1FIFO ports.
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CFIFO port selection register [CFIFOSEL] D0FIFO port selection register [D0FIFOSEL] D1FIFO port selection register [D1FIFOSEL]
RCNT DCLRM DREQE TRENB TRCLR DEZPM ISEL
<Address: 1EH> <Address: 24H> <Address: 2AH>
CURPIPE
Name
Function DTLN cleared when reception data been read. DTLN decremented when reception data read. Invalid. buffer pointer rewound. Auto Buffer Clear mode disabled. Auto Buffer Clear mode enabled.
Note
RCNT Read Count mode
R(0)/W R/W(0) 3.4.2.2 Buffer pointer rewind 3.4.3.5 DCLRM This Auto Buffer Memory clear mode accessed after data specified pipe been read. DREQE Output disabled. 3.4.3 DREQ signal output enabled Output enabled. Nothing placed here. This should fixed "0". 8-bit width 3.4.2 FIFO port access width 16-bit width TRENB transaction counter function invalid. 3.4.2.5 Transaction counter enabled transaction counter function valid. TRCLR Invalid R(0)/ 3.4.2.5 Transaction counter clear current count cleared. W(1) DEZPM packet added. 3.4.3.3 Zero-Length Packet Added mode packet added. Nothing placed here. This should fixed "0". This selects reading from buffer ISEL Access direction FIFO port when memory. selected This selects writing buffer memory. Nothing placed here. These should fixed "0". CURPIPE 000: specification FIFO port access pipe specification 001: Pipe 010: Pipe 011: Pipe 100: Pipe 101: Pipe 110: Pipe 111: Pipe <<Notes>> DCLRM, DREQE, TRENB, TRCLR DEZPM bits valid D0/D1FIFOSEL registers. DCLRM, TRENB TRCLR bits valid when receiving direction (reading from buffer memory) been pipe specified CURPIPE bit. DEZPM valid when sending direction (writing buffer memory) been pipe specified CURPIPE bit. ISEL valid only when selected using CFIFO port selection register. Software should ISEL according folowing (b). setting CURPIPE ("CURPIPE="0") setting ISEL should done same time. First software sets CURPIPE ("CURPIPE="0"), then sets ISEL after 200ns more. Once reading from buffer memory begun, access width FIFO port cannot changed until data been read. Also, width cannot changed from 8-bit width 16-bit width while data being written buffer memory. Specifying"CURPIPE=0"using D0/D1FIFOSEL register will interpreted pipe having been specified. Also, pipe number should changed while DREQ output enabled. Don't same pipe CURPIPE C/D0 D1FIFOSEL register.
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CFIFO port control register [CFIFOCTR] D0FIFO port control register [D0FIFOCTR] D1FIFO port control register [D1FIFOCTR]
BVAL BCLR FRDY DTLN
<Address: 20H> <Address: 26H> <Address: 2CH>
Name
Function
Note 3.4.2 3.4.2 *8), 3.4.4 *10) 3.4.4
BVAL Invalid W(1) Buffer Memory Valid flag Writing ended BCLR Invalid R(0)/ R/W(0) Buffer Clear Clears buffer memory side. W(1) FRDY FIFO port access disabled. FIFO Port Ready FIFO port accessed. Nothing placed here. This should fixed "0". 11-0 DTLN length reception data Reception Data Length confirmed.
<<Notes>> Writing BVAL valid when direction data packet sending direction (when data being written buffer memory). When direction receiving direction, "BVAL=0" should set. BCLR DTLN valid buffer memory side. Software should "BCLR=1" refer DTLN after making sure that "FRDY=1". Using BCLR clear buffer should done with pipe invalid state pipe configuration ("PID=NAK"). *10) FRDY requires access cycle least after pipe been selected.
CFIFO port register [CFIFOSIE]
SCLR SBUSY
<Address: 22H>
Name
Function
Note
Invalid Access Right Switch Switches access right SCLR Invalid Buffer Clear Clears buffer memory side SBUSY being accessed. Buffer Busy being accessed. 12-0 Nothing placed here. These should fixed "0".
R(0)/ R/W(0) 3.4.2.3 W(1) *11) R(0)/ R/W(0) 3.4.2.4 W(1) *12) 3.4.2.3
<<Note>> *11) function buffer memory side side. "PID=NAK" check SBUSY make sure accessing buffer ("SBUSY=0"). Then write (toggle operation). This valid only pipes which reception direction (reading from buffer memory) been set. *12) function SCLR clear buffer memory side. "PID=NAK" check SBUSY make sure accessing buffer ("SBUSY=0"). Then clear buffer. This valid only pipes which sending direction (writing buffer memory) been set.
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transaction counter register [D0FIFOTRN] transaction counter register [D1FIFOTRN]
TRNCNT
<Address: 28H> <Address: 2EH>
Name
Function Writing: Sets number transfer transactions. Reading: Reads number transactions.
Note 3.4.2.5 *13)
15-0 TRNCNT Transaction counter
<<Note>> *13) transaction counter valid when data being read from buffer memory. number transactions read while counting taking place only TRENB DxFIFOSEL register "1". "TRENB=0", number transactions read.
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Interrupts enabled
Interrupts enabled register 0[INTENB0]
VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE URST SADR SCFG SUSP WDST
<Address: 30H>
RDST CMPL SERR
Name VBSE VBUS interrupts enabled RSME Resume interrupts enabled SOFE Frame number refresh interrupts enabled DVSE Device state transition interrupts enabled CTRE
Function Interrupt output disabled Interrupt output enabled Interrupt output disabled Interrupt output enabled Interrupt output disabled Interrupt output enabled Interrupt output disabled Interrupt output enabled Interrupt output disabled
Note 2.7.1 2.7.8 3.2.9 2.7.1 2.7.8 3.2.10 2.7.1 3.2.8 2.7.1 2.7.2 3.2.6 2.7.1 2.7.3 3.2.7 2.7.1 3.2.5 2.7.1 3.2.4 2.7.1 3.2.3 2.7.2 3.2.6
Control transfer stage transition interrupts enabled Interrupt output enabled
BEMPE Interrupt output disabled Buffer Empty interrupts enabled Interrupt output enabled NRDYE Interrupt output disabled Buffer Ready response interrupts enabled Interrupt output enabled BRDYE Interrupt output disabled Buffer Ready interrupts enabled Interrupt output enabled URST DVST interrupt disabled transition Default state transition notifications enabled default state DVST interrupt enabled transition default state DVST interrupt disabled transition SADR Address state transition notifications enabled address state DVST interrupt enabled transition address state SCFG DVST interrupt disabled transition Configuration state transition notifications configuration state enabled DVST interrupt enabled transition configuration state SUSP DVST interrupt disabled. transition Suspend state transition notifications enabled suspend state DVST interrupt enabled transition suspend state WDST CTST interrupt disabled transition Control write transfer status stage transition status stage control write transfer notifications enabled CTST interrupt enabled transition status stage control write transfer RDST CTST interrupt disabled transition Control read transfer status stage transition status stage control read transfer notifications enabled CTST interrupt enabled transition status stage control read transfer CMPL CTST interrupt disabled Control transfer notifications enabled control transfer CTST interrupt enabled control transfer SERR CTST interrupt disabled detection Control transfer sequence error notifications control transfer sequence error enabled CTST interrupt enabled detection control transfer sequence error
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2.7.2 3.2.6
2.7.2 3.2.6
2.7.2 3.2.6
2.7.3 3.2.7
2.7.3 3.2.7
2.7.3 3.2.7
2.7.3 3.2.7
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<<Note>> None particular Interrupt enabled register 1[INTENB1]
BCHGE DTCHE SIGNE SACKE
<Address: 32H>
BRDYM INTL PCSE
Name
Function
Note 2.7.1 2.7.4 2.7.8 3.2.11 2.7.1 2.7.5 3.2.12 *1), 2.7.1 2.7.6 3.2.14 2.7.1 2.7.7 3.2.13 3.2.1
Nothing placed here. These should fixed "0". BCHGE Interrupt output disabled change interrupt enabled Interrupt output enabled
Nothing placed here. This should fixed "0". DTCHE Full-Speed detach detect interrupt enabled Interrupt output disabled Interrupt output enabled
11-6 Nothing placed here. This should fixed "0". SIGNE Interrupt output disabled Setup transaction error detect interupt Interrupt output enabled enabled SACKE Setup transaction complete interrupt enabled Interrupt output disabled Interrupt output enabled
Nothing placed here. This should fixed "0". BRDYM Software clears BRDY interrupt status BRDY interrupt status clear timing control controller clears BRDY interrupt status INTL Edge sensing Interrupt output sensing control Level sensing PCSE resume detectionm, VBUS interrupt returning fact selection from low-power detection during suspend, CS_N signal sleep mode input resume detectionm, VBUS interrupt detection during suspend
<<Notes>> DTCHE, SIGNE, SACKE effective only time Host mode. DTCHE effective only time Full-Speed mode. Please perform detach detection S/W, such detecting ignore packet from peripheral device time Hi-Speed mode. When software sets "BRDYM=1", will "INTL=1" also. PCSE shoud after "USBE=1" setting.
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BRDY interrupt enabled register [BRDYENB]
<Address: 36H>
PIPEBRDYE
Name
Function
Note 2.7.1 3.2.3
15-8 Nothing placed here. These should fixed "0". PIPEBRDYE Interrupt output disabled BRDY interrupts each pipe Interrupt output enabled enabled. <<Note>> numbers correspond pipe numbers.
NRDY interrupt enabled register [NRDYENB]
<Address: 38H>
PIPENRDYE
Name
Function
Note 2.7.1 3.2.4
15-8 Nothing placed here. These should fixed "0". PIPENRDYE Interrupt output disabled NRDY interrupts each pipe Interrupt output enabled enabled. <<Note>> numbers correspond pipe numbers.
BEMP interrupt enabled register [BEMPENB]
<Address: 3AH>
PIPEBEMPE
Name
Function
Note 2.7.1 3.2.5
15-8 Nothing placed here. These should fixed "0". PIPEBEMPE Interrupt output disabled BEMP interrupts each pipe Interrupt output enabled enabled. <<Note>> numbers correspond pipe numbers.
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2.7.1
Interrupt masks
VBSE, RSME, SOFE, DVSE, CTRE, BEMPE, NRDYE, BRDYE bits INTENB0 register BCHGE, DTCHE, SIGNE, SACKE INTENB1 register operate interrupt mask bits. Each bits should used specify whether interrupt signal output enabled disabled INT_N pin. BRDYENB register, NRDYENB register BEMPENB register operate BRDY interrupt mask bit, NRDY interrupt mask bit, BEMP interrupt mask bit, respectively, each corresponding pipe.
2.7.2
Device state transition interrupts
URST, SADR, SCFG, SUSP bits INTENB0 register operate interrupt mask bits device state transition interrupt (DVST). factor disabled, device state transition interrupt issued response pertinent factor. However, device state (DVSQ) transits keeping with circumstances. This function effective only time peripheral mode.
2.7.3
Control transfer stage transition interrupts
WDST, RDST, CMPL SERR bits INTENB0 register should used interrupt factors control transfer stage transition interrupt (CTRT). factor disabled, control transfer stage transition interrupts issued response pertinent factor. This function effective only time peripheral mode.
2.7.4
change interrupt
Interruption generated when state changes. This interruption enable with BCHGE INTENB1 register. This interruption used peripheral connection detection remote wakeup signal Host mode. Please enable interruption during communication time "UACT=1" setup). change interruption generated whichever chosen Host Peripheral mode.
2.7.5
Full-Speed detach detect interrupt
When Host mode, interruption generated when peripheral device detached time Full-Speed mode. This interruption enable with DTCHE INTENB1 register.
2.7.6
Setup transaction error detect interupt
Interruption generated when packet from peripheral device isn't able received time sending setup transaction Host mode. This interruption enable with SIGN INTENB1 register.
2.7.7
Setup transaction complete interrupt
Interruption generated when packet from peripheral device received time sending setup transaction Host mode. This interruption enable with SACKE INTENB1 register.
2.7.8
Operations low-power sleep state
VBSE, RSME, BCHG interrupts generated low-power sleep state well.
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control register
configuration register [SOFCFG]
<Address: 3CH>
SOFM
Name
Function
Note 3.10.1 *1),*2)
15-4 Nothing placed here. These should fixed "0". SOFM This selects pulse output mode. function setting pulse output disabled pulse output units uSOF output units Reserved Nothing placed here. These should fixed "0".
<<Notes>> With Full-Speed operation, (when "HSE=0" been set, RHST indicates "RHST=0" result reset handshake), "SOFM=10" should set. This should after reset handshake been completed, when recovering from low-power sleep state, should changed during subsequent communication.
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Interrupt statuses
Interrupt status register 0[INTSTS0]
VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS DVSQ
<Address: 40H>
VALID CTSQ
Name
Function VBUS interrupts issued VBUS interrupts issued
Note 3.2.9 3.2.10 3.2.10 3.2.8 3.2.6 3.2.7
VBINT VBUS interrupt status RESM Resume interrupt status SOFR Frame number refresh interrupt status DVST Device state transition interrupt status CTRT Control transfer stage transition interrupt status BEMP Buffer Empty interrupt status NRDY Buffer Ready interrupt status BRDY Buffer Ready interrupt status VBSTS VBUS input status DVSQ Device state
Resume interrupts issued Resume interrupts issued interrupts issued R/W(0) interrupts issued Device state transition interrupts issued R/W(0) Device state transition interrupts issued Control transfer stage transition interrupts R/W(0) issued Control transfer stage transition interrupts issued BEMP interrupts issued BEMP interrupts issued NRDY interrupts issued NRDY interrupts issued BRDY interrupts issued BRDY interrupts issued VBUS level VBUS level 000: Powered state 001: Default state 010: Address state 011: Configured state 1xx: Suspended state detected Setup packet reception 000: Idle setup stage 001: Control read data stage 010: Control read status stage 011: Control write data stage 100: Control write status stage 101: Control write (NoData) status stage 110: Control transfer sequence error 111: Reserved R/W(0)
3.2.5 3.2.4 3.2.3 3.2.9 3.2.6
VALID Setup packet reception CTSQ Control transfer stage
3.2.7 3.2.7
<<Note>> BEMP, BRDY NRDY bits cleared when factors each pipe correcponding registers have been eliminated, i.e. BEMPSTS, BRDYSTS NRDYSTS. VBUS input status based VBSTS requires that chattering eliminated using software. multiple factors being generated among VBINT, RESM, SOFR, DVST, CTRT bits, access cycle least required order clear bits succession, rather than simultaneously.
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Interrupt status register 1[INTSTS1]
BCHG SOFR DTCH BEMP NRDY BRDY SIGN
<Address: 42H>
SACK
Name
Function
R/W(0)
Note 3.2.11 3.2.8 2.9.1 3.2.12 *4),*5) 2.9.1 3.2.5 2.9.1 3.2.4 2.9.1 3.2.3
Nothing placed here. These should fixed "0". BCHG BCHG Interrupts issued change interrupt status BCHG Interrupts issued SOFR This mirror SOFR bit. Frame number refresh interrupt status Interrupts issued Interrupts issued DTCH DTCH Interrupts issued Full-Speed detach detect interrupt status DTCH Interrupts issued Nothing placed here. This should fixed "0". BEMP This mirror BEMP bit. Buffer Empty interrupt status BEMP interrupts issued BEMP interrupts issued NRDY This mirror NRDY bit. Buffer Ready response interrupt NRDY interrupts issued status NRDY interrupts issued BRDY This mirror BRDY bit. Buffer Ready interrupt status BRDY interrupts issued BRDY interrupts issued Nothing placed here. This should fixed "0". SIGN SIGN interrupts issued Setup transaction error detect interrupt SIGN interrupts issued status SACK SACK interrupts issued Setup transaction complete interrupt SACK interrupts issued status Nothing placed here. This should fixed "0".
3.2.14 3.2.13
<<Notes>> DTCH, SIGN, SACK effective only time Host mode. DTCH effective only time Full-Speed mode. Please perform detach detection S/W, such detecting ignore packet from peripheral device time Hi-Speed mode.
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BRDY interrupt status register [BRDYSTS]
PIPEBRDY
<Address: 46H>
Name
Function
Note 3.2.3
15-8 Nothing placed here. These should fixed "0". PIPEBRDY Interrupts issued. BRDY interrupt status theeach pipe Interrupts issued.
R/W(0) W(1)
<<Note>> numbers correspond pipe numbers. Also, factors being generated more than pipe, access cycle least required order clear bits succession, rather than simultaneously.
NRDY interrupt status register [NRDYSTS]
<Address: 48H>
PIPENRDY
Name
Function
Note 3.2.4
15-8 Nothing placed here. These should fixed "0". PIPENRDY Interrupts issued. NRDY interrupt each pipe Interrupts issued.
R/W(0) W(1)
<<Note>> numbers correspond pipe numbers. Also, factors being generated more than pipe, access cycle least required order clear bits succession, rather than simultaneously.
BEMP interrupt status register [BEMPSTS]
<Address: 4AH>
PIPEBEMP
Name
Function
Note 3.2.5
15-8 Nothing placed here. These should fixed "0". PIPEBEMP Interrupts issued. BEMP interrupt each pipe Interrupts issued.
R/W(0) W(1)
<<Note>> numbers correspond pipe numbers. Also, factors being generated more than pipe, access cycle least required order clear bits succession, rather than simultaneously.
2.9.1
Mirror bits INTSTS0 registor INTSTS1
SOFR, BEMP, NRDY, BRDY INTSTS1 register mirror bits INTSTS0 register. When software reads, same value same INTSTS0 register read. When writes, same value same INTSTS0 register written
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2.10 Frame number register
Frame number register [FRMNUM]
OVRN CRCE SOFRM FRNM
<Address: 4CH>
Name
Function
Note 2.10.1 2.10.1
OVRN error R/W(0) Overrun Underrun Error issued CRCE error R/W(0) Reception data error Error issued 13-12 Nothing placed here. These should fixed "0". SOFRM Interrupt asserted upon reception Frame number update interrupt mode timer interpolation. Interrupt asserted damaged missing. 10-0 FRNM frame number confirmed. Frame number
2.10.2 3.2.8 2.10.2
<<Note>> Frame number update interrupts issued uSOF packet detection other than "UFRNM=0".
micro frame number register [UFRMNUM]
<Address: 4EH>
UFRNM
Name
Function
Note 2.10.2
15-3 Nothing placed here. These should fixed "0". UFRNM micro frame number confirmed. micro frame <<Note>> When using Full-Speed operation, "000" normally read with this bit.
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2.10.1 Isochronous errors
With this controller, data transfer errors that occur isochronous transfers confirmed using OVRN CRCE FRMNUM register. isochronous transfers, error notification NRDY interrupt differentiated using OVRN CRCE between data buffer errors packet errors. Table Table 2.10 show conditions under which OVRN CRCE "1".
Table Error information when NRDY interrupt issued isochronous transfer reciving direction
status "OVRN=1" Issued when: Data packet received Data packet received Issue conditions Detected error data packet received Reception data buffer overrun before reading buffer memory completed error, stuffing Received packet error error detected Operation data packet thrown data packet thrown
"CRCE=1"
Table 2.10 Error information when NRDY interrupt issued isochronous transfer sending direction
status "OVRN=1" Issued when: token received issued Issue conditions Detected error Operation in-token received before Transmission data buffer Zero-Length packet underrun transmission writing buffer memory completed
"CRCE=1"
2.10.2 interrupts frame numbers
SOFR interrupt operation mode should selected using SOFRM FRMNUM register. Also, current frame number confirmed using FRNM FRMNUM register UFRNM UFRNUM register. peripheral mode, with this controller, frame numbers refreshed timing which packets received. controller unable detect packet because packet been corrupted, another reason, FRNM value retained until packet received. that point, FRNM based interpolation timer refreshed. Also, UFRNM incremented response uSOF packet being received.
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2.11 address (low-power recovery)
address/low-power status recovery register [RECOVER]
STSRECOV
<Address: 50H>
USBADDR
Name
Function
Note 3.1.7 *1),*2)
15-11 Nothing placed here. These should fixed "0". 10-8 STSRECOV Status recovery after low-power sleep state Status recovery 000: reserved 001: Full-Speed Default state 010: Full-Speed Address state 011: Full-Speed Configured state 100: reserved 101: Hi-Speed Default state 110: Hi-Speed Address state 111: Hi-Speed Configured state Nothing placed here. This should fixed "0". USBADDR address confirmation recovery address
3.1.7 *1),*2)
<<Notes>> When recovery been made from low-power sleep state normal mode, communication speed, device state address have returned values backed control program software. "STSRECOV=x00" should set. RECOVER register effective only time peripheral mode. When operating host mode, peripheral address should DEVSEL PIPEMAXP register.
2.12 request register
request register used store setup requests control transfers. values requests that have been received stored here when peripheral mode selected. requests sent should here when host mode selected. request type register [USBREQ]
bRequest
<Address: 54H>
bmRequestType
15-8 bRequest Request
Name
Function
peripheral mode:W Host mode:R peripheral mode:W Host mode:R
Note 3.6.1 3.6.2 3.6.1 3.6.2
bmRequestType Request type <<Note>> None particular
request bRequest value peripheral stored here. mode:R Host mode:R/W request bmRequestType peripheral stored here. mode:R Host mode:R/W
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request value register [USBVAL]
wValue
<Address: 56H>
15-0 wValue Value <<Note>> None particular
Name
Function request wValue value stored here.
Note 3.6.1 3.6.2
peripheral peripheral mode:R mode:W Host mode:R/W Host mode:R
request index register [USBINDX]
Windex
<Address: 58H>
15-0 wIndex Index <<Note>> None particular
Name
Function request wIndex value stored here.
Note 3.6.1 3.6.2
peripheral peripheral mode:R mode:W Host mode:R/W Host mode:R
request length register [USBLENG]
wLength
<Address: 5AH>
15-0 wLength Length <<Note>> None particular
Name
Function request wLength value stored here.
Note 3.6.1 3.6.2
peripheral peripheral mode:R mode:W Host mode:R/W Host mode:R
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2.13 configuration
When data communication being carried using control transfers, default control pipe should used. configuration register [DCPCFG] <Address: 5CH>
CNTMD
Name
Function
Note 3.4.1 3.6.1
15-9 Nothing placed here. These should fixed "0". CNTMD Non-continuous transfer mode Continuous transfer mode Continuous transfer mode Nothing placed here. These should fixed "0". Control transfer direction host mode. Transfer direction Receiving (Control read data stage Control write status stage) Sending (Control write data stage Control read status stage) Nothing placed here. These should fixed "0".
<<Notes>> Because buffer memory used both control read transfers control write transfers, CNTMD will serve common both, regardless transfer direction. This should peripheral mode. maximum packet size register [DCPMAXP]
DEVSEL
<Address: 5EH>
MXPS
15-14 DEVSEL Device select
Name
Function
Note 3.6.1
This specifies device adress Host mode. Address Address Address Address 13-7 Nothing placed here. These should fixed "0". MXPS This specifies maximum packet size Maximum packet size DCP.
<<Notes>> This should "00" peripheral mode. This should anything other than specification. Also, because b2-b0 bits fixed "0", writing these invalid.
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control register [DCPCTR]
BSTS SUREQ SQCLR SQSET SQMON
<Address: 60H>
CCPL
Name
Function
Note 3.4.1.1 3.6.1 *11)
Buffer access disabled. Buffer access enabled. SETUP packet transmitted setting this R/W(1) R/W(0) Invalid transmit SETUP packet 14-9 Nothing placed here. These should fixed "0". SQCLR Invalid R(0)/ Toggle Clear Specifies DATA0 W(1) SQSET Invalid R(0)/ Toggle Specifies DATA1 W(1) SQMON DATA0 Toggle Confirm DATA1 Nothing placed here. These should fixed "0". CCPL Invalid R(0)/ R/W(0) Control Transfer enabled control transfer ended. W(1) response Response response keeping with buffer state) STALL response STALL response
BSTS Buffer Status SUREQ Request transmit SETUP packet
*7),*8) *7),*8) 3.6.2 *10)
<<Notes>> direction buffer access, writing reading, depend setting ISEL bit. peripheral mode CCPL cleared right after SETUP token been received. host mode this should "CCPL=0"(not use). SQSET bits SQCLR bits DCPCTR register PIPExCTR registers being changed succession (the sequence toggle bits multiple pipes being changed succession), access cycle least required. SQCLR SQSET should both same time. Before operating either bit, "PID=NAK" should set. Peripheral mode SQMON initialized controller right after SETUP token control transfer been received. *10) peripheral mode cleared "00" right after SETUP token been received. time occurring transmission error etc., bits controller transmission ended. *11) When SUREQ after SETUP transaction sending out. While SUREQ write USBREQ, USBVAL, USBINDX, USBLENG register.
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2.14 Pipe configuration register
PIPE1-7 settings should using PIPESEL, PIPECFG, PIPEBUF, PIPEMAXP, PIPEPERI, PIPExCTR registers. After selecting pipe using PIPESEL register, functions pipe using PIPECFG, PIPEBUF, PIPEMAXP PIPEPERI registers. PIPExCTR register separately from pipe selection specified with PIPESEL register, with relation between them. reset, reset, reset, when shifting low-power sleep state, pertinent bits only selected pipe, pipes initialized. Pipe window selection register [PIPESEL]
<Address: 64H>
PIPESEL
Name
Function
Note
15-3 Nothing placed here. These should fixed "0". PIPESEL 000: selected Pipe window selection 001: Pipe 010: Pipe 011: Pipe 100: Pipe 101: Pipe 110: Pipe 111: Pipe
<<Note>> When"PIPESEL=000" set, read from bits five related registers noted above.
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Pipe configuration register [PIPECFG]
TYPE BFRE DBLB CNTMD SHTNAK
<Address: 66H>
EPNUM
15-14 TYPE Transfer type
Name
Function Pipe disabled Bulk transfer Interrupt transfer Isochronous transfer
Note
13-11 Nothing placed here. These should fixed "0". BFRE BRDY interrupt upon sending receiving BRDY interrupt operation specified data BRDY interrupt upon reading data DBLB Single buffer Double buffer mode Double buffer CNTMD Non-continuous transfer mode Continuous transfer mode Continuous transfer mode SHTNAK Pipe continued transfer Pipe disabled transfer Pipe disabled transfer Nothing placed here. These should fixed "0". Receiving (OUT transfer) Transfer direction Sending transfer) EPNUM Specifies point number pertinent point number pipe
3.4.3.6 3.4.1.5 3.4.1.6
<<Notes>> pipe number selected PIPESEL PIPESEL register, value follows. When using PIPE1-5, this select "TYPE=00", "TYPE=01", "TYPE=11". When using PIPE6-7, this should "TYPE=10". "BFRE=1" set, BRDY interrupts generated when buffer data writing direction. DBLB valid when PIPE1-5 selected. procedure change DBLB PIPE following; Single buffer double buffer ("DBLB=0" "DBLB="1"); "NAK" pertinent pipe "ACLRM=1" (wait least 100ns) "ACLRM=0" "DBLB="1" "BUF" pipe Double buffer singlee buffer ("DBLB=1" "DBLB="0"); "NAK" pertinent pipe "DBLB="0" "ACLRM=1" (wait least 100ns) "ACLRM=0" "BUF" pipe CNTMD valid when bulk transfer ("TYPE=01") selected using PIPE1-5. "CNTMD=1" should when isochronous transfer been selected ("TYPE=11"). CNTMD should PIPE6-7.
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Pipe buffer setting register [PIPEBUF]
BUFSIZE
<Address: 68H>
BUFNMB
Name
Function
Note 3.4.1 3.4.1
Nothing placed here. This should fixed "0". 14-10 BUFSIZE Specifies size pertinent pipe. Buffer Size (from bytes 0x1F: 2KB) Nothing placed here. These should fixed "0". BUFNMB Specifies buffer number pertinent Buffer Number pipe.(From 0x5F)
<<Notes>> valid value BUFSIZE depends selected PIPE PIPESEL PIPESEL register. When using PIPE1-5, this select "BUFSIZE=00-1F" When using PIPE6-7, writing this invalid. BUFNMB match user system when PIPE1-5 selected. "BUFNMB=0-3"is used exclusively DCP."BUFNMB=4-5"is allocated PIPE6-7. When using PIPE6, writing this invalid, "BUFNMB=4" always used reading. When using PIPE7, writing this invalid, "BUFNMB=5" always used reading. Pipe maximum packet size register [PIPEMAXP]
DEVSEL MXPS 0(1)*9) 0(1) 0(1)
<Address: 6AH>
DEVSEL Device select
Name
Function
Note
This specifies device adress Host mode. Address Address Address Address Nothing placed here. These should fixed "0". 10-0 MXPS Specifies maximum packet size Maximum Packet Size pertinent pipe.
*9), *10)
<<Note>> This should "00" peripheral mode. MXPS should to"0x00", setting defined specification should used. *10) default value MXPS "0x0" when "PIPSEL=0", "0x40" when select "PIPESEL>0".
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Pipe timing control register [PIPEPERI]
IFIS
<Address: 6CH>
IITV
Name
Function
Note 3.9.5
15-13 Nothing placed here. These should fixed "0". IFIS buffer flushed. Isochronous buffer flush buffer flushed. 11-3 Nothing placed here. These should fixed "0". IITV Specifies interval timing IITV-th power Interval error detection spacing
3.9.3 *11)
<<Note>> *11) peripheral mode IITV valid only when isochronous transfer selected. only when PIPE1-2 selected. OUT-direction: interval error occurs upon NRDY interrupt caused token having been issued. IN-direction: When controller doesn't receive IN-token until time indicated IITV bit, detects interval error flushs buffer. host mode IITV valid only when isochronous interrupt transfer selected. IITV controls interval transaction.
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PIPE1 control register [PIPE1CTR] PIPE2 control register [PIPE2CTR] PIPE3 control register [PIPE3CTR] PIPE4 control register [PIPE4CTR] PIPE5 control register [PIPE5CTR] PIPE6 control register [PIPE6CTR] PIPE7 control register [PIPE7CTR]
BSTS INBUFM ACLRM SQCLR SQSET SQMON
<Address: 70H> <Address: 72H> <Address: 74H> <Address: 76H> <Address: 78H> <Address: 7AH> <Address: 7CH>
Name
Function
Note 3.4.1.1 *12) 3.4.1.1 *13), *14)
Buffer access disabled. Buffer access enabled. data which transmitted buffer data which transmitted buffer memory. 13-10 Nothing placed here. These should fixed "0". Disabled ACLRM Auto Buffer Clear mode Enabled (all buffers initialized) SQCLR Invalid Toggle Clear Specifies DATA0 SQSET Invalid Toggle Specifies DATA1
BSTS Buffer Status INBUFM Sending buffer status monitor
SQMON DATA0 Toggle Confirm DATA1 Nothing placed here. These should fixed "0". response Response response keeping with buffer state) *18) STALL response STALL response <<Notes>> *12) direction buffer access, writing reading, depend setting PIPECFG register. *13) INBUFM valid when softwware sets Sending-direction. *14) INBUFM valid PIPE1-5. *15) Software should "ACLRM=1" PIPE whith selected CURPIPE CFIFOSEL, DxFIFOSEL register. After "ACLRM=1", when setting "ACLRM=0", Software need wait lease 100ns. *16) SQCLR bits SQSET bits DCPCTR register PIPExCTR registers being used change data sequence toggle several pipes succession, access cycle least required. *17) SQCLR SQSET should both same time. Before operating either bit, "PID=NAK" should set. *18) operation follows, when setting PID=BUF. Host mode transmitting direction (OUT). transaction issued when there transmitting data buffer. transaction issued when there transmitting data buffer. Host mode receiving direction (IN). transaction issued when there receiving data buffer. transaction issued when there receiving data buffer. Peripheral mode transmitting direction (OUT). response receiving data when there receiving data buffer. response carried token, when there receiving data buffer. Peripheral mode receiving direction (IN). Data transmitted token. response carried token, when there transmitting data buffer. time occurring transmission error etc., bits controller transmission ended.
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R(0)/ R/W(0) 3.4.1.4 W(1) *15) R(0)/ 3.3*16), W(1) *17) R(0)/ W(1) *16), *17)
M66596FP/WG
Description
Operation
System control oscillation control
This chapter describes register operations that necessary default settings controller, registers necessary power consumption control.
3.1.1
Resets
Table shows table controller resets. information initialized states registers following various reset operations, please refer Chapter Registers.
Table Types Resets
Name reset reset reset Operation level input from RST_N Operation using USBE SYSCFG register Automatically detected controller from lines Peripheral mode
3.1.2
interface settings
Table shows interface settings controller.
Table interface settings
Register name PINCFG PINCFG DMAxCFG DMAxCFG DMAxCFG DMAxCFG INTENB1 name LDRV BIGEND DREQA DACKA DENDA OBUS INTL Setting contents Control setting drive current Byte Endian setting being connected This effective access FIFO register Active setting DREQx_N Active setting DACKx_N Active setting DENDx_N OBUS mode setting Output sensing setting INT_N
3.1.3
Selection function
This controller select either Host function Peripheral function software. select function controller, DCFM SYSCFG register. Changing DCFM (writing access) should done with internal clock stopped ("SCKE=0").
3.1.4
Enabling Hi-Speed operation
With this controller, either Hi-Speed operation Full-Speed operation selected communication speed (communication rate), using software. enable Hi-Speed operation controller, SYSCFG register "1". Changing should done with internal clock stopped ("SCKE=0"). Hi-Speed operation been enabled, controller executes reset handshake protocol, communication speed automatically. results reset handshake confirmed using RHST DVSTCTR register. Hi-Speed operation been disabled, controller will Full-Speed operation.
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3.1.5
data resistor control
Figure shows diagram connections between controller connectors. Peripheral mode, controller built-in pull-up resistor signal. should DPRPU SYSCFG register, then line pulled pull-up power supply AFE33V. Host mode, controller built-in pull-down resistor signals. should DPRPD SYSCFG register, then lines pulled down. Also, controller built-in terminal resistor when signals operating Hi-Speed, built-in output resistor Full-Speed operation. controller automatically switches built-in resistor after connection with means reset handshake, suspended state resume detection. disconnection from detected, should initialized means reset (USBE=0). DPRPU SYSCFG register Peripheral mode, pull-up resistor terminal resistor) data line disabled, making possible notify host controller device disconnection.
Impedance control taken into consideration when designing lines.
M66596
VBUS
Host mode)
RERFIN 5.6K
Vbus
connector
Figure connector connections
3.1.6
Clock supply control
Figure shows block diagram controller clock control. Frequency input clock should selected using XTAL SYSCFG register, while oscillation buffer enabled using XCKE clock supply controlled using RCKE, PLLC, SCKE bits. information register control timing, please refer 3.1.8, State transition timing.
Clock control unit
XCKE (bit13) RCKE (bit12) PLLC, SCKE (bit11, bit10)
Input clock
Oscillation buffer Low-power control
Divider circuit Auto clock supply
Internal clock
PCUT (bit1)
ATCKM (bit8)
Figure Clock control block
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3.1.7 power consumption control 3.1.7.1 Overview Low-power sleep state
order reduce power consumption, controller equipped with function setting low-power sleep state. Controlling clock low-power sleep state enables reduced power consumption when communication being carried out, such suspended state disconnected state. order coordinate relationship between controller clock supply being enabled disabled low-power sleep state, values shown Table indicate correspondence between controller state value SYSCFG register, while Figure shows transitions controller state. timing which transitions between various states take place, register control timing, please refer 3.1.8
Table Correspondence between controller state SYSCFG register value
Controller state reset Values various SYSCFG register bits XTAL=0, XCKE=0, RCKE=0, PLLC=0, SCKE=0, ATCKM=0, HSE=0, DPRPD=0, DPRPU=0, FSRPC=0, PCUT=0, USBE=0 XTAL=xx *1), XCKE=1, RCKE=1, PLLC=x *1), SCKE=1, ATCKM=x *1), HSE=x *1), DPRPD=x*1), DPRPU=x *1), FSRPC=x *1), PCUT=0, USBE=1 XTAL=xx *1), XCKE=0, RCKE=0, PLLC=0, SCKE=0, ATCKM=x *1), HSE= *1), DPRPD=x*1), DPRPU=x *1), FSRPC=x *1), PCUT=1, USBE=1 Explanation
Normal operating state
Low-power sleep state
this state, clock supplied controller, communication enabled. this state, communication carried out, such when communication suspended cable disconnected.
indicates that value user retained.
reset Default setting Attached Normal operating state Resume, attached Figure Controller state transitions (using low-power sleep state)
Hsot mode, Remote Wake signal received when suspend state, necessary supply internal clock (SCKE) within after signal detection, start resume signal output. this reason, when enable Remote Wake stop internal clock, setup Low-power sleep state.
Suspended, detached Low-power sleep
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3.1.7.2 Overview Clock stop state
This controller equipped with setting function power consumption state clock stop well M66291, M66591, M66592. Software transplantable this controller from M66291, M66591, M66592 fewer changes. states where controller communicating such suspend connect state, power consumption clock stop realized. Correspondence state controller value SYSCFG register shown Table 3.4. transitions controller state shown Figure 3.4.For timing which transitions between various states take place, register control timing, please refer 3.1.8. Moreover, when power consumption state clock stop, please auto clock supply function ("ATCKM=1").
Table Correspondence betweek controller state SYSCFG register value
Values various SYSCFG register bits Normal operating state XTAL=xx *1),XCKE=1,RCKE=1,PLLC=x *1),SCKE=1,ATCKM=1,HSE=x USBE=1 Clock stop state XTAL=xx ,HSE= =0,USBE=1 indicates that value user retained. Controller state reset Explanation
this state, clock supplied controller, communication enabled. this state, communication carried out, such when communication suspended cable disconnected.
reset Default setting, Attached
Suspend, Detached Clock stop Resume, Attached
Normal operating state
Figure Controller state transitions(Clock stop mode)
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3.1.7.3 Low-power sleep state
low-power sleep state setting PCUT SYSCFG register. information sequence which settings entered low-power sleep state, please refer Chapter 3.1.8.2 information register control timing, please refer timing diagram noted later (Figure Low-power control timing diagram). low-power sleep state, registers software, only registers other than those noted below initialized. After returning normal operating state, settings must re-entered using software. Table shows registers that initialized when controller low-power sleep state.
Table Registers that initialized low-power sleep state
Register SYSCFG XTAL ATCKM DCFM DMRPD DPRPU FSRPC USBE LDRV DREQA VBSE VBINT RSME RESM INTENB1/ INTSTS1 BCHGE BCHG Description This retained system information. This retained system information. This retained system information. This retained system information. This retained system information. This retained system information. This retained system information. This retained system information. state output drive current settings retained. polarity DREQ0_N DREQ1_N retained. When "VBSE=1", there change VBUS signal low-power sleep state, INT_N asserted notification made CPU. When "RSME=1", there change data low-power sleep state, INT_N asserted notification made CPU. When "BCHGE=1", there change data low-power sleep state, INT_N asserted notification made CPU.
PINCFG DMAxCFG INTENB0/ INTSTS0
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3.1.7.4 Recovering from low-power sleep state
events noted below occurs from low-power sleep state, controller notifies through INT_N pin. interrupt factor related those events should enabled, before sofware sets controller low-power sleep state. VBUS detection change VBUS detected low-power sleep state RESUME detection change state (J-State K-State SE0)was detected when state shifted from suspended state low-power sleep state Peripheral mode. CHANGE detection change state detected when state low-power sleep state state during suspended state When PCSE INTENB1 register "0", low-power sleep state also canceled operations noted below, controller returns normal operating state. Dummy writing 0x7E address controller actual writing done this address). When system returned from low-power sleep state normal state, some controller registers need returned values effect prior transition low-power sleep state. registers which settings have returned, special registers available that used re-setting data read-only registers. Table shows re-settings read-only registers which settings have returned.
Table Re-settings read-only registers which settings have returned
Register DVSTCTR INTSTS0 Method re-setting registers Setting communication speed device state using STSRECOV RECOVER register before shifting low-power sleep state recovers values RHST DVSQ bit. RECOVER USBADDR device address prior shift low-power sleep state USBADDR RECOVER register. PIPExCTR SQMON sequence toggle bits various pipes prior low-power sleep state using SQSET SQCLR PIPExCTR. SQMON DCPCTR register initialized when SETUP stage ends, necessary return state effect prior normal operating state. RHST DVSQ
3.1.7.5 Recovering from clock stop state
events noted below occurs from clock stop state, controller notifies through INT_N pin. interrupt factor related those events should enabled, before sofware sets controller clock stop state. VBUS detection change VBUS detected clock stop state. RESUME detection suspended state Peripheral mode change state (J-State K-State/SE0)was detected. CHAGE detection change state detected. used when detecting attach peripheral detach perripheral, Remote Wake Host mode.
3.1.7.6 Auto clock supply function
This controller equipped with auto clock supply function. With auto clock supply function, controller automatically implements series sequence control operations, from oscillation stabilization standby timing supply internal clock, when system returning from low-power sleep state from clock stop mode normal operating state. This function enbaled setting ATCKM SYSCFG register following events occur. information specific register control, please refer Chapter 3.1.8.3 RESUME detection suspended state Peripheral mode change state (J-State K-State/SE0)was detected. Software "XCKE=1" SYSCFG register.
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3.1.7.7 Oscillation enable Hardware
following cases, this controller enables oscillation automatically ("XCKE=1"). using accordance with automatic clock supply function, timing design easy. RESUME detection suspended state Peripheral mode change state (J-State K-State/SE0)was detected. Return from low-power sleep state
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3.1.8 State transition timing 3.1.8.1 Starting internal clock supply (from reset state normal operating state)
Figure shows diagram clock supply start control timing controller. transition from reset state normal operating state should done through operation bits timing noted below. Software enables oscillation buffer. "XCKE=1" Software waits oscillation stabilize. (The oscillation stabilization time varies depending oscillator.) Software enables reference clock suppliance "RCKE=1", "PLLC=1" operation Software waits lock. waiting time least necessary.) Software enables internal clock suppliance. "SCKE=1"
Start internal clock supply procedure Approximately (varies depending oscillation probe) 8.3us
XCKE RCKE PLLC SCKE PCUT
Figure Clock supply start control timing 3.1.8.2 Stopping internal clock supply (from normal operating state low-power sleep state)
Figure shows diagram low-power control timing from normal operating state low-power sleep state. transition from normal operating state low-power sleep state should done through operation bits timing noted below. Software disables internal clock suppliance. "SCKE=0" Software waits until internal clock stops. waiting time least necessary.) Software disables PLL. "PLLC=0" Software waits stop. waiting time least necessary.) Software disables reference clock suppliance. "RCKE=0" Software waits until reference clock stops. waiting time least necessary.) Software sets low-power sleep state. "PCUT=1" controller disables oscillation buffer. "XCKE=0(H/W)" software must XCKE "0".
Start transit power state XCKE(H/W) RCKE PLLC SCKE PCUT
300ns 300ns
300ns
Figure Transition control timing low-power sleep state
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3.1.8.3 Starting internal clock supply (from low-power sleep state normal operating state: Auto clock supply function enabled)
Figure shows diagram timing which transition from low-power sleep state normal operating state takes place when auto clock supply function enabled ("ATCKM=1"). When auto clock supply function enabled, controller carries register control, after interrupt generated, transition normal operating state completed simply waiting amount time that access disabled. operation registers using softwear necessary. Peripheral mode when operation been resumed from suspended state using Reset signal, necessary recover normal operating state within after data line change been detected that controller begin reset handshake protocol. When auto clock supply function enabled, controller waits automatically oscillation stabilize then carries clock supply control handles reset handshake. Because there signal output time Reset signal Resume signal, control program provided with plenty allowance process recovery normal state. recovery sequence when auto clock supply function enabled shown below. interrupt generated recover from low-power sleep state, INT_N asserted. (Or, control program writes dummy data 0x7E address cause controller recover.) same time, controller automatically enables oscillation buffer. "XCKE=1(H/W)" softwear directs system wait until access enabled. waiting time least necessary.) controller automatically enables RCKE, PLLC, SCKE. softwear resets registers that have been held state before going into low-power sleep state. Peripheral mode when system recovered from low-power sleep state normal operating state, communication speed device state recovery settings have STSRECOV RECOVER register, address USBADDR that register, recovery take place. auto clock supply function been enabled, however, recovery settings above bits should entered after DVSQ been confirmed. This because, recovery been made using Reset signal, there possibility that controller initialized device state address default state, which case rewriting register values waiting state will cause erroneous operation. recovery settings written RECOVER register using procedure outlined below. "DVSQ=000", recovery made method other than Reset signal. communication speed, device state, address should returned state they were prior shifting low-power sleep state, writing RECOVER register. "DVSQ=001", recovery made using Reset signal. recovery settings should entered writing RECOVER register. Also, low-power sleep state, there registers that initialized controller. When recovery been made normal operating state, initialized registers should reset match user system.
Low-power sleep state recovery (1),(2) (3)2.5ms (access disabled) XCKE(H/W) RCKE(H/W) PLLC(H/W) SCKE(H/W) PCUT(H/W) INT_N Event CS_N
Figure Recovery control timing from low-power sleep state with "ATCKM=1"
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3.1.8.4 Stopping internal clock supply (From normal operating state clock stop state)
timing diagram transition from normal operation state clock stop state controller shown Figure 3.8. transitions should operated according following sequence. Software disables internal clock suppliance. "SCKE=0" Software waits until internal clock stops. waiting time least necessary.) Software disables PLL. "PLLC=0" Software waits stop. waiting time least necessary.) Software disables reference clock suppliance. "RCKE=0" Software waits until reference clock stops. waiting time least necessary.) Software disables oscillation buffer. "XCKE=0" Start transit clock stop 300ns 300ns 300ns
XCKE RCKE PLLC SCKE
Figure Transition control timing clock stop state 3.1.8.5 Starting internal clock supply (From clock stop state normal operating state: with "ATCKM=1")
timing diagram from clock stop state normal operation state shown Figure 3.9. timing diagram case auto clock supply function enabled ("ATCKM=1"; recommended setting). this case, controller operates registers when resume signal detected. controller changes normal operation state waiting access prohibition time after resume interruption generated. register operation software required. VBUS interrupt occurs, softwear need enable oscillation buffer controller detects resume signal VBUS changes bus, INT_N asserted. When resume signal received, controller automatically enables oscillation buffer. "XCKE=1(H/W)" When VBUS change occurs, softwear needs enable oscillation buffer. "XCKE=1. softwear waits until access enabled. waiting time least necessary.) controller automatically enables RCKE, PLLC, SCKE during (3). Software performs resume processing depending interrupt factor, resume attachment. Clock stop (1),(2) recovery XCKE 2.5ms (access disabled) Resume :H/W VBUS chage :S/W
RCKE(H/W) PLLC(H/W) SCKE(H/W) INT_N Event CS_N
Figure Recovery control timing from clock stop state with "ATCKM=1"
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3.1.8.6 Starting internal clock (From clock stop state normal operating state with "ATCKM=0")
timing diagram from clock stop state normal operation shown Figure 3.10. diagram case auto clock supply function disabled ("ATCKM=0"). When auto clock supply function disabled, register control performed software. Softwear should operate registers according following sequence. controller detects resume attachment cable, INT_N asserted. When resume detected, controller automatically enables oscillation buffer. "XCKE=1(H/W)" When attachment cable detected, software enables oscillation buffer. "XCKE=1(S/W)" software waits oscillation stabilize. (The oscillation stabilization time varies depending oscillator.) software enables reference clock suppliance "RCKE=1", "PLLC=1" operation software waits lock. waiting time least necessary.) software enables internal clock suppliance. "SCKE=1" Software performs depending interrupt factor, resume attachment. When returns with reset signal from suspend state, necessary return normal operation state less than controller start reset handshake protocol. this reason, when auto clock supply function disabled, necessary perform processings oscillation stability waiting clock supply software within 3ms.
Clock stop recovery XCKE Resume :H/W VBUS chage :S/W RCKE(H/W) PLLC(H/W) SCKE(H/W) INT_N Event
(1),(2)
8.3us
Figure 3.10 Recovery control timing from clock stop state with "ATCKM=0"
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Interrupt functions
3.2.1 overview interrupt functions
Table shows interrupt functions controller.
Table Interrupt functions
VBINT RESM Interrupt name VBUS interrupt Resume interrupt Cause interrupt When change state VBUS input been detected (change both edge, "L""H", "L") When change state been detected suspended state (J-StateK-State J-StateSE0) <Host mode> When packet with different frame number been transmited <Peripheral mode> When "SOFRM=0" When packet with different frame number When "SOFRM=1" When controller detects corruption packet When device state transition been detected reset detected Suspend state detected Address request received Configuration request received When stage transition been detected control transmission Setup stage completed Control write transfer status stage transition Control read transfer status stage transition Control transfer completed Control transfer sequence error occurred When transmission data buffer memory been completed When excessive maximum packet size error been detected <Host Mode> When STALL token received from peripheral. When response from unreceivable(Pachet ignore). <Peripheral mode> When token been received there data that sent buffer memory When token been received there area which data stored buffer memory, reception possible When error stuffing error occurred isochronous transfer When buffer ready (reading writing enabled) When state changes. Please enable interruption during communication time "UACT=1" setup). change interruption generated whichever chosen Host Peripheral mode. When packet from peripheral device received time sending setup transaction Host mode. When packet from peripheral device received time sending setup transaction Host mode.
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Mode Host, Peripheral Peripheral
Related status VBSTS
Note 3.2.9 3.2.10
SOFR
Frame Refresh interrupt
Host, Peripheral
3.2.8
DVST
Device State Transition interrupt
Peripheral
DVSQ
3.2.6
CTRT
Control Transfer Stage Transition interrupt
Peripheral
CTSQ
3.2.7
BEMP
Buffer Empty interrupt
Host, Peripheral
PIPEBE
3.2.5
NRDY
Buffer Ready interrupt
Host, Peripheral
PIPEN
3.2.4
BRDY BCHG
Buffer Ready interrupt change interrupt
Host, Peripheral Host, Peripheral
PIPEB
3.2.3 3.2.11
SACK SIGN
Setup Transaction complete Setup Transaction Error detect
Host Host
3.2.13 3.2.14
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DTCH
Full-Speed detach detect
When Host mode, interruption generated when peripheral device detached time Full-Speed mode. Please perform detach detection S/W, such detecting ignore packet from peripheral device time Hi-Speed mode.
Host
3.2.12
Table shows INT_N operations controller. multiple interrupt causes have occurred, method used INT_N output using INTL INTENB1 register. operation setting INT_N should match user system.
Table INT_N operations
INT_N operation INTL setting Edge sensing ("INTL=0") Level sensing ("INTL=1") When interrupt cause occurred level output until cause been eliminated level output until cause been eliminated When multiple interrupt causes occurred When cause eliminated, clock negated ("H" pulse output) MHz. level output until causes have been eliminated.
<Edge sensing>
Cause occurs Cause occurs Cause cleared Cause cleared
Interrupt cause
Interrupt cause INT_N
Negated interval
<Level sensing>
Cause occurs Cause occurs Cause cleared Cause cleared
Interrupt cause
Interrupt cause INT_N
Figure 3.11 INT_N operation
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Figure 3.12 shows diagram relating controller interrupts.
INTENB0
URST
INTENB0
VBSE
INTSTS0
SADR VBINT
reset detected Set_Address detected SCFG Set_Configuration detected SUSP Suspended state detected WDST Control Write Data Stage Control Read Data Stage Control Transfer Control Transfer Error Control Transfer Setup Receive
INT_N Edge Level Generation Circuit
RSME
RESM SOFE SOFR DVSE DVST CTRE CTRT BEMPE BEMP NRDYE NRDY BRDYE BRDY BCHGE BCHE DTCHE DTCH SIGNE SIGN SACKE SACK
RDST CMPL SERR
BEMPENB BEMPSTS
INTENB1
INTSTS1
NRDYENB NRDYSTS
BRDYENB BRDYSTS
Figure 3.12 Items relating interrupts
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3.2.2
Operation notes clock stop state
VBINT, RESM, BCHG generate interrupt status clock stop(include low-power sleep state) When clearing interrupt status VBINT, RESM, BCHG clock stop state, necessary write interrupt status register, then write further.
3.2.3
BRDY interrupt
BRDY interruption generated whichever chosen Host Peripheral mode. Table shows conditions under which controller sets pertinent BRDYSTS register. Under above condition, controller generats BRDY interrupt, software enables PIPERDYE BRDYENB register BRDYE INTENB0 register. Figure 3.13 shows timing which BRDY interrupts generated. conditions elimination BRDY INTSTS0 register depend setting BRDYM INTENB1 register. Table 3.10 shows conditions. Under conditions noted below Peripheral mode, Zero-Length packet sent token, BRDY interrupt generated. When "0x000" MXPS PIPEMAXP register pipe, transfer type pertinent pipe bulk
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Table Conditions under which BRDY interrupt generated
Access direction Reading Transfer direction Receive Pipe BFRE DBLB Conditions under which BRDY interrupt generated bellow; Short packet reception including Zero-Length packet reception Buffer full reception bellow; Short packet reception including Zero-Length packet reception Buffer full reception Transaction Counter when buffer full (1), (2), bellow conditions occur when both buffers waiting receiption
short packet reception including Zero-Length packet reception buffer full reception Transaction Counter when buffer full
Don't Care
Writing
Transmit
Reading complete buffer, when both buffer waiting reading Software "BCLR=1" clear buffer, when both buffer waiting reading Software "TGL=1", when side buffer data continuous transfer mode. (1), bellow Zero-Length packet reception After short packet reception, reading data packet complete. After Transaction Counter reading data last packet complete,. Doesn't take place (1), (2), bellow; Software direction transfer transmitting Packet transmission completed Software "ACLRM=1", when there data waiting transmitted Software "SCLR=1", when there data waiting transmitte (1), (2), (3), bellow; Software direction transfer transmitting Data enabled transmitted, when there buffer waiting transmitted. Data enabled transmitted,, when there buffer waiting transmitted.
buffer full writing Software "BVAL=1" enable buffer ready tarnsmit DMAC asserts DEND signal make buffer ready transmit
Don't Care
Software "ACLRM=1", when there data waiting transmitted Software "SCLR=1", when there data waiting transmitte Doesn't take place
Buffer full shows following cases. continuous mode ("CBTMD=1" setup), data buffer size received. continuous mode ("CNTMD=0") data packet size received.
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Zero-Length packet been received, pertinent BRDYSTS register goes "1", data pertinent packet cannot read. buffer should cleared ("BCLR=1") after clearing BRDYSTS register. With PIPE1-PIPE7, transfer being carried reading direction, interrupts generated transfer units, setting BFRE PIPECFG register.
Zero-Length packet reception Data packet reception using BFRE (Short Packet Transaction Counter Buffer Full) Token Packet Zero-Length Packet Short Data Packet Data Packet (Full) (Transaction Count) Handshake
BRDY interrupt
BRDY interrupt generated because reading from buffer enabled.
Data packet reception using BFRE (Short Packet Transaction Counter) Token Packet Short Data Packet Data Packet (Transaction Count) Handshake Buffer Read
BRDY interrupt generated because transfer ended.
BRDY interrupt
Packet transmission Buffer Write BRDY interrupt
BRDY interrupt generated because writing buffer enabled.
Token Packet
Data Packet
Handshake
Figure 3.13 Timing which BRDY interrupts generated
conditions which this controller clears BRDY INTSTS0 register change with setting values BRDYM INTENB1 register. BRDY clear conditions shown Table 3.10.
Table 3.10 Conditions elimination BRDY
BRDYM Conditions elimination BRDY When software clears enabled bits BRDYSTS register, controller clears BRDY bit. When controller clears BSTS bits which corresponding BRDY interrupt enebled pipe, controller clears BRDY bit.
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3.2.4
NRDY interrupt
Chapter 3.2.4.1 ,3.2.4.2 show conditions under which NRDY interrupts generated. cause NRDY various pipes should confirmed using pertinent NRDYSTS register. interrupt been disabled using NRDYE INTENB0 register, interrupt request pertinent NRDYSTS register. When bits NRDYSTS register cleared using user system control program, controller clears NRDY INTSTS0 register.
3.2.4.1 NRDY interrupt Host mode
followings generating conditions NRDY interruption Host mode. When STALL received from peripheral token which transmitted. When there response from peripheral token which transmitted. When Isochronous transfer, following errors occurred time transmission. stuffing error error packet size over error Over error, under error However, when controller doesn't receive packet SETUP transaction, controller generate SIGN interrupt.
3.2.4.2 NRDY interrupt Peripheral mode
followings generating conditions NRDY interruption Peripheral mode. data transmission token been received (data underrun) when PIPExCTR register "PID=BUF" there data sent buffer memory data reception token PING token been received (data overrun) when PIPExCTR control register "PID=BUF" there area buffer memory where data stored bulk transfer, when maximum packet size been ("MXPS=0") token PING token been received When error, stuffing error, interval error occurred during isochronous transfer When token recived other than interval frame duaring isochronous transfer. Figure 3.14 shows timing which controller generates NRDY interrupts.
Data transfer
NRDY interrupt
Data reception
Token Packet
Handshake
NRDY interrupt (CRC error, etc.) NRDY interrupt
Token Packet
Data Packet
Handshake
PING Packet
Handshake
Figure 3.14 Timing which NRDY interrupts generated
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3.2.5
BEMP interrupt
BEMP interruption generated whichever chosen Host Peripheral mode. (1), shows conditions under which BEMP interrupts generated. cause BEMP various pipes should confirmed using pertinent BEMPSTS register. interrupt been disabled using BEMPE INTENB0 register, interrupt request pertinent BEMPSTS register. When bits BEMPSTS register cleared softwear, controller clears BEMP INTSTS0 register. pipe under conditions such (1)(a), (1)(b), bellow, controller sets pertinent BEMPSTS register. this case, controller generats BEMP interrupt, software enables PIPENBEMPE BEMPENB register BEMPE INTENB0 register. When software clears enabled bits BEMPSTS register, controller clears BEMP bit. When sending direction (writing buffer memory) been When data stored buffer memory been sent double buffer being used buffer memory, however, following conditions observed. BEMP interrupt generated buffer side empty sending data from buffer opposite side been completed. BEMP interrupt generated data consisting less than eight bytes being written buffer side sending data from buffer opposite side been completed. BEMP interrupt generated data consisting eight bytes more being written buffer side sending data from buffer opposite side been completed. When receiving direction (reading buffer memory) been size data packet that received exceeded maximum packet size this point, other maximum packet size parameters were value other than ("MXPS0"), controller sets pertinent pipe "STALL". Figure 3.15 shows timing which BEMP interrupts generated.
Peripheral device data sending
BEMP interrupt
Peripheral device data
Token Packet
Data Packet
Handshake
BEMP interrupt
Token Packet
Data Packet
STALL Handshake
Figure 3.15 Timing which BEMP interrupts generated
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3.2.6
Device state transition interrupt
Figure 3.16 shows diagram controller device state transitions. Peripheral mode, controller controls device states generates device state transition interrupts. However, recovery from suspended state (Resume signal detection) detected means Resume interrupt. device state transition interrupt when interrupts enabled disabled individually, using INTENB0 register. Also, device state that underwent transition confirmed using DVSQ INTSTS0 register. When making transition default state, device state transition interrupt generated after reset handshake protocol been completed.
Suspended state detection (When SUSP="1", DVST "1") Powered State
(DVSQ="000")
Suspended State
(DVSQ="100")
Resume (RESM "1") reset detection (When URST="1", DVST "1") reset detection (When URST="1", DVST "1") Suspended state detection (When SUSP="1", DVST "1") Default State
(DVSQ="001")
Suspended State
(DVSQ="101")
Resume (RESM "1") SetAddress execution (Address=0) (When URST="1", DVST "1") SetAddress execution (When SADR="1", DVST "1") Suspended state detection (When SUSP="1", DVST "1") Address State
(DVSQ="010")
Suspended State
(DVSQ="110")
Resume (RESM "1") SetConfiguration execution (ConfigurationValue=0) (When SADR="1", DVST "1") SetConfiguration execution (ConfigurationValue?0) (When SCFG="1", DVST "1") Suspended state detection (When SUSP="1", DVST "1") Suspended State
(DVSQ="111")
Configured State
(DVSQ="011")
Resume (RESM "1")
Note: URST, SADR, SCFG SUSP bits parentheses bits that permitted when controller sets DVST when pertinent stage transition generated (interrupt enable register [INTENB0]). Stage transitions carried even setting DVST inhibited these bits.
Figure 3.16 Device state transitions
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3.2.7
Control transfer stage transition interrupt
Figure 3.17 shows diagram controller handles control transfer stage transition. Peripheral mode, controller controls control transfer sequence generates control transfer stage transition interrupts. Control transfer stage transition interrupts enabled disabled individually, using INTENB0 register. Also, transfer stage that underwent transition confirmed using CTSQ INTSTS0 register. control transfer sequence errors noted below. error occurs, DCPCTR register goes "1X" (STALL). During control read transfers token data stage, PING token received when there have been data transfers token received status stage packet received status stage which data packet "DATAPID=DATA0" During control write transfers token data stage, when there have been responses all, token received packet received data stage which first data packet "DATAPID=DATA0" status stage, PING token received During control write no-data transfers status stage, PING token received control write transfer stage, number received data elements exceeds wLength value request, cannot recognized control transfer sequence error. Also, control read transfer status stage, packets other than Zero-Length packets received response being carried out, transfer ends normally. CTRT interrupt occurs response sequence error ("SERR=1"), "CTSQ=110" value held until "CTRT=0" written from user system (the interrupt status cleared). Because this, while "CTSQ=110" being held, CTRT interrupt that ends setup stage will generated even request received. (The controller holds setup stage end, after interrupt status been cleared software, setup stage interrupt generated.)
Setup token received "CTSQ=110" Control transfer sequence error
Error detected
Setup token received
errors detected stages box, token reception valid.
Setup token received "CTSQ=000" Setup stage
sent
"CTSQ=001" Control read data stage
token
"CTSQ=010" sent Control read status stage
"CTSQ=000" Idle stage
sent
"CTSQ=011" Control write data stage
token
"CTSQ=100" received Control write status stage "CTSQ=101" Control write received no-data status stage
sent
CTRT interrupts Setup stage completed Control read transfer status stage transition Control write transfer status stage transition Control transfer completed Control transfer sequence error
Figure 3.17 Control transfer stage transitions
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3.2.8
Frame refresh interrupt
Figure 3.18 shows example SOFR interrupt output timing controller. Host mode, SOFR interrupt generated when frame number refreshed, Peripheral mode, SOFR interrupt generated, when frame number refreshed, damaged packet detected. interrupt operation should specified using SOFRM FRMNUM register. When "SOFRM=0" selected SOFR interrupt generated timing which frame number refreshed (intervals approximately ms). Interrupts generated internal interpolation function even packet damaged missing. During Hi-Speed communication well, interrupts generated timing which frame number refreshed (intervals approximately ms). When "SOFRM=1" selected SOFR interrupt generated when packets damaged when they missing. During Hi-Speed communication, interrupt generated only first packet uSOF packet with same frame number damaged missing. (Corrupted missing SOFs recognized interpolation function. detailed information, please refer Chapter interpolation function.) SOFRM should "SFRM=1" Host mode. Peripheral mode, controller detects packet during Full-Speed operation, refreshes frame number generates S
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