SH7065 SH7065 Hardware Manual Renesas 32-Bit RISC Microcompu
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REJ09B0332-0500
SH7065
SH7065
Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series HD6437065A HD64F7065SF HD64F7065AF
Rev. 5.00 Revision Date: 2006
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General Precautions Handling Product
Treatment Pins Note: connect anything pins. (not connected) pins either connected internal circuitry used test pins reduce noise. something connected pins, operation guaranteed. Treatment Unused Input Pins Note: unused input pins high level. Generally, input pins CMOS products high-impedance input pins. unused pins their open states, intermediate levels induced noise vicinity, passthrough current flows internally, malfunction occur. Processing before Initialization Note: When power first supplied, product's state undefined. states internal circuits undefined until full power supplied throughout chip level input reset pin. During period where states undefined, register settings output state each also undefined. Design your system that does malfunction because processing while this undefined state. those products which have reset function, reset immediately after power supply been turned Prohibition Access Undefined Reserved Addresses Note: Access undefined reserved addresses prohibited. undefined reserved addresses used expand functions, test registers have been allocated these addresses. access these registers; system's operation guaranteed they accessed.
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Preface
SH7065 microprocessor that integrates peripheral functions necessary system configuration with 32-bit internal architecture SH2-DSP core. On-chip peripheral functions include large-capacity RAM, interrupt controller, four kinds timers, serial communication interface, user break controller (UBC), state controller (BSC), direct memory access controller (DMAC), converter, converter, ports, enabling SH7065 used microcontroller electronic products requiring high speed power consumption. Flash memory (F-ZTATTM*) mask available onchip ROM, enabling users respond quickly flexibly changing application specifications demands transition from initial full-fledged volume production. Note: F-ZTAT trademark Renesas Technology Corp. Intended Readership: This manual intended users undertaking design application system using SH7065. Readers using this manual require basic knowledge electrical circuits, logic circuits, microcomputers. Purpose: purpose this manual give users understanding hardware functions electrical characteristics SH7065. Details execution instructions found SH-1, SH-2, SH-DSP Programming Manual, which should read conjunction with present manual.
Using this Manual: overall understanding SH7065's functions Follow Table Contents. This manual broadly divided into sections CPU, system control functions, peripheral functions, electrical characteristics. detailed understanding functions Refer separate publication SH-1, SH-2, SH-DSP Programming Manual. Note notation: Related Material: Bits shown high-to-low order from left right.
latest information available Site. Please make sure that have most up-to-date information available. http://www.renesas.com/
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User's Manuals SH7065:
Manual Title SH7065 Hardware Manual SH-1, SH-2, SH-DSP Software Manual Document This manual REJ09B0171-0500
Users manuals development tools:
Manual Title C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Simulator/Debugger User's Manual High-performance Embedded Workshop User's Manual Document REJ10B0047-0100 REJ10B0210-0200 REJ10B0025-0200
Application Note:
Manual Title C/C++ Compiler Document REJ05B0463-0300
Rev. 5.00 2006 page xxii
Main Revisions This Edition
Item 9.3.4 Types Transfer Relationship between Transfer Type, Request Mode, Mode Table Relationship between Transfer Type, Request Mode, Mode Page Revision (See Manual Details) Notification change company name amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. Table amended
Address Mode Dual Type Transfer External memory external memory External memory memory-mapped external device Memory-mapped external device memory-mapped external device External memory on-chip memory External memory on-chip peripheral module Memory-mapped external device on-chip memory Memory-mapped external device on-chip peripheral module On-chip memory on-chip memory Request Mode
Any*
Mode
Transfer Size (Bits) 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32* 8/16/32 8/16/32* 8/16/32 8/16/32* 8/16/32*
Usable Channels
Any*
Any* Any*
Any*
Any*
Any* On-chip memory on-chip peripheral Any* module On-chip peripheral module on-chip Any* peripheral module
11.6 Usage Notes
Description added Attention Notices Below, When Value Written into Timer General Register (TGRU), Timer General Register (TGRV), Timer General Register (TGRW), Case Written into Free Operation Address (*): Writing Operation into Timer Period Data Register (TPDR) Timer Dead Time Data Register (TDDR) When Operating: Notes Halting TCNT Counter Operation:
15.7.2 Handling Analog Input Pins Figure 15.8 Example Analog Input Protection Circuit Figure 15.9 Analog Input Equivalent Circuit Table 15.5 Analog Input Specifications
619, Description preliminary deleted
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Item 22.3.1 Clock Timing Table 22.4 Clock Timing
Page
Revision (See Manual Details) Table amended
Item Operating frequency (master clock) Clock cycle time Clock low-level pulse width Clock high-level pulse width Clock rise time Clock fall time EXTAL/CKIO clock input frequency EXTAL/CKIO clock input cycle time EXTAL/CKIO clock input low-level pulse width EXTAL/CKIO clock input high-level pulse width EXTAL/CKIO clock input rise time EXTAL/CKIO clock input fall time Reset oscillation settling time Standby recovery oscillation settling time Symbol tcyc tEXcyc tEXL tEXH tEXR tEXF tOSC1 tOSC2 16.7 33.3 11.6 11.6 Unit Figure 22.4 Figure 22.3 Figure Figure 22.2
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Contents
Section Overview
Features SH7065. Block Diagram Arrangement Functions. 1.3.1 Arrangement 1.3.2 Functions
Section
Register Configuration 2.1.1 General Registers 2.1.2 Control Registers. 2.1.3 System Registers 2.1.4 Registers 2.1.5 Notes Guard Bits Overflow Treatment. 2.1.6 Initial Register Values. Data Formats 2.2.1 Register Data Formats. 2.2.2 Memory Data Formats 2.2.3 Immediate Data Formats 2.2.4 Type Data Formats 2.2.5 Type Instructions Data Formats Features Core Instructions. Instruction Formats 2.4.1 Instruction Addressing Modes. 2.4.2 Data Addressing. 2.4.3 Instruction Formats. 2.4.4 Instruction Formats Instruction 2.5.1 Instruction 2.5.2 Data Transfer Instruction 2.5.3 Operation Instruction Usage Note.
Section Operating Modes.
Operating Mode Selection. 3.1.1 Operating Modes. 3.1.2 Configuration. 3.1.3 Register Configuration
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Register Descriptions 3.2.1 Mode Status Register (MSR) 3.2.2 Mode Control Register (MODECR)
Section Clock Pulse Generator (CPG) Power-Down Modes
Overview. 4.1.1 Features. 4.1.2 Block Diagram 4.1.3 Configuration 4.1.4 Register Configuration Clock Operating Modes Register Description 4.3.1 Frequency Control Register (FRQCR). Changing Frequency. Output Clock Control. Oscillator. 4.6.1 Connecting Crystal Resonator 4.6.2 External Clock Input Methods 4.6.3 Notes Board Design Oscillation Stoppage Detection Function. Power-Down Modes. 4.8.1 States Power-Down Modes 4.8.2 Configuration. Register Descriptions 4.9.1 Standby Control Register (SBYCR). 4.9.2 Module Stop Control Registers (MSTPCR1, MSTPCR2) 4.9.3 Module Clock Control Registers (MCLKCR1 MCLKCR5). Sleep Mode 4.10.1 Transition Sleep Mode. 4.10.2 Exit from Sleep Mode Software Standby Mode 4.11.1 Transition Software Standby Mode. 4.11.2 Exit from Software Standby Mode. 4.11.3 Software Standby Mode Application Example Hardware Standby Mode. 4.12.1 Transition Hardware Standby Mode 4.12.2 Exit from Hardware Standby Mode 4.12.3 Hardware Standby Mode Timing Module Standby Function 4.13.1 Transition Module Standby Function. 4.13.2 Exit from Module Standby Function.
4.10
4.11
4.12
4.13
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4.14 Module Clock Division Function 4.14.1 Clock Definitions 4.14.2 Transition Module Clock Division Function. 4.14.3 Exit from Module Clock Division Function. 4.14.4 Notes Module Clock Division Function 4.15 Note Initialization.
Section Exception Handling
Overview. 5.1.1 Exception Handling Types Priority 5.1.2 Timing Exception Source Detection Start Exception Handling. 5.1.3 Exception Vector Table Power-on Reset Address Errors 5.3.1 Address Error Sources 5.3.2 Address Error Exception Handling Interrupts 5.4.1 Interrupt Sources. 5.4.2 Interrupt Priority 5.4.3 Interrupt Exception Handling. Instruction Exceptions. 5.5.1 Types Instruction Exception 5.5.2 Trap Instruction. 5.5.3 Slot Illegal Instructions 5.5.4 General Illegal Instructions Cases Which Exceptions Accepted 5.6.1 After Delayed Branch Instruction. 5.6.2 After Instruction Which Interruption Prohibited. 5.6.3 Instructions Repeat Loops. Stack Status after Exception Handling Usage Notes 5.8.1 Stack Pointer (SP) Value. 5.8.2 Vector Base Register (VBR) Value 5.8.3 Address Errors Occurring Address Error Exception Handling Stacking
Section Interrupt Controller (INTC)
Overview. 6.1.1 Features. 6.1.2 Block Diagram 6.1.3 Configuration. 6.1.4 Register Configuration
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Interrupt Sources 6.2.1 Interrupt. 6.2.2 User Break Interrupt 6.2.3 External Interrupts. 6.2.4 On-Chip Peripheral Module Interrupts 6.2.5 Interrupt Exception Vectors Priority Order Register Descriptions 6.3.1 Interrupt Priority Registers (IPRA IPRL) 6.3.2 Interrupt Control Register (ICR1) 6.3.3 Interrupt Control Register (ICR2) 6.3.4 Status Register (ISR) Operation. 6.4.1 Interrupt Operation Sequence 6.4.2 Interrupt Response Time 6.4.3 Stack Status after Interrupt Exception Handling Sampling Signals IRQ3 IRQ0 Mode Data Transfer Means Interrupt Request Signal 6.6.1 Designate Source DMAC Activation Source, Interrupt Source 6.6.2 Designate Source Interrupt Source, DMAC Activation Source Usage Notes 6.7.1 IRQ3 IRQ0 Sampling Interrupt Source Determination Interrupt Mode. 6.7.2 Noise Cancellation Function
Section User Break Controller (UBC)
Overview. 7.1.1 Features. 7.1.2 Block Diagram 7.1.3 Register Configuration Register Descriptions 7.2.1 User Break Address Register (UBAR). 7.2.2 User Break Address Mask Register (UBAMR) 7.2.3 User Break Cycle Register (UBBR) Operation. 7.3.1 User Break Operation Sequence 7.3.2 Instruction Fetch Cycle Break. 7.3.3 Data Access Cycle Break 7.3.4 Memory Memory Cycle Break 7.3.5 Program Counter (PC) Value Saved
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Examples Usage Notes 7.5.1 Changes Register Settings. 7.5.2 Repeat Condition Breaks
Section State Controller (BSC)
Overview. 8.1.1 Features. 8.1.2 Block Diagram 8.1.3 Configuration. 8.1.4 Register Configuration 8.1.5 Address Format Register Descriptions 8.2.1 Control Register (BCR) 8.2.2 Area Control Registers (ACR1_0 ACR1_5) 8.2.3 Wait Control Registers (WCR_0 WCR_3) 8.2.4 DRAM Control Register (DCR1) 8.2.5 DRAM Control Register (DCR2) 8.2.6 DRAM Control Register (DCR3) 8.2.7 Refresh Timer Control/Status Register (RTCSR) 8.2.8 Refresh Timer Counter (RTCNT) 8.2.9 Refresh Time Constant Register (RTCOR). 8.2.10 Refresh Count Register (RFCR). Operation. 8.3.1 Endian/Access Size Data Alignment 8.3.2 Areas 8.3.3 Normal Space Access. 8.3.4 DRAM Interface 8.3.5 Multiplexed Address/Data Interface 8.3.6 Waits between Access Cycles 8.3.7 Arbitration. Number Access Cycles (SH7065A). Usage Notes
Section Direct Memory Access Controller (DMAC)
Overview. 9.1.1 Features. 9.1.2 Block Diagram 9.1.3 Configuration. 9.1.4 Register Configuration Register Descriptions
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9.2.1 Source Address Registers (SAR0 SAR3) 9.2.2 Destination Address Registers (DAR0 DAR3). 9.2.3 Transfer Count Registers (DMATCR0 DMATCR3). 9.2.4 Channel Control Registers (CHCR0 CHCR3) 9.2.5 Next Source Address Registers (NSAR0 NSAR3) 9.2.6 Next Destination Address Registers (NDAR0 NDAR3). 9.2.7 Next Transfer Count Registers (NDMATCR0 NDMATCR3). 9.2.8 Chain Transfer Count Registers (CHNCNT0 CHNCNT3). 9.2.9 Operation Register (DMAOR). Operation. 9.3.1 Transfer Procedure. 9.3.2 Transfer Requests 9.3.3 Channel Priorities. 9.3.4 Types Transfer. 9.3.5 Number Cycle States DREQ Sampling Timing 9.3.6 Parallel Operation 9.3.7 Transfer When External Released. 9.3.8 Chain Transfer Example 9.4.1 Example Transfer between On-Chip External Memory. Usage Notes DMAC Restrictions. 9.6.1 TEND Output. 9.6.2 Notes Suspension Transfer
Section 16-Bit Timer Pulse Unit (TPU)
10.1 Overview. 10.1.1 Features. 10.1.2 Block Diagram 10.1.3 Configuration. 10.1.4 Register Configuration 10.2 Register Descriptions 10.2.1 Timer Control Registers (TCR) 10.2.2 Timer Mode Registers (TMDR). 10.2.3 Timer Control Registers (TIOR). 10.2.4 Timer Interrupt Enable Registers (TIER). 10.2.5 Timer Status Registers (TSR) 10.2.6 Timer Counters (TCNT) 10.2.7 Timer General Registers (TGR). 10.2.8 Timer Start Register (TSTR). 10.2.9 Timer Sync Register (TSYR).
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10.3 Interface Master 10.3.1 16-Bit Registers 10.3.2 8-Bit Registers 10.4 Operation. 10.4.1 Overview. 10.4.2 Basic Functions 10.4.3 Synchronous Operation. 10.4.4 Buffer Operation 10.4.5 Cascaded Operation 10.4.6 Modes 10.4.7 Phase Counting Mode 10.5 Interrupts 10.5.1 Interrupt Sources Priorities. 10.5.2 DMAC Activation. 10.5.3 Converter Activation 10.6 Operation Timing 10.6.1 Input/Output Timing 10.6.2 Interrupt Signal Timing. 10.7 Usage Notes
Section Motor Management Timer (MMT)
11.1 Overview. 11.1.1 Features. 11.1.2 Block Diagram 11.1.3 Configuration. 11.1.4 Register Configuration 11.2 Register Descriptions 11.2.1 Timer Mode Register (TMDR) 11.2.2 Timer Control Register (TCNR) 11.2.3 Timer Status Register (TSR) 11.2.4 Timer Counter (TCNT). 11.2.5 Timer Buffer Registers (TBR) 11.2.6 Timer General Registers (TGR). 11.2.7 Timer Dead Time Counters (TDCNT). 11.2.8 Timer Dead Time Data Register (TDDR). 11.2.9 Timer Period Buffer Register (TPBR) 11.2.10 Timer Period Data Register (TPDR). 11.3 Operation. 11.3.1 Sample Setting Procedure 11.3.2 Overview Operation. 11.3.3 Output Protection Functions
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11.4 Interrupts 11.4.1 Compare Match Interrupts 11.4.2 Controller Activation 11.4.3 Converter Activation 11.5 Operation Timing 11.5.1 Input/Output Timing 11.5.2 Interrupt Signal Timing. 11.6 Usage Notes 11.7 Port Output Enable (POE). 11.7.1 Overview. 11.7.2 Register Description. 11.7.3 Operation
Section Compare Match Timer (CMT)
12.1 Overview. 12.1.1 Features. 12.1.2 Block Diagram 12.1.3 Register Configuration 12.2 Register Descriptions 12.2.1 Compare Match Timer Start Register (CMSTR) 12.2.2 Compare Match Timer Control/Status Registers (CMCSR0, CMCSR1) 12.2.3 Compare Match Counters (CMCNT0, CMCNT1) 12.2.4 Compare Match Constant Registers (CMCOR0, CMCOR1) 12.3 Operation. 12.3.1 Cyclic Count Operation. 12.3.2 CMCNT Count Timing 12.4 Interrupts 12.4.1 Interrupt Sources. 12.4.2 Timing Compare Match Flag Setting. 12.4.3 Timing Compare Match Flag Clearing 12.5 Usage Notes
Section Watchdog Timer
13.1 Overview. 13.1.1 Features. 13.1.2 Block Diagram 13.1.3 Configuration. 13.1.4 Register Configuration 13.2 Register Descriptions 13.2.1 Timer Counter (TCNT).
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13.2.2 Timer Control/Status Register (TCSR) 13.2.3 Reset Control/Status Register (RSTCSR) 13.2.4 Notes Register Access. 13.3 Operation. 13.3.1 Operation Watchdog Timer Mode 13.3.2 Operation Interval Timer Mode 13.3.3 Operation When Clearing Software Standby Mode
Section Serial Communication Interface (SCI).
14.1 Overview. 14.1.1 Features. 14.1.2 Block Diagrams. 14.1.3 Configuration. 14.1.4 Register Configuration 14.2 Register Descriptions 14.2.1 Receive Shift Register (SCRSR) 14.2.2 Receive FIFO Data Register (SCFRDR). 14.2.3 Transmit Shift Register (SCTSR). 14.2.4 Transmit FIFO Data Register (SCFTDR) 14.2.5 Serial Mode Register (SCSMR). 14.2.6 Serial Control Register (SCSCR) 14.2.7 Serial Status Register (SC1SSR). 14.2.8 Serial Status Register (SC2SSR). 14.2.9 Rate Register (SCBRR). 14.2.10 FIFO Control Register (SCFCR). 14.2.11 FIFO Data Count Register (SCFDR) 14.2.12 FIFO Error Register (SCFER) 14.2.13 IrDA Mode Register (SCIMR). 14.3 Operation. 14.3.1 Overview. 14.3.2 Operation Asynchronous Mode 14.3.3 Multiprocessor Communication Function 14.3.4 Operation Synchronous Mode. 14.3.5 Transmit/Receive FIFO Buffers 14.3.6 Operation IrDA Mode. 14.4 Interrupt Sources DMAC. 14.5 Usage Notes
Section Converter
15.1 Overview. 15.1.1 Features.
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15.2
15.3 15.4
15.5 15.6 15.7
15.1.2 Block Diagram 15.1.3 Configuration. 15.1.4 Register Configuration Register Descriptions 15.2.1 Data Registers (ADDRA0 ADDRD0, ADDRA1 ADDRD1). 15.2.2 Control/Status Registers (ADCSR0, ADCSR1) 15.2.3 Control Registers (ADCR0, ADCR1) Interface. Operation. 15.4.1 Single Mode (MULTI 15.4.2 Multi Mode 15.4.3 Input Sampling Conversion Time. 15.4.4 External Trigger Input Timing Interrupt Sources Transfer Requests Conversion Accuracy Definitions. Usage Notes 15.7.1 Analog Voltage Settings. 15.7.2 Handling Analog Input Pins. 15.7.3 Note Output. 15.7.4 Port Settings. 15.7.5 Simultaneous Conversion
Section Converter
16.1 Overview. 16.1.1 Features. 16.1.2 Block Diagram 16.1.3 Configuration. 16.1.4 Register Configuration 16.2 Register Descriptions 16.2.1 Data Registers (DADR0, DADR1). 16.2.2 Control Register (DACR). 16.3 Operation. 16.4 Usage Note.
Section Function Controller (PFC)
17.1 Overview. 17.2 Register Configuration 17.3 Register Descriptions 17.3.1 Port Register (PAIORH) 17.3.2 Port Register (PAIORL) 17.3.3 Port Control Registers (PACRH1, PACRH2).
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17.3.4 Port Control Registers (PACRL1, PACRL2). 17.3.5 Port Register (PBIORH). 17.3.6 Port Register (PBIORL) 17.3.7 Port Control Register (PBCRH2) 17.3.8 Port Control Registers (PBCRL1, PBCRL2) 17.3.9 Port Register (PCIORH). 17.3.10 Port Register (PCIORL). 17.3.11 Port Control Registers (PCCRH1, PCCRH2) 17.3.12 Port Control Registers (PCCRL1, PCCRL2) 17.3.13 Port Register (PDIORH) 17.3.14 Port Register (PDIORL) 17.3.15 Port Control Registers (PDCRH1, PDCRH2). 17.3.16 Port Control Registers (PDCRL1, PDCRL2) 17.3.17 Port Register (PEIORH) 17.3.18 Port Register (PEIORL) 17.3.19 Port Control Register (PECRH2). 17.3.20 Port Control Register (PECRL). 17.3.21 Port Register (PFIORL) 17.3.22 Port Control Register (PFCRL2) 17.3.23 Port Register (PGIOR). 17.3.24 Port Control Register (PGCRH1). 17.3.25 Port Register (PHIOR). 17.3.26 Port Control Register (PHCR). 17.3.27 Function Control Register (FCR) 17.4 Restrictions
Section Ports (I/O)
18.1 Overview. 18.2 Port 18.2.1 Register Configuration 18.2.2 Port Data Register (PADRH) 18.2.3 Port Data Register (PADRL) 18.3 Port 18.3.1 Register Configuration 18.3.2 Port Data Register (PBDRH). 18.3.3 Port Data Register (PBDRL). 18.4 Port 18.4.1 Register Configuration 18.4.2 Port Data Register (PCDRH). 18.4.3 Port Data Register (PCDRL). 18.5 Port
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18.6
18.7
18.8
18.9
18.10
18.5.1 Register Configuration 18.5.2 Port Data Register (PDDRH) 18.5.3 Port Data Register (PDDRL) Port 18.6.1 Register Configuration 18.6.2 Port Data Register (PEDRH) 18.6.3 Port Data Register (PEDRL) Port 18.7.1 Register Configuration 18.7.2 Port Data Register (PFDRL) Port 18.8.1 Register Configuration 18.8.2 Port Data Register (PGDRH) Port 18.9.1 Register Configuration 18.9.2 Port Data Register (PHDR) Port 18.10.1 Register Configuration 18.10.2 Port Data Register (PIDR)
Section Flash Memory (F-ZTAT)
19.1 Features 19.2 Overview. 19.2.1 Block Diagram 19.2.2 Mode Transitions 19.2.3 On-Board Programming Modes 19.2.4 Flash Memory Emulation RAM. 19.2.5 Differences between Boot Mode User Program Mode. 19.2.6 Block Configuration. 19.3 Configuration 19.4 Register Configuration 19.5 Register Descriptions 19.5.1 Flash Memory Control Register (FLMCR1) 19.5.2 Flash Memory Control Register (FLMCR2) 19.5.3 Erase Block Register (EBR1) 19.5.4 Erase Block Register (EBR2) 19.5.5 Emulation Register (RAMER) 19.6 On-Board Programming Modes 19.6.1 Boot Mode 19.6.2 User Program Mode. 19.7 Programming/Erasing Flash Memory.
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19.8
19.9 19.10 19.11
19.12 19.13
19.7.1 Program Mode 19.7.2 Program-Verify Mode. 19.7.3 Erase Mode Addresses H'00000 H'07FFF, Addresses H'08000 H'3FFFF) 19.7.4 Erase-Verify Mode Addresses H'00000 H'07FFF, Addresses H'08000 H'3FFFF) 19.7.5 Wait Time Widths Programming/Erasing Protection 19.8.1 Hardware Protection 19.8.2 Software Protection. 19.8.3 Error Protection. Flash Memory Emulation Note Flash Memory Programming/Erasing. Flash Memory Programmer Mode 19.11.1 Socket Adapter Correspondence Diagram. 19.11.2 Operation Programmer Mode 19.11.3 Memory Read Mode 19.11.4 Auto-Program Mode 19.11.5 Auto-Erase Mode 19.11.6 Status Read Mode 19.11.7 Status Polling 19.11.8 Programmer Mode Transition Time. 19.11.9 Cautions Concerning Memory Programming. Usage Notes Cautions Transition from F-ZTAT Mask Version.
Section Mask ROM.
20.1 Overview.
Section XRAM YRAM
21.1 Overview. 21.2 Operation.
Section Electrical Characteristics.
22.1 Absolute Maximum Ratings. 22.2 Electrical Characteristics. 22.2.1 Characteristics (1). 22.2.2 Characteristics (2). 22.3 Characteristics Test Conditions 22.3.1 Clock Timing 22.3.2 Control Signal Timing.
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22.3.3 Timing. 22.3.4 Direct Memory Access Controller Timing. 22.3.5 16-Bit Timer Pulse Unit (TPU) Timing 22.3.6 Motor Management Timer (MMT) Timing 22.3.7 Port Output Enable (POE) Timing. 22.3.8 Port Timing. 22.3.9 Watchdog Timer Timing. 22.3.10 Serial Communication Interface Timing 22.3.11 Conversion Timing. 22.3.12 Conversion Characteristics. 22.3.13 Conversion Characteristics.
Appendix On-Chip Peripheral Module Registers Appendix States
States Reset, Power-Down State, Bus-Released State. Bus-Related Signal States
Appendix Port Block Diagrams. Appendix Restrictions Caution HD64F7065S (and HD64F7065A Lots Prior "1D5")
Restrictions Restrictions Case Contention between Instruction DMAC Transfer. State Related Restrictions Caution Concerning Electrical Characteristics. DMAC Restrictions. Restrictions about Changing Saturation Operation Mode during Execution Multiply/Multiply Accumulate, Instructions.
Appendix Product Lineup Appendix Package Dimensions
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Section Overview
Section Overview
Features SH7065
SH7065 CMOS single-chip microcomputer featuring SH2-DSP core-a functionally enhanced version SuperH RISC engine using original Renesas Technology architecture-with same signal processing capability general-purpose digital signal processor (DSP), together with peripheral functions required system configuration. SH2-DSP core offers enhancement functions (multiply multiply-andaccumulate) SuperH RISC engine, provides full type data functionality, enabling efficient execution various kinds signal processing image processing. With this CPU, become possible create low-cost, systems even applications such realtime control, which could previously handled microcomputers because their high-speed processing requirements. addition, SH7065 includes on-chip peripheral functions necessary system configuration, such large-capacity RAM, timers, serial communication interface (SCI), converter, converter, interrupt controller (INTC), ports. external memory access support function allows efficient connection memory peripheral LSIs, greatly reducing system cost. There versions SH7065, with different kinds on-chip ROM: F-ZTAT version with on-chip flash memory, mask version. F-ZTAT version, programs written rewritten with Renesas-recommended programmer, on-board.
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Section Overview
Table
Item
Features
Specifications Original Renesas Technology architecture 32-bit internal configuration General register machine Sixteen 32-bit general registers 32-bit control registers (including three added use) 32-bit system registers (including added use) RISC (reduced instruction computer) type instruction Fixed 16-bit instruction length improved code efficiency Load-store architecture (basic operations executed between registers) Delayed branch instructions reduce pipeline disruption during branches C-oriented instruction Instruction execution time: instruction cycle Address space: Architecture supports Gbytes Enhanced on-chip multiplier: multiply operations executed three cycles multiply operations executed four cycles multiply-and-accumulate operations executed four cycles Five-stage pipeline
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Section Overview Item Specifications engine Multiplier Arithmetic logic unit (ALU) Shifter registers Multiplier bits bits bits Single-cycle multiplier registers 40-bit data registers 32-bit data registers Modulo register (MOD, bits) added control registers Repeat counter (RC) added status register (SR) Repeat start register (RS, bits) repeat register (RE, bits) added control registers data Extended Harvard architecture Simultaneous access data buses instruction Parallel processing Maximum four parallel processes operations, multiplication, loads stores Address processors address processors Address operations access memories data addressing modes Increment index Each with without modulo addressing Repeat control: Zero-overhead repeat (loop) control Instruction 16-bit length case load store only) 32-bit length (including operations multiplication) Added system control instructions accessing registers Fifth last pipeline stage stage
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Section Overview Item Interrupt controller (INTC) Specifications Nine external interrupt pins (NMI, IRQ0 IRQ7) external interrupt sources (encoded input) also selected pins IRQ0 IRQ3 User break controller (UBC) state controller (BSC) programmable priority levels noise canceler function Interrupt acceptance reported externally (IRQOUT pin) Requests interrupt when DMAC generates cycle with specific conditions Simplifies configuration on-chip debugger Supports external expansion memory access 32-bit external data Address space divided into areas (four areas SRAM space, areas DRAM space), with following parameters settable each area: size (8/16/32 bits) Number wait cycles SRAM, DRAM, DRAM easily connectable space type setting Output signals DRAM DRAM Addressing multiplexing supported internally, allowing direct connection DRAM DRAM DRAM DRAM burst access functions DRAM DRAM fast access mode supported DRAM DRAM refresh functions Programmable refresh interval CAS-before-RAS refreshing self-refreshing supported eight consecutive CAS-before-RAS refreshes possible Wait cycles inserted using external WAIT signal access devices that address/data multiplexing Big-endian little-endian mode independently each area
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Section Overview Item Direct memory access controller (DMAC) channels) Specifications transfer possible following devices: External memory, external I/O, on-chip supporting modules (excluding DMAC, BSC, UBC) Timer pulse unit (TPU) channels) Motor management timer (MMT) channel) transfer requests external pins (for channels) on-chip peripheral modules, plus auto-request Cycle steal burst transfer Relative channel priorities Selection dual single address mode transfer Chain mode transfer possible Transfer data width: 8/16/32 bits 4-Gbyte address space, maximum (4,294,967,296) transfers TEND output asserted each channel transfer Maximum kinds waveform output maximum kinds input/output processing based 16-bit timer channels dual-function output compare registers/input capture registers Total independent comparators Selection eight counter input clocks Input capture function Pulse output modes One-shot, toggle, Phase counting mode Two-phase encoder count processing capability Non-overlap waveform output 6-phase inverter control Dead times generated dead time counters duty from 100% Toggle output possible synchronization with cycle Data transfer performed DMAC activation converter conversion start trigger generated Output-off functions
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Section Overview Item Compare-match timer (CMT) channels) Specifications 16-bit free-running counter compare register Interrupt request generated compare-match switched between watchdog timer interval timer function Internal reset, external signal, interrupt generated count overflow Selection asynchronous synchronous mode Simultaneous transmission/reception (full-duplex) capability Built-in dedicated baud rate generator Multiprocessor communication function Separate 16-stage FIFO registers transmission reception, enabling continuous high-speed communication Selection MSB-first LSB-first transfer Selection base clock 4/8/16 times rate asynchronous mode Built-in IrDA interface (conforming IrDA 1.0) Total port pins: input/output, input Input/output voltage level some ports circuit power supply PVCC bits channels modules Conversion activated external trigger bits channels ROM: kbytes X-RAM: kbytes Y-RAM: kbytes
Watchdog timer (WDT) channel) Serial communication interface (SCI) channels) ports converter converter On-chip memory
each channel:
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Section Overview Item Operating modes Specifications Operating modes Expanded ROMless mode Expanded mode Single-chip mode Processing states Program execution state Exception handling state Bus-released state Power-down modes Sleep mode Hardware standby mode Software standby mode Module standby function Module clock division function Clock pulse generator (CPG) Package Product lineup Built-in clock pulse generator Selection crystal external clock clock source Built-in clock-multiplication circuits Built-in circuit phase synchronization between external clock internal clock Internal clock on-chip peripheral module clock frequencies scaled independently
176-pin plastic LQFP (LQFP2424-176), pitch SH7065: flash/mask Operating frequency: (max.)
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Section Overview
Block Diagram
Internal address (CAB)
32-bit internal data (CDB)
Internal address
16-bit internal data
16-bit internal data
Internal address
Buffer
16-bit peripheral data
64-bit internal
Peripheral address
Interrupt controller
Serial communication interface Motor management timer
X-RAM Timer pulse unit Y-RAM
Compare-match timer
User break controller
converter
converter
32-bit internal data (IDB)
Internal address (IAB)
Direct memory access controller
state controller
Watchdog timer
Clock pulse generator
Operating mode controller
ports
External interface
Figure Block Diagram
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Section Overview
1.3.1
Arrangement Functions
Arrangement
PLLVSS PLLCAP2 PLLCAP1 PLLVCC CKIO HSTBY FWE* EXTAL XTAL PD0/D0 PD1/D1 PD2/D2 PD3/D3 PD4/D4 PD5/D5 PD6/D6 PD7/D7 PD8/D8/TIOC1A PD9/D9/TIOC1B PD10/D10/TIOC2A PD11/D11/TIOC2B PD12/D12/TIOC4A PD13/D13/TIOC4B PD14/D14/TIOC5A PD15/D15/TIOC5B PD16/D16/POE0
PA1/OE1 PA0/OE0 PF3/DREQ0/TIOC0A PF2/DRAK0/TIOC0C PF1/DACK0/TIOC0B PA19/BS PF5/DACK1/RxD1/TIOC2B PF6/DRAK1/TxD1/TIOC2A PF7/DREQ1/IRQOUT/TIOC0D WDTOVF AVSS PH0/DA0 PH1/DA1 PI0/AN0 PI1/AN1 PI2/AN2 PI3/AN3 PI4/AN4 PI5/AN5 PI6/AN6 PI7/AN7 AVCC PVCC PG31/RxD2 PG30/TxD2 PG29/SCK2 PB7/BACK PB6/BREQ PVSS PE23/IRQ7/PWOB PE22/IRQ6/PVOB PE21/IRQ5/PUOB PE20/IRQ4/PCO/PCI PE19/IRQ3/PWOA PE18/IRQ2/PVOA PVCC PE17/IRQ1/PUOA/SCK0 PE16/IRQ0/SCK1/AH PE15/IRQ7
FP-176 (Top view)
PD17/D17/POE1/ADTRG PD18/D18/POE2/IRQ4 PD19/D19/POE3/IRQ5 PD20/D20/PUOA/IRQ6 PD21/D21/PVOA/IRQ7 PD22/D22/PWOA/SCK0 PD23/D23/PCO/PCI/SCK1 PD24/D24/PUOB PD25/D25/PVOB PD26/D26/PWOB PD27/D27/TCLKA/TIOC3C PD28/D28/TCLKB/TIOC3D PD29/D29/SCK2/TIOC4A PD30/D30/TxD2/TIOC4B PD31/D31/RxD2/TIOC5A PB13/RDWR PB16/CASLL0 PB17/CASLH0 PB18/CASHL0/RxD0 PB19/CASHH0/TxD0 PB20/CASLL1 PB21/CASLH1 PB22/CASHL1/RxD1/TEND1 PB23/CASHH1/TxD1/TEND0 PA8/RAS0 PA9/RAS1 PA12/WAIT PA13/WRLL/LLBS PA14/WRLH/LHBS PA15/WRHL/HLBS/TCLKD/TIOC3B PA16/WRHH/HHBS/TCLKC/TIOC3A PA17/WR PA18/RD PA20/CS0 PA21/CS1
Note: mask version (can pulled down with resistance
PVSS PE14/IRQ6 PE13/IRQ5 PE12/IRQ4 PVcc PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14/TIOC3C PC15/A15/TIOC3D PC16/A16/TIOC3A PC17/A17/TIOC3B PC18/A18/TIOC4A PC19/A19/TIOC4B PC20/A20/TIOC5A PC21/A21/TIOC5B PC22/A22/TIOC1A/TCLKA PC23/A23/TIOC1B/TCLKB PC24/A24/TIOC3A/TCLKC PC25/A25/TIOC3B/TCLKD PA25/CS5 PA24/CS4 PA23/CS3 PA22/CS2
Figure Arrangement
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Section Overview
1.3.2
Functions
Table summarizes functions. Table
Type Power supply
Functions
Symbol Input Name Power supply Function connection power supply. Connect pins system power supply. chip will operate there open pins. Apply same voltage pins.* connection ground. Connect pins system ground. chip will operate there open pins. Power supply circuits. chip will operate there open pins. Apply same voltage PVCC pins.* Ground circuits. chip will operate there open pins. On-chip oscillator power supply. chip will operate there open pins. On-chip oscillator ground. chip will operate there open pins.
Input
Ground
PVcc
Input
circuit power supply
PVss Clock PLLVcc
Input Input
circuit ground power supply ground
PLLVss
Input
PLLCAP1 PLLCAP2 EXTAL
Input Input Input
capacitance On-chip oscillator external capacitance pin. capacitance On-chip oscillator external capacitance pin. External clock connection crystal resonator. external clock also input EXTAL pin. connection crystal resonator
XTAL CKIO
Output Output
Crystal
System clock Used external clock input internal clock output pin. System clock output Internal clock output pin.
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Section Overview Type Symbol Input Output Input Output Name Power-on reset Watchdog timer overflow request request acknowledge Function Executes power-on reset when driven low. overflow output signal Driven when external device requests release bus. Indicates that been granted external device. device that output BREQ signal recognizes that been acquired when receives BACK signal. Hardware standby input pin. Drive high when used. These pins determine operating mode. change input values during operation. On-chip flash memory program/erase hardware protection pin. Nonmaskable interrupt request pin. Acceptance rising edge falling edge selected. Maskable interrupt request pins. Level input edge input selected. Indicates that interrupt request been generated. Enables interrupt generation recognized busreleased state. Address output pins. 32-bit bidirectional data bus. Chip select signals external memory devices. Indicates reading from external device. Used DRAM write directive signal. Indicates writing bits external data. Indicates writing bits external data.
System control WDTOVF BREQ BACK
HSTBY Operating mode control MD0-MD5
Input Input
Hardware standby Mode setting
Interrupts
Input Input
Flash write enable Nonmaskable interrupt Interrupt request Interrupt request output
IRQ0-IRQ7 Input IRQOUT Output
Address Data control
A0-A25 D0-D31 CS0-CS5 RDWR WRLL WRLH
Output Output Output Output Output Output
Address Data Chip select Read Read/write write write
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Section Overview Type control Symbol WRHL WRHH WAIT LLBS LHBS HLBS HHBS Output Output Input Output Output Output Output Output Name write write Wait byte strobe byte strobe byte strobe byte strobe Write Function Indicates writing bits external data. Indicates writing bits external data. Input wait cycle insertion cycles during external space access Indicates access bits external data. Indicates access bits external data. Indicates access bits external data. Indicates access bits external data. Indicates data input/output direction. Also used write directive byte-strobe type memory. DRAM address strobe timing signals Output when accessing bits DRAM data. Output when accessing bits DRAM data. Output when accessing bits DRAM data. Output when accessing bits DRAM data. Output enable signal DRAM down mode. Address hold timing signal device using multiplexed address/data bus. Indicates start cycle.
RAS0- RAS1 CASLL0- CASLL1 CASLH0- CASLH1 CASHL0- CASHL1 CASHH0- CASHH1 OE0-OE1
Output Output
address strobe column address strobe column address strobe column address strobe column address strobe Output enable Address hold cycle start
Output
Output
Output
Output Output Output
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Section Overview Type Symbol Input Name transfer request (channels DREQ request acknowledgment (channels transfer strobe (channels transfer (channels timer clock input input capture/output compare (channel input capture/output compare (channel input capture/output compare (channel input capture/output compare (channel input capture/output compare (channel input capture/output compare (channel Function Input pins external requests transfer.
Direct memory DREQ0- DREQ1 access controller (DMAC) DRAK0- DRAK1
Output
These pins output input sampling acknowledgment external requests transfer. These pins output strobe external external transfer requests. These pins transfer. counter external clock Input pins. Channel input capture input/output compare output/PWM output pins.
DACK0- DACK1 TEND0- TEND1 Timer pulse unit (TPU) TCLKA- TCLKD TIOC0A- TIOC0D
Output
Output
Input
TIOC1A- TIOC1B
Channel input capture input/output compare output/PWM output pins.
TIOC2A- TIOC2B
Channel input capture input/output compare output/PWM output pins.
TIOC3A- TIOC3D
Channel input capture input/output compare output/PWM output pins.
TIOC4A- TIOC4B
Channel input capture input/output compare output/PWM output pins.
TIOC5A- TIOC5B
Channel input capture input/output compare output/PWM output pins.
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Section Overview Type Motor management timer (MMT) Symbol PUOA- PUOB PVOA- PVOB PWOA- PWOB POE0- POE3 Serial TxD0- communication TxD2 interface (SCI) RxD0- RxD2 SCK0- SCK2 Analog power supply AVcc AVss converter AN0-AN7 ADTRG converter DA0-DA1 Input Output Output Output Output Input Name Counter clear input cycle output U-phase output V-phase output Function Counter clear input pin. toggle output synchronized with cycle. U-phase waveform output pin. V-phase waveform output pin.
W-phase W-phase waveform output pin. output Port output enable input These pins input request signals place large-current pins high-impedance state.
Output Input Input Input Input Input Output
Transmit data Transmit data output pins. (channels Receive data Receive data input pins. (channels Serial clock Clock input/output pins. (channels Analog power supply Analog ground Analog input connection analog power supply. connection analog power supply ground. Analog signal input pins
conversion External input starting conversion trigger input Analog output converter analog signal output pins
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Section Overview Type ports Symbol Input Name General port General port General port General port General port General port General port General port General port Function General input/output port pins. Input output specified bit. General input/output port pins. Input output specified bit. General input/output port pins. Input output specified bit. General input/output port pins. Input output specified bit. General input/output port pins. Input output specified bit. General input/output port pins. Input output specified bit. General input/output port pins. Input output specified bit. General input/output port pins. Input output specified bit. General input port pins.
Notes: Unused input pins must pulled pulled down with resistance following power-on/power-off order recommended when applying voltage power supply voltage PVCC. When PVCC also used with same voltage VCC, etc., simultaneous powering recommended power supplies. Powering Turn power (PVCC) first, then power (VCC, PLLVCC, AVCC). states undefined while only power (PVCC) reset input invalid. Powering Power reverse order powering Turn power first, then power. states undefined while only power being supplied. Power-on/off interval minimize length time during which states undefined, power-on/off interval should kept short possible. Also, system design should ensure that erroneous system operation will result from states becoming undefined.
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Section Overview
Table
Function List
Control Power No.* Supply Function PLLVcc PLVss PLLCAP1 PLLCAP2 AVcc AVss EXTAL XTAL CKIO WDTOVF HSTBY General input/output (PA25) General input/output (PA24) General input/output (PA23) General input/output (PA22) General input/output (PA21) General input/output (PA20) General input/output (PA19) General input/output (PA18)
Function Function Function Function
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Section Overview Control Power No.* Supply Function General input/output (PA17) General input/output (PA16) General input/output (PA15) General input/output (PA14) General input/output (PA13) General input/output (PA12) General input/output (PA9) General input/output (PA8) General input/output (PB23) General input/output (PB22) General input/output (PB21) General input/output (PB20) General input/output (PB19) General input/output (PB18) General input/output (PB17) General input/output (PB16) General input/output (PB13) General input/output (PC25) General input/output (PC24) General input/output (PC23) General input/output (PC22) General input/output (PC21) General input/output (PC20) General input/output (PC19) General input/output (PC18) General input/output (PC17) General input/output (PC16) General input/output (PC15) General input/output (PC14) General input/output (PC13) General input/output (PC12)
Function Function Function Function WRHH WRHL WRLH WRLL WAIT RAS1 RAS0 CASHH1 CASHL1 CASLH1 CASLL1 CASHH0 CASHL0 CASLH0 CASLL0 RDWR HHBS HLBS LHBS LLBS TxD1 RxD1 TxD0 RxD0 TIOC3B TIOC3A TIOC1B TIOC1A TIOC5B TIOC5A TIOC4B TIOC4A TIOC3B TIOC3A TIOC3D TIOC3C TCLKC TCLKD TEND0 TEND1 TCLKD TCLKC TCLKB TCLKA TIOC3A TIOC3B
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Section Overview Control Power No.* Supply Function General input/output (PC11) General input/output (PC10) General input/output (PC9) General input/output (PC8) General input/output (PC7) General input/output (PC6) General input/output (PC5) General input/output (PC4) General input/output (PC3) General input/output (PC2) General input/output (PC1) General input/output (PC0) General input/output (PD31) General input/output (PD30) General input/output (PD29) General input/output (PD28) General input/output (PD27) General input/output (PD26) General input/output (PD25) General input/output (PD24) General input/output (PD23) General input/output (PD22) General input/output (PD21) General input/output (PD20) General input/output (PD19) General input/output (PD18) General input/output (PD17) General input/output (PD16) General input/output (PD15) General input/output (PD14)
Function Function Function Function RxD2 TxD2 SCK2 TCLKB TCLKA PWOB PVOB PUOB PWOA PVOA PUOA POE3 POE2 POE1 POE0 TIOC5B TIOC5A TIOC5A TIOC4B TIOC4A TIOC3D TIOC3C SCK0 IRQ7 IRQ6 IRQ5 IRQ4 ADTRG SCK1
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Section Overview Control Power No.* Supply Function PVcc PVcc PVcc PVcc PVcc PVcc PVcc PVcc AVcc AVcc AVcc General input/output (PD13) General input/output (PD12) General input/output (PD11) General input/output (PD10) General input/output (PD9) General input/output (PD8) General input/output (PD7) General input/output (PD6) General input/output (PD5) General input/output (PD4) General input/output (PD3) General input/output (PD2) General input/output (PD1) General input/output (PD0) General input/output (PA1) General input/output (PA0) General input/output (PE23) General input/output (PE22) General input/output (PE21) General input/output (PE20) General input/output (PE19) General input/output (PE18) General input/output (PE17) General input/output (PE16) General input/output (PF7) General input/output (PF6) General input/output (PF5) General input (PI7) General input (PI6) General input (PI5)
Function Function Function Function IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 DREQ1 DRAK1 DACK1 TIOC4B TIOC4A TIOC2B TIOC2A TIOC1B TIOC1A PWOB PVOB PUOB PWOA PVOA PUOA SCK1 IRQOUT TxD1 RxD1 SCK0 TIOC0D TIOC2A TIOC2B
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Section Overview Control Power No.* Supply Function Note: AVcc AVcc AVcc AVcc AVcc AVcc AVcc PVcc PVcc PVcc PVcc PVcc PVcc PVcc PVcc PVcc General input (PI4) General input (PI3) General input (PI2) General input (PI1) General input (PI0) General input/output (PH1) General input/output (PH0) General input/output (PE12) General input/output (PE13) General input/output (PE14) General input/output (PE15) General input/output (PG31) General input/output (PG30) General input/output (PG29) General input/output (PF2) General input/output (PF1) General input/output (PF3) General input/output (PB7) General input/output (PB6)
Function Function Function Function IRQ4 IRQ5 IRQ6 IRQ7 RxD2 TxD2 SCK2 DRAK0 DACK0 DREQ0 BACK BREQ TIOC0C TIOC0B TIOC0A
These numbers package numbers.
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Section
Section
Register Configuration
SH7065 sixteen 32-bit general registers, 32-bit control registers, 32-bit system registers. SH7065 upward-compatible with SH-1 SH-2 object code level, number registers have been added those provided previous SuperH microcomputers. additions comprise three control registers (the repeat start register (RS), repeat register (RE), modulo register (MOD)), system register (the status register (DSR)), registers (A0, within data registers. With SuperH microcomputer type instructions, general registers used same SH-1 SH-2, with type instructions, general registers used address index registers accessing memory. 2.1.1 General Registers
There sixteen 32-bit general registers (Rn), designated R15. general registers used data processing address calculation. With SuperH microcomputer type instructions, used index register. With number instructions, only register that used. used stack pointer (SP). exception handling, used reference stack when saving restoring status register (SR) program counter (PC). With type instructions, eight sixteen general registers used addressing data memory data memory (single data) that uses I-bus. access memory, used address register [Ax] used index register [Ix]. access memory, used address register [Ay] used index register [Iy]. access single data that uses I-bus, used single data address register [As] used single data index register [Is]. type instructions access access data memory simultaneously. sets address pointers provided specify data memory addresses. general registers shown figure 2.1.
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R0*1 [As]*3 [As]*3 [As, Ax]*3 [As, Ax]*3 [Ay]*3 [Ay]*3 [Ix, Is]*3 [Iy]*3 R15, SP*2
Notes: register used index register indexed register indirect addressing mode indexed indirect addressing mode. With certain instructions, only used source register destination register. register used stack pointer (SP) during exception handling. Used memory address register memory index register with type instructions.
Figure General Register Configuration assembler, symbols used. wished name that indicates role register type instructions, different register name (alias) used. coding assembler follows.
.REG (R8)
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name alias Other aliases assigned follows.
Ax0: Ax1: Ay0: Ay1: As0: As1: As2: As3: .REG .REG .REG .REG .REG .REG .REG .REG .REG .REG .REG (R4) (R5) (R8) (R6) (R7) (R9) (R4); Definition when alias required single data transfer. (R5); Definition when alias required single data transfer. (R2); Definition when alias required single data transfer. (R3); Definition when alias required single data transfer. (R8); Definition when alias required single data transfer.
2.1.2
Control Registers
There 32-bit control registers: status register (SR), repeat start register (RS), repeat register (RE), global base register (GBR), vector base register (VBR), modulo register (MOD). register shows processing status. register used base address indirect addressing mode, used data transfer involving on-chip peripheral module registers, etc. register used base address exception handling vector area, including interrupts. register register used control program repeats (loops). number loops specified repeat counter (RC) register, repeat start address specified register, repeat address specified register. However, address values stored register register necessarily same physical repeat start address address. register used modulo addressing repeat data buffering. modulo addressing specification made with register, modulo address (ME) specified upper bits register, modulo start address (MS) lower bits. bits cannot both specify modulo addressing simultaneously. Modulo addressing used with data transfer instructions (MOVX, MOVY), with single data transfer instruction (MOVS).
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Figure shows control register, table shows bits register.
Status register (SR) 0000 0000 IMASK Repeat start register (RS) Repeat register (RE) Global base register (GBR) Vector base register (VBR) Modulo register (MOD) Legend: Modulo address Modulo start address
Figure Control Register Configuration
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Section
Table
Bits 27-16
Register Bits
Name (Abbreviation) Repeat counter (RC) pointer modulo addressing specification (DMY) pointer modulo addressing specification (DMX) Interrupt request mask (IMASK) Repeat flags (RF1, RF0) These bits show interrupt request acceptance level 15). Used zero-overhead repeat (loop) control. follows when SETRC instruction used. 1-step repeat: 2-step repeat: 3-step repeat: more steps: Function These bits specify number repeats repeat (loop) control 4095). Modulo addressing mode enabled memory address pointer (R6, R7). Modulo addressing mode enabled memory address pointer (R4, R5). Used DIV0S/U DIV1 instructions.
Saturation operation
Used with instructions. Specifies saturation operation (preventing overflow)
With MOVT, CMP/cond, TAS, TST, BT/S, BF/S, SETT, CLRT, instructions: Indicates True Indicates False With ADDV/C, SUBV/C, DIV0U/S, DIV1, NEGC, SHAR/L, SHLR/L, ROTR/L. ROTCR/L instructions: Indicates occurrence carry, borrow, overflow, underflow
31-28, 15-12
bits
Always read Only should written these bits.
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Section
Special load/store instructions provided accessing registers. example, coding accessing register follows.
LDC.L STC.L Rm,RS; @Rm+,RS; RS,Rn; RS,@-Rn; (Rm) Rm+4 Rn-4 (Rn)
instructions setting address registers zero-overhead repeat control follows.
LDRS LDRE @(disp,PC); @(disp,PC); disp disp
registers same previous SuperH microcomputer registers. SH7065, four control bits (DMX, DMY, RF1, RF0) counter have been added register, registers provided registers. 2.1.3 System Registers
There four 32-bit system registers: multiply accumulate register high (MACH), multiply accumulate register (MACL), procedure register (PR), program counter (PC). MACH MACL store results multiply multiply accumulate operations*, stores return destination address subroutine procedure, shows executing program address controls processing flow. shows address bytes ahead currently executing instruction. These registers same SuperH microcomputer registers. Note: These registers used only when executing instruction supported SH-1 SH-2. They used with multiply instruction provided SH-DSP (PMULS).
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MACH MACL
Multiply accumulate register high (MACH) Multiply accumulate register (MACL)
Procedure register (PR)
Program counter (PC)
Figure System Register Configuration SH7065, unit registers (DSP registers) described below, status register (DSR) five eight data registers (A0, treated system registers. 40-bit register, when data output from register guard field (A0G) ignored, when data input register copied into guard field (A0G). 2.1.4 Registers
unit eight data registers control register registers. data registers comprise 40-bit registers, 32-bit registers, Registers each have 8-bit guard field, designated A1G, respectively. data registers used instruction operands data transfer processing. Instructions that access data registers three types, data processing, data transfer processing. control register 32-bit status register (DSR), which shows operation results. register contains bits that indicate result operation-the Signed Greater Than (GT), Zero Value (Z), Negative Value (N), Overflow (V), Condition (DC)-and also Condition Select bits (CS) that control setting. status flag that closely resembles SuperH microcomputer core. case conditional type instruction, execution during data processing controlled accordance with bit. This control extends only unit execution, only registers updated. effect address calculation SuperH microcomputer
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core execution instructions such load/store instructions. control bits (bits specify conditions setting bit. type instructions include unconditional type instructions conditional type instructions. unconditional type data processing, with exception PMULS, MOVX, MOVY, MOVS instructions, status bits updated. Conditional type instructions executed accordance with setting, register updated regardless whether these instructions executed. registers shown figure 2.4, register functions summarized table 2.2.
status register (DSR) data registers
CS[2:0]
Figure Register Configuration
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Section
Table
Bits 31-8
Register Bits
Name (Abbreviation) Reserved Signed Greater Than (GT) Function Always read write value should also Indicates that operation result positive (except zero) that operand greater than operand Operation result positive operand greater than operand
Zero Value
Indicates that operation result zero that operand equal operand Operation result zero operands equal Indicates that operation result negative that operand smaller than operand Operation result negative operand smaller than operand
Negative Value
Overflow Condition Select (CS)
Indicates that operation result overflowed. Operation result overflowed These bits specify mode selecting operation result status bit. these bits 111. 000: Carry/borrow mode 001: Negative value mode 010: Zero mode 011: Overflow mode 100: Signed greater than mode 101: Signed greater than equal mode
Condition (DC)
Sets status operation result mode specified bits. Specified mode status occurred (false) Specified mode status occurred
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register treated system register core instructions. following load/store instructions used data transfer from register.
STS.L LDS.L DSR,Rn; DSR,@-Rn; Rn,DSR; @Rn+,DSR;
registers also treated system registers core instructions. following load/store instructions used data transfer from these registers.
STS.L LDS.L Dm,Rn; Dm,@-Rn; Rn,Dm; @Rn+,Dm;
(Dm:
2.1.5
Notes Guard Bits Overflow Treatment
Data operations unit basically 32-bit operations, these operations always executed with 40-bit length including 8-bit guard field. guard field does match value 32-bit field, operation result treated overflow. this case, shows correct status operation result regardless whether overflow occurred. This also applies when destination operand 32-bit register. 8-bit guard field always assumed present, each status flag updated. overflow occurs that prevents result from being indicated correctly despite guard bits, flag will able show correct status.
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2.1.6
Initial Register Values
Register values after reset shown table 2.3. Table
Type General registers Control registers
Initial Register Values
Registers R0-R14 (SP) Undefined H'0000 0000 Undefined Undefined value vector address table Undefined H'0000 0000 Initial Value Undefined value vector address table 1111 (H'F); reserved bits, DMY, cleared other bits undefined Undefined
System registers registers
MACH, MACL, A0G, A1G,
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Section
2.2.1
Data Formats
Register Data Formats
register operand data size always longword bits). When data memory loaded into register, memory operand data size byte bits) word bits), sign-extended longword length.
Longword
Figure Register Data Format 2.2.2 Memory Data Formats
Byte, word, longword data formats used. Byte data located address, while word data must start address longword data address data accessed other than these boundaries, address error will result, result access cannot guaranteed. particular, since program counter (PC) status register (SR) stored longword format stack area indicated stack pointer (SP: R15), setting musty made that stack pointer value
Address Address Byte Address Address Word Longword Byte Address Address Address Address Byte Word Longword Address Address
Address Byte Byte Word Byte
Address Byte Word Byte
Big-endian
Little-endian
Figure Memory Data Format
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Section
2.2.3
Immediate Data Formats
Byte immediate data placed inside instruction code. With MOV, ADD, CMP/EQ instructions, immediate data sign-extended longword operation performed with register. With TST, AND, instructions, other hand, longword operation performed after zero-extending immediate data. Therefore, when immediate data used with instruction, upper bits destination register always cleared. Word longword immediate data should placed table memory, inside instruction code. table memory should referenced with immediate data transfer instruction (MOV) using relative addressing mode with displacement. 2.2.4 Type Data Formats
SH7065 three different data formats instructions: fixed-point data format, integer data format, logical data format. type fixed-point data format, there binary point between There three kinds format-with guard bits, without guard bits, multiplication input-each with different valid length range expressable values. type integer data format, there binary point between There three kinds format-with guard bits, without guard bits, shift amount-each with different valid length range expressable values. shift amount arithmetic shift (PSHA) 7-bit area, values from expressed, only values from actually valid. Similarly, shift amount logical shift (PSHL) 6-bit area, only values from actually valid. There radix point type logical data format. data format valid data length determined register. three type data formats position binary point each shown figure 2.7, together with SuperH type data format reference.
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type fixed-point With guard bits 2-31 Multiplication input 2-31 2-15
Without guard bits
type integer With guard bits -223 +223 Arithmetic shift (PSHA) Logical shift (PSHL) -215 +215
Without guard bits
type logical
bits)
SuperH type integer (word) [For reference]
-231 +231
Legend: Sign Binary point related processing (ignored)
Figure Type Data Formats
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Section
2.2.5
Type Instructions Data Formats
data format valid data length determined type instruction register. There three types instruction that access data registers: data processing instructions, data transfer processing instructions, single data transfer processing instructions. Data Processing: When register used source register fixedpoint data processing, guard bits (bits valid. When register other than (register used source register, sign-extension that register data used data bits When register used destination register, guard bits (bits valid. When register other than used destination register, bits result data ignored. integer data processing, situation same fixed-point data processing, except that lower word (lower bits: bits source register ignored, lower word destination register cleared logical data processing, upper word (upper bits: bits source register valid. lower word guard bits registers ignored. upper word destination register valid. lower word guard bits registers cleared Data Transfer: MOVX.W MOVY.W instructions access memory 16-bit data buses. data loaded into register data stored from register always upper word (upper bits: bits 16). load, MOVX.W loads memory with register destination register, while MOVY.W loads memory with register destination register. Data loaded into upper word register, while lower word cleared Data upper word register stored memory with data transfer instruction, data cannot stored from other register. guard bits lower word register ignored. Single Data Transfer: MOVS.W MOVS.L instructions access memory data (CDB). registers connected bus, used source destination registers data transfer. There data transfer modes: word longword. word mode, with exception registers, load performed store performed from, upper word register. longword mode, with exception registers, load performed store performed from, bits
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register. single data transfer, registers handled independent registers. load store data length registers bits. When register used source register word mode, data stored from register other than A1G, upper word register transferred. case registers, guard bits ignored. When register used source register word mode, only bits data stored from register, upper bits sign-extended. When register used destination register word mode, with exception registers, data loaded into upper word register. When data loaded into register other than A1G, lower word register cleared case registers, data sign extended loaded into guard bits, lower word cleared When register used destination register word mode, lowest bits data loaded into register, register cleared retains prior value. When register used source register longword mode, data stored from register other than A1G, bits register transferred. When register used source register, guard bits ignored. When register used source register longword mode, only bits data stored from register, upper bits sign-extended. When register used destination register longword mode, with exception registers, data loaded into bits register. case registers, data sign extended loaded into guard bits. When register used destination register longword mode, lowest bits data loaded into register, register cleared retains prior value.
register data formats used with instructions shown tables 2.5. With some instructions, registers accessed. example, with PMULS instruction, register specified source register, register cannot. descriptions instructions details. relationship between registers buses data transfer shown figure 2.8.
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Section
Table
Registers
Instruction Source Register Data Formats
Instructions operations Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer MOVX/Y.W, MOVS.W MOVS.L Guard Bits 40-bit data 24-bit data 16-bit data 16-bit data 32-bit data Data Data Sign* Sign* 32-bit data 16-bit data 16-bit data 16-bit data 32-bit data Register Bits
A0G,
Data transfer MOVS.W MOVS.L operations Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer MOVS.W MOVS.L
Note:
sign extended stored guard bits.
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Section
Table
Registers
Instruction Destination Register Data Formats
Instructions operations Fixed-point, PSHA, PMULS Integer, PDMSB Logical, PSHL Data transfer MOVS.W MOVS.L Guard Bits (Sign extension) (Sign extension) Sign extension Sign extension Data Data Register Bits 40-bit result 24-bit result Cleared Cleared Cleared
Cleared 16-bit result 16-bit result 32-bit data updated updated 32-bit result 16-bit result 16-bit data 32-bit data
A0G,
Data transfer MOVS.W MOVS.L operations Fixed-point, PSHA, PMULS Integer, logical, PDMSB, PSHL Data transfer MOVX.W, MOVY.W, MOVS.W MOVS.L
Cleared Cleared
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Section
bits bits bits [7:0] bits bits MOVS.W, MOVS.L MOVX.W, MOVY.W
bits MOVS.W, MOVS.L
Figure Relationship between Registers Buses Data Transfer
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Section
Features Core Instructions
core instructions RISC type instructions with following features: Fixed 16-Bit Length: instructions have fixed length bits. This improves program code efficiency. Instruction State: Pipelining used, basic instructions executed state (equivalent 16.7 60-MHz operation). Data Size: basic data size operations longword. Byte, word, longword selected memory access size. Memory byte word data sign-extended operated longword data. Immediate data sign-extended longword size arithmetic operations zero-extended longword size logical operations. Table Word Data Sign Extension
Description Example Other #H'1234,R0
SH7065 MOV.W .DATA.W H'1234 @(disp,PC),R1 R1,R0
Sign-extended bits, ADD.W becomes H'00001234, then operated instruction.
Note: Immediate data referenced @(disp,PC).
Load/store Architecture: Basic operations executed between registers. operations involving memory, data first loaded into register (load/store architecture). However, manipulation instructions such executed directly memory. Delayed Branching: Unconditional branch instructions, etc., executed delayed branches. With delayed branch instruction, branch made after execution instruction (called slot instruction) immediately following delayed branch instruction. This minimizes disruption pipeline when branch made. With delayed branch, actual branch operation occurs after execution slot instruction. However, instruction execution register updating, etc., excluding branch operation, performed delayed branch instruction delay slot instruction order. example, even though contents register holding branch destination address changed delay slot, branch destination address remains register contents prior change.
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Table
Delayed Branch Instructions
Description executed before branch TRGET. Example Other ADD.W R1,R0 TRGET
SH7065 TRGET R1,R0
Multiply/Multiply Accumulate Operations: multiply operation executed states, multiply accumulate operation states. multiply operation multiply accumulate operation each executed states. Bit: result comparison indicated status register (SR), conditional branch performed according whether result True False. Processing speed been improved keeping number instructions that modify minimum. Table
Description set. branch made TRGET0 TRGET1 ADD. set. branch made Example Other CMP.W SUB.W R1,R0 TRGET0 TRGET1 #1,R0 TRGET
SH7065 CMP/GE CMP/EQ R1,R0 TRGET0 TRGET1 #-1,R0 #0,R0 TRGET
Immediate Data: Byte immediate data placed inside instruction code. Word longword immediate data placed inside instruction code, table memory. table memory referenced with immediate data transfer instruction (MOV) using relative addressing mode with displacement.
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Table
Type
Immediate Data Referencing
SH7065 MOV.W #H'12,R0 @(disp,PC),R0 .DATA.W H'1234 Example Other MOV.B #H'12,R0 MOV.W #H'1234,R0
8-bit immediate 16-bit immediate
32-bit immediate
MOV.L .DATA.L
@(disp,PC),R0 H'12345678
MOV.L
#H'12345678,R0
Note: Immediate data referenced @(disp,PC).
Absolute Addresses: When data referenced absolute address, absolute address value placed table memory beforehand. With method whereby immediate data loaded when instruction executed, this value transferred register data referenced using register indirect addressing mode. Table 2.10 Absolute Address Referencing
Type Absolute address SH7065 MOV.L MOV.B .DATA.L @(disp,PC),R1 @R1,R0 H'12345678 Example Other MOV.B @H'12345678,R0
16-Bit/32-Bit Displacement: When data referenced with 32-bit displacement, displacement value placed table memory beforehand. With method whereby immediate data loaded when instruction executed, this value transferred register data referenced using indexed register indirect addressing mode. Table 2.11 Displacement Referencing
Type 16-bit displacement SH7065 MOV.W MOV.W @(disp,PC),R0 @(R0,R1),R2 Example Other MOV.W @(H'1234,R1),R2
.DATA.W H'1234
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Section
2.4.1
Instruction Formats
Instruction Addressing Modes
following table shows addressing modes effective address calculation methods instructions executed core. Table 2.12 Addressing Modes Effective Addresses Instructions
Addressing Mode Register direct Register indirect Register indirect with postincrement Instruction Format Effective Address Calculation Method Effective address register (Operand register contents.) Effective address register contents.
Calculation Formula
@Rn+
Effective address register contents. constant added after instruction execution: byte operand, word operand, longword operand.
1/2/4 1/2/4
After instruction execution Byte: Word: Longword:
Register indirect with predecrement
@-Rn
Effective address register contents, decremented constant beforehand: byte operand, word operand, longword operand.
1/2/4 1/2/4 1/2/4
Byte: Word: Longword: (Instruction executed with after calculation)
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Section Addressing Mode Instruction Format Calculation Formula Byte: disp Word: disp Longword: disp
Effective Address Calculation Method
Register @(disp:4,Rn) Effective address register contents indirect with with 4-bit displacement disp added. displacement After disp zero-extended, multiplied (byte), (word), (longword), according operand size.
disp (zero-extended) 1/2/4 disp 1/2/4
Indexed register indirect
@(R0,Rn)
Effective address register contents.
indirect @(disp:8, GBR) with displacement
Effective address register contents with 8-bit displacement disp added. After disp zero-extended, multiplied (byte), (word), (longword), according operand size.
disp (zero-extended) 1/2/4 disp 1/2/4
Byte: disp Word: disp Longword: disp
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Section Addressing Mode Instruction Format Calculation Formula
Effective Address Calculation Method Effective address register contents.
Indexed @(R0,GBR) indirect
@(disp:8,PC) Effective address with 8-bit PC-relative displacement disp added. After disp zerowith extended, multiplied (word) displacement (longword), according operand size. With longword operand, lower bits masked.
H'FFFFFFFC disp (zero-extended) With longword operand disp H'FFFFFFFC disp
Word: disp Longword: H'FFFFFFFC disp
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Section Addressing Mode PC-relative Instruction Format disp:8 Calculation Formula disp
Effective Address Calculation Method Effective address with 8-bit displacement disp added after being signextended multiplied
disp (sign-extended) disp
disp:12
Effective address with 12-bit displacement disp added after being signextended multiplied
disp (sign-extended) disp
disp
PC-relative
Effective address
Immediate
#imm:8 #imm:8 #imm:8
8-bit immediate data TST, AND, instruction zero-extended. 8-bit immediate data MOV, ADD, CMP/EQ instruction sign-extended.
8-bit immediate data TRAPA instruction zero-extended multiplied
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Section
2.4.2
Data Addressing
different memory accesses made with instructions. kinds instructions data transfer instructions (MOVX.W, MOVY.W) single data transfer instructions (MOVS.W, MOVSL). data addressing different these kinds instruction. overview data transfer instructions given table 2.13. Table 2.13 Overview Data Transfer Instructions
Data Transfer Processing (MOVX.W, MOVY.W) Address register Index register Addressing Nop/Inc (+2)/index addition: post-updating Modulo addressing Data Data length contention Memory Source register Destination register Possible XDB, bits (word) data memory X0/X1, Y0/Y1 Single Data Transfer Processing (MOVS.W, MOVS.L) Nop/Inc (+2, +4)/index addition: post-updating (-2, -4): pre-updating possible 16/32 bits (word/longword) Entire memory space A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A0/A1, M0/M1, X0/X1, Y0/Y1, A0G,
Data Addressing With instructions, data memory accessed simultaneously using MOVX.W MOVY.W instructions. address pointers provided instructions enable simultaneous access data memory. Only pointer addressing used with instructions; immediate addressing available. Address registers divided into two, with register functioning memory address register (Ax), register memory address register (Ay). following three kinds addressing used with data transfer instructions. Non-update address register addressing: registers address pointers. They updated.
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Addition index register addressing: registers address pointers. After data transfer, value register added each (post-updating). Increment address register addressing: registers address pointers. After data transfer, they each incremented (post-updating). There index register each address pointer. register index register (Ix) memory address register (Ax), register index register (Iy) memory address register (Ay). data transfer instructions perform word-length processing, 16-bit access data memory. value therefore added address register increment processing. perform decrementing, index register addition index register addressing specified. data addressing, only bits address pointer valid. When using data addressing, must always written address pointer index register. data transfer addressing shown figure 2.9. When accessing memory using buses, upper word ignored. result @AY+ @Ay+Iy stored lower word while upper word retains original value.
R8[Ix] (INC) update)
R4[Ax] R5[Ax]
R9[Iy] (INC) update)
R6[Ay] R7[Ay]
Adder provided addressing Note: Three address processing methods: Increment Index register addition (Ix/Iy) update Post-updating used cases. address pointer decremented setting -2/-4 index register.
Figure Data Transfer Addressing
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Section
Single Data Addressing instructions include single data transfer instructions (MOVS.W, MOVS.L) that load data into, store data from, register. With these instructions, registers used single data transfer address register (As). following four kinds addressing used with single data transfer instructions. Non-update address register addressing: register address pointer. updated. Addition index register addressing: register address pointer. After data transfer, value register added register (post-updating). Increment address register addressing: register address pointer. After data transfer, register incremented (post-updating). Decrement address register addressing: register address pointer. Before data transfer, added register (i.e. subtracted) (pre-updating). register index register (Is) address pointer (As). Single data transfer addressing shown figure 2.10.
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R2[As] R8[Is] -2/-4 (DEC) +2/+4 (INC) update) R3[As] R4[As] R5[As]
Note: Four address processing methods: update Index register addition (Is) Increment Decrement
Post-updating Pre-updating
Figure 2.10 Single Data Transfer Addressing Modulo Addressing Like other DSPs, SH7065 modulo addressing mode. Address registers updated same this mode. When address pointer value reaches preset modulo address, address pointer value becomes modulo start address. Modulo addressing only available data transfer instructions (MOVX.W, MOVY.W). Modulo addressing mode specified address register setting register, address register setting bit. Modulo addressing valid either address register, only; cannot both same time. Therefore, cannot both simultaneously they are, setting will valid). register provided start addresses modulo address area. register contains (Modulo Start) (Modulo End). example register fields) shown below.
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Section MOV.L ModAddr,Rn; Rn=ModEnd, ModStart Rn,MOD; ModAddr: .DATA.W .DATA.W ME=ModEnd, MS=ModStart mEnd; mStart; ModEnd ModStart
ModStart:
.DATA
ModEnd:
.DATA
start addresses specified then address register contents compared with they match, start address stored address register. lower bits address register compared with maximum modulo size kbytes. This sufficient access memory. block diagram modulo addressing shown figure 2.11.
Instruction (MOVX/MOVY) R4[Ax] R6[Ay] R5[Ax] CONT R7[Ay]
R9[Iy]
R8[Ix]
Figure 2.11 Modulo Addressing
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example modulo addressing given below.
H'C008; H'C00C; H'C008;
(Modulo addressing setting address register (R4, R5))
result above settings, register changes follows.
H'C008 Inc. Inc. Inc. H'C00A H'C00C H'C008
(Reaches modulo address, becomes modulo start address)
Place data that upper bits modulo start addresses same. This because modulo start address overwrites only lower bits address register, excluding Note: When addition indexing used data addressing, address pointer exceed value without actually reaching this case, address pointer will return modulo start address. only with modulo addressing, when data addressing used, ignored. must always written address pointer, index register, Addressing Operations addressing operations pipeline execution stage (EX), including modulo addressing, shown below.
Operation MOVX.W MOVY.W ABx=Ax; ABy=Ay; memory access cycle uses ABy. addresses used have been updated
R4,5 DMX==0 DMX==1 Ax=Ax+(+2 R8[Ix] +0); Inc,Index,Not-Update else not-update) Ax=modulo( R8[Ix])
R6,7
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Section DMY==0 Ay=Ay+(+2 R9[Iy] +0); Inc,Index,Not-Update else not-update) Ay=modulo( R9[Iy]) else Operation MOVS.W MOVS.L Addressing Nop, Inc, Add-index-reg MAB=As; memory access cycle uses MAB. address used been updated R2-5 As=As+(+2 R8[Is] +0); Inc,Index,Not-Update else Decrement, Pre-update R2-5 As=As+(-2 -4); MAB=As; memory access cycle uses MAB. address used been updated
value added address register depends addressing operations. example, R8[Ix] means that R8[Ix] operation increment operation add-index-reg operation not-update
function modulo AddrReg, Index AdrReg[15:0]==ME AdrReg[15:0]==MS; else AdrReg=AdrReg+Index; return AddrReg;
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Section
2.4.3
Instruction Formats
Table 2.14 shows instruction formats, meaning source destination operands, instructions executed core. meaning operands depends instruction code. following symbols used table. xxxx: mmmm: nnnn: iiii: dddd: Instruction code Source register Destination register Immediate data Displacement
Table 2.14 Instruction Formats
Instruction Formats type type
xxxx xxxx nnnn xxxx xxxx xxxx xxxx xxxx
Source Operand Control register system register Control register system register
Destination Operand nnnn: register direct nnnn: register direct
Sample Instruction MOVT MACH,Rn
nnnn: preSTC.L SR,@-Rn decrement register indirect Control register system register Rm,SR
type
xxxx mmmm xxxx xxxx
mmmm: register direct mmmm: postincrement register indirect mmmm: register indirect
Control register LDC.L system @Rm+,SR register
mmmm: PC-relative using
BRAF
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Section Source Operand
xxxx nnnn mmmm xxxx
Instruction Formats type
Destination Operand nnnn: register direct nnnn: register indirect MACH, MACL
Sample Instruction Rm,Rn
mmmm: register direct mmmm: register direct mmmm: postincrement register indirect (multiply accumulate operation) nnnn: postincrement register indirect (multiply accumulate operation) mmmm: postincrement register indirect mmmm: register direct mmmm: register direct
MOV.L Rm,@Rn MAC.W @Rm+,@Rn+
nnnn: register direct
MOV.L @Rm+,Rn
nnnn: preMOV.L decrement Rm,@-Rn register indirect nnnn: indexed MOV.L register indirect Rm,@(R0,Rn) (register direct) MOV.B @(disp,Rm),R0
type
xxxx xxxx mmmm dddd
mmmmdddd: register indirect with displacement (register direct)
type
xxxx xxxx nnnn dddd
nnnndddd: register indirect with displacement nnnndddd: register indirect with displacement nnnn: register direct
MOV.B R0,@(disp,Rn)
type
xxxx nnnn mmmm dddd
mmmm: register direct
MOV.L Rm,@(disp,Rn)
mmmmdddd: register indirect with displacement
MOV.L @(disp,Rm),Rn
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Section Source Operand
xxxx xxxx dddd dddd
Instruction Formats type
Destination Operand (register direct)
Sample Instruction MOV.L @(disp,GBR),R0
dddddddd: indirect with displacement (register direct)
dddddddd: indirect with displacement (register direct)
MOV.L R0,@(disp,GBR)
dddddddd: PC-relative with displacement dddddddd: PC-relative type
xxxx dddd dddd dddd
MOVA @(disp,PC),R0 label
dddddddddddd: PC-relative dddddddd: PC-relative with displacement iiiiiiii: immediate iiiiiiii: immediate iiiiiiii: immediate nnnn: register direct Indexed indirect (register direct) nnnn: register direct
label (label=disp+PC) MOV.L @(disp,PC),Rn AND.B #imm,@(R0,GBR) #imm,R0
type
xxxx nnnn dddd dddd
type
xxxx xxxx iiii iiii
TRAPA #imm #imm,Rn
type
xxxx nnnn iiii iiii
iiiiiiii: immediate
Note:
multiply accumulate instructions, nnnn source register.
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Section
2.4.4
Instruction Formats
SH7065 includes instructions digital signal processing. instructions following kinds. Memory register double single data transfer instructions (16-bit length) Parallel processing instructions processed unit (32-bit length) instruction formats shown figure 2.12.
core instructions 0000 1110 field
Double data transfer instructions Single data transfer instructions Parallel processing instructions
111100
field field field
111101
111110
Figure 2.12 Instruction Formats
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Section
Double Single Data Transfer Instructions format double data transfer instructions shown table 2.15, that single data transfer instructions table 2.16. Table 2.15 Double Data Transfer Instruction Formats
Type Mnemonic
memory NOPX data MOVX.W @Ax,Dx transfer MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix memory NOPY data MOVY.W @Ay,Dy transfer MOVY.W @Ay+,Dy MOVY.W @Ay+Iy,Dy MOVY.W Da,@Ay MOVY.W Da,@Ay+ MOVY.W Da,@Ay+Iy Legend:
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Table 2.16 Single Data Transfer Instruction Formats
Type Single data transfer Mnemonic MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As+,Ds MOVS.W @As+Ix,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Ix MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Ix,Ds MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As+ MOVS.L Ds,@As+Ix Note: Codes reserved system use. 0:R4 1:R5 2:R2 3:R3
0:(*) 1:(*) 2:(*) 3:(*) 4:(*) 5:A1 6:(*) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 E:M1 F:A0G
D:A1G
Parallel Processing Instructions Parallel processing instructions provided efficient execution digital signal processing using unit. They bits long allow four simultaneous processes, operation, multiplication, data transfers. Parallel processing instructions divided into field field. field defines data transfer instructions field operation instruction multiply instruction. These instructions defined independently, processing executed parallel, independently simultaneously. field parallel data transfer instructions shown table 2.17, field operation instructions multiply instructions table 2.18.
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Category field
Mnemonic
Section
memory data transfer
field
memory data transfer
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NOPX MOVX.W @Ax, MOVX.W @Ax+, MOVX.W @Ax+Ix, MOVX.W MOVX.W @Ax+ MOVX.W @Ax+Ix NOPY MOVY.W @Ay, MOVY.W @Ay+, MOVY.W @Ay+Iy, MOVY.W MOVY.W @Ay+ MOVY.W @Ay+Iy
Table 2.17 Field Parallel Data Transfer Instructions
Legend:
Category
field 0:M0 1:M1 2:A0 3:A1 0:X0 1:Y0 2:A0 3:A1 0:X0 1:X1 2:Y0 3:A1 0:Y0 1:Y1 2:X0 3:A1 0:X0 1:X1 2:A0 3:A1 0:Y0 1:Y1 2:M0 3:M1
Mnemonic
Imm. shift
PSHL #Imm, PSHA #Imm, Reserved
PMULS
operand parallel instruction
Reserved
PSUB PMULS PADD PMULS Reserved
Table 2.18 Field Operation Instructions Multiply Instructions
Three operand instructions PSUBC PADDC PCMP Reserved Reserved Reserved PABS PRND PABS PRND Reserved
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0:(*1) 1:(*1) 2:(*1) 3:(*1) 4:(*1) 5:A1 6:(*1) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:(*1) E:M1 F:(*1)
Section
Category
0:Y0 1:Y1 2:M0 3:M1 field 0:X0 1:X1 Uncon- 2:A0 ditional 3:A1
Mnemonic
Section
Conditional three operand instructions
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0:(*1) 1:(*1) 2:(*1) 3:(*1) 4:(*1) 5:A1 6:(*1) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:(*1) E:M1 F:(*1)
PSHL PSHA PSUB PADD Reserved PAND PXOR PDEC PINC PDEC PINC PCLR PDMSB Reserved PDMSB PNEG PCOPY PNEG PCOPY Reserved PSTS MACH, PSTS MACL, PLDS MACH PLDS MACL (*2) Reserved
Reserved
Notes: Codes reserved system use. cc]: True), False) none (unconditional instruction)
Section
Instruction
SH7065 instructions divided into three kinds: instructions executed core, data transfer instructions operation instructions executed unit. instructions include several supporting functions. instruction sets each these three kinds instructions described below. 2.5.1 Instruction
instructions listed type table 2.19. Table 2.19 Instruction Types
Type Data transfer instructions Kinds Instruction Code Function Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer MOVA MOVT SWAP XTRCT Arithmetic operation instructions ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU Effective address transfer transfer Upper/lower swap Extraction middle linked registers Binary addition Binary addition with carry Binary addition with overflow Comparison Division Signed division initialization Unsigned division initialization Signed double-precision multiplication Unsigned double-precision multiplication Decrement test Number Instructions
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Section Kinds Instruction Number Instructions
Type Arithmetic operation instructions
Code EXTS EXTU MULS MULU NEGC SUBC SUBV
Function Sign extension Zero extension Multiply accumulate, doubleprecision multiply accumulate Double-precision multiplication Signed multiplication Unsigned multiplication Sign inversion Sign inversion with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow Logical inversion Logical Memory test Logical state Exclusive logical 1-bit left shift with 1-bit right shift with 1-bit left shift 1-bit right shift Arithmetic 1-bit left shift Arithmetic 1-bit right shift Logical 1-bit left shift Logical n-bit left shift Logical 1-bit right shift Logical n-bit right shift
Logic operation instructions
Shift instructions
ROTCL ROTCR ROTL ROTR SHAL SHAR SHLL SHLLn SHLR SHLRn
Rev. 5.00 2006 page REJ09B0332-0500
Section Kinds Instruction Number Instructions
Type Branch instructions
Code
Function Condition branch, delayed conditional branch (branches Condition branch, delayed conditional branch (branches Unconditional branch Unconditional branch Branch subroutine procedure Branch subroutine procedure Unconditional branch Branch subroutine procedure Return from subroutine procedure register clear clear Load into control register Load into repeat register Load into repeat start register Load into system register operation Return from exception handling Repeat count setting setting Transition power-down mode Store from control register Store from system register Trap exception handling
BRAF BSRF System control instructions CLRMAC CLRT LDRE LDRS SETRC SETT SLEEP TRAPA Total:
Total:
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Section
instruction code, operation, number execution states instructions shown following tables, classified instruction type, using format shown below.
Instruction Indicated mnemonic. Instruction Code Indicated order. Explanation Symbols mmmm: Source register nnnn: Destination register 0000: 0001: 1111: iiii: Immediate data Operation Indicates summary operation. Execution States Value when wait states inserted* Value after instruction executed. Explanation Symbols change
Explanation Symbols OP.Sz SRC, DEST Operation code Size SRC: Source DEST: Destination Source register Destination register imm: Immediate data disp: Displacement*
Explanation Symbols Transfer direction (xx): Memory operand
M/Q/T: Flag bits Logical each Logical each Exclusive logical each Logical each n-bit left shift n-bit right shift
dddd: Displacement
<<n: >>n:
Notes: table shows minimum number execution states. practice, number instruction execution states will increased cases such following: When there conflict between instruction fetch data access When destination register load instruction (memory register) also used following instruction Scaling executed according instruction operand size. SH-1/SH-2/SH-DSP Software Manual details.
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Section
Table 2.20 Data Transfer Instructions
Instruction #imm,Rn Instruction Code Operation Execution States
1110nnnniiiiiiii sign extension 1001nnnndddddddd (disp sign extension 1101nnnndddddddd (disp 0110nnnnmmmm0011 0010nnnnmmmm0000 (Rn) 0010nnnnmmmm0001 (Rn) 0010nnnnmmmm0010 (Rn) 0110nnnnmmmm0000 (Rm) sign extension 0110nnnnmmmm0001 (Rm) sign extension 0110nnnnmmmm0010 (Rm)
MOV.W @(disp,PC),Rn MOV.L MOV.B MOV.L MOV.B @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn @Rm,Rn
MOV.W Rm,@Rn
MOV.W @Rm,Rn MOV.L MOV.B MOV.L MOV.B @Rm,Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn
0010nnnnmmmm0100 (Rn) 0010nnnnmmmm0101 (Rn) 0010nnnnmmmm0110 (Rn) 0110nnnnmmmm0100 (Rm) sign extension 0110nnnnmmmm0101 (Rm) sign extension 0110nnnnmmmm0110 (Rm) 10000000nnnndddd (disp 10000001nnnndddd (disp 0001nnnnmmmmdddd (disp 10000100mmmmdddd (disp sign extension 10000101mmmmdddd (disp sign extension 0101nnnnmmmmdddd (disp 0000nnnnmmmm0100
MOV.W Rm,@-Rn
MOV.W @Rm+,Rn MOV.L MOV.B MOV.L MOV.B @Rm+,Rn R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0
MOV.W R0,@(disp,Rn)
MOV.W @(disp,Rm),R0 MOV.L MOV.B @(disp,Rm),Rn Rm,@(R0,Rn)
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Section Execution States
Instruction MOV.W Rm,@(R0,Rn) MOV.L MOV.B Rm,@(R0,Rn) @(R0,Rm),Rn
Instruction Code
Operation
0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 sign extension 0000nnnnmmmm1101 sign extension 0000nnnnmmmm1110
MOV.W @(R0,Rm),Rn MOV.L MOV.B MOV.L MOV.B @(R0,Rm),Rn
R0,@(disp,GBR) 11000000dddddddd (disp GBR) R0,@(disp,GBR) 11000010dddddddd (disp GBR) @(disp,GBR),R0 11000100dddddddd (disp GBR) sign extension
MOV.W R0,@(disp,GBR) 11000001dddddddd (disp GBR)
MOV.W @(disp,GBR),R0 11000101dddddddd (disp GBR) sign extension MOV.L MOVA MOVT @(disp,GBR),R0 11000110dddddddd (disp GBR) @(disp,PC),R0 11000111dddddddd disp 0000nnnn00101001 0110nnnnmmmm1000 swap lower bytes 0110nnnnmmmm1001 swap upper/lower words 0010nnnnmmmm1101 Middle bits
SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn
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Section
Table 2.21 Arithmetic Operation Instructions
Instruction ADDC ADDV Rm,Rn #imm,Rn Rm,Rn Rm,Rn Instruction Code Operation Execution States Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result
0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 carry 0011nnnnmmmm1111 overflow 10001000iiiiiiii When imm, 0011nnnnmmmm0000 When 0011nnnnmmmm0010 When (unsigned),
CMP/EQ #imm,R0 CMP/EQ Rm,Rn CMP/HS Rm,Rn CMP/GE Rm,Rn CMP/HI Rm,Rn
0011nnnnmmmm0011 When (signed), 0011nnnnmmmm0110 When (unsigned),
CMP/GT Rm,Rn CMP/PL CMP/PZ
0011nnnnmmmm0111 When (signed), 0100nnnn00010101 When 0100nnnn00010001 When 0010nnnnmmmm1100 When bytes equal, 0011nnnnmmmm0100 1-step division 0010nnnnmmmm0111 0000000000011001 M/Q/T 0011nnnnmmmm1101 Signed, MACH, MACL bits
CMP/STR Rm,Rn DIV1 DIV0S Rm,Rn Rm,Rn
DIV0U DMULS.L Rm,Rn
2-4*
Rev. 5.00 2006 page REJ09B0332-0500
Section Execution States 2-4*
Instruction DMULU.L Rm,Rn
Instruction Code
Operation
0011nnnnmmmm0101 Unsigned, MACH, MACL bits 0100nnnn00010000 when When 0110nnnnmmmm1110 sign-extended from byte 0110nnnnmmmm1111 sign-extended from word 0110nnnnmmmm1100 zero-extended from byte 0110nnnnmmmm1101 zero-extended from word
Comparison result
EXTS.B
Rm,Rn
3/(2-4)*
EXTS.W Rm,Rn EXTU.B Rm,Rn
EXTU.W Rm,Rn MAC.L
@Rm+,@Rn+ 0000nnnnmmmm1111 Signed, (Rn) (Rm) bits @Rm+,@Rn+ 0100nnnnmmmm1111 Signed, (Rn) (Rm) bits Rm,Rn 0000nnnnmmmm0111 MACL bits 0010nnnnmmmm1111 Signed, bits 0010nnnnmmmm1110 Unsigned, bits 0110nnnnmmmm1011 0110nnnnmmmm1010 borrow 0011nnnnmmmm1000
MAC.W
3/(2)*
MUL.L
2-4* 1-3*
MULS.W Rm,Rn
MULU.W Rm,Rn
1-3*
NEGC
Rm,Rn Rm,Rn Rm,Rn
Borrow
Rev. 5.00 2006 page REJ09B0332-0500
Section Execution States Borrow Underflow
Instruction SUBC SUBV Note: Rm,Rn Rm,Rn
Instruction Code
Operation
0011nnnnmmmm1010 borrow 0011nnnnmmmm1011 underflow
normal number execution states shown. number parentheses number execution cycles case contention with preceding following instructions.
Table 2.22 Logic Operation Instructions
Instruction Rm,Rn #imm,R0 Instruction Code Operation Execution States Test result Test result Test result Test result
0010nnnnmmmm1001 11001001iiiiiiii
AND.B #imm,@(R0,GBR) 11001101iiiiiiii GBR) GBR) Rm,Rn Rm,Rn #imm,R0 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii
OR.B #imm,@(R0,GBR) 11001111iiiiiiii GBR) GBR) TAS.B Rm,Rn #imm,R0 0100nnnn00011011 When (Rn) (Rn) 0010nnnnmmmm1000 when result 11001000iiiiiiii imm; when result
TST.B #imm,@(R0,GBR) 11001100iiiiiiii GBR) imm; when result Rm,Rn #imm,R0 0010nnnnmmmm1010 11001010iiiiiiii
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii GBR) GBR)
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Section
Table 2.23 Shift Instructions
Instruction ROTL ROTR ROTCL SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Instruction Code Operation Execution States
0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001
ROTCR
SHLL16 SHLR16
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Section
Table 2.24 Branch Instructions
Instruction label Instruction Code 10001011dddddddd Operation When disp when Delayed branch; when disp when When disp when Delayed branch; when disp when Delayed branch, disp Delayed branch, Delayed branch, disp Delayed branch, Delayed branch, Delayed branch, Delayed branch, Execution States 3/1*
BF/S
label
10001111dddddddd
2/1*
label
10001001dddddddd
3/1*
BT/S
label
10001101dddddddd
2/1*
label
1010dddddddddddd 0000mmmm00100011 1011dddddddddddd
BRAF label
BSRF
0000mmmm00000011
Note:
0100mmmm00101011 0100mmmm00001011 0000000000001011
state when branch executed.
Rev. 5.00 2006 page REJ09B0332-0500
Section
Table 2.25 System Control Instructions
Instruction CLRMAC CLRT LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDRE LDRS LDS.L LDS.L LDS.L LDS.L Rm,SR Rm,GBR Rm,VBR Rm,MOD Rm,RE Rm,RS @Rm+,SR @Rm+,GBR @Rm+,VBR @Rm+,RE @Rm+,RS @(disp,PC) @(disp,PC) Rm,MACH Rm,MACL Rm,PR Rm,DSR Rm,A0 Rm,X0 Rm,X1 Rm,Y0 Rm,Y1 Instruction Code Operation Execution States
0000000000101000 MACH, MACL 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm01011110 0100mmmm01111110 0100mmmm01101110 0100mmmm00000111 (Rm) 0100mmmm00010111 (Rm) GBR, 0100mmmm00100111 (Rm) VBR, 0100mmmm01110111 (Rm) 0100mmmm01100111 (Rm) 10001110dddddddd disp 10001100dddddddd disp 0100mmmm00001010 MACH 0100mmmm00011010 MACL 0100mmmm00101010 0100mmmm01101010 0100mmmm01111010 0100mmmm10001010 0100mmmm10011010 0100mmmm10101010 0100mmmm10111010
@Rm+,MOD 0100mmmm01010111 (Rm) MOD,
@Rm+,MACH 0100mmmm00000110 (Rm) MACH, @Rm+,MACL 0100mmmm00010110 (Rm) MACL, @Rm+,PR @Rm+,DSR 0100mmmm00100110 (Rm) 0100mmmm01100110 (Rm) DSR,
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Section Execution States
Instruction LDS.L LDS.L LDS.L LDS.L LDS.L SETRC @Rm+,A0 @Rm+,X0 @Rm+,X1 @Rm+,Y0 @Rm+,Y1
Instruction Code
Operation
0100mmmm01110110 (Rm) 0100mmmm10000110 (Rm) 0100mmmm10010110 (Rm) 0100mmmm10100110 (Rm) 0100mmmm10110110 (Rm) 0000000000001001 operation 0000000000101011 Delayed branch, stack area PC/SR 0100mmmm00010100 operation result (repeat status) RF1, [11:0] [27:16]) 10000010iiiiiiii operation result (repeat status) RF1, [23:16]), zeros [27:24]
SETRC
#imm
SETT SLEEP STC.L STC.L STC.L STC.L STC.L STC.L SR,Rn GBR,Rn VBR,Rn MOD,Rn RE,Rn RS,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MOD,@-Rn RE,@-Rn RS,@-Rn MACH,Rn MACL,Rn PR,Rn
0000000000011000 0000000000011011 Sleep 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn01010010 0000nnnn01110010 0000nnnn01100010 0100nnnn00000011 (Rn) 0100nnnn00010011 (Rn) 0100nnnn00100011 (Rn) 0100nnnn01010011 (Rn) 0100nnnn01110011 (Rn) 0100nnnn01100011 (Rn) 0000nnnn00001010 MACH 0000nnnn00011010 MACL 0000nnnn00101010
Rev. 5.00 2006 page REJ09B0332-0500
Section Execution States
Instruction STS.L STS.L STS.L STS.L STS.L STS.L STS.L STS.L STS.L TRAPA Note: DSR,Rn A0,Rn X0,Rn X1,Rn Y0,Rn Y1,Rn
Instruction Code
Operation
0000nnnn01101010 0000nnnn01111010 0000nnnn10001010 0000nnnn10011010 0000nnnn10101010 0000nnnn10111010
MACH,@-Rn 0100nnnn00000010 MACH (Rn) MACL,@-Rn 0100nnnn00010010 MACL (Rn) PR,@-Rn DSR,@-Rn A0,@-Rn X0,@-Rn X1,@-Rn Y0,@-Rn Y1,@-Rn #imm 0100nnnn00100010 (Rn) 0100nnnn01100010 (Rn) 0100nnnn01110010 (Rn) 0100nnnn10000010 (Rn) 0100nnnn10010010 (Rn) 0100nnnn10100010 (Rn) 0100nnnn10110010 (Rn) 11000011iiiiiiii PC/SR stack area, (imm VBR)
Number states until transition sleep state.
Caution: table shows minimum number execution states. practice, number instruction execution states will increased cases such following: When there conflict between instruction fetch data access When destination register load instruction (memory register) also used following instruction When branch destination address branch instruction address Depending number cycles instruction fetch destination data access destination (see 8.4, Number Access Cycles (SH7065A) section State Controller (BSC), details).
Rev. 5.00 2006 page REJ09B0332-0500
Section
Instructions Supporting Functions number system control instructions have been added core instructions support functions. registers have been added, supporting repeat control modulo addressing, repeat counter (RC) been added status register (SR). instructions have been added order access these additions, while instructions have been added access registers DSR, Another addition SETRC instruction which sets value repeat counter (RC: bits repeat flags (RF1, RF0: bits register. When immediate operand used SETRC instruction, 8-bit immediate data stored bits bits cleared When operand register, bits from register stored bits According values 1-instruction repeat (00), 2-instruction repeat (01), 3-instruction repeat (11), 4-plus-instruction repeat (10) set. addition instruction, LDRS LDRE instructions have been added instructions that repeat start address repeat address registers. added instructions shown table 2.26. Table 2.26 Added Instructions
Instruction Rm,MOD Rm,RE Rm,RS Instruction Code Operation Execution States
0100mmmm01011110 0100mmmm01111110 0100mmmm01101110 0100mmmm01010111 (Rm) MOD, 0100mmmm01110111 (Rm) 0100mmmm01100111 (Rm) 0000nnnn01010010 0000nnnn01110010 0000nnnn01100010 0100nnnn01010011 (Rn) 0100nnnn01110011 (Rn) 0100nnnn01100011 (Rn) 0100mmmm01101010
LDC.L @Rm+,MOD LDC.L @Rm+,RE LDC.L @Rm+,RS MOD,Rn RE,Rn RS,Rn
STC.L MOD,@-Rn STC.L RE,@-Rn STC.L RS,@-Rn Rm,DSR
Rev. 5.00 2006 page REJ09B0332-0500
Section Execution States
Instruction LDS.L @Rm+,DSR Rm,A0 Rm,X0 Rm,X1 Rm,Y0 Rm,Y1 DSR,Rn A0,Rn X0,Rn X1,Rn Y0,Rn Y1,Rn LDS.L @Rm+,A0 LDS.L @Rm+,X0 LDS.L @Rm+,X1 LDS.L @Rm+,Y0 LDS.L @Rm+,Y1 STS.L DSR,@-Rn STS.L A0,@-Rn STS.L X0,@-Rn STS.L X1,@-Rn STS.L Y0,@-Rn STS.L Y1,@-Rn SETRC SETRC #imm LDRS LDRE @(disp,PC) @(disp,PC)
Instruction Code
Operation
0100mmmm01100110 (Rm) DSR, 0100mmmm01111010 0100mmmm01110110 (Rm) 0100mmmm10001010 0100mmmm10000110 (Rm) 0100mmmm10011010 0100mmmm10010110 (Rm) 0100mmmm10101010 0100mmmm10100110 (Rm) 0100mmmm10111010 0100mmmm10110110 (Rm) 0000nnnn01101010 0100nnnn01100010 (Rn) 0000nnnn01111010 0100nnnn01110010 (Rn) 0000nnnn10001010 0100nnnn10000010 (Rn) 0000nnnn10011010 0100nnnn10010010 (Rn) 0000nnnn10101010 0100nnnn10100010 (Rn) 0000nnnn10111010 0100nnnn10110010 (Rn) 0100mmmm00010100 [11:0] [27:16]) 10000010iiiiiiii [23:16]), [27:24] 10001100dddddddd disp 10001110dddddddd disp
Rev. 5.00 2006 page REJ09B0332-0500
Section
2.5.2
Data Transfer Instruction
data transfer instructions listed type table 2.27. Table 2.27 Data Transfer Instruction Types
Type Double data transfer instructions Kinds Instruction Code NOPX MOVX NOPY MOVY Single data transfer instruction Total: MOVS Function memory operation memory data transfer memory operation memory data transfer Single data transfer Total: Number Instructions
Data transfer instructions divided into groups: double data transfer single data transfer. Double data transfer executed parallel processing instructions combination with operation instructions. Parallel processing instructions bits long, incorporate double data transfer instruction field. Double data transfer instructions that parallel processing instructions, single data transfer instructions, bits long. double data transfer, memory memory simultaneously accessed parallel. Instructions specified from memory data accesses, respectively. pointer used access memory, pointer access memory. Double data transfer only used access memory. single data transfer, access possible from area. single data transfer, pointer other pointers used pointer.
Rev. 5.00 2006 page REJ09B0332-0500
Section
Table 2.28 Double Data Transfer Instructions Memory Data)
Instruction NOPX MOVX.W @Ax,Dx MOVX.W @Ax+,Dx Operation operation (Ax) (Ax) Instruction Code Execution States
1111000*0*0*00** 111100A*D*0*01** 111100A*D*0*10** 111100A*D*0*11** 111100A*D*1*01**
MOVX.W @Ax+Ix,Dx (Ax) MOVX.W Da,@Ax MOVX.W Da,@Ax+ (Ax)
(Ax), 111100A*D*1*10**
MOVX.W Da,@Ax+Ix (Ax), 111100A*D*1*11**
Table 2.29 Double Data Transfer Instructions Memory Data)
Instruction NOPY MOVY.W @Ay,Dy MOVY.W @Ay+,Dy Operation operation (Ay) (Ay) Instruction Code Execution States
111100*0*0*0**00 111100*A*D*0**01 111100*A*D*0**10 111100*A*D*0**11 111100*A*D*1**01
MOVY.W @Ay+Iy,Dy (Ay) MOVY.W Da,@Ay MOVY.W Da,@Ay+ (Ay)
(Ay), 111100*A*D*1**10
MOVY.W Da,@Ay+Iy (Ay), 111100*A*D*1**11
Rev. 5.00 2006 page REJ09B0332-0500
Section
Table 2.30 Single Data Transfer Instructions
Instruction MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As+,Ds Operation (As) (As) (As) Instruction Code Execution States
111101AADDDD0000 111101AADDDD0100 111101AADDDD1000 111101AADDDD1100
MOVS.W @As+Ix,Ds (As) MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds
(As)* 111101AADDDD0001 (As)* 111101AADDDD0101 (As)*, 111101AADDDD1001 (As) (As) (As) 111101AADDDD0010 111101AADDDD0110 111101AADDDD1010 111101AADDDD1110 111101AADDDD0011 111101AADDDD0111 111101AADDDD1011 111101AADDDD1111
MOVS.W Ds,@As+Is (As)*, 111101AADDDD1101
MOVS.L @As+Is,Ds (As) MOVS.L Ds,@-As (As)* MOVS.L Ds,@As MOVS.L Ds,@As+ Note: (As)* (As)*,
MOVS.L Ds,@As+Is (As)*,
When guard register specified source operand data sign-extended before being transferred.
correspondence between data transfe
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