16-bit SMBus Port with Interrupt 400kHz compatible 2.3V 5.5V oper

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16-bit SMBus Port with Interrupt 400kHz compatible 2.3V 5.5V oper

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CAT9555
16-bit SMBus Port with Interrupt
400kHz compatible 2.3V 5.5V operation stand-by current tolerant I/Os pins that default inputs power-up High drive capability Individual configuration Polarity inversion register Active interrupt output Internal power-on reset glitch power-up Noise filter SDA/SCL inputs Cascadable devices Industrial temperature range RoHS-compliant 24-lead SOIC TSSOP, 24-pad TQFN 4mm) packages
DESCRIPTION
CAT9555 CMOS device that provides 16-bit parallel input/output port expansion SMBus compatible applications. These expanders provide simple solution applications where additional I/Os needed: sensors, power switches, LEDs, pushbuttons, fans. CAT9555 consists 8-bit Configuration ports (input output), Input, Output Polarity inversion registers, serial interface. sixteen I/Os configured input output writing configuration register. system master invert CAT9555 input data writing active-high polarity inversion register. CAT9555 features active interrupt output which indicates system master that input state changed. three address input pins provide device's extended addressing capability allow eight devices share same bus. fixed part slave address same CAT9554, allowing eight these devices combination connected same bus. Ordering Information details, page
APPLICATIONS
White goods (dishwashers, washing machines) Handheld devices (cell phones, PDAs, digital cameras) Data Communications (routers, hubs servers)
BLOCK DIAGRAM
I/O1.0 8-BIT INPUT/ OUTPUT PORTS I/O1.1 I/O1.2 I/O1.3 I/O1.4 I/O1.5 I/O1.6 I/O1.7 I/O0.0 8-BIT INPUT/ OUTPUT PORTS I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 VINT I/O0.6 I/O0.7 FILTER
WRITE pulse READ pulse I2C/SMBUS CONTROL INPUT FILTER
WRITE pulse POWER-ON RESET READ pulse
Notes: I/Os inputs RESET
2008 SCILLC. rights reserved Characteristics subject change without notice
Doc. MD-9003, Rev.
CAT9555
CONFIGURATION
SOIC (W), TSSOP
I/O0.0
TQFN (HV6) (Top View)
I/O0.0 I/O0.1
I/O1.7 I/O1.6 I/O1.5 I/O1.4 I/O1.3
I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 I/O0.6 I/O0.7
I/O1.7 I/O1.6 I/O1.5 I/O1.4 I/O1.3 I/O1.2 I/O1.1 I/O1.0
I/O0.2 I/O0.3 I/O0.4 I/O0.5
I/O0.6
I/O0.7
I/O1.0
I/O1.1
DESCRIPTION
SOIC TSSOP 4-11 13-20 TQFN 10-17 Name I/O0.0 I/O0.7 I/O1.0 I/O1.7 Function Interrupt Output (open drain) Address Input Address Input Port Port Ground Port Port Address Input Serial Clock Serial Data Power Supply
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I/O1.2
CAT9555
ABSOLUTE MAXIMUM RATINGS
Parameters with Respect Ground Voltage with Respect Ground Current I/O1.0 I/O1.7, I/O0.0 I/O0.7 Input Current Supply Current Supply Current Package Power Dissipation Capability 25°C) Junction Temperature Storage Temperature Ratings -0.5 +6.5 -0.5 +5.5 +150 +150 Units
RELIABILITY CHARACTERISTICS
Symbol VZAP(2) ILTH Parameter Susceptibility Latch-up Reference Test Method JEDEC Standard JESD JEDEC JESD78A 2000 Units Volts
Notes: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability. This parameter tested initially after design process change that affects parameter.
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CAT9555
D.C. OPERATING CHARACTERISTICS
2.3V 5.5V; -40°C +85°C, unless otherwise specified. Symbol Supplies Istbl Istbh VPOR
Parameter Supply voltage Supply current Standby current Standby current Power-on reset voltage level input voltage High level input voltage level output current Leakage current Input capacitance Output capacitance level input voltage High level input voltage Input leakage current level input voltage High level input voltage
Conditions
0.75
1.65 -100
Unit
Operating mode; 5.5V; load; fSCL 100kHz Standby mode; 5.5V; load; VSS; fSCL 0kHz; inputs Standby mode; 5.5V; load; VCC; fSCL 0kHz; inputs
-0.5
load;
SCL, SDA,
0.4V
-0.5 -0.5
VIL(1) I/Os
level output current
0.5V; 2.3V 5.5V(3) 0.7V; 2.3V 5.5V(3) 2.3V(4) 2.3V
High level output voltage
3.0V
3.0V 4.75V
-10mA; 4.75V
Input leakage current Input leakage current Input capacitance Output capacitance
3.6V; 5.5V;
Notes: reference values only tested. This parameter characterized initially after design process change that affects parameter. 100% tested. Each I/Os must externally limited maximum 25mA each octal (I/O0.0 I/O0.7 I/O1.0 I/O1.7) must limited maximum current 100mA device total 200mA. total current sourced I/Os must limited 160mA.
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CAT9555
A.C. CHARACTERISTICS
2.3V 5.5V; -40°C +85°C, unless otherwise specified. Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT
Parameter Clock Frequency START Condition Hold Time Period Clock High Period Clock START Condition Setup Time Data Hold Time Data Setup Time Rise Time Fall Time STOP Condition Setup Time Free Time Between STOP START Data Valid Data Hold Time Noise Pulse Filtered Inputs Parameter Output Data Valid Input Data Setup Time Input Data Hold Time Interrupt Valid Interrupt Reset
Standard 1000
Fast
Units Units
tSU:STO tBUF
Symbol Port Timing
Interrupt Timing
Notes: Test conditions according Test Conditions" table. This parameter characterized initially after design process change that affects parameter. 100% tested.
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CAT9555
A.C. TEST CONDITIONS
Input Rise Fall time CMOS Input Voltages CMOS Input Reference Voltages Output Reference Voltages Output Load: SDA, Output Load: I/Os 10ns 0.2VCC 0.8VCC 0.3VCC 0.7VCC 0.5VCC Current Source 3mA; 100pF Current Source: IOL/IOH 10mA; 50pF
tLOW tSU:STA tHD:STA
tHIGH tLOW
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Figure Serial Interface Timing
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CAT9555
DESCRIPTION
SCL: Serial Clock serial clock input clocks data transferred into device. line requires pull-up resistor driven open drain output. SDA: Serial Data/Address bidirectional serial data/address used transfer data into device. open drain output wire-ORed with other open drain open collector outputs. pullup resistor must connected from line VCC. value pull-up resistor, calculated based minimum maximum values from Figure Figure (see Note). Device Address Inputs These inputs used extended addressing capability. pins should hardwired VSS. When hardwired, eight CAT9555s addressed single system. levels these inputs compared with corresponding bits, from slave address byte. I/O0.0 I/O0.7, I/O1.0 I/O1.7: Input Output Ports these pins configured input output. simplified schematic I/O0 I/O7 shown Figure When configured input, output transistors creating high impedance input with weak pull-up resistor (typical 100k). configured output, push-pull output stage enabled. Care should taken external voltage applied configured output impedance paths that exist between either VSS.
VOLmax
8.00
Fast Mode 300ns
7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00
RPmax
RPmin
CBUS (pF)
Figure Minimum Function Supply Voltage
Figure Maximum Value versus Capacitance
Note: According Fast Mode specification, capacitance 200pF, pull device resistor. loads between 200pF 400pF, pull-up device current source (Imax 3mA) switched resistor circuit.
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CAT9555 Interrupt Output open-drain interrupt output activated when port pins configured input changes state (differs from corresponding input port register state). interrupt deactivated when input returns previous state input port register read.
Since there 8-bit ports that read independently, interrupt caused Port will cleared read Port vice versa. Changing from output input cause false interrupt state does match contents input port register.
Data from Shift Register Data from Shift Register
Configuration Register
Output Port Register Data 100k
Write Configuration Pulse
Write Pulse
Output Port Register
Input Port Register
Input Port Register Data
LATCH Read Pulse
Data from Shift Register Write Polarity Register
Polarity Register Data
Polarity Inversion Register
Figure Simplified Schematic I/Os
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CAT9555
FUNCTIONAL DESCRIPTION
CAT9555 general purpose input/output (GPIO) peripheral provides sixteen ports, controlled through compatible serial interface CAT9555 supports data transmission protocol. This Inter-Integrated Circuit protocol defines device that sends data transmitter device receiving data receiver. transfer controlled Master device which generates serial clock START STOP conditions access. CAT9555 operates Slave device. Both Master device Slave device operate either transmitter receiver, Master device controls which mode activated. PROTOCOL features protocol defined follows: Data transfer initiated only when busy. During data transfer, data line must remain stable whenever clock line high. changes data line while clock line high will interpreted START STOP condition (Figure START STOP CONDITIONS START Condition precedes commands device, defined HIGH transition when HIGH. CAT9555 monitors lines will respond until this condition met. HIGH transition when HIGH determines STOP condition. operations must with STOP condition. DEVICE ADDRESSING After Master sends START condition, slave address byte required enable CAT9555 read write operation. four most significant bits slave address fixed binary 0100 (Figure CAT9555 uses next three bits address bits. address bits used select which device accessed from maximum eight devices same bus. These bits must compare their hardwired input pins. following slave address that specifies whether read write operation performed. When this "1", read operation initiated, when "0", write operation selected. Following START condition slave address byte, CAT9555 monitors responds with acknowledge line) when address matches transmitted slave address. CAT9555 then performs read write operation depending state bit.
START CONDITION STOP CONDITION
Figure START/STOP Condition
SLAVE ADDRESS
FIXED
PROGRAMMABLE HARDWARE SELECTABLE
Figure CAT9555 Slave Address
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CAT9555 ACKNOWLEDGE After successful data transfer, each receiving device required generate acknowledge. acknowledging device pulls down line during ninth clock cycle, signaling that received bits data. line remains stable during HIGH period acknowledge related clock pulse (Figure CAT9555 responds with acknowledge after receiving START condition slave address. device been selected along with write operation, responds with acknowledge after receiving each data byte. When CAT9555 begins READ mode transmits bits data, releases line, monitors line acknowledge. Once receives this acknowledge, CAT9555 will continue transmit data. acknowledge sent Master, device terminates data transmission waits STOP condition. master must then issue stop condition return CAT9555 standby power mode place device known state. REGISTERS TRANSACTIONS CAT9555 internal registers their address function shown Table Table Register Command Byte Command (hex) Register Input Port Input Port Output Port Output Port Polarity Inversion Port Polarity Inversion Port Configuration Port Configuration Port Table Registers Configuration Registers default default C0.7 C1.7 C0.6 C1.6 C0.5 C1.5 C0.4 C1.4 C0.3 C1.3 C0.2 C1.2 C0.1 C1.1 C0.0 C1.0 Table Registers Polarity Inversion Registers default default N0.7 N1.7 N0.6 N1.6 N0.5 N1.5 N0.4 N1.4 N0.3 N1.3 N0.2 N1.2 N0.1 N1.1 N0.0 N1.0 command byte first byte follow device address byte during write/read transaction. register command byte acts pointer determine which register will written read. input port register read only port. reflects incoming logic levels pins, regardless whether defined input output configuration register. Writes input port register ignored. Table Registers Input Port Registers default default I0.7 I1.7 I0.6 I1.6 I0.5 I1.5 I0.4 I1.4 I0.3 I1.3 I0.2 I1.2 I0.1 I1.1 I0.0 I1.0
Table Registers Output Port Registers default default O0.7 O1.7 O0.6 O1.6 O0.5 O1.5 O0.4 O1.4 O0.3 O1.3 O0.2 O1.2 O0.1 O1.1 O0.0 O1.0
RELEASE DELAY (TRANSMITTER) FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START
RELEASE DELAY (RECEIVER)
SETUP tSU:DAT) DELAY tAA)
Figure Acknowledge Timing
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CAT9555 output port register sets outgoing logic levels ports, defined outputs configuration register. values this register have effect pins defined inputs. Reads from output port register reflect value that flip-flop controlling output, actual value. polarity inversion register allows user invert polarity input port register data. this register ("1") corresponding input port data inverted. polarity inversion register cleared ("0"), original input port polarity retained. configuration register sets directions ports. configuration register enable corresponding port input with high impedance output driver. this register cleared, corresponding port enabled output. power-up, I/Os configured inputs with weak pull-up resistor VCC. Writing Port Registers Data transmitted CAT9555 registers using write mode shown Figure Figure CAT9555 registers configured operate four register pairs: Input Ports, Output Ports, Polarity Inversion Ports Configuration Ports. After sending data register, next data byte will sent other register pair. example, first byte data sent Configuration Port (register next byte will stored Configuration Port (register Each 8-bit register updated independently other registers. Reading Port Registers CAT9555 registers read according timing diagrams shown Figure Figure Data from register, defined command byte, will sent serially line. Data clocked into register failing edge acknowledge clock pulse. After first byte read, additional data bytes read, second read will reflect data from other register pair. example, first read data from Input Port next read data will from Input Port transfer stopped when master will acknowledge data byte received issue STOP condition.
command byte data port DATA acknowledge from slave data port DATA stop condition
slave address
start condition
acknowledge from slave
acknowledge from slave
WRITE PORT DATA FROM PORT DATA FROM PORT DATA VALID
Figure Write Output Port Register
slave address
command byte
data configuration acknowledge from slave DATA
data configuration DATA
start condition
acknowledge from slave
acknowledge from slave
Figure Write Configuration Register
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CAT9555 POWER-ON RESET OPERATION When power supply applied pin, internal power-on reset pulse holds CAT9555 reset state until reaches VPOR level. this point, reset condition released internal state machine CAT9555 registers initialized their default state.
slave address
acknowledge from slave
acknowledge from slave
slave address
acknowledge from slave
data from lower upper byte register
acknowledge from master
COMMAND BYTE
DATA
this moment master-transmitter becomes master-receiver slave-receiver becomes slave-transmitter
first byte
data from upper lower byte register
DATA
acknowledge from master
Note: Transfer stopped time STOP condition. last byte
Figure Read from Register
I0.x I1.x DATA I0.x DATA I1.x DATA
DATA
ACKNOWLEDGE FROMSLAVE READFROMPORT DATA INTO READFROMPORT DATA INTO DATA DATA DATA
ACKNOWLEDGE FROMMASTER
ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MASTER
DATA
DATA
DATA
DATA
Note:
Transfer data stopped moment STOP condition. When this occurs, data present latest acknowledge phase valid (output mode). assumed that command byte previously been (read input port register).
Figure Read Input Port Register
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CAT9555
PACKAGE OUTLINE DRAWINGS
SOIC 24-Lead 300mils
SYMBOL
2.35 0.10 2.05 0.31 0.20 15.20 10.11 7.34 1.27 0.25 0.40
2.65 0.30 2.55 0.51 0.33 15.40 10.51 7.60 0.75 1.27
PIN#1 IDENTIFICATION
VIEW
SIDE VIEW
VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Angles degrees. Complies with JEDEC standard MS-013
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CAT9555
TSSOP 24-Lead 4.4mm
SYMBOL
1.20 0.05 0.80 0.19 0.09 7.70 6.25 4.30 7.80 6.40 4.40 0.65 1.00 0.50 0.60 0.70 0.15 1.05 0.30 0.20 7.90 6.55 4.50
VIEW
SIDE VIEW VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Angles degrees. Complies with JEDEC standard MO-153.
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CAT9555
TQFN 24-Pad (HV6)
DETAIL
PIN#1 PIN#1 INDEX AREA VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
0.70 0.00 0.20 3.90 2.70 3.90 2.70 0.30
0.75 0.02 0.25 4.00 2.80 4.00 2.80 0.50 0.40
0.80 0.05 0.30 4.10 2.90 4.10 2.90 0.50
FRONT VIEW DETAIL
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC standard MO-220.
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CAT9555
EXAMPLE ORDERING INFORMATION
Prefix
Optional Company
Device 95554
Product Number
Suffix
Package SOIC TSSOP HV6: TQFN
Lead Finish Blank: Matte-Tin NiPdAu
Tape Reel Tape Reel 1,000/Reel SOIC only 2,000/Reel
9555
Temperature Range Industrial
ORDERING PART NUMBER
Part Number CAT9555WI CAT9555WI-T1 CAT9555YI CAT9555YI-T2 CAT9555HV6I-G CAT9555HV6I-GT2 Package SOIC SOIC TSSOP TSSOP TQFN TQFN Lead Finish Matte-Tin Matte-Tin Matte-Tin Matte-Tin NiPdAu NiPdAu
Product Mark Codes, click here:
Notes: packages RoHS-compliant (Lead-free, Halogen-free). standard lead finish Matte-Tin SOIC TSSOP packages NiPdAu TQFN package. device used above example CAT9555HV6I-GT2 (TQFN, Industrial Temperature, NiPdAu, Tape Reel, 2,000/Reel). additional package temperature options, please contact your nearest Semiconductor Sales office.
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CAT9555
REVISION HISTORY
Date 09-Dec-04 07-Jan-05 11-Mar-05 25-Sep-06 12-Mar-07 07-Jun-07 21-Jan-08 Revision Description Advance Information Initial Issue Advance Information Minor changes Advance Information Edit Features Edit Ordering Information Initial Release Update Ordering Information: Tape Reel SOIC package Update Figure NiPdAu lead finish TQFN package Update Example Ordering Information Update Package Outline Drawings Change document number from 8551 Delete TQFN package Matte-Tin Update Package Outline Drawings TQFN 24-Pad Update A.C. Characteristics table include Standard Fast I2C. Change logo fine print Semiconductor
05-May-08 01-Dec-08
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
PUBLICATION ORDERING INFORMATION
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16-bit SMBus Port with Interrupt 400kHz compatible 2.3V 5.5V oper

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