8-bit SMBus Port with Interrupt 400kHz compatible 2.3V 5.5V opera
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CAT9534
8-bit SMBus Port with Interrupt
400kHz compatible 2.3V 5.5V operation stand-by current tolerant I/Os pins that default inputs power-up High drive capability Individual configuration Polarity inversion register Active interrupt output Internal power-on reset glitch power-up Noise filter SDA/SCL inputs Cascadable devices Industrial temperature range RoHS-compliant 16-lead SOIC TSSOP, 16-pad TQFN 4mm) packages
DESCRIPTION
CAT9534 8-bit parallel input/output port expander SMBus compatible applications. These expanders provide simple solution applications where additional I/Os needed: sensors, power switches, LEDs, pushbuttons, fans. CAT9534 consists input port register, output port register, configuration register, polarity inversion register serial interface. eight I/Os configured input output writing configuration register. system master invert CAT9534 input data writing active-high polarity inversion register. CAT9534 features active interrupt output which indicates system master that input state changed. device's extended addressing capability allows devices share same bus. CAT9534 offered SOIC, TSSOP TQFN packages operates over full industrial temperature range. Ordering Information details, page
APPLICATIONS
White goods (dishwashers, washing machines) Handheld devices (cell phones, PDAs, digital cameras) Data Communications (routers, hubs servers)
BLOCK DIAGRAM
I/O0 I/O1 8-BIT INPUT FILTER I2C/SMBUS CONTROL WRITE pulse READ pulse INPUT/ OUTPUT PORTS I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 FILTER
POWER-ON RESET
Notes: I/Os inputs RESET.
2009 SCILLC. rights reserved Characteristics subject change without notice
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CAT9534
CONFIGURATION
SOIC (W), TSSOP
I/O0 I/O1 I/O2 I/O3
I/O7
TQFN (HV4) (Top View)
I/O0 I/O1 I/O2 I/O7 I/O6
I/O6
I/O5
I/O4
I/O3 I/O4 I/O5
DESCRIPTION
SOIC TSSOP 9-12 TQFN 7-10 Name I/O0-3 I/O4-7 Function Address Input Address Input Address Input Input/Output Port Input/Output Port Ground Input/Output Port Input/Output Port Interrupt Output (open drain) Serial Clock Serial Data Power Supply
ABSOLUTE MAXIMUM RATINGS
Parameters with Respect Ground Voltage with Respect Ground Current I/O0 I/O7 Input Current Supply Current Supply Current Package Power Dissipation Capability 25°C) Junction Temperature Storage Temperature Ratings -0.5 +6.5 -0.5 +5.5 +150 +150 Units
RELIABILITY CHARACTERISTICS
Symbol VZAP(2) ILTH (2)(3) Parameter Susceptibility Latch-up Reference Test Method JEDEC Standard JESD JEDEC Standard 2000 Units Volts
Notes: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability. This parameter tested initially after design process change that affects parameter. Latch-up protection provided stresses 100mA address data pins from +1V.
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CAT9534
D.C. OPERATING CHARACTERISTICS
5.5V; -40°C +85°C, unless otherwise specified. Symbol Supplies Istbl Istbh VPOR
Parameter Supply voltage Supply current Standby current Standby current Power-on reset voltage level input voltage
Conditions
0.25 0.25
1.65
Unit
Operating mode; 5.5V; load; fSCL 100kHz Standby mode; 5.5V; load; VSS; fSCL 0kHz; inputs Standby mode; 5.5V; load; VCC; fSCL 0kHz; inputs load;
-0.5
SCL, SDA, High level input voltage level output current Leakage current Input capacitance Output capacitance level input voltage High level input voltage Input leakage current I/Os level input voltage High level input voltage
0.4V
-0.5 -0.5
level output current
High level output voltage
Input leakage current Input capacitance Output capacitance
0.5V; 2.3V 4.75 4.75 3.6V;
Notes: reference values only tested. This parameter characterized initially after design process change that affects parameter. 100% tested. total current sunk I/Os must limited 100mA each limited 25mA maximum. total current sourced I/Os must limited 85mA.
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CAT9534
A.C. CHARACTERISTICS
5.5V; -40°C +85°C, unless otherwise specified. Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT
Parameter Clock Frequency START Condition Hold Time Period Clock High Period Clock START Condition Setup Time Data Hold Time Data Setup Time Rise Time Fall Time STOP Condition Setup Time Free Time Between STOP START Data Valid Data Hold Time Noise Pulse Filtered Inputs Parameter Output Data Valid Input Data Setup Time Input Data Hold Time Interrupt Valid Interrupt Reset
Standard 1000
Fast
Units Units
tSU:STO tBUF
Symbol Port Timing
Interrupt Timing
Notes: Test conditions according Test Conditions" table. This parameter characterized initially after design process change that affects parameter. 100% tested.
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CAT9534
A.C. TEST CONDITIONS
Input Rise Fall time CMOS Input Voltages CMOS Input Reference Voltages Input Voltages Input Reference Voltages Output Reference Voltages Output Load: SDA, Output Load: I/Os 10ns 0.2VCC 0.8VCC 0.3VCC 0.7VCC 0.4V 2.4V 0.8V, 2.0V 0.5VCC Current Source 3mA; 100pF Current Source: IOL/IOH 10mA; 50pF
tLOW tSU:STA tHD:STA
tHIGH tLOW
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Figure Serial Interface Timing
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CAT9534
DESCRIPTION
SCL: Serial Clock serial clock input clocks data transferred into device. line requires pull-up resistor driven open drain output. SDA: Serial Data/Address bidirectional serial data/address used transfer data into device. open drain output wire-ORed with other open drain open collector outputs. pullup resistor must connected from line VCC. value pull-up resistor, calculated based minimum maximum values from Figure Figure (see Note). Device Address Inputs These inputs used extended addressing capability. pins should hardwired VSS. When hardwired, eight CAT9534s addressed single system. levels these inputs compared with corresponding bits, from slave address byte. I/O0 I/O7: Input Output Ports these pins configured input output. simplified schematic I/O0 I/O7 shown Figure When configured input, output transistors creating high impedance input. configured output, push-pull output stage enabled. Care should taken external voltage applied configured output impedance paths that exist between either VSS.
VOLmax
8.00
Fast Mode 300ns
7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00
RPmax
RPmin
CBUS (pF)
Figure Minimum Value versus Supply Voltage
Figure Maximum Value versus Capacitance
Note: According Fast Mode specification, capacitance 200pF, pull device resistor. loads between 200pF 400pF, pull-up device current source (Imax 3mA) switched resistor circuit.
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CAT9534 Interrupt Output open-drain interrupt output activated when port pins configured input changes state (differs from corresponding input port register state). interrupt deactivated when input
Data from Shift Register Data from Shift Register
returns previous state input port register read. Changing from output input cause false interrupt state does match contents input port register.
Configuration Register
Output Port Register Data
Write Configuration Pulse
Write Pulse
Output Port Register
Input Port Register
Input Port Register Data
LATCH Read Pulse
Data from Shift Register Write Polarity Register
Polarity Register Data
Polarity Inversion Register
Figure Simplified Schematic I/O0 I/O7
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CAT9534
FUNCTIONAL DESCRIPTION
CAT9534's general purpose input/ output (GPIO) peripherals provide eight ports, controlled through compatible serial interface CAT9534 supports data transmission protocol. This protocol defines device that sends data transmitter device receiving data receiver. transfer controlled Master device which generates serial clock START STOP conditions access. CAT9534 operates Slave device. Both Master device Slave device operate either transmitter receiver, Master device controls which mode activated. PROTOCOL features protocol defined follows: Data transfer initiated only when busy. During data transfer, data line must remain stable whenever clock line high. changes data line while clock line high will interpreted START STOP condition (Figure START STOP CONDITIONS START Condition precedes commands device, defined HIGH transition when HIGH. CAT9534 monitors lines will respond until this condition met. HIGH transition when HIGH determines STOP condition. operations must with STOP condition. DEVICE ADDRESSING After Master sends START condition, slave address byte required enable CAT9534 read write operation. four most significant bits slave address fixed binary 0100 next three bits individual address bits (Figure address bits used select which device accessed from maximum eight devices same bus. These bits must compare their hardwired input pins. following slave address that specifies whether read write operation performed. When this "1", read operation initiated, when "0", write operation selected. Following START condition slave address byte, CAT9534 monitors responds with acknowledge line) when address matches transmitted slave address. CAT9534 then performs read write operation depending state bit.
START CONDITION STOP CONDITION
Figure START/STOP Condition
SLAVE ADDRESS
FIXED
PROGRAMMABLE HARDWARE SELECTABLE
Figure CAT9534 Slave Address
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CAT9534 ACKNOWLEDGE After successful data transfer, each receiving device required generate acknowledge. acknowledging device pulls down line during ninth clock cycle, signaling that received bits data. line remains stable during HIGH period acknowledge related clock pulse (Figure CAT9534 responds with acknowledge after receiving START condition slave address. device been selected along with write operation, responds with acknowledge after receiving each 8-bit byte. When CAT9534 begins READ mode transmits bits data, releases line, monitors line acknowledge. Once receives this acknowledge, CAT9534 will continue transmit data. acknowledge sent Master, device terminates data transmission waits STOP condition. master must then issue STOP condition return CAT9534 standby power mode place device known state. REGISTERS TRANSACTIONS CAT9534 consists input port register, output port register, polarity inversion register configuration register. Table shows register address table. Tables list Register through Register information. Table Register Command Byte
Command (hex) 0x00 0x01 0x02 0x03 Protocol Read byte Read/write byte Read/write byte Read/write byte Function Input port register Output port register Polarity inversion register Configuration register
command byte first byte follow device address byte during write/read transaction. register command byte acts pointer determine which register will written read. input port register read only port. reflects incoming logic levels pins, regardless whether defined input output configuration register. Writes input port register ignored. Table Register Input Port Register default
Table Register Output Port Register default
Table Register Polarity Inversion Register default
Table Register Configuration Register default
RELEASE DELAY (TRANSMITTER) FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START
RELEASE DELAY (RECEIVER)
SETUP DELAY
Figure Acknowledge Timing
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CAT9534
output port register sets outgoing logic levels ports, defined outputs configuration register. values this register have effect pins defined inputs. Reads from output port register reflect value that flip-flop controlling output, actual value. polarity inversion register allows user invert polarity input port register data. this register ("1") corresponding input port data inverted. polarity inversion register cleared ("0"), original input port polarity retained. configuration register sets directions ports. configuration register enable
corresponding port input with high impedance output driver. this register cleared, corresponding port enabled output. power-up, I/Os configured inputs with weak pull-up resistor VCC. Data transmitted CAT9534's registers using write mode shown Figure Figure CAT9534's registers read according timing diagrams shown Figure Figure Once command byte been sent, register which addressed will continue accessed reads until command byte will sent.
slave address
command byte
data port DATA acknowledge from slave stop condition
start condition WRITE PORT DATA FROM
acknowledge from slave
acknowledge from slave
DATA VALID
Figure Write Output Port Register
slave address
command byte
data register DATA acknowledge from slave stop condition
start condition WRITE REGISTER
acknowledge from slave
acknowledge from slave
Figure Write Configuration Polarity Inversion Register
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CAT9534
INTERRUPT OUTPUT CAT9534's interrupt otuput active opendrain output that activated when port configured input changes state. interrupt output reset when input returns previous state Input Port Register read. Note that changing from output input cause false interrupt occur state does match contents Input Port register.
POWER-ON RESET OPERATION When power supply applied pin, internal power-on reset pulse holds CAT9534 reset state until reaches VPOR level. this point, reset condition released internal state machine CAT9534's registers initialized their default state.
slave address
COMMAND BYTE acknowledge from slave
slave address
acknowledge from master data from register DATA first byte
acknowledge from slave
acknowledge from slave
this moment master-transmitter becomes master-receiver slave-receiver becomes slave-transmitter acknowledge from master data from register DATA last byte
Figure Read from Register
slave address
data from port DATA acknowledge from master
data from port DATA acknowledge from master stop condition
start condition READ FROM PORT DATA INTO PORT
acknowledge from slave
DATA
DATA
DATA
DATA
Figure Read Input Port Register
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CAT9534
PACKAGE OUTLINE DRAWINGS
SOIC 16-Lead 150mils
SYMBOL
1.35 0.10 0.33 0.19 9.80 5.80 3.80 0.25 0.40 9.90 6.00 3.90 1.27
1.75 0.25 0.51 0.25 10.00 6.20 4.00 0.50 1.27
PIN#1 IDENTIFICATION
VIEW
SIDE VIEW
VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Angles degrees. Complies with JEDEC standard MS-012
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CAT9534
TSSOP 16-Lead 4.4mm
SYMBOL
1.10 0.05 0.85 0.19 0.13 4.90 6.30 4.30 0.65 1.00 0.45 0.75 0.15 0.95 0.30 0.20 5.10 6.50 4.50
PIN#1 IDENTIFICATION VIEW
SIDE VIEW VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Angles degrees. Complies with JEDEC standard MO-153.
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CAT9534
TQFN 16-Pad (HV4)
DETAIL
PIN#1
PIN#1 INDEX AREA
SIDE VIEW
VIEW
BOTTOM VIEW
SYMBOL
0.70 0.00 0.25 3.90 2.00 3.90 2.00 0.45
0.75 0.02 0.20 0.30 4.00 4.00 0.65
0.80 0.05 0.35 4.10 2.25 4.10 2.25
DETAIL
0.65
FRONT VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Refer JEDEC standard MO-220.
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CAT9534
EXAMPLE ORDERING INFORMATION
Prefix
Optional Company
Device
9534
Product Number
Suffix
Package SOIC TSSOP HV4: TQFN
Lead Finish Blank: Matte-Tin NiPdAu
Tape Reel Tape Reel 2,000/Reel
9534
Temperature Range Industrial
ORDERING PART NUMBER
Part Number CAT9534WI-G CAT9534WI-GT2 CAT9534YI-G CAT9534YI-GT2 CAT9534HV4I-G CAT9534HV4I-GT2 Package SOIC SOIC TSSOP TSSOP TQFN TQFN Lead Finish NiPdAu NiPdAu NiPdAu NiPdAu NiPdAu NiPdAu
Product Mark Codes, click here:
Notes: packages RoHS-compliant (Lead-free, Halogen-free). standard lead finish NiPdAu. device used above example CAT9534WI-GT2 (SOIC, Industrial Temperature, NiPdAu, Tape Reel, 2,000/Reel). additional package temperature options, please contact your nearest Semiconductor Sales office.
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CAT9534
REVISION HISTORY
Date 23-May-08 03-Dec-08 06-May-09 Revisio Description Initial Issue Update A.C. Characteristics table include Standard Fast I2C. Change logo fine print Semiconductor Update D.C. Operating Characteristics table (Supplies)
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center Semiconductor P.O. 5163, Denver, Colorado 80217 Phone: 303-675-2175 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East Africa Technical Support: Phone: 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit additional information, please contact your local Sales Representative
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