drivers with dimming control brightness steps open drain outputs drive

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drivers with dimming control brightness steps open drain outputs drive

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CAT9532 16-bit Programmable Dimmer with Interface
drivers with dimming control brightness steps open drain outputs drive each selectable programmable blink rates: frequency: 0.593Hz 152Hz duty cycle: 99.6% I/Os used GPIOs 400kHz compatible* 2.3V 5.5V operation tolerant I/Os Active reset input RoHS-compliant 24-Lead SOIC, TSSOP 24-pad TQFN 4mm) packages
CAT9532 CMOS device that provides 16-bit parallel input/output port expander optimized dimming control. CAT9532 outputs drive directly LEDs parallel. Each individual turned OFF, blinking programmable rates. device provides simple solution dimming LEDs brightness steps backlight color mixing applications. CAT9532 suitable SMBus compatible applications where necessary limit traffic free-up master's timer. CAT9532 contains internal oscillator signals that drive outputs. user program period duty cycle each individual signal. After initial set-up command program Blink Rate Blink Rate (frequency duty cycle), only command from master required turn each individual open drain output OFF, cycle Blink Rate Blink Rate Each open drain output provide maximum output current 25mA. total current sunk I/Os must exceed 200mA.
APPLICATIONS
Backlighting color mixing Sensors control Power switches, push-buttons Alarm systems
TYPICAL APPLICATION CIRCUIT
Ordering Information details, page
RS11
RESET I2C/SMBus Master
LED0 LED1
RESET
CAT9532 LED11 LED15 LED12 GPIOs
Catalyst Semiconductor licensed Philips Corporation carry Protocol.
Notes:
LED0 LED11 used drivers LED12 LED15 used regular GPIOs
2008 SCILLC. rights reserved Characteristics subject change without notice
Doc. MD-9001 Rev.
CAT9532 CONFIGURATION
SOIC (W), TSSOP
TQFN (HV6)
LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7
RESET LED15 LED14 LED13 LED12 LED11 LED10 LED9 LED8
LED5 LED0 LED1 LED2 LED3 LED4
RESET LED15 LED14 LED13 LED12 LED11
LED8 LED10 LED9 LED6 LED7
SOIC TSSOP 4-11 13-20 TQFN 10-17 NAME LED0 LED7 LED8 LED15 RESET FUNCTION Address Input Address Input Address Input Driver Output Port Ground Driver Output Port Reset Input Serial Clock Serial Data Power Supply
BLOCK DIAGRAM
RESET
POWER RESET CONTROL
INPUT REGISTER SELECT (LSx) REGISTER
INPUT FILTERS
LEDx PRESCALER REGISTER OSCILLATOR PRESCALER REGISTER REGISTER BLINK REGISTER BLINK CONTROL LOGIC
Note: Only shown clarity
CAT9532
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2008 SCILLC. rights reserved Characteristics subject change without notice
CAT9532 ABSOLUTE MAXIMUM RATINGS
Parameters with Respect Ground Voltage with Respect Ground Current I/Os Supply Current Package Power Dissipation Capability Junction Temperature Storage Temperature Lead Soldering Temperature seconds) Operating Ambient Temperature Ratings -2.0 +7.0 -0.5 +5.5 +150 +150 Units
Notes: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability.
2008 SCILLC. rights reserved Characteristics subject change without notice
Doc. MD-9001 Rev.
CAT9532 D.C. OPERATING CHARACTERISTICS
5.5V, unless otherwise specified Symbol Supplies Istb Istb VPOR
Parameter Supply Voltage Supply Current Standby Current Additional Standby Current Power-on Reset Voltage
Conditions
Unit
Operating mode; 5.5V; load; fSCL 100kHz Standby mode; 5.5V; load; VCC, fSCL 0kHz Standby mode; 5.5V; every 4.3V, fSCL 0kHz 3.3V, load;
SCL, SDA, RESET
Level Input Voltage High Level Input Voltage Level Output Current Leakage Current Input Capacitance Output Capacitance Level Input Voltage High Level Input Voltage Input Leakage Current Level Input Voltage High Level Input Voltage 0.4V; 2.3V 0.4V; 3.0V 0.4V; 5.0V 0.7V; 2.3V 0.7V; 3.0V 0.7V; 5.0V 0.4V
-0.5 -0.5 -0.5
I/Os
Level Output Current
CI/O
Input Leakage Current Input/Output Capacitance
3.6V;
Notes: must lowered 0.2V order reset device. reference values only tested. This parameter characterized initially after design process change that affects parameter. 100% tested. output current must limited maximum 25mA each I/O; total current sunk must limited 200mA 100mA eight I/Os)
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2008 SCILLC. rights reserved Characteristics subject change without notice
CAT9532
A.C. CHARACTERISTICS
2.3V 5.5V, unless otherwise specified Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT
Parameter Clock Frequency START Condition Hold Time Period Clock High Period Clock START Condition Setup Time Data Hold Time Data Setup Time Rise Time Fall Time STOP Condition Setup Time Free Time Between STOP START Data Valid Data Hold Time Noise Pulse Filtered Inputs Parameter Output Data Valid Input Data Setup Time Input Data Hold Time Reset Pulse Width Reset Recovery Time Time Reset
Standard 1000
Fast
Units Units
tSU:STO tBUF
Symbol Reset tW(2) tREC tRESET
Port Timing
Notes: Test conditions according Test Conditions" table. This parameter characterized initially after design process change that affects parameter. 100% tested. full delay reset part will tRESET time constant line.
2008 SCILLC. rights reserved Characteristics subject change without notice
Doc. MD-9001 Rev.
CAT9532 TEST CONDITIONS
Input Pulse Voltage Input Rise Fall Times Input Reference Voltage Output Reference Voltage Output Load 0.2VCC 0.8VCC 0.3VCC, 0.7VCC 0.5VCC Current source: 3mA; 400pF fSCL(max) 400kHz
tLOW tSU:STA tHD:STA
tHIGH tLOW
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Figure 2-Wire Serial Interface Timing
SCL: Serial Clock serial clock input clocks data transferred into device. line requires pull-up resistor driven open drain output. SDA: Serial Data/Address bidirectional serial data/address used transfer data into device. open drain output wire-ORed with other open drain open collector outputs. pullup resistor must connected from line VCC. LED0 LED15: Driver Outputs General Purpose I/Os pins open drain outputs used drive directly LEDs. these pins programmed drive OFF, Blink Rate1 Blink Rate2. When used controlling LEDs, these pins used general purpose parallel input/output. RESET: External Reset Input Active Reset input used initialize CAT9532 internal registers state machine. internal registers held their default state while Reset input active. external pull-up resistor maximum required when this actively driven.
Doc. MD-9001 Rev.
2008 SCILLC. rights reserved Characteristics subject change without notice
CAT9532 FUNCTIONAL CAT9532 16-bit expander that provides programmable dimmer, controlled through compatible serial interface. CAT9532 supports data transmission protocol. This Inter-Integrated Circuit protocol defines device that sends data transmitter device receiving data receiver. transfer controlled Master device which generates serial clock START STOP conditions access. CAT9532 operates Slave device. Both Master device Slave device operate either transmitter receiver, Master device controls which mode activated. Protocol features protocol defined follows: Data transfer initiated only when busy. During data transfer, data line must remain stable whenever clock line high. changes data line while clock line high will interpreted START STOP condition (Figure START STOP Conditions START Condition precedes commands device, defined HIGH transition
when HIGH. CAT9532 monitors lines will respond until this condition met. HIGH transition when HIGH determines STOP condition. operations must with STOP condition. Device Addressing After Master sends START condition, slave address byte required enable CAT9532 read write operation. four most significant bits slave address fixed binary 1100 (Figure CAT9532 uses next three bits address bits. address bits used select which device accessed from maximum eight devices same bus. These bits must compare their hardwired input pins. following 7bit slave address that specifies whether read write operation performed. When this "1", read operation initiated, when "0", write operation selected. Following START condition slave address byte, CAT9532 monitors responds with acknowledge line) when address matches transmitted slave address. CAT9532 then performs read write operation depending state bit.
Figure Start/Stop Timing
START CONDITION STOP CONDITION
Figure CAT9532 Slave Address
SLAVE ADDRESS
FIXED
PROGRAMMABLE HARDWARE SELECTABLE
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Doc. MD-9001 Rev.
CAT9532
Acknowledge After successful data transfer, each receiving device required generate acknowledge. acknowledging device pulls down line during ninth clock cycle, signaling that received bits data. line remains stable during HIGH period acknowledge related clock pulse (Figure CAT9532 responds with acknowledge after receiving START condition slave address. device been selected along with write operation, responds with acknowledge after receiving each byte. When CAT9532 begins READ mode transmits bits data, releases line, monitors line acknowledge. Once receives this acknowledge, CAT9532 will continue transmit data. acknowledge sent Master, device terminates data transmission waits STOP condition. master must then issue stop condition return CAT9532 standby power mode place device known state. Registers Transactions After successful acknowledgement slave address, master will send command byte CAT9532 which will stored Control Register. format Control Register shown Figure Control Register acts pointer determine which register will written read. four least significant bits, used select which internal register accessed, according Table auto increment flag (AI) set, four least significant bits Control Register automatically incremented after read write operation. This allows user access CAT9532 internal registers sequentially. content these bits will rollover "0000" after last register accessed. Table Internal Registers Selection
Register Name INPUT0 INPUT1 PSC0 PWM0 PSC1 PWM1 Type READ READ READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE Register Function Input Register Input Register Frequency Prescaler Register Frequency Prescaler Register Selector Selector 8-11 Selector 12-15 Selector
Figure Acknowledge Timing
FROM MASTER
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure Control Register
REGISTER ADDRESS RESET STATE: AUTO-INCREMENT FLAG
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CAT9532
Input Register Input Register reflect incoming logic levels pins, regardless whether defined input output. These registers read only ports. Writes input registers will acknowledged will have effect. Table Input Register Input Register
INPUT0
Table Register Register
PWM0 default PWM1 default
default INPUT1
Every driver output programmed four states, OFF, blinks BLINK0 rate blinks BLINK1 rate using Selector Registers (Table Table Selector Registers
default
Frequency Prescaler Frequency Prescaler registers (PSC0, PSC1) used program period pulse width modulated signals BLINK0 BLINK1 respectively: T_BLINK0 (PSC0 152; T_BLINK1 (PSC1 Table Frequency Prescaler Frequency Prescaler Registers
PSC0 default PSC1 default
default
default default default
Register Register (PWM0, PWM1) used program duty cycle BLINK0 BLINK1 respectively: Duty Cycle_BLINK0 PWM0 256; Duty Cycle_BLINK1 PWM1 After writing PWM0/1 register 8-bit internal counter starts count from 255. outputs (LED when counter value less than value programmed into register. when counter value higher than value written into register.
output (LED0 LED15) bits value from corresponding Register Output Hi-Z (LED Default) Output (LED Output blinks BLINK0 Rate Output blinks BLINK1 Rate
2008 SCILLC. rights reserved Characteristics subject change without notice
Doc. MD-9001 Rev.
CAT9532
Write Operations Data transmitted CAT9532 registers using write sequence shown Figure from command byte "1", CAT9532 internal registers written sequentially. After sending data register, next data byte will sent next register sequentially addressed. Read Operations CAT9532 registers read according timing diagrams shown Figure Figure Data from register, defined command byte, will sent serially line. After first byte read, additional data bytes read when auto-increment flag, set. additional data byte will reflect data read from next register sequentially addressed bits command byte. When reading Input Port Registers (Figure data clocked into register failing edge acknowledge clock pulse. transfer stopped when master will acknowledge data byte received issue STOP condition. Figure Write Register Timing Diagram
Command Byte Data Register Acknowledge From Slave DATA Acknowledge From Slave Data Register
Pins Used General Purpose pins used drive LEDs used general purpose input/output, GPIO. When used input, user should program corresponding Hi-Z ("00" register bits). state read Input Register according sequence shown Figure output, external pull-up resistor should connected pin. value pull-up resistor calculated according operating characteristics. output high, user program output Hi-Z writing "00" into corresponding Selector (LSx) register bits. output when output programmed through register bits ("01" register bits).
Slave Address
Start Condition
Acknowledge From Slave
WRITE REGISTER DATA FROM PORT
Figure Read from Register Timing Diagram
Slave Address
Acknowledge From Slave
Acknowledge From Slave
Slave Address
Acknowledge From Slave
Data From Register
DATA
Acknowledge From Master
COMMAND BYTE
This Moment Master-Transmitter Becomes Master-receiver Slave-Receiver Becomes Slave-Transmitter
First Byte Auto-increment Register Address Acknowledge From Master
Data From Register
DATA
Note: Transfer stopped time STOP condition.
Last Byte
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CAT9532
External Reset Operation CAT9532 registers state machine initialized their default state when RESET input held minimum external Reset timing shown Figure Power-On Reset Operation CAT9532 incorporates Power-On Reset (POR) circuitry which protects internal logic against powering wrong state. device reset state less than internal threshold level (VPOR). When exceeds VPOR level, reset state released CAT9532 internal state machine registers initialized their default state.
Figure Read Input Port Register Timing Diagram
Slave Address Data From Port Data From Port
Acknowledge From Slave
DATA
Acknowledge From Master
DATA
Acknowledge From Master
Stop Condition
Start Condition
READ FROM PORT
DATA INTO PORT
DATA
DATA
DATA
DATA
Figure RESET Timing Diagram
START READ CYCLE
tRESET
RESET
tREC
tRESET LEDx
2008 SCILLC. rights reserved Characteristics subject change without notice
Doc. MD-9001 Rev.
CAT9532 APPLICATION INFORMATION
Programming Example following programming sequence example set: LED0 LED3: LED4 LED7: Dimming brightness; Blink 152Hz, duty cycle LED8 LED11: Blink with duty cycle (Blink LED12 LED15: Command Description START Send Slave address, A0-A2 Command Byte: AI="1"; PSC0 Addr Blink 152Hz, T_Blink1 1/152 Write PSC0 PWM0 duty cycle PWM0 0.3; Write PWM0=77 Blink 2Hz, T_Blink1 Write PSC1 PWM1 duty cycle PWM1 0.5; Write PWM1=128 Write LS0: LED0 LED3 Write LS1: LED4 LED7 Blink1 Write LS2: LED8 LED11 Blink2 Write LS3: LED12 LED15 STOP Data
RESET RESET
LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 LED13 LED14 LED15
Note: LED0 LED11 used drivers LED12 LED15 used regular GPIOs.
CAT9532
I2C/SMBus MASTER
GPIOs
Figure Typical Application
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CAT9532
PACKAGE OUTLINE DRAWINGS
SOIC 24-Lead (1)(2)
SYMBOL
2.35 0.10 2.05 0.31 0.20 15.20 10.11 7.34 1.27 0.25 0.40
2.65 0.30 2.55 0.51 0.33 15.40 10.51 7.60 0.75 1.27
PIN#1 IDENTIFICATION
VIEW
SIDE VIEW
VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Angles degrees. Complies with JEDEC MS-013.
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CAT9532
TSSOP 24-Lead 4.4mm (1)(2)
SYMBOL
1.20 0.05 0.80 0.19 0.09 7.70 6.25 4.30 7.80 6.40 4.40 0.65 1.00 0.50 0.60 0.70 0.15 1.05 0.30 0.20 7.90 6.55 4.50
VIEW
SIDE VIEW VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Angles degrees. Complies with JEDEC MO-153.
Doc. MD-9001 Rev.
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CAT9532
TQFN 24-Lead (HV6) (1)(2)
DETAIL
PIN#1 PIN#1 INDEX AREA VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
0.70 0.00 0.18 3.90 2.40 3.90 2.40 0.30
0.75 0.02 0.20 0.25 4.00 4.00 0.50 0.40
0.80 0.05
DETAIL
0.30 4.10 2.90 4.10 2.90 0.50
FRONT VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC standard MO-220.
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CAT9532 EXAMPLE ORDERING INFORMATION
Prefix
Company
Device Suffix 9532
Package SOIC, JEDEC TSSOP HV6: TQFN
Tape Reel Tape Reel 1000/Reel SOIC only 2000/Reel
Product Number
Lead Finish Blank: Matte-Tin NiPdAu
9532
Temperature Range Industrial
ORDERING PART NUMBER
Part Number CAT9532WI CAT9532WI-T1 CAT9532YI CAT9532YI-T2 CAT9532HV6I-G CAT9532HV6I-GT2 Package SOIC SOIC TSSOP TSSOP TQFN TQFN Lead Finish Matte-Tin Matte-Tin Matte-Tin Matte-Tin NiPdAu NiPdAu
Product Mark Codes, click here:
Notes: packages RoHS-compliant (Lead-free, Halogen-free). standard plated finish Matte-Tin SOIC TSSOP packages. standard plated finish NiPdAu TQFN package. device used above example CAT9532WI-T1 (SOIC, Industrial Temperature, Matte-Tin, Tape Reel). additional temperature options, please contact your nearest Semiconductor Sales office.
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CAT9532
REVISION HISTORY
Date 23-Oct-07 07-Dec-07 16-Apr-08 03-Dec-08 Revision Description Initial Issue Update Example Ordering Information Ordering Part Number Delete TQFN package Matte-Tin Update Package Outline Drawing TQFN 24-Pad Update A.C. Characteristics table include Standard Fast I2C. Change logo fine print Semiconductor
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center Semiconductor P.O. 5163, Denver, Colorado 80217 Phone: 303-675-2175 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East Africa Technical Support: Phone: 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit additional information, please contact your local Sales Representative
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drivers with dimming control brightness steps open drain outputs drive

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