ADP3611 dual MOSFET driver optimized driving N-channel switching MOSFE

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ADP3611 dual MOSFET driver optimized driving N-channel switching MOSFE

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ADP3611 Product Preview Dual Bootstrapped, High Voltage MOSFET Driver with Output Disable
ADP3611 dual MOSFET driver optimized driving N-channel switching MOSFETs nonisolated synchronous buck power converters used power CPUs portable computers. driver impedances have been chosen provide optimum performance multiphase regulators phase. high-side driver bootstrapped relative switch node buck converter designed accommodate high voltage slew rate associated with floating high-side gate drivers. internal synchronous MOSFET used replace external bootstrap Schottky diode. This allows larger high side gate voltage increased efficiency. ADP3611 includes anticross-conduction protection circuit, undervoltage lockout hold switches until driver sufficient voltage proper operation, crowbar input that turns low-side MOSFET independently input signal state, low-side MOSFET disable provide higher efficiency light loads. shuts both high-side low-side MOSFETs prevent rapid output capacitor discharge during system shutdown. ADP3611 specified over extended commercial temperature range -10°C 100°C available 10-lead MSOP package 8-lead package.
DFN8 SUFFIX CASE 506AA
MSOP10 SUFFIX CASE 846AC
MARKING DIAGRAMS
All-in-one Synchronous Buck Driver Signal Generates Both Drives Anticross-conduction Protection Circuitry Output Disable Function Crowbar Control Synchronous Override Control This Pb-Free Device
XXMG Specific Device Code Date Code Pb-Free Package (Note: Microdot either location)
Applications
Mobile Computing Core Power Converters Multiphase Desk-note Supplies Single-supply Synchronous Buck Converters Nonsynchronous-to-Synchronous Drive Conversion
ORDERING INFORMATION
detailed ordering shipping information package dimensions section page this data sheet.
This document contains information product under development. Semiconductor reserves right change discontinue this product without notice.
Semiconductor Components Industries, LLC, 2008
October, 2008 Rev.
Publication Order Number: ADP3611/D
ADP361SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
Figure MSOP-10 Package Block Diagram
GENERAL APPLICATION CIRCUIT
Figure MSOP-10 Package Application Circuit
Table ORDERING INFORMATION
Model ADP3611JRMZ-REEL* ADP3611MNR2G-REEL* Pb-Free Part information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specification Brochure, BRD8011/D. Temperature Range -10°C 100°C -10°C 100°C Package Description 10-Lead Mini Small Outline Package (MSOP) 8-Lead Package Package Option RM-10 Quantity Reel 3000 3000 Branding 3611
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ADP361Table ELECTRICAL CHARACTERISTICS (VCC -10°C 100°C, unless otherwise noted)
Parameter Symbol Conditions Unit LOGIC INPUTS (IN, DRVLSD, CROWBAR) Input Voltage High Input Voltage Input Current CROWBAR Resistance DRVLSD Propagation Delay Time HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times trDRVH tfDRVH Propagation Delay Times (Note tpdhDRVH tpdlDRVH LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times trDRVL tfDRVL Propagation Delay Times (Notes Transition Timeout (Note Zero-crossing Threshold BOOTSTRAP RECTIFIER Output Resistance SWITCH NODE RESISTOR Switch Node Resistor SUPPLY Supply Voltage Range Supply Current Normal Mode Supply Current Shutdown Mode Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis (Note ISYS(NM) ISYS(SD) IBST, IBST, Rising Falling 4.35 RBOOT tpdhDRVL tpdlDRVL tSWTO CLOAD Figure CLOAD Figure CLOAD Figure CLOAD Figure CLOAD Figure CLOAD Figure CLOAD Figure CLOAD Figure tpdlDRVLSD tpdhDRVLSD Inputs DRVLSD Resistance from CROWBAR CLOAD Figure
NOTE: limits temperature extremes guaranteed correlation using standard statistical quality control (SQC) methods. propagation delays, tpdh refers specified signal going high, tpdl refers signal going with transitions measured 50%. turn-on DRVL initiated after goes either crossing threshold expiration tSWTO. Guaranteed characterization, production tested.
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ADP361IN
DRVLSD
tpdlDRVLSD tpdhDRVLSD
DRVL
Figure Output Disable Timing Diagram (Timing Referenced Points Unless Otherwise Noted)
tpdlDRVL tfDRVL tpdlDRVH DRVL tfDRVH trDRVL
tpdhDRVH DRVH-SW
trDRVH
tSWTO
tpdhDRVL
Figure Nonoverlap Timing Diagram (Timing Referenced Points Unless Otherwise Noted)
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ADP361Table ABSOLUTE MAXIMUM RATINGS (Unless otherwise specified, voltages referenced GND.)
Parameter BST, DRVH DRVH DRVH DRVL Other Inputs Outputs MSOP-10 Package 2-Layer Board 4-Layer Board Rating -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +100 +150 +150 Soldering Vapor Phase Infrared Unit °C/W °C/W
QFN-8 Package Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Range
Stresses exceeding Maximum Ratings damage device. Maximum Ratings stress ratings only. Functional operation above Recommended Operating Conditions implied. Extended exposure stresses above Recommended Operating Conditions affect device reliability. NOTE: This device sensitive. standard precautions when handling.
Configuration
DRVLSD CROWBAR
DRVH DRVL
ADP361TOP VIEW (Not Scale)
Figure 10-Lead MSOP Package
DRVLSD
ADP361TOP VIEW (Not Scale)
DRVH DRVL
Figure 8-Lead Package
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ADP361Table FUNCTION DESCRIPTIONS
MSOP Symbol Description Logic Level Input. This primary control drive outputs. normal operation, pulling this turns low-side driver; pulling high turns high-side driver. Shutdown Input. When low, this disables normal operation, forcing DRVH DRVL low.
DRVLSD Synchronous Rectifier Shutdown Input. When low, DRVL forced low; when high, DRVL enabled controlled adaptive overlap protection control circuitry. CROWBAR Crowbar Input. When high, DRVL forced high regardless high-side MOSFET switch condition. Input Supply. This should bypassed with larger ceramic capacitor. Synchronous Rectifier Drive. Output drive lower (synchronous rectifier) MOSFET. Ground. This should closely connected source lower MOSFET. DRVL Switch Node Input. This connected buck-switching node, close upper MOSFET's source. floating return upper MOSFET drive signal. also used monitor switched voltage prevent turn-on lower MOSFET until voltage below Buck Drive. Output drive upper (buck) MOSFET. DRVH Upper MOSFET Floating Bootstrap Supply. capacitor connected between pins holds this bootstrapped voltage high-side MOSFET switched.
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ADP361THEORY OPERATION ADP3611 dual MOSFET driver optimized driving N-channel MOSFETs synchronous buck converter topology. single input signal that required properly drive high-side low-side MOSFETs. Each driver capable driving load speeds MHz. more detailed description ADP3611 features follows. Refer detailed block diagram Figure
High-Side Driver
high-side driver designed drive floating RDS(ON) N-channel MOSFET. bias voltage high-side driver developed external bootstrap supply circuit, which connected between pins. bootstrap circuit comprises diode, bootstrap capacitor, CBST. When ADP3611 starting ground, bootstrap capacitor charges through Once supply voltage ramps exceeds UVLO threshold, driver enabled. When goes high, high-side driver begins turn high-side MOSFET (Q1) transferring charge from CBST. turns rises VDCIN, forcing VDCIN VC(BST), which enough gate-to-source voltage hold complete cycle, switched pulling gate down voltage pin. When low-side MOSFET (Q2) turns pulled ground. This allows bootstrap capacitor charge again. When driver enabled, driver's output phase with pin. Table shows relationship between DRVH different control inputs ADP3611.
Overlap Protection Circuit
Figure Detailed Block Diagram ADP3611 Undervoltage Lockout
undervoltage lockout (UVLO) circuit holds both MOSFET driver outputs during supply ramp-up. UVLO logic becomes active control driver outputs supply voltage greater than UVLO circuit waits until supply reached voltage high enough bias logic level MOSFETs fully before releasing control drivers control pins.
Driver Control Input
driver control input (IN) connected duty ratio modulation signal switch-mode controller. driven logic. output MOSFETs driven that node follows polarity
Low-Side Driver
low-side driver designed drive groundreferenced RDS(ON) N-channel synchronous rectifier MOSFET. bias low-side driver internally connected supply GND. Once supply voltage ramps exceeds UVLO threshold, driver enabled. When driver enabled, driver's output 180° phase with pin. Table shows relationship between DRVL different control inputs ADP3611.
overlap protection circuit prevents both main power switches, from being same time. This done prevent shoot-through currents from flowing through both power switches associated losses that occur during their on-off transitions. overlap protection circuit accomplishes this adaptively controlling delay from Q1's turn-off Q2's turn-on, delay from Q2's turn-off Q1's turn-on. prevent overlap gate drives during Q1's turn-off Q2's turn-on, overlap circuit monitors voltage DRVH pin. When goes low, begins turn off. overlap protection circuit waits voltage DRVH pins both fall below Once both these conditions met, begins turn Using this method, overlap protection circuit ensures that before turns regardless variations temperature, supply voltage, gate charge, drive current. There however, timeout circuit that overrides waiting period DRVH pins reach After timeout period expired, DRVL asserted high regardless DRVH voltages. opposite case, when goes high, begins turn after propagation delay. overlap protection circuit waits voltage DRVL fall below after which DRVH asserted high turns
Low-Side Driver Shutdown
low-side driver shutdown DRVLSD allows control signal shut down synchronous rectifier. Under light load conditions, DRVLSD should pulled before
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ADP361polarity reversal inductor current maximize light load conversion efficiency. DRVLSD also pulled reverse voltage protection purposes. When DRVLSD low, low-side driver stays low. When DRVLSD high, low-side driver enabled controlled driver signals, previously described.
Low-Side Driver Timeout Crowbar Function
normal operation, DRVH signal tracks signal turns high-side switch with delay (tpdlDRVH) following falling edge input signal. When turned off, DRVL allowed high, turns node voltage collapses zero. fault condition such high-side switch drain-source short circuit, node cannot fall zero, even when DRVH goes low. ADP3611 timer circuit address this scenario. Every time goes low, DRVL on-time delay timer triggered. node voltage does trigger low-side turn-on, DRVL on-time delay circuit does instead, when times with tSW(TO) delay. still turned that drain shorted source, turns creates direct short circuit across VDCIN voltage rail. crowbar action causes fuse VDCIN current path open. opening fuse saves load (CPU) from potential damage that high-side switch short circuit could have caused.
addition internal low-side drive time-out circuit, ADP3611 includes CROWBAR input provide means additional overvoltage protection. When CROWBAR goes high, ADP3611 turns DRVH turns DRVL. crowbar logic overrides overlap protection circuit, shutdown logic, DRVLSD logic, UVLO protection DRVL. Thus, crowbar function maximizes overvoltage protection coverage application. CROWBAR either driven CLAMP buck controllers, such ADP3207A, ADP3210, controlled independent overvoltage monitoring circuit.
Table ADP3611 Truth Table
CROWBAR Don't Care UVLO DRVLSD DRVH DRVL
APPLICATION INFORMATION
Supply Capacitor Selection
supply input (VCC) ADP3611, local bypass capacitor recommended reduce noise supply some peak currents drawn. multilayer ceramic (MLC) capacitor. capacitors provide best combination small size, obtained from following vendors.
Table
Vendor Murata Taiyo-Yuden Tokin Part Number GRM235Y5V106Z16 EMK325F106ZF C23Y5V1C106ZP Address www.murata.com www.t-yuden.com www.tokin.com
Keep ceramic capacitor close possible ADP3611.
Bootstrap Circuit
bootstrap circuit uses charge storage capacitor (CBST) synchronous MOSFET rectifier (D1), shown Figure Selection these components done after high-side MOSFET been chosen. bootstrap capacitor must have voltage rating that able handle least more than maximum supply voltage. capacitance determined
CBST HSGATE DVBST
(eq.
where: QHSGATE total gate charge high-side MOSFET. DVBST voltage droop allowed high-side MOSFET drive. example, NTMFS4821N MOSFETs parallel have total gate charge about allowed droop required bootstrap capacitance good quality ceramic capacitor should used, derating significant capacitance drop MLCs high temperature must applied. this example, selection even would recommended. Normally Schottky diode recommended bootstrap diode forward drop, which maximizes drive available high-side MOSFET. Using synchronous MOSFET rectifier instead Schottky diode advantage even lower forward voltage drop. lower forward voltage drop gives larger drive voltage high-side MOSFET lower conduction loss high-side MOSFET. bootstrap diode must also able handle least more than maximum battery voltage. average forward current estimated
IF(AVG) HSGATE
(eq.
where fMAX maximum switching frequency controller.
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ADP361Power Thermal Considerations
major power consumption ADP3611-based driver circuit from dissipation MOSFET gate charge. estimated
PMAX (QHSGATE QLSGATE) fMAX
(eq.
Part this power consumption generates heat inside ADP3611. temperature rise ADP3611 against environment estimated
PMAX
(eq.
where: supply voltage fMAX highest switching frequency. QHSGATE QLSGATE total gate charge high-side low-side MOSFETs, respectively. example, ADP3611 drives NTMFS4821N high-side MOSFETs NTMFS4846N low-side MOSFETs. According MOSFET data sheets, QHSGATE QLSGATE Given that fMAX kHz, PMAX would about
QHSGATE QHSGATE QLSGATE QLSGATE QHSGATE LSGATE
where ADP3611's thermal resistance from junction air, given absolute maximum ratings 220°C/W layer board. total MOSFET drive power dissipates output resistance ADP3611 MOSFET gate resistance well. represents ratio power dissipation inside ADP3611 over total MOSFET gate driving power. normal applications, rough estimation 0.7. more accurate estimation calculated using
RHSGATE RHSGATE RLSGATE RLSGATE
(eq.
where: output resistances high-side driver: (DRVH BST), (DRVH SW). output resistances low-side driver: (DRVL VCC), (DRVL GND). external resistor between capacitor. RHSGATE RLSGATE gate resistances high-side low-side MOSFETs, respectively. Assuming that that RHSGATE RLSGATE 0.5, Equation gives value 0.71. Based Equation estimated temperature rise this example about 22°C.
Board Layout Considerations
best have low-side MOSFET gate close
following general guidelines when designing printed circuit boards. Figure gives example typical land patterns based guidelines given here. bypass capacitor should located close possible pins. Place ADP3611 bypass capacitor same layer board, that trace between ADP3611 capacitor does contain via. ideal location bypass capacitor near ADP3611. High frequency switching noise coupled into ADP3611 diode. Therefore, connect anode diode with short trace. separate trace connect anode diode directly power rail.
DRVL pin; otherwise, short very thick trace between DRVL low-side MOSFET gate. Fast switching high-side MOSFET reduce switching loss. However, problems arise severe ringing switch node voltage. Depending character low-side MOSFET, very fast turn-on high-side MOSFET falsely turn low-side MOSFET through dv/dt coupling Miller capacitance. Therefore, when fast turn-on high-side MOSFET required application, resistor about placed between capacitor limit turn-on speed high-side MOSFET.
RBST
CBST
Switch Node
Short, Thick Trace Gates Low-Side MOSFETs
CVCC
Figure External Component Placement Example
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ADP361PACKAGE DIMENSIONS
DFN8 CASE 506AA-01 ISSUE
REFERENCE NOTES: DIMENSIONING TOLERANCING ASME Y14.5M, 1994 CONTROLLING DIMENSION: MILLIMETERS. DIMENSION APPLIES PLATED TERMINAL MEASURED BETWEEN 0.25 0.30 FROM TERMINAL. COPLANARITY APPLIES EXPOSED WELL TERMINALS. MILLIMETERS 0.80 1.00 0.00 0.05 0.20 0.20 0.30 2.00 1.10 1.30 2.00 0.70 0.90 0.50 0.20 0.25 0.35
0.10
0.10
0.10
0.08
SEATING PLANE
VIEW
(A3)
SIDE VIEW
0.10 0.05 NOTE
BOTTOM VIEW
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ADP361PACKAGE DIMENSIONS
MSOP10 CASE 846AC-01 ISSUE
0.08 (0.003)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH, PROTRUSIONS GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. 846B-01 OBSOLETE. STANDARD 846B-02 MILLIMETERS 2.90 3.10 2.90 3.10 0.95 1.10 0.20 0.30 0.50 0.05 0.15 0.10 0.21 4.75 5.05 0.40 0.70 INCHES 0.114 0.122 0.114 0.122 0.037 0.043 0.008 0.012 0.020 0.002 0.006 0.004 0.008 0.187 0.199 0.016 0.028
0.038 (0.0015)
SEATING PLANE
SOLDERING FOOTPRINT*
1.04 0.04
0.32 0.0126
3.20 0.126
4.24 0.167
5.28 0.208
0.50 0.0196
SCALE
inches
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
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ADP3611/D

ADP3611 dual MOSFET driver optimized driving N-channel switching MOSFE

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