ADP3121 dual, high voltage MOSFET driver optimized driving N-channel M

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ADP3121 dual, high voltage MOSFET driver optimized driving N-channel M

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ADP3121 Dual Bootstrapped, MOSFET Driver with Output Disable
ADP3121 dual, high voltage MOSFET driver optimized driving N-channel MOSFETs, switches non-isolated synchronous buck power converter. Each driver capable driving 3000 load with propagation delay transition time. drivers bootstrapped designed handle high voltage slew rate associated with floating high-side gate drivers. ADP3121 includes overlapping drive protection prevent shoot-through current external MOSFETs. shuts both high-side low-side MOSFETs prevent rapid output capacitor discharge during system shutdown. ADP3121 specified over commercial temperature range 85°C available 8-lead SOIC_N 8-lead LFCSP packages.
SO-8 SUFFIX CASE P3121 ALYW
All-in-one Synchronous Buck Driver Bootstrapped High-side Drive Signal Generates Both Drives Anticross Conduction Protection Circuitry Over Voltage Protection Disabling Driver Outputs Meets Requirement when Used with Flex-ModeController These Pb-Free Devices
P3121 Specific Device Code Assembly Location Year Work Week Pb-Free Package LFCSP8 SUFFIX CASE 932AF
Typical Applications
#YWW Specific Device Code Year Work Week Pb-Free Package
Multiphase Desktop Supplies Single-supply Synchronous Buck Converters
ORDERING INFORMATION
Device ADP3121JRZ-RL Package SOIC_N (Pb-Free) Shipping 2500/Tape Reel
ADP3121JCPZ-RL LFCSP_VD 5000/Tape Reel (Pb-Free) information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specification Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2009
April, 2009 Rev.
Publication Order Number: ADP3121/D
ADP3121
CONNECTIONS DRVH PGND DRVL
ADP3121 LATCH DELAY
CBST1 DRVH
CBST2
RBST
INDUCTOR
CONTROL LOGIC DELAY
DRVL
PGND
Figure Block Diagram
FUNCTION DESCRIPTION
Name DRVL PGND Description Upper MOSFET Floating Bootstrap Supply. capacitor connected between pins holds this bootstrapped voltage high-side MOSFET while switching. Logic Level Input. This primary control drive outputs. normal operation, pulling this turns low-side driver; pulling high turns high-side driver. Output Disable. When low, this disables normal operation, forcing DRVH DRVL low. Input Supply. This should bypassed PGND with ceramic capacitor. Synchronous Rectifier Drive. Output drive lower (synchronous rectifier) MOSFET. Power Ground. This should closely connected source lower MOSFET. Switch Node Connection. This connected buck switching node, close upper MOSFET source. floating return upper MOSFET drive signal. also used monitor switched voltage prevent lower MOSFET from turning until voltage below Buck Drive. Output drive upper (buck) MOSFET.
DRVH
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ADP3121
MAXIMUM RATINGS
Rating qJA, SOIC_N 2-Layer Board 4-Layer Board qJA, LFCSP_VD (Note 4-Layer Board Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Soldering sec) Vapor Phase sec) Infrared sec) 64.3 +150 °C/W °C/W °C/W Value Unit
Stresses exceeding Maximum Ratings damage device. Maximum Ratings stress ratings only. Functional operation above Recommended Operating Conditions implied. Extended exposure stresses above Recommended Operating Conditions affect device reliability. Internally limited thermal shutdown, 150°C min. layer board, thickness. 60-180 seconds minimum above 237°C. This device sensitive. standard precautions when handling
ABSOLUTE MAXIMUM RATINGS
Symbol Name Main supply voltage input Ground Bootstrap Supply Voltage Input <200 Switching Node (Bootstrap Supply Return) <200 DRVH High-Side Driver Output <200 DRVL Low-Side Driver Output <200 DRVH DRVL Control Input Outside Disable -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Vmax Vmin -0.3
NOTE: voltages with respect PGND except where noted. Stresses exceeding Maximum Ratings damage device. Maximum Ratings stress ratings only. Functional operation above Recommended Operating Conditions implied. Extended exposure stresses above Recommended Operating Conditions affect device reliability.
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ADP3121
ELECTRICAL CHARACTERISTICS (VCC 85°C, unless otherwise noted) (Note
Characteristic SUPPLY Supply Voltage Range Supply Current INPUTS Input Voltage High Input Voltage Input Current Hysteresis INPUTS Input Voltage High Input Voltage Input Current Hysteresis HIGH-SIDE DRIVER Output Resistance, Sourcing Current 25°C 85°C Output Resistance, Sinking Current 25°C 85°C Output Resistance, Unbiased Transition Times CLOAD Figure CLOAD Figure Propagation Delay Times CLOAD 25°C 85°C, Figure CLOAD Figure Figure Figure Pull-Down Resistance LOW-SIDE DRIVER Output Resistance, Sourcing Current 25°C 85°C Output Resistance, Sinking Current 25°C 85°C Output Resistance, Unbiased Transition Times PGND CLOAD Figure CLOAD Figure Propagation Delay Times CLOAD Figure CLOAD Figure Figure Figure trDRVL tfDRVL tpdhDRVL tpdlDRVL tpdlOD tpdhOD PGND tpdlDRVH tpdlOD tpdhOD trDRVH tfDRVH tpdhDRVH ISYS 4.15 13.2 Test Conditions Symbol Unit
limits temperature extremes guaranteed correlation using standard statistical quality control (SQC) methods
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ADP3121
ELECTRICAL CHARACTERISTICS (VCC 85°C, unless otherwise noted) (Note
Characteristic LOW-SIDE DRIVER Timeout Delay Over-voltage Protection Threshold UNDERVOLTAGE LOCKOUT UVLO Voltage Hysteresis rising PGND VSW(OVD) Test Conditions Symbol Unit
limits temperature extremes guaranteed correlation using standard statistical quality control (SQC) methods
APPLICATIONS INFORMATION
Theory Operation Overlap Protection Circuit
ADP3121 optimized driving N-channel MOSFETs synchronous buck converter topology. single input signal that required properly drive high side low-side MOSFETs. Each driver capable driving load speeds kHz. functional block diagram ADP3121 shown Figure
Low-Side Driver
low-side driver designed drive ground referenced N-channel MOSFET. bias low-side driver internally connected supply PGND. When driver enabled, driver output 180° phase with input. When ADP3121 disabled, low-side gate held low.
High-Side Driver
high-side driver designed drive floating N-channel MOSFET. bias voltage high-side driver developed external bootstrap supply circuit that connected between pins. bootstrap circuit comprises Diode Bootstrap Capacitor CBST1. CBST2 RBST included reduce high-side gate drive voltage limit switch node slew rate (called Boot-Snapt circuit). When ADP3121 starts ground, bootstrap capacitor charges through When input goes high, high-side driver begins turn high-side MOSFET, pulling charge CBST1 CBST2. turns rises forces (BST). This holds because enough gate-to-source voltage provided. complete cycle, switched pulling gate down voltage pin. When low-side MOSFET, turns pulled ground. This allows bootstrap capacitor charge again. output high-side driver phase with input. When driver disabled, high-side gate held low.
overlap protection circuit prevents both main power switches, from being same time. This done prevent shoot-through currents from flowing through both power switches associated losses that occur during their on/off transitions. overlap protection circuit accomplishes this adaptively controlling delay from turn-off turn-on, internally setting delay from turn-off turn-on. prevent overlap gate drives during turn-off turn-on, overlap circuit monitors voltage pin. When input signal goes low, begins turn (after propagation delay). Before turn overlap protection circuit makes sure that first gone high then waits voltage fall from Once voltage falls begins turn-on. gone high first, turn-on delayed fixed waiting voltage reach fixed delay time, overlap protection circuit ensures that before turns regardless variations temperature, supply voltage, input pulse width, gate charge, drive current. does below after DRVL turns This occur current flowing output inductor negative flows through high-side MOSFET body diode.
OVERVOLTAGE PROTECTION
ADP3121 includes over-voltage protection (OVP) feature protect from high voltages even before main controller enough operate. ADP3121 looks node during startup. voltage greater than threshold, DRVL latched DRVH latched off. node will cause DRVL high remain high. prevent false triggering OVP, input logic detection latch first occurrence either
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ADP3121
going high. this second latch set, then enabled. clear input detected latch, must fall below UVLO.
Supply Capacitor Selection
where fMAX maximum switching frequency controller. peak surge current rating should calculated
F(PEAK) MOSFET Selection
(eq.
supply input (VCC) ADP3121, local bypass capacitor recommended reduce noise supply some peak currents that drawn. capacitor. Multilayer ceramic chip (MLCC) capacitors provide best combination small size. Keep ceramic capacitor close possible ADP3121.
Bootstrap Circuit
bootstrap circuit uses charge storage capacitor (CBST) diode, shown Figure These components selected after high-side MOSFET chosen. bootstrap capacitor must have voltage rating that handle twice maximum supply voltage. minimum rating recommended. capacitor values determined
BST1 BST2 GATE GATE
(eq.
When interfacing ADP3121 external MOSFETs, designer should consider ways make robust design that minimizes stresses both driver MOSFETs. These stresses include exceeding short time duration voltage ratings driver pins well external MOSFET. also highly recommended Boot-Snap circuit improve interaction driver with characteristics MOSFETs. simple bootstrap arrangement used, make sure include proper snubber network node.
High-Side (Control) MOSFETs
BST1 GATE BST1 BST2
(eq.
where: QGATE total gate charge high-side MOSFET VGATE. VGATE desired gate drive voltage (usually range being typical). voltage drop across Rearranging Equation Equation solve CBST1 yields
BST1 GATE GATE BST1 GATE
CBST2 then found rearranging Equation
BST2
example, NTD60N02 total gate charge about VGATE Using then CBST1 CBST2 Good quality ceramic capacitors should used. RBST used limit slew rate minimize ringing switch node. also provides peak current limiting through RBST value good choice. resistor needs handle least peak currents that flow through small signal diode used bootstrap diode ample gate drive voltage supplied VCC. bootstrap diode must have minimum rating withstand maximum supply voltage. average forward current estimated
F(AVG) GATE
(eq.
high-side, high speed MOSFET usually selected minimize switching losses (see ADP3186 ADP3188 data sheet Flex-Mode controller details). This typically implies gate resistance input capacitance/charge device. Yet, significant source lead inductance also exist that depends mainly MOSFET package; best contact MOSFET vendor this information. ADP3121 DRVH output impedance input resistance MOSFETs determine rate charge delivery internal capacitance gate. This determines speed which MOSFETs turn off. However, because potentially large currents flowing MOSFETs times (this current usually larger turn-off ramping output current output inductor), source lead inductance generates significant voltage when high-side MOSFETs switch off. This creates significant drain-source voltage spike across internal MOSFETs lead catastrophic avalanche. mechanisms involved this avalanche condition referenced literature from MOSFET suppliers. MOSFET vendor should provide rating maximum voltage slew rate drain current around which this designed. Once this specification obtained, determine maximum current expected MOSFET
DC(per phase) OUT)
(eq.
where: DMAX determined controller being used with driver. This current divided roughly equally between MOSFETs more than used (assume worst-case mismatch design margin). LOUT output inductor value.
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ADP3121
When producing design, there exact method calculating dV/dt parasitic effects external MOSFETs well PCB. However, measured determine safe. appears that dV/dt fast, optional gate resistor added between DRVH high-side MOSFETs. This resistor slows down dV/dt, increases switching losses high-side MOSFETs. ADP3121 optimally designed with internal drive impedance that works with most MOSFETs switch them efficiently, minimizes dV/dt. However, some high speed MOSFETs require this external gate resistor depending currents being switched MOSFET.
Low-Side (Synchronous) MOSFETs
turns Contact Semiconductor updated list recommended low-side MOSFETs.
Board Layout Considerations
low-side MOSFETs usually selected have resistance minimize conduction losses. This usually implies large input gate capacitance gate charge. first concern make sure power delivery from ADP3121 DRVL does exceed thermal rating driver (see ADP3186, ADP3188, ADP3189 data sheets Flex-Mode controller details). next concern low-side MOSFETs prevent them from being inadvertently switched when high-side MOSFET turns This occurs drain-gate (Miller capacitance, also specified Crss capacitance) MOSFET. When drain low-side MOSFET switched high-side turning dV/dt rate), internal gate low-side MOSFET pulled amount roughly equal (Crss/Ciss). important make sure this does MOSFET into conduction. Another consideration nonoverlap circuitry ADP3121 that attempts minimize nonoverlap period. During state high-side turning low-side turning monitored well conditions prior switching) adequately prevent overlap. However, during low-side turn-off high-side turn-on, does contain information determining proper switching time, state DRVL monitored below sixth VCC; then, delay added. Miller capacitance internal delays low-side MOSFET gate, ensure that Miller-to-input capacitance ratio enough, that low-side MOSFET internal delays large allow accidental turn-on low-side when high-side
these general guidelines when designing printed circuit boards: Trace high current paths short, wide (>20 mil) traces make these connections. Minimize trace inductance between DRVH DRVL outputs MOSFET gates. Connect PGND ADP3121 closely possible source lower MOSFET. Locate bypass capacitor close possible PGND pins. vias other layers, when possible, maximize thermal conduction away from Figure shows example typical land patterns based guidelines given previously. more detailed layout guidelines complete voltage regulator subsystem, refer Board Layout Considerations section ADP3188 data sheet.
CBST1
CBST2
RBST
CVCC
Figure External Component Placement Example
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ADP3121
tpdlOD DRVH DRVL
tpdhOD
Figure Output Disable Timing Diagram
tpdlDRVL
tfDRVL tpdlDRVH
trDRVL
DRVL
tpdhDRVH
trDRVH
tfDRVH
DRVH-SW
tpdhDRVL
Figure Timing Diagram
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ADP3121
PACKAGE DIMENSIONS
SOIC-8 CASE 751-07 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. 751-01 THRU 751-06 OBSOLETE. STANDARD 751-07. MILLIMETERS 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 0.10 0.25 0.19 0.25 0.40 1.27 0.25 0.50 5.80 6.20 INCHES 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 0.004 0.010 0.007 0.010 0.016 0.050 0.010 0.020 0.228 0.244
0.25 (0.010)
0.25 (0.010)
SEATING PLANE
0.10 (0.004)
SOLDERING FOOTPRINT*
1.52 0.060
0.275
0.155
0.024
1.270 0.050
SCALE inches
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
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ADP3121
PACKAGE DIMENSIONS
LFCSP8 3x3, 0.5P CASE 932AF-01 ISSUE
REFERENCE
0.25 0.25 VIEW 0.10
NOTE
NOTES: DIMENSIONING TOLERANCING ASME Y14.5M, 1994. CONTROLLING DIMENSIONS: MILLIMETERS. DIMENSION APPLIES PLATED TERMINAL MEASURED BETWEEN 0.15 0.30mm FROM TERMINAL TIP. COPLANARITY APPLIES EXPOSED WELL TERMINALS. MILLIMETERS 0.80 0.90 0.00 0.05 0.20 0.18 0.30 3.00 2.75 1.59 1.89 3.00 2.75 1.30 1.60 0.50 0.20 0.30 0.50 0.60
(A3)
0.08
SIDE VIEW
SEATING PLANE
INDICATOR
SOLDERING FOOTPRINT*
1.90 0.63
0.10 0.05
NOTE PACKAGE OUTLINE
BOTTOM VIEW
1.61
3.30
0.50 PITCH
0.30
DIMENSIONS: MILLIMETERS
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
Flex-Mode protected U.S. Patent 6683441; other patents pending.
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ADP3121/D

ADP3121 dual, high voltage MOSFET driver optimized driving N-channel M

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