ADP3120A single Phase MOSFET gate drivers optimized drive gates both h

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ADP3120A single Phase MOSFET gate drivers optimized drive gates both h

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ADP3120A Dual Bootstrapped, MOSFET Driver with Output Disable
ADP3120A single Phase MOSFET gate drivers optimized drive gates both high-side low-side power MOSFETs synchronous buck converter. high-side low-side driver capable driving 3000 load with propagation delay transition time. With wide operating voltage range, high side MOSFET gate drive voltage optimized best efficiency. Internal adaptive nonoverlap circuitry further reduces switching losses preventing simultaneous conduction both MOSFETs. floating driver design accommodate VBST voltages high with transient voltages high Both gate outputs driven applying logic level Output Disable (OD) pin. Undervoltage Lockout function ensures that both driver outputs when supply voltage low, Thermal Shutdown function provides with overtemperature protection.
SO-8 SUFFIX CASE 3120A ALYW ALYWG
DFN8 SUFFIX CASE 506BJ
All-In-One Synchronous Buck Driver Bootstrapped High-Side Drive Signal Generates Both Drives Anticross Conduction Protection Circuitry Disabling Driver Outputs Meets Requirement when Used with Patented FlexModet Controller These Pb-Free Devices
Assembly Location Wafer Year Work Week Pb-Free Package
CONNECTIONS
(Top View) DRVH PGND DRVL DRVH PGND DRVL
Applications
Multiphase Desktop Supplies Single-Supply Synchronous Buck Converters
ORDERING INFORMATION
Device ADP3120AJRZ ADP3120AJRZ-RL ADP3120AJCPZ-RL Package SO-8 (Pb-Free) Shipping Units Rail
SO-8 2500 Tape Reel (Pb-Free) DFN8 5000 Tape Reel (Pb-Free)
information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specification Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2008
August, 2008 Rev.
Publication Order Number: ADP3120A/D
ADP3120A
UVLO DRVH
FALLING EDGE DELAY FALLING EDGE DELAY START STOP NON-OVERLAP TIMERS
MONITOR
MONITOR
DRVL TIMER
DRVL PGND
Figure Block Diagram
DESCRIPTION
SO-8 DFN8 Symbol Description Upper MOSFET Floating Bootstrap Supply. capacitor connected between pins holds this bootstrap voltage high-side MOSFET switched. recommended capacitor value between external diode required with ADP3120A. Logic-Level Input. This primary control drive outputs. Output Disable. When low, normal operation disabled forcing DRVH DRVL low. Input Supply. ceramic capacitor should connected from this PGND. Output drive lower MOSFET. Power Ground. Should closely connected source lower MOSFET. Switch Node. Connect source upper MOSFET. Output drive upper MOSFET.
DRVL PGND DRVH
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ADP3120A
MAXIMUM RATINGS
Rating Operating Ambient Temperature, Operating Junction Temperature, (Note Package Thermal Resistance: SO-8 Junction-to-Case, RqJC Junction-to-Ambient, RqJA (2-Layer Board) Package Thermal Resistance: DFN8 (Note Junction-to-Case, RqJC (From exposed pad) Junction-to-Ambient, RqJA Storage Temperature Range, Lead Temperature Soldering sec): Reflow (SMD styles only) JEDEC Moisture Sensitivity Level Pb-Free (Note SO-8 (260 peak profile) Value peak Unit °C/W °C/W °C/W °C/W
Stresses exceeding Maximum Ratings damage device. Maximum Ratings stress ratings only. Functional operation above Recommended Operating Conditions implied. Extended exposure stresses above Recommended Operating Conditions affect device reliability. Internally limited thermal shutdown, 150°C min. layer board, thickness. 60-180 seconds minimum above 237°C. NOTE: This device sensitive. standard precautions when handling.
MAXIMUM RATINGS
Symbol PGND Name Main Supply Voltage Input Ground Bootstrap Supply Voltage Input VMAX wrt/PGND wrt/PGND wrt/SW VMIN -0.3 -0.3 wrt/SW
DRVH DRVL NOTE:
Switching Node (Bootstrap Supply Return) High-Side Driver Output Low-Side Driver Output DRVH DRVL Control Input Output Disable
-5.0 -0.3 wrt/SW -2.0 wrt/SW -0.3 -5.0 -0.3 -0.3
voltages with respect PGND except where noted.
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ADP3120A
ELECTRICAL CHARACTERISTICS (Note (VCC +85°C, +125°C unless otherwise noted.)
Characteristic Supply Supply Voltage Range Supply Current Input Input Voltage High Input Voltage Hysteresis Input Current Input Input Voltage High Input Voltage Hysteresis Input Current High-Side Driver Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times (Note trDRVH tfDRVH tpdhDRVH tpdlDRVH tpdlOD tpdhOD Pulldown Resitance Low-Side Driver Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times (Note trDRVL tfDRVL tpdhDRVL tpdlDRVL tpdlOD tpdhOD Timeout Delay Undervoltage Lockout UVLO Startup UVLO Shutdown Hysteresis PGND CLOAD (See Figure CLOAD (See Figure (Note tpdhDRVL only) (See Figure (See Figure DRVH CLOAD (See Figure CLOAD (See Figure CLOAD (See Figure (See Figure (See Figure PGND VPWM_HI VPWM_LO internal pullup pulldown resistors -1.0 +1.0 VOD_HI VOD_LO internal pullup pulldown resistors -1.0 +1.0 ISYS 13.2 Symbol Condition Unit
limits temperature extremes guaranteed correlation using standard Statistical Quality Control (SQC). propagation delays, "tpdh" refers specified signal going high; "tpdl" refers going low. Guaranteed design; tested production.
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ADP3120A
APPLICATIONS INFORMATION
Theory Operation
ADP3120A single phase MOSFET drivers designed driving N-channel MOSFETs synchronous buck converter topology. ADP3120A will operate from have been optimized high current multi-phase buck regulators that convert rail directly core voltage required complex logic chips. single input signal that required properly drive high-side low-side MOSFETs. Each driver capable driving load frequencies MHz.
Low-Side Driver
Likewise, when input goes low, DRVH will after propagation delay (tpdDRVH). time turn high-side MOSFET (tfDRVH) dependent total gate charge high-side MOSFET. timer will triggered once high-side mosfet stopped conducting, delay (tpdhDRVL) turn low-side MOSFET
Power Supply Decoupling
low-side driver designed drive ground-referenced RDS(on) N-Channel MOSFET. voltage rail low-side driver internally connected supply PGND.
High-Side Driver
ADP3120A source sink relatively large currents gate pins external MOSFETs. order maintain constant stable supply voltage (VCC) capacitor should placed near power ground pins. multi layer ceramic capacitor (MLCC) usually sufficient.
Input Pins
high-side driver designed drive floating RDS(on) N-channel MOSFET. gate voltage high side driver developed bootstrap circuit referenced Switch Node (SW) pin. bootstrap circuit comprised external diode, external bootstrap capacitor. When ADP3120A starting ground, bootstrap capacitor will charge through bootstrap diode Figure When input goes high, high-side driver will begin turn high-side MOSFET using stored charge bootstrap capacitor. high-side MOSFET turns will rise. When high-side MOSFET fully switch node will will plus charge bootstrap capacitor (approaching bootstrap capacitor recharged when switch node goes during next cycle.
Safety Timer Overlap Protection Circuit
input Output Disable pins ADP3120A have internal protection Electro Static Discharge (ESD), normal operation they present relatively high input impedance. controller does have internal pulldown resistors, they should added externally ensure that driver outputs high before controller reached under voltage lockout threshold. NCP5381 controller does include passive internal pulldown resistor drive-on output pin.
Bootstrap Circuit
bootstrap circuit uses charge storage capacitor (CBST) internal external) diode. Selection these components done after high-side MOSFET been chosen. bootstrap capacitor must have voltage rating that able withstand twice maximum supply voltage. minimum rating recommended. capacitance determined using following equation:
CBST QGATE DVBST
very important that MOSFETs synchronous buck regulator both conduct same time. Excessive shoot-through cross conduction damage MOSFETs, even small amount cross conduction will cause decrease power conversion efficiency. ADP3120A prevent cross conduction monitoring status external mosfets applying appropriate amount "dead-time" time between turn MOSFET turn other MOSFET. When input goes high, DRVL will after propagation delay (tpdlDRVL). time takes low-side MOSFET turn (tfDRVL) dependent total charge low-side MOSFET gate. ADP3120A monitor gate voltage both MOSFETs switchnode voltage determine conduction status MOSFETs. Once low-side MOSFET turned internal timer will delay (tpdhDRVH) turn high-side MOSFET
where QGATE total gate charge high-side MOSFET, DVBST voltage droop allowed high-side MOSFET drive. example, NTD60N03 total gate charge about allowed droop required bootstrap capacitance good quality ceramic capacitor should used. bootstrap diode must rated withstand maximum supply voltage plus peak ringing voltages that present average forward current estimated
IF(AVG) QGATE fMAX
where fMAX maximum switching frequency controller. peak surge current rating should checked in-circuit, since this dependent source impedance supply CBST.
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ADP3120A
VOD_LO tpdlOD DRVH DRVL tpdhOD VOD_HI
Figure Output Disable Timing Diagram
VPWM_HI VPWM_LO tpdlDRVL tpdhDRVH DRVH-SW tpdhDRVL trDRVH tpdlDRVH tfDRVH trDRVL tfDRVL
DRVL
Figure Nonoverlap Timing Diagram
ADP3120A
Output Enable
DRVH DRVL PGND
Vout
Figure ADP3120A Example Circuit
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ADP3120A
PACKAGE DIMENSIONS
DFN8 3x3, 0.5P CASE 506BJ-01 ISSUE
EDGE PACKAGE
REFERENCE
OPTIONAL CONSTRUCTION
DETAIL
NOTES: DIMENSIONS TOLERANCING ASME Y14.5M, 1994. CONTROLLING DIMENSION: MILLIMETERS. DIMENSION APPLIES PLATED TERMINAL MEASURED BETWEEN 0.15 0.30 FROM TERMINAL. COPLANARITY APPLIES EXPOSED WELL TERMINALS. MILLIMETERS 0.80 1.00 0.00 0.05 0.20 0.18 0.30 3.00 1.64 1.84 3.00 1.35 1.55 0.50 0.20 0.30 0.50 0.00 0.03
0.10
0.10
0.05
0.05
NOTE
BOTTOM VIEW
0.10 0.05
NOTE
SOLDERMASK DEFINED MOUNTING FOOTPRINT
1.85 0.35
3.30
0.63
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
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VIEW
DETAIL
DETAIL
OPTIONAL CONSTRUCTION
(A3)
DETAIL
SIDE VIEW
SEATING PLANE
EXPOSED
MOLD CMPD
DETAIL
OPTIONAL CONSTRUCTION
1.55
0.50 PITCH
DIMENSION: MILLIMETERS
ADP3120A
PACKAGE DIMENSIONS
SOIC-8 SUFFIX CASE 751-07 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. 751-01 THRU 751-06 OBSOLETE. STANDARD 751-07. MILLIMETERS 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 0.10 0.25 0.19 0.25 0.40 1.27 0.25 0.50 5.80 6.20 INCHES 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 0.004 0.010 0.007 0.010 0.016 0.050 0.010 0.020 0.228 0.244
0.25 (0.010)
0.25 (0.010)
SEATING PLANE
0.10 (0.004)
SOLDERING FOOTPRINT*
1.52 0.060
0.275
0.155
0.024
1.270 0.050
SCALE
inches
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
FlexMode trademark Analog Devices, Inc.
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
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ADP3120A/D

ADP3120A single Phase MOSFET gate drivers optimized drive gates both h

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