Single-chip 16-bit/32-bit MCU; flash with ISP/IAP, Ethernet, device/ho
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LPC2361/62
Single-chip 16-bit/32-bit MCU; flash with ISP/IAP, Ethernet, device/host/OTG, CAN, 10-bit ADC/DAC
Rev. November 2008 Product data sheet
LPC2361/62 microcontrollers based 16-bit/32-bit ARM7TDMI-S with real-time emulation that combines microcontroller with embedded high-speed flash memory. 128-bit wide memory interface unique accelerator architecture enable 32-bit code execution maximum clock rate. critical performance interrupt service routines algorithms, this increases performance over Thumb mode. critical code size applications, alternative 16-bit Thumb mode reduces code more than with minimal performance penalty. LPC2361/62 ideal multi-purpose serial communication applications. They incorporate 10/100 Ethernet Media Access Controller (MAC) (LPC2362 only), full speed device with endpoint RAM, four UARTs, channels, interface, Synchronous Serial Ports (SSP), three interfaces, interface. This blend serial communications interfaces combined with on-chip internal oscillator, SRAM SRAM Ethernet (available general purpose SRAM LPC2361), SRAM general purpose use, together with battery powered SRAM make these devices very well suited communication gateways protocol converters. Various 32-bit timers, improved 10-bit ADC, 10-bit DAC, unit, control unit, fast GPIO lines with edge level sensitive external interrupt pins make these microcontrollers particularly suitable industrial control medical systems.
Features
ARM7TDMI-S processor, running MHz. on-chip flash program memory with In-System Programming (ISP) In-Application Programming (IAP) capabilities. Flash program memory local high performance access. (LPC2361) (LPC2362) SRAM local high performance access. SRAM Ethernet interface. also used general purpose SRAM. SRAM general purpose also accessible USB. Dual Advanced High-performance (AHB) system that provides simultaneous Ethernet (LPC2362 only), DMA, program execution from on-chip flash with contention between those functions. bridge allows Ethernet access other subsystem. Advanced Vectored Interrupt Controller (VIC), supporting vectored interrupts. General Purpose controller (GPDMA) that used with serial interfaces, port, well memory-to-memory transfers.
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Serial interfaces: Ethernet with associated controller (LPC2362 only). These functions reside independent AHB. device/host/OTG with on-chip associated controller. Four UARTs with fractional baud rate generation, with modem control I/O, with IrDA support, with FIFO. controller with channels. controller. controllers, with FIFO multi-protocol capabilities. alternate port, sharing interrupt pins. These used with GPDMA controller. Three I2C-bus interfaces (one with open-drain with standard port pins). (Inter-IC Sound) interface digital audio input output. used with GPDMA. Other peripherals: general purpose pins with configurable pull-up/down resistors. 10-bit with input multiplexing among pins. 10-bit DAC. Four general purpose timers/counters with total capture inputs compare outputs. Each timer block external count input. PWM/timer block with support three-phase motor control. external count inputs. Real-Time Clock (RTC) with separate power pin, clock source oscillator clock. SRAM powered from power pin, allowing data stored when rest chip powered off. WatchDog Timer (WDT). clocked from internal oscillator, oscillator, clock. Standard test/debug interface compatibility with existing tools. Emulation trace module supports real-time trace. Single power supply (3.0 Three reduced power modes: idle, sleep, power-down. Four external interrupt inputs configurable edge/level sensitive. pins PORT0 PORT2 used edge sensitive interrupt sources. Processor wake-up from Power-down mode interrupt able operate during Power-down mode (includes external interrupts, interrupt, activity, Ethernet wake-up interrupt). independent power domains allow fine tuning power consumption based needed features. Each peripheral clock divider further power saving. Brownout detect with separate thresholds interrupt forced reset. On-chip power-on reset. On-chip crystal oscillator with operating range MHz. internal oscillator trimmed accuracy that optionally used system clock. When used clock, does allow run.
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
On-chip allows operation maximum rate without need high frequency crystal. from main oscillator, internal oscillator, oscillator. Versatile function selections allow more possibilities using on-chip peripheral functions.
Applications
Industrial control Medical systems Protocol converter Communications
Ordering information
Table Ordering information Package Name LPC2361FBD100 LPC2362FBD100 LQFP100 LQFP100 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT407-1 SOT407-1 Type number
Ordering options
Table Ordering options Flash (kB) SRAM (kB) Ethernet buffer Ethernet device FIFO Channels Temp range Type number
Local
GP/USB
Total
LPC2361FBD100 LPC2362FBD100
16[1]
RMII
Available general purpose SRAM LPC2361.
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Block diagram
XTAL1 XTAL2 VDDA
trace signals
TRST EXTIN0
RESET
VDD(3V3) VREF VSSA, VDD(DCDC)(3V3)
LPC2361/62
TEST/DEBUG INTERFACE EMULATION TRACE MODULE HIGH-SPEED GPI/O PINS TOTAL 8/32 SRAM 64/128 FLASH system clock
SYSTEM FUNCTIONS INTERNAL OSCILLATOR
INTERNAL CONTROLLERS SRAM FLASH
ARM7TDMI-S
VECTORED INTERRUPT CONTROLLER BRIDGE SRAM AHB1
AHB2
BRIDGE
RMII(8)
ETHERNET WITH DMA(1)
SRAM
MASTER SLAVE PORT BRIDGE PORT BRIDGE
WITH
VBUS port
CONTROLLER I2SRX_CLK I2STX_CLK I2SRX_WS I2STX_WS I2SRX_SDA I2STX_SDA SCK, SCK0 MOSI, MOSI0 MISO, MISO0 SSEL, SSEL0 SCK1 MOSI1 MISO1 SSEL1 TXD0, TXD2, TXD3 RXD0, RXD2, RXD3 TXD1 RXD1 DTR1, RTS1 DSR1, CTS1, DCD1,
EINT3 EINT0 CAP0/CAP1/ CAP2/CAP3 MAT2, MAT0/MAT1/ MAT3 PWM1 PCAP1
EXTERNAL INTERRUPTS CAPTURE/COMPARE TIMER0/TIMER1/ TIMER2/TIMER3 INTERFACE
PWM1
SPI, SSP0 INTERFACE
LEGACY GPI/O PINS TOTAL
SSP1 INTERFACE
CONVERTER
UART0, UART2, UART3
AOUT
CONVERTER UART1 BATTERY
VBAT power domain power domain RTCX1 RTCX2
OSCILLATOR
REALTIME CLOCK
CAN1, CAN2 I2C0, I2C1, I2C2
RD1, TD1, SCL0, SCL1, SCL2 SDA0, SDA1, SDA2
WATCHDOG TIMER SYSTEM CONTROL
002aad964
LPC2362 only.
LPC2361/62 block diagram
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Pinning information
Pinning
002aad965
LPC2361FBD100 LPC2362FBD100
LPC2361/62 pinning
description
Table Symbol P0[0] P0[31] description Type Description Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins this port available. P0[0] General purpose digital input/output pin. CAN1 receiver input. TXD3 Transmitter output UART3. SDA1 I2C1 data input/output (this open-drain pin). P0[1] General purpose digital input/output pin. CAN1 transmitter output. RXD3 Receiver input UART3. SCL1 I2C1 clock input/output (this open-drain pin). P0[2] General purpose digital input/output pin. TXD0 Transmitter output UART0. P0[3] General purpose digital input/output pin. RXD0 Receiver input UART0. P0[4] General purpose digital input/output pin. I2SRX_CLK Receive Clock. driven master received slave. Corresponds signal I2S-bus specification. CAN2 receiver input. CAP2[0] Capture input Timer channel
P0[0]/RD1/TXD3/ SDA1
46[1]
P0[1]/TD1/RXD3/ SCL1
47[1]
P0[2]/TXD0 P0[3]/RXD0 P0[4]/I2SRX_CLK/ RD2/CAP2[0]
98[1] 99[1] 81[1]
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Table Symbol
description .continued 80[1] Type Description P0[5] General purpose digital input/output pin. I2SRX_WS Receive Word Select. driven master received slave. Corresponds signal I2S-bus specification. CAN2 transmitter output. CAP2[1] Capture input Timer channel P0[6] General purpose digital input/output pin. I2SRX_SDA Receive data. driven transmitter read receiver. Corresponds signal I2S-bus specification. SSEL1 Slave Select SSP1. MAT2[0] Match output Timer channel P0[7] General purpose digital input/output pin. I2STX_CLK Transmit Clock. driven master received slave. Corresponds signal I2S-bus specification. SCK1 Serial Clock SSP1. MAT2[1] Match output Timer channel P0[8] General purpose digital input/output pin. I2STX_WS Transmit Word Select. driven master received slave. Corresponds signal I2S-bus specification. MISO1 Master Slave SSP1. MAT2[2] Match output Timer channel P0[9] General purpose digital input/output pin. I2STX_SDA Transmit data. driven transmitter read receiver. Corresponds signal I2S-bus specification. MOSI1 Master Slave SSP1. MAT2[3] Match output Timer channel P0[10] General purpose digital input/output pin. TXD2 Transmitter output UART2. SDA2 I2C2 data input/output (this open-drain pin). MAT3[0] Match output Timer channel P0[11] General purpose digital input/output pin. RXD2 Receiver input UART2. SCL2 I2C2 clock input/output (this open-drain pin). MAT3[1] Match output Timer channel P0[15] General purpose digital input/output pin. TXD1 Transmitter output UART1. SCK0 Serial clock SSP0. Serial clock SPI. P0[16] General purpose digital input/output pin. RXD1 Receiver input UART1. SSEL0 Slave Select SSP0. SSEL Slave Select SPI.
P0[5]/I2SRX_WS/ TD2/CAP2[1]
P0[6]/I2SRX_SDA/ SSEL1/MAT2[0]
79[1]
P0[7]/I2STX_CLK/ SCK1/MAT2[1]
78[1]
P0[8]/I2STX_WS/ MISO1/MAT2[2]
77[1]
P0[9]/I2STX_SDA/ MOSI1/MAT2[3]
76[1]
P0[10]/TXD2/ SDA2/MAT3[0]
48[1]
P0[11]/RXD2/ SCL2/MAT3[1]
49[1]
P0[15]/TXD1/ SCK0/SCK
62[1]
P0[16]/RXD1/ SSEL0/SSEL
63[1]
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Table Symbol
description .continued 61[1] Type Description P0[17] General purpose digital input/output pin. CTS1 Clear Send input UART1. MISO0 Master Slave SSP0. MISO Master Slave SPI. P0[18] General purpose digital input/output pin. DCD1 Data Carrier Detect input UART1. MOSI0 Master Slave SSP0. MOSI Master Slave SPI. P0[19] General purpose digital input/output pin. DSR1 Data Ready input UART1. SDA1 I2C1 data input/output (this open-drain pin). P0[20] General purpose digital input/output pin. DTR1 Data Terminal Ready output UART1. SCL1 I2C1 clock input/output (this open-drain pin). P0[21] General purpose digital input/output pin. Ring Indicator input UART1. CAN1 receiver input. P0[22] General purpose digital input/output pin. RTS1 Request Send output UART1. CAN1 transmitter output. P0[23] General purpose digital input/output pin. AD0[0] converter input I2SRX_CLK Receive Clock. driven master received slave. Corresponds signal I2S-bus specification. CAP3[0] Capture input Timer channel P0[24] General purpose digital input/output pin. AD0[1] converter input I2SRX_WS Receive Word Select. driven master received slave. Corresponds signal I2S-bus specification. CAP3[1] Capture input Timer channel P0[25] General purpose digital input/output pin. AD0[2] converter input I2SRX_SDA Receive data. driven transmitter read receiver. Corresponds signal I2S-bus specification. TXD3 Transmitter output UART3. P0[26] General purpose digital input/output pin. AD0[3] converter input AOUT converter output. RXD3 Receiver input UART3. P0[27] General purpose digital input/output pin. Output open-drain. SDA0 I2C0 data input/output. Open-drain output (for I2C-bus compliance).
P0[17]/CTS1/ MISO0/MISO
P0[18]/DCD1/ MOSI0/MOSI
60[1]
P0[19]/DSR1/SDA1
59[1]
P0[20]/DTR1/SCL1
58[1]
P0[21]/RI1/RD1
57[1]
P0[22]/RTS1/TD1
56[1]
P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]
9[2]
P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]
8[2]
P0[25]/AD0[2]/ I2SRX_SDA/ TXD3
7[2]
P0[26]/AD0[3]/ AOUT/RXD3
6[3]
P0[27]/SDA0
25[4]
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Table Symbol
description .continued 24[4] 29[5] 30[5] Type Description P0[28] General purpose digital input/output pin. Output open-drain. SCL0 I2C0 clock input/output. Open-drain output (for I2C-bus compliance). P0[29] General purpose digital input/output pin. USB_D+ bidirectional line. P0[30] General purpose digital input/output pin. USB_D- bidirectional line. Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins this port available. P1[0] General purpose digital input/output pin. ENET_TXD0 Ethernet transmit data (LPC2362 only). P1[1] General purpose digital input/output pin. ENET_TXD1 Ethernet transmit data (LPC2362 only). P1[4] General purpose digital input/output pin. ENET_TX_EN Ethernet transmit data enable (LPC2362 only). P1[8] General purpose digital input/output pin. ENET_CRS Ethernet carrier sense (LPC2362 only). P1[9] General purpose digital input/output pin. ENET_RXD0 Ethernet receive data (LPC2362 only). P1[10] General purpose digital input/output pin. ENET_RXD1 Ethernet receive data (LPC2362 only). P1[14] General purpose digital input/output pin. ENET_RX_ER Ethernet receive error (LPC2362 only). P1[15] General purpose digital input/output pin. ENET_REF_CLK Ethernet reference clock (LPC2362 only). P1[16] General purpose digital input/output pin. ENET_MDC Ethernet MIIM clock (LPC2362 only). P1[17] General purpose digital input/output pin. ENET_MDIO Ethernet MIIM data input output (LPC2362 only). P1[18] General purpose digital input/output pin. USB_UP_LED GoodLink indicator. when device configured (non-control endpoints enabled). HIGH when device configured during global suspend. PWM1[1] Pulse Width Modulator channel output. CAP1[0] Capture input Timer channel P1[19] General purpose digital input/output pin. USB_TX_E1 Transmit Enable signal port (OTG transceiver). USB_PPWR1 Port Power enable signal port CAP1[1] Capture input Timer channel
P0[28]/SCL0 P0[29]/USB_D+ P0[30]/USB_D- P1[0] P1[31]
P1[0]/ENET_TXD0 P1[1]/ENET_TXD1 P1[4]/ENET_TX_EN P1[8]/ENET_CRS P1[9]/ENET_RXD0 P1[10]/ENET_RXD1 P1[14]/ ENET_RX_ER P1[15]/ ENET_REF_CLK P1[16]/ENET_MDC P1[17]/ENET_MDIO P1[18]/ USB_UP_LED/ PWM1[1]/CAP1[0]
95[1] 94[1] 93[1] 92[1] 91[1] 90[1] 89[1] 88[1] 87[1] 86[1] 32[1]
P1[19]/ USB_TX_E1/ USB_PPWR1/ CAP1[1] 33[1]
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Table Symbol
description .continued 34[1] Type 35[1] 36[1] 37[1] 38[1] 39[1] 40[1] 43[1] 44[1] Description P1[20] General purpose digital input/output pin. USB_TX_DP1 transmit data port (OTG transceiver). PWM1[2] Pulse Width Modulator channel output. SCK0 Serial clock SSP0. P1[21] General purpose digital input/output pin. USB_TX_DM1 transmit data port (OTG transceiver). PWM1[3] Pulse Width Modulator channel output. SSEL0 Slave Select SSP0. P1[22] General purpose digital input/output pin. USB_RCV1 Differential receive data port (OTG transceiver). USB_PWRD1 Power Status port (host power switch). MAT1[0] Match output Timer channel P1[23] General purpose digital input/output pin. USB_RX_DP1 receive data port (OTG transceiver). PWM1[4] Pulse Width Modulator channel output. MISO0 Master Slave SSP0. P1[24] General purpose digital input/output pin. USB_RX_DM1 receive data port (OTG transceiver). PWM1[5] Pulse Width Modulator channel output. MOSI0 Master Slave SSP0. P1[25] General purpose digital input/output pin. USB_LS1 Low-speed status port (OTG transceiver). USB_HSTEN1 Host Enabled status port MAT1[1] Match output Timer channel P1[26] General purpose digital input/output pin. USB_SSPND1 port suspend status (OTG transceiver). PWM1[6] Pulse Width Modulator channel output. CAP0[0] Capture input Timer channel P1[27] General purpose digital input/output pin. USB_INT1 port transceiver interrupt (OTG transceiver). USB_OVRCR1 port Over-Current status. CAP0[1] Capture input Timer channel P1[28] General purpose digital input/output pin. USB_SCL1 port I2C-bus serial clock (OTG transceiver). PCAP1[0] Capture input PWM1, channel MAT0[0] Match output Timer channel P1[29] General purpose digital input/output pin. USB_SDA1 port I2C-bus serial data (OTG transceiver). PCAP1[1] Capture input PWM1, channel MAT0[1] Match output Timer channel
P1[20]/ USB_TX_DP1/ PWM1[2]/SCK0
P1[21]/ USB_TX_DM1/ PWM1[3]/SSEL0
P1[22]/ USB_RCV1/ USB_PWRD1/ MAT1[0] P1[23]/ USB_RX_DP1/ PWM1[4]/MISO0
P1[24]/ USB_RX_DM1/ PWM1[5]/MOSI0
P1[25]/ USB_LS1/ USB_HSTEN1/ MAT1[1] P1[26]/ USB_SSPND1/ PWM1[6]/ CAP0[0] P1[27]/ USB_INT1/ USB_OVRCR1/ CAP0[1] P1[28]/USB_SCL1/ PCAP1[0]/MAT0[0]
P1[29]/USB_SDA1/ PCAP1[1]/MAT0[1]
45[1]
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Table Symbol
description .continued 21[2] Type Description P1[30] General purpose digital input/output pin. VBUS Monitors presence power. Note: This signal must HIGH reset occur. AD0[4] converter input P1[31] General purpose digital input/output pin. SCK1 Serial Clock SSP1. AD0[5] converter input Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins through this port available. P2[0] General purpose digital input/output pin. PWM1[1] Pulse Width Modulator channel output. TXD1 Transmitter output UART1. TRACECLK Trace Clock. P2[1] General purpose digital input/output pin. PWM1[2] Pulse Width Modulator channel output. RXD1 Receiver input UART1. PIPESTAT0 Pipeline Status, P2[2] General purpose digital input/output pin. PWM1[3] Pulse Width Modulator channel output. CTS1 Clear Send input UART1. PIPESTAT1 Pipeline Status, P2[3] General purpose digital input/output pin. PWM1[4] Pulse Width Modulator channel output. DCD1 Data Carrier Detect input UART1. PIPESTAT2 Pipeline Status, P2[4] General purpose digital input/output pin. PWM1[5] Pulse Width Modulator channel output. DSR1 Data Ready input UART1. TRACESYNC Trace Synchronization. P2[5] General purpose digital input/output pin. PWM1[6] Pulse Width Modulator channel output. DTR1 Data Terminal Ready output UART1. TRACEPKT0 Trace Packet, P2[6] General purpose digital input/output pin. PCAP1[0] Capture input PWM1, channel Ring Indicator input UART1. TRACEPKT1 Trace Packet,
P1[30]/VBUS/AD0[4]
P1[31]/SCK1/AD0[5]
20[2]
P2[0] P2[31]
P2[0]/PWM1[1]/ TXD1/TRACECLK
75[1]
P2[1]/PWM1[2]/ RXD1/PIPESTAT0
74[1]
P2[2]/PWM1[3]/ CTS1/PIPESTAT1
73[1]
P2[3]/PWM1[4]/ DCD1/PIPESTAT2
70[1]
P2[4]/PWM1[5]/ DSR1/TRACESYNC
69[1]
P2[5]/PWM1[6]/ DTR1/TRACEPKT0
68[1]
P2[6]/PCAP1[0]/RI1/ TRACEPKT1
67[1]
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Table Symbol
description .continued 66[1] Type Description P2[7] General purpose digital input/output pin. CAN2 receiver input. RTS1 Request Send output UART1. TRACEPKT2 Trace Packet, P2[8] General purpose digital input/output pin. CAN2 transmitter output. TXD2 Transmitter output UART2. TRACEPKT3 Trace Packet, P2[9] General purpose digital input/output pin. USB_CONNECT Signal used switch external resistor under software control. Used with SoftConnect feature. RXD2 Receiver input UART2. EXTIN0 External Trigger Input. P2[10] General purpose digital input/output pin. Note: this while RESET forces on-chip bootloader take over control part after reset. EINT0 External interrupt input. P2[11] General purpose digital input/output pin. EINT1 External interrupt input. I2STX_CLK Transmit Clock. driven master received slave. Corresponds signal I2S-bus specification. P2[12] General purpose digital input/output pin. EINT2 External interrupt input. I2STX_WS Transmit Word Select. driven master received slave. Corresponds signal I2S-bus specification. P2[13] General purpose digital input/output pin. EINT3 External interrupt input. I2STX_SDA Transmit data. driven transmitter read receiver. Corresponds signal I2S-bus specification. Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins through through this port available. P3[25] General purpose digital input/output pin. MAT0[0] Match output Timer channel PWM1[2] Pulse Width Modulator output P3[26] General purpose digital input/output pin. MAT0[1] Match output Timer channel PWM1[3] Pulse Width Modulator output Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins through this port available.
P2[7]/RD2/RTS1/ TRACEPKT2
P2[8]/TD2/TXD2/ TRACEPKT3
65[1]
P2[9]/ USB_CONNECT/ RXD2/EXTIN0
64[1]
P2[10]/EINT0
53[6]
P2[11]/EINT1/ I2STX_CLK
52[6]
P2[12]/EINT2/ I2STX_WS
51[6]
P2[13]/EINT3/ I2STX_SDA
50[6]
P3[0] P3[31]
P3[25]/MAT0[0]/ PWM1[2]
27[1]
P3[26]/MAT0[1]/ PWM1[3]
26[1]
P4[0] P4[31]
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Table Symbol
description .continued 82[1] Type 85[1] 1[1] 2[1] 3[1] 4[1] 5[1] 100[1] Description P4[28] General purpose digital input/output pin. MAT2[0] Match output Timer channel TXD3 Transmitter output UART3. P4[29] General purpose digital input/output pin. MAT2[1] Match output Timer channel RXD3 Receiver input UART3. Test Data JTAG interface. Test Data JTAG interface. Test Mode Select JTAG interface. TRST Test Reset JTAG interface. Test Clock JTAG interface. This clock must slower than clock (CCLK) JTAG interface operate RTCK JTAG interface control signal. Note: this while RESET enables Epins (P2[9:0]) operate trace port after reset.
P4[28]/MAT2[0]/ TXD3
P4[29]/MAT2[1]/ RXD3
TRST RTCK
RSTOUT RESET
17[7]
RSTOUT This pin. this indicates LPC2361/62 being Reset state. External reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Input oscillator circuit. Output from oscillator circuit. ground: reference.
XTAL1 XTAL2 RTCX1 RTCX2
22[8] 23[8] 16[8] 18[8]
83[9] 11[10]
VSSA VDD(3V3)
analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. supply voltage: This power supply voltage ports.
96[11] 84[12] 10[13]
VDD(DCDC)(3V3) VDDA
DC-to-DC converter supply voltage: This supply voltage on-chip DC-to-DC converter only. analog supply voltage: This should nominally same voltage VDD(3V3) should isolated minimize noise error. This voltage used power DAC. reference: This should nominally same voltage VDD(3V3) should isolated minimize noise error. Level this used reference DAC. power supply: this supplies power peripheral.
VREF
12[13]
VBAT
19[13]
tolerant providing digital functions with levels hysteresis. tolerant providing digital functions (with levels hysteresis) analog input. When configured input, digital section disabled.
B.V. 2008. rights reserved.
LPC2361_62_3
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
tolerant providing digital with levels hysteresis analog output function. When configured output, digital section disabled. Open-drain tolerant digital pad, compatible with I2C-bus specification. This requires external pull-up provide output functionality. When power switched off, this connected I2C-bus floating does disturb lines. Open-drain configuration applies functions this pin. provides digital functions. designed accordance with specification, revision (Full-speed Low-speed mode only). tolerant with glitch filter providing digital functions with levels hysteresis. tolerant with glitch filter providing digital function with levels hysteresis. provides special analog functionality. provides special analog functionality.
[10] provides special analog functionality. [11] provides special analog functionality. [12] provides special analog functionality. [13] provides special analog functionality.
Functional description
Architectural overview
LPC2361/62 microcontroller consists ARM7TDMI-S with emulation support, ARM7 local closely coupled, high-speed access majority on-chip memory, AMBA interfacing high-speed on-chip peripherals, AMBA connection other on-chip peripheral functions. microcontroller permanently configures ARM7TDMI-S processor little-endian byte order. LPC2362 implements AHBs order allow Ethernet block operate without interference caused other system activity. primary AHB, referred AHB1, includes GPDMA controller. second AHB, referred AHB2, includes only Ethernet block associated SRAM. addition, bridge provided that allows secondary master AHB1, allowing expansion Ethernet buffer space into off-chip memory unused space memory residing AHB1. summary, masters with access AHB1 ARM7 itself, GPDMA function, Ethernet block (via bridge from AHB2). masters with access AHB2 ARM7 Ethernet block. peripherals allocated range addresses very memory space. Each peripheral allocated address space within address space. Lower speed peripheral functions connected APB. bridge interfaces AHB. peripherals also allocated range addresses, beginning address point. Each peripheral allocated address space within address space. ARM7TDMI-S processor general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed complex instruction computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core.
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Product data sheet
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LPC2361/62
Single-chip 16-bit/32-bit
Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit 16-bit Thumb
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-chip flash programming memory
LPC2361/62 incorporate flash memory system respectively. This memory used both code data storage. Programming flash memory accomplished several ways. programmed System serial port (UART0). application program also erase and/or program flash while application running, allowing great degree flexibility data storage field firmware upgrades. flash memory bits wide includes pre-fetching buffering techniques allow operate SRAM speeds MHz. LPC2361/62 provides minimum 100000 write/erase cycles years data retention.
On-chip SRAM
LPC2361/62 include SRAM memory (LPC2361) (LPC2362), reserved processor exclusive use. This used code and/or data storage accessed bits, bits, bits. SRAM block serving buffer Ethernet controller (available general purpose SRAM LPC2361) SRAM used GPDMA controller device used both data code storage. SRAM used data storage only. SRAM battery powered retains content absence main power supply.
Memory
LPC2361/62 memory incorporates several distinct regions shown Figure
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addition, interrupt vectors remapped allow them reside either flash memory (default), boot ROM, SRAM (see Section 7.24.6).
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000
0xE000 0000
RESERVED ADDRESS SPACE
0xC000 0000
BOOT BOOT FLASH (BOOT FLASH REMAPPED FROM ON-CHIP FLASH) RESERVED ADDRESS SPACE ETHERNET GENERAL PURPOSE
0x8000 0000
0x7FE0 3FFF 0x7FE0 0000 0x7FD0 1FFF 0x7FD0 0000
RESERVED ADDRESS SPACE 0x4000 8000 0x4000 7FFF LOCAL ON-CHIP STATIC (LPC2362) 0x4000 2000 0x4000 1FFF LOCAL ON-CHIP STATIC (LPC2361) 0x4000 0000
RESERVED ON-CHIP MEMORY
TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2362) TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2361)
0x0002 0000 0x0001 FFFF 0x0001 0000 0x0000 FFFF 0x0000 0000
002aae283
LPC2361/62 memory
Interrupt controller
processor core interrupt inputs called Interrupt Request (IRQ) Fast Interrupt Request (FIQ). takes interrupt request inputs which programmed vectored types. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted.
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FIQs have highest priority. more than request assigned FIQ, requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt. Vectored IRQs, which include interrupt requests that classified FIQs, have programmable interrupt priority. When more than interrupt assigned same priority occur simultaneously, connected lowest numbered channel will serviced first. requests from vectored IRQs produce signal processor. service routine start reading register from jumping address supplied that register.
7.5.1 Interrupt sources
Each peripheral device interrupt line connected have several interrupt flags. Individual interrupt flags also represent more than interrupt source. PORT0 PORT2 (total pins) regardless selected function, programmed generate interrupt rising edge, falling edge, both. Such interrupt request coming from PORT0 and/or PORT2 will combined with EINT3 interrupt requests.
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined.
General purpose controller
GPDMA AMBA compliant peripheral allowing selected LPC2361/62 peripherals have support. GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, memory-to-memory transactions. Each stream provides unidirectional serial transfers single source destination. example, bidirectional port requires stream transmit receive. source destination areas each either memory region peripheral, accessed through master.
7.7.1 Features
channels. Each channel support unidirectional transfer. GPDMA transfer data between SRAM peripherals such
SSP, interfaces.
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Single burst request signals. Each peripheral connected
GPDMA assert either burst request single request. burst size programming GPDMA.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory,
peripheral-to-peripheral transfers.
Scatter gather supported through linked lists. This means that
source destination areas have occupy contiguous areas memory.
Hardware channel priority. Each channel specific hardware priority.
channel highest priority channel lowest priority. requests from channels become active same time channel with highest priority serviced first.
slave programming interface. GPDMA programmed writing
control registers over slave interface.
master transferring data. This interface transfers data when
request goes active.
32-bit master width. Incrementing non-incrementing addressing source destination. Programmable burst size. burst size programmed more
efficiently transfer data. Usually burst size half size FIFO peripheral.
Internal four-word FIFO channel. Supports 8-bit, 16-bit, 32-bit wide transactions. interrupt processor generated completion when
error occurred.
Interrupt masking. error terminal count interrupt requests
masked.
interrupt status. error count interrupt status read
prior masking.
Fast general purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back well current state port pins. LPC2361/62 accelerated GPIO functions:
GPIO registers relocated local that fastest possible
timing achieved.
Mask registers allow treating sets port bits group, leaving other bits
unchanged.
GPIO registers byte half-word addressable. Entire port value written instruction.
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Additionally, PORT0 PORT2 (total pins) providing digital function programmed generate interrupt rising edge, falling edge, both. edge detection asynchronous, operate when clocks present such during Power-down mode. Each enabled interrupt used wake chip from Power-down mode.
7.8.1 Features
level clear registers allow single instruction clear number
bits port.
Direction control individual bits. default inputs after reset. Backward compatibility with other earlier devices maintained with legacy PORT0
PORT1 registers appearing original addresses APB.
Ethernet (LPC2362 only)
Ethernet block contains full featured Mbit/s Mbit/s Ethernet designed provide optimized performance through hardware acceleration. Features include generous suite control registers, half full duplex operation, flow control, control frames, hardware acceleration transmit retry, receive packet filtering wake-up activity. Automatic frame transmission reception with scatter-gather off-loads many operations from CPU. Ethernet block share dedicated subsystem that used access Ethernet SRAM Ethernet data, control, status information. other traffic LPC2362 takes place different subsystem, effectively separating Ethernet activity from rest system. Ethernet also access SRAM being used block. Ethernet block interfaces between off-chip Ethernet using Reduced (RMII) protocol on-chip Media Independent Interface Management (MIIM) serial bus.
7.9.1 Features
Ethernet standards support:
Supports Mbit/s Mbit/s devices including Base-T, Base-TX, Base-FX, Base-T4. Fully compliant with IEEE standard 802.3. Fully compliant with 802.3x full duplex flow control half duplex back pressure. Flexible transmit receive frame options. Virtual Local Area Network (VLAN) frame support.
Memory management:
Independent transmit receive buffers memory mapped shared SRAM. managers with scatter/gather arrays frame descriptors. Memory traffic optimized buffering pre-fetching.
Enhanced Ethernet features:
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Receive filtering. Multicast broadcast frame support both transmit receive. Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) transmit. Selectable automatic transmit frame padding. Over-length frame support both transmit receive allows length frames. Promiscuous receive mode. Automatic collision back-off frame retransmission. Includes power management clock switching. Wake-on-LAN power management support allows system wake-up: using receive filters magic frame detection filter.
Physical interface:
Attachment external chip through standard RMII interface. register access available MIIM interface.
7.10 interface
Universal Serial (USB) 4-wire that supports communication between host more 127) peripherals. Host Controller allocates bandwidth attached devices through token-based protocol. supports plugging dynamic configuration devices. transactions initiated Host Controller. LPC2361/62 interface includes device, Host, Controller. Details typical interfacing solutions found Section 11.1.
7.10.1 device controller
device controller enables Mbit/s data exchange with Host Controller. consists register interface, serial interface engine, endpoint buffer memory, controller. serial interface engine decodes data stream writes data appropriate endpoint buffer. status completed transfer error condition indicated status registers. interrupt also generated enabled. When enabled, controller transfers data between endpoint buffer RAM. 7.10.1.1 Features
Fully compliant with specification (full speed). Supports physical logical) endpoints with endpoint buffer RAM. Supports Control, Bulk, Interrupt Isochronous endpoints. Scalable realization endpoints time. Endpoint Maximum packet size selection maximum specification) software time.
Supports SoftConnect GoodLink features. While Suspend mode, LPC2361/62 enter reduced
power modes wake activity.
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Supports transfers with non-control endpoints. Allows dynamic switching between CPU-controlled modes. Double buffer implementation Bulk Isochronous endpoints.
7.10.2 host controller
host controller enables full- low-speed data exchange with devices attached bus. consists register interface, serial interface engine, controller. register interface complies with OHCI specification. 7.10.2.1 Features
OHCI compliant. downstream ports. Supports per-port power switching.
7.10.3 controller
(On-The-Go) supplement specification that augments capability existing mobile devices peripherals adding host functionality connection peripherals. Controller integrates Host Controller, device controller, master-only interface implement dual-role device functionality. dedicated interface controls external transceiver. 7.10.3.1 Features
Fully compliant with On-The-Go supplement Specification, Revision
1.0a.
Hardware support Host Negotiation Protocol (HNP). Includes programmable timer required Session Request Protocol
(SRP).
Supports transceiver compliant with Transceiver Specification
(CEA-2011), Rev. 1.0.
7.11 controller acceptance filters
Controller Area Network (CAN) serial communications protocol which efficiently supports distributed real-time control with very high level security. domain application ranges from high-speed networks cost multiplex wiring. block intended support multiple buses simultaneously, allowing device used gateway, switch, router among number buses industrial automotive applications. Each controller register structure similar SJA1000 PeliCAN Library block, 8-bit registers those devices have been combined 32-bit words allow simultaneous access environment. main operational difference that recognition received Identifiers, known terminology Acceptance Filtering, been removed from controllers centralized global Acceptance Filter.
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7.11.1 Features
controllers buses. Data rates Mbit/s each bus. 32-bit register access. Compatible with specification 2.0B, 11898-1. Global Acceptance Filter recognizes 11-bit 29-bit receive identifiers buses. Standard Identifiers.
Acceptance Filter provide FullCAN-style automatic reception selected FullCAN messages generate interrupts. 7.12 10-bit
LPC2361/62 contain ADC. single 10-bit successive approximation with channels.
7.12.1 Features
10-bit successive approximation ADC. Input multiplexing among pins. Power-down mode. Measurement range Vi(VREF). 10-bit conversion time 2.44 Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal. Individual result registers each channel reduce interrupt overhead.
7.13 10-bit
allows LPC2361/62 generate variable analog output. maximum output value Vi(VREF).
7.13.1 Features
10-bit Resistor string architecture Buffered output Power-down mode Selectable output drive
7.14 UARTs
LPC2361/62 each contain four UARTs. addition standard transmit receive data lines, UART1 also provides full modem control handshake interface. UARTs include fractional baud rate generator. Standard baud rates such 115200 achieved with crystal frequency above MHz.
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7.14.1 Features
Receive Transmit FIFOs. Register locations conform 16C550 industry standard. Receiver FIFO trigger points Built-in fractional baud rate generator covering wide range baud rates without need external crystals particular values. mechanism that enables software flow control implementation.
Fractional divider baud rate control, auto baud capabilities FIFO control UART1 equipped with standard modem interface signals. This module also provides
full support hardware flow control (auto-CTS/RTS).
UART3 includes IrDA mode support infrared communication. 7.15 serial controller
LPC2361/62 each contain controller. full duplex serial interface designed handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends bits bits data slave, slave always sends bits bits data master.
7.15.1 Features
Compliant with specification Synchronous, serial, full duplex communication Combined master slave Maximum data rate eighth input clock rate bits bits transfer
7.16 serial controller
LPC2361/62 each contain controllers. controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. Only single master single slave communicate during given data transfer. supports full duplex transfers, with frames bits bits data flowing from master slave from slave master. practice, often only these data flows carries meaningful data.
7.16.1 Features
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, National
Semiconductor Microwire buses
LPC2361_62_3
Synchronous serial communication Master slave operation 8-frame FIFOs both transmit receive 4-bit 16-bit frame transfers supported GPDMA
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7.17 I2C-bus serial controllers
LPC2361/62 each contain three I2C-bus controllers. I2C-bus bidirectional, inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver) transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. multi-master bus, controlled more than master connected I2C-bus implemented LPC2361/62 supports rates kbit/s (Fast I2C-bus).
7.17.1 Features
I2C0 standard compliant interface with open-drain pins. I2C1 I2C2 standard pins support powering individual
devices connected same lines.
Easy configure master, slave, master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. 7.18 I2S-bus serial controllers
I2S-bus provides standard communication interface digital audio applications. I2S-bus specification defines 3-wire serial using data line, clock line, word select signal. basic connection master, which always master, slave. interface LPC2361/62 provides separate transmit receive channel, each which operate either master slave.
7.18.1 Features
interface separate input/output channels each which operate master
slave mode.
Capable handling 8-bit, 16-bit, 32-bit word sizes. Mono stereo audio data supported. sampling frequency range from (16, 22.05, 44.1,
kHz.
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Configurable word select period master mode (separately input output). 8-word FIFO data buffers provided, transmit receive. Generates interrupt requests when buffer levels cross programmable boundary. requests, controlled programmable buffer levels. These connected GPDMA block.
Controls include reset, stop mute options separately input output. 7.19 General purpose 32-bit timers/external event counters
LPC2361/62 include four 32-bit Timer/Counters. Timer/Counter designed count cycles system derived clock externally-supplied clock. optionally generate interrupts perform other actions specified timer values, based four match registers. Timer/Counter also includes capture inputs trap timer value when input signal transitions, optionally generating interrupt.
7.19.1 Features
32-bit Timer/Counter with programmable 32-bit prescaler. Counter Timer operation. 32-bit capture channels timer, that take snapshot timer value
when input signal transitions. capture event also generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
four external outputs corresponding match registers, with following
capabilities: match. HIGH match. Toggle match. nothing match.
7.20 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2361/62. Timer designed count cycles system derived clock optionally switch pins, generate interrupts perform other actions when specified timer values occur, based seven match registers. function addition these features, based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (PWMMR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge
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controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when PWMMR0 match occurs. Three match registers used provide output with both edges controlled. Again, PWMMR0 match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
7.20.1 Features
LPC2361/62 block with Counter Timer operation (may
peripheral clock capture inputs clock source).
Seven match registers allow single edge controlled double edge
controlled outputs, both types. match registers also allow: Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs high beginning each cycle unless output constant low. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler. 7.21 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
7.21.1 Features
Internally resets chip periodically reloaded.
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Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) (Tcy(WDCLK) multiples Tcy(WDCLK) Internal oscillator (IRC), peripheral clock. This gives wide range potential timing choices Watchdog operation under different power reduction conditions. also provides ability from entirely internal source that dependent external crystal associated components wiring, increased reliability.
Watchdog Clock (WDCLK) source selected from clock,
7.22 battery
counters measuring time when system power optionally when off. uses little power Power-down mode. LPC2361/62, clocked separate 32.768 oscillator, programmable prescale divider based clock. Also, powered power supply pin, VBAT, which connected battery same supply used rest device. VBAT supplies power only battery RAM. These functions require minimum power operate, which supplied external battery.
7.22.1 Features
Measures passage time maintain calendar clock. Ultra power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Dedicated oscillator programmable prescaler from clock. Dedicated power supply connected battery main Periodic interrupts generated from increments field time registers,
selected fractional second values.
data SRAM powered VBAT. battery power supply isolated from rest chip. 7.23 Clocking power control
7.23.1 Crystal oscillators
LPC2361/62 includes three independent oscillators. These Main Oscillator, Internal oscillator, oscillator. Each oscillator used more than purpose required particular application. three clock sources chosen software drive ultimately CPU.
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Following reset, LPC2361/62 will operate from Internal oscillator until switched software. This allows systems operate without external crystal bootloader code operate known frequency. 7.23.1.1 Internal oscillator used clock source WDT, and/or clock that drives subsequently CPU. nominal frequency MHz. trimmed accuracy. Upon power-up chip reset, LPC2361/62 uses clock source. Software later switch other available clock sources. 7.23.1.2 Main oscillator main oscillator used clock source CPU, with without using PLL. main oscillator operates frequencies MHz. This frequency boosted higher frequency, maximum operating frequency, PLL. clock selected input PLLCLKIN. processor clock frequency referred CCLK elsewhere this document. frequencies PLLCLKIN CCLK same value unless active connected. clock frequency each peripheral selected individually referred PCLK. Refer Section 7.23.2 additional information. 7.23.1.3 oscillator oscillator used clock source and/or WDT. Also, oscillator used drive CPU.
7.23.2
accepts input clock frequency range MHz. input frequency multiplied high frequency, then divided down provide actual clock used block. input, range MHz, initially divided down value `N', which range 256. This input division provides wide range output frequencies from same input frequency. Following input divider multiplier. This multiply input divider output through Current Controlled Oscillator (CCO) value `M', range through 32768. resulting frequency must range MHz. multiplier works dividing output value then using phase-frequency detector compare divided output multiplier input. error value used adjust frequency. turned bypassed following chip Reset entering Power-down mode. enabled software only. program must configure activate PLL, wait Lock, then connect clock source.
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7.23.3 Wake-up timer
LPC2361/62 begins operation power-up when awakened from Power-down mode using oscillator clock source. This allows chip operation resume quickly. main oscillator needed application, software will need enable these features wait them stabilize before they used clock source. When main oscillator initially activated, wake-up timer allows software ensure that main oscillator fully functional before processor uses clock source starts execute instructions. This important power types Reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes wake-up Timer. Wake-up Timer monitors crystal oscillator check whether safe begin code execution. When power applied chip, when some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate VDD(3V3) ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g., capacitors), characteristics oscillator itself under existing ambient conditions.
7.23.4 Power control
LPC2361/62 supports variety power control features. There three special modes processor power reduction: Idle mode, Sleep mode, Power-down mode. clock rate also controlled needed changing clock sources, reconfiguring values, and/or altering clock divider value. This allows trade-off power versus processing speed based application requirements. addition, Peripheral Power Control allows shutting down clocks individual on-chip peripherals, allowing fine tuning power consumption eliminating dynamic power peripherals that required application. Each peripherals clock divider which provides even better power control. LPC2361/62 also implements separate power domain order allow turning power bulk device while maintaining operation small SRAM, referred battery RAM. 7.23.4.1 Idle mode Idle mode, execution instructions suspended until either Reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates dynamic power used processor itself, memory systems related controllers, internal buses. 7.23.4.2 Sleep mode Sleep mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Sleep mode logic levels chip pins remain static. output disabled powered down fast wake-up later.
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oscillator stopped because interrupts used wake-up source. automatically turned disconnected. CCLK clock dividers automatically reset zero. Sleep mode terminated normal operation resumed either Reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Sleep mode reduces chip power consumption very value. flash memory left Sleep mode, allowing very quick wake-up. wake-up Sleep mode, used before entering Sleep mode, code execution peripherals activities will resume after cycles expire. main external oscillator used, code execution will resume when 4096 cycles expire. customers need reconfigure clock dividers accordingly. 7.23.4.3 Power-down mode Power-down mode does everything that Sleep mode does, also turns oscillator flash memory. This saves more power, requires waiting resumption flash operation before execution code data access flash memory accomplished. wake-up Power-down mode, used before entering Power-down mode, will take start-up. After this cycles will expire before code execution then resumed code running from SRAM. meantime, flash wake-up timer then counts clock cycles make flash start-up time. When times out, access flash will allowed. customers need reconfigure clock dividers accordingly. 7.23.4.4 Power domains LPC2361/62 provides independent power domains that allow bulk device have power removed while maintaining operation battery RAM. LPC2361/62, pads powered (VDD(3V3)) pins, while VDD(DCDC)(3V3) powers on-chip DC-to-DC converter which turn provides power most peripherals. Depending LPC2361/62 application, design power options manage power consumption. first option assumes that power consumption concern design ties VDD(3V3) VDD(DCDC)(3V3) pins together. This approach requires only power supply both pads, CPU, peripherals. While this solution simple, does support powering down ring fly" while keeping peripherals alive. second option uses power supplies; supply pads (VDD(3V3)) dedicated supply (VDD(DCDC)(3V3)). Having on-chip DC-to-DC converter powered independently from ring enables shutting down power supply fly", while peripherals stay active.
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VBAT supplies power only battery RAM. These functions require minimum power operate, which supplied external battery. When rest chip functions stopped power removed, supply alarm output that used external hardware restore chip power resume operation.
7.24 System control
7.24.1 Reset
Reset four sources LPC2361/62: RESET pin, Watchdog reset, power-on reset, BrownOut Detection (BOD) circuit. RESET Schmitt trigger input pin. Assertion chip Reset source, once operating voltage attains usable level, starts Wake-up timer (see description Section 7.23.3 "Wake-up timer"), causing reset remain asserted until external Reset de-asserted, oscillator running, fixed number clocks have passed, flash controller completed initialization. When internal Reset removed, processor begins executing address which initially Reset vector mapped from Boot Block. that point, processor peripheral registers have been initialized predetermined values.
7.24.2 Brownout detection
LPC2361/62 includes 2-stage monitoring voltage VDD(3V3) pins. this voltage falls below 2.95 asserts interrupt signal Vectored Interrupt Controller. This signal enabled interrupt Interrupt Enable Register order cause interrupt; not, software monitor signal reading dedicated status register. second stage low-voltage detection asserts Reset inactivate LPC2361/62 when voltage VDD(3V3) pins falls below 2.65 This Reset prevents alteration flash operation various elements chip would otherwise become unreliable voltage. circuit maintains this reset down below which point power-on reset circuitry maintains overall Reset. Both 2.95 2.65 thresholds include some hysteresis. normal operation, this hysteresis allows 2.95 detection reliably interrupt, regularly executed event loop sense condition.
7.24.3 Code security (Code Read Protection CRP)
This feature LPC2361/62 allows user enable different levels security system that access on-chip flash JTAG restricted. When needed, invoked programming specific pattern into dedicated flash location. commands affected CRP. There three levels Code Read Protection. CRP1 disables access chip JTAG allows partial flash update (excluding flash sector using limited commands. This mode useful when required flash field updates needed sectors erased. CRP2 disables access chip JTAG only allows full flash erase update using reduced commands.
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Running application with level CRP3 selected fully disables access chip JTAG pins ISP. This mode effectively disables override using P2[10] pin, too. user's application provide needed) flash update mechanism using calls call reinvoke command enable flash update UART0.
CAUTION level three Code Read Protection (CRP3) selected, future factory testing performed device.
7.24.4
LPC2362 implements AHBs order allow Ethernet block operate without interference caused other system activity. primary AHB, referred AHB1, includes Vectored Interrupt Controller, GPDMA controller, interface, SRAM primarily intended USB. second AHB, referred AHB2, includes only Ethernet block associated SRAM. addition, bridge provided that allows secondary master AHB1, allowing expansion Ethernet buffer space into unused space memory residing AHB1. summary, masters with access AHB1 ARM7 itself, block, GPDMA function, Ethernet block (via bridge from AHB2). masters with access AHB2 ARM7 Ethernet block.
7.24.5 External interrupt inputs
LPC2361/62 include edge sensitive interrupt inputs combined with four level sensitive external interrupt inputs selectable functions. external interrupt inputs optionally used wake processor from Power-down mode.
7.24.6 Memory mapping control
memory mapping control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom Boot SRAM. This allows code running different memory spaces have control interrupts.
7.25 Emulation debugging
LPC2361/62 support emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs P2[0] P2[9]. This means that communication, timer, interface peripherals residing other pins available during development debugging phase they when application embedded system itself.
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
7.25.1 EmbeddedICE
EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access ARM7TDMI-S core present target system. core Debug Communication Channel (DCC) function built-in. allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. accessed co-processor program running ARM7TDMI-S core. allows JTAG port used sending receiving data without affecting normal program flow. data control registers mapped addresses EmbeddedICE logic. JTAG clock (TCK) must slower than clock (CCLK) JTAG interface operate.
7.25.2 Embedded trace
Since LPC2361/62 have significant amounts on-chip memories, possible determine processor core operating simply observing external pins. Eprovides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. software debugger allows configuration Eusing JTAG interface displays trace information that been captured. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external Trace Port Analyzer captures trace information under software debugger control. trace port broadcast Instruction trace information. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code traced because this restriction.
7.25.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real-time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using DCC, which present EmbeddedICE logic. LPC2361/62 contain specific configuration RealMonitor software programmed into on-chip memory.
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) Parameter supply voltage (3.3 Conditions core external rail -0.5 related pins tolerant pins; only valid when VDD(3V3) supply voltage present other pins Tstg Ptot(pack) supply current ground current storage temperature total power dissipation (per package) based package heat transfer, device power consumption human body model; pins
+4.6 +4.6 +4.6 +5.1 +6.0
Unit
VDD(DCDC)(3V3) DC-to-DC converter supply voltage (3.3 VDDA Vi(VBAT) Vi(VREF) analog supply voltage input voltage VBAT input voltage VREF analog input voltage input voltage
-0.5 -0.5 -0.5 -0.5
[2][3]
-0.5
VDD(3V3) +125
supply ground
Vesd
electrostatic discharge voltage
-2000
+2000
following applies limiting values: This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Including voltage outputs 3-state mode. exceed peak current limited times corresponding maximum current. Dependent package type. Human body model: equivalent discharging capacitor through series resistor.
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Static characteristics
Table Static characteristics Tamb commercial applications, unless otherwise specified. Symbol VDD(3V3) VDD(DCDC)(3V3) VDDA Vi(VBAT) Vi(VREF) Parameter supply voltage (3.3 DC-to-DC converter supply voltage (3.3 analog supply voltage input voltage VBAT input voltage VREF LOW-level input current pull-up HIGH-level input current VDD(3V3); pull-down OFF-state output current latch-up current VDD(3V3); pull-up/down -(0.5VDD(3V3)) (1.5VDD(3V3)); Vhys IOHS IOLS input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current VDD(3V3)
Conditions core external rail
Typ[1]
VDDA
Unit
Standard port pins, RESET, RTCK Ilatch
configured provide digital function output active
[3][4][5]
VDD(3V3)
VDD(3V3)
HIGH-level short-circuit output current LOW-level short-circuit output current pull-down current pull-up current VDDA VDD(3V3)
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
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Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol Parameter Conditions VDD(DCDC)(3V3) Tamb code Typ[1] Unit IDD(DCDC)act(3V3) active mode DC-to-DC converter supply current (3.3
while(1){}
executed from flash; peripherals enabled; PCLK CCLK CCLK CCLK peripherals enabled; PCLK CCLK CCLK CCLK peripherals enabled; PCLK CCLK CCLK CCLK
IDD(DCDC)pd(3V3)
power-down mode DC-to-DC converter supply current (3.3 active mode battery supply current
VDD(DCDC)(3V3) Tamb DC-to-DC converter DC-to-DC converter
[10] [10]
IBATact I2C-bus Vhys Oscillator pins Vi(XTAL1) Vo(XTAL2) Vi(RTCX1) Vo(RTCX2)
pins (P0[27] P0[28]) HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS VDD(3V3) input voltage XTAL1 output voltage XTAL2 input voltage RTCX1 output voltage RTCX2
0.7VDD(3V3)
0.3VDD(3V3)
0.5VDD(3V3)
[11]
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol pins VBUS Vth(rs)se OFF-state output current supply voltage differential input sensitivity voltage differential common mode voltage range single-ended receiver switching threshold voltage LOW-level output voltage low-/full-speed HIGH-level output voltage (driven) low-/full-speed |(D+) (D-)| includes range 5.25 Parameter Conditions Typ[1] Unit
0.18
Ctrans ZDRV
transceiver capacitance with series resistor; driver output steady state drive impedance driver which high-speed capable
[11]
44.1
Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. typically fails when Vi(VBAT) drops below Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded. Please also errata note mentioned errata sheet. Accounts voltage drop supply lines. Allowed long current limit does exceed maximum current allowed device. Minimum condition maximum condition
[10] VBAT. [11] VSS.
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Table static characteristics VDDA Tamb unless otherwise specified; frequency MHz. Symbol EL(adj) Rvsi Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance
Conditions: VSSA VDDA monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure Figure
[1][2][3] [1][4] [1][5] [1][6] [1][7]
Conditions
VDDA ±0.5
Unit
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
offset error (LSBideal)
VDDA VSSA 1024
002aac046
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
LPC23XX
AD0[y]SAMPLE
AD0[y]
Rvsi
VEXT
002aac610
Suggested interface LPC2361/62 AD0[y]
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Dynamic characteristics
Table Dynamic characteristics pins (full-speed) VDD(3V3), unless otherwise specified. Symbol tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise fall time matching output signal crossover voltage source interval source jitter differential transition transition receiver jitter next transition receiver jitter paired transitions width receiver must reject EOP; Figure must accept EOP; Figure
Conditions
13.8 13.7 +18.5
Unit
Figure Figure
-18.5
tEOPR2
width receiver
Characterized implemented production test. Guaranteed design.
Table Dynamic characteristics Tamb commercial applications; VDD(3V3) over specified ranges.[1] Symbol External clock fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL I2C-bus tf(o) interface tsu(SPI_MISO) SPI_MISO set-up time Tamb measured Master mode; Figure oscillator frequency clock cycle time clock HIGH time clock time clock rise time clock fall time pins (P0[27] P0[28]) output fall time Cb[3] Tcy(clk) Tcy(clk) 1000 Parameter Conditions Typ[2] Unit
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. capacitance from
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
10.1 Timing
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
External clock timing
tPERIOD crossover point differential data lines
crossover point extended
source width: tFEOPT differential data SE0/EOP skew tPERIOD tFDEOP
receiver width: tEOPR1, tEOPR2
002aab561
Differential data-to-EOP transition skew width
shifting edges
sampling edges
MOSI
MISO
tsu(SPI_MISO)
002aad326
MISO line set-up time Master mode
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Application information
11.1 Suggested interface solutions
VDD(3V3)
USB_UP_LED USB_CONNECT
LPC23XX
soft-connect switch
VBUS USB_D+ USB_D-
002aac578
USB-B connector
LPC2361/62 interface self-powered device
VDD(3V3)
LPC23XX
USB_UP_LED VBUS USB_D+ USB_D-
USB-B connector
002aac579
LPC2361/62 interface bus-powered device
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
RSTOUT
RESET_N ADR/PSW OE_N/INT_N SPEED SUSPEND
VBUS
Mini-AB connector
ISP1301
LPC2361/62
USB_SCL USB_SDA EINTn USB_D+ USB_D-
INT_N
002aad966
LPC2361/62 port configuration
USB_UP_LED USB_D+ USB_D-
USB-A connector
LPC2361/62
USB_PWRD USB_OVRCR USB_PPWR
VBUS
FLAGA
LM3526-L
OUTA
002aad967
LPC2361/62 host port configuration
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
USB_UP_LED
LPC2361/62
USB_CONNECT
USB_D+ USB_D- VBUS
VBUS USB-B connector
002aad968
LPC2361/62 device port configuration
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Package outline
LQFP100: plastic profile quad flat package; leads; body SOT407-1
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.75 0.45 0.08 0.08 1.15 0.85 1.15 0.85
16.25 16.25 15.75 15.75
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT407-1 REFERENCES 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-02-01 03-02-20
Package outline SOT407-1 (LQFP100)
LPC2361_62_3 B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Abbreviations
Table Acronym AMBA GPIO IrDA JTAG MIIM OHCI RMII UART Abbreviations Description Analog-to-Digital Converter Advanced High-performance Advanced Microcontroller Architecture Advanced Peripheral BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel Direct Memory Access Digital Signal Processing Packet Embedded Trace Macrocell General Purpose General Purpose Input/Output Infrared Data Association Joint Test Action Group Microcontroller Unit Media Independent Interface Media Independent Interface Management Open Host Controller Interface On-The-Go Physical Layer Phase-Locked Loop Pulse Width Modulator Reduced Media Independent Interface Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Revision history
Table Revision history Release date 20081111 Data sheet status Product data sheet Product data sheet Change notice Supersedes LPC2361_62_2 LPC2361_62_1 Document LPC2361_62_3 Modifications: LPC2361_62_2 Modifications:
Figure corrected memory map. Clarify Ethernet availability between devices throughout data sheet. Section Section 7.3: clarify SRAM size difference between devices. Table table note clarify Ethernet SRAM usage, changed orientation from landscape portrait. Table removed table note "Includes external resistors.". Table removed Rpu. Table added Table note Table Vhys, moved from column. Table IOHS, IOLS, updated Table note Figure removed figure note "VDD Product data sheet
20081016
LPC2361_62_1
20080804
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
15.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
15.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental
15.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V. SoftConnect trademark B.V. GoodLink trademark B.V.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Contents
General description Features Applications Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-chip flash programming memory On-chip SRAM Memory map. Interrupt controller 7.5.1 Interrupt sources. connect block General purpose controller 7.7.1 Features Fast general purpose parallel 7.8.1 Features Ethernet (LPC2362 only) 7.9.1 Features 7.10 interface 7.10.1 device controller 7.10.1.1 Features 7.10.2 host controller. 7.10.2.1 Features 7.10.3 controller 7.10.3.1 Features 7.11 controller acceptance filters 7.11.1 Features 7.12 10-bit 7.12.1 Features 7.13 10-bit 7.13.1 Features 7.14 UARTs 7.14.1 Features 7.15 serial controller. 7.15.1 Features 7.16 serial controller 7.16.1 Features 7.17 I2C-bus serial controllers. 7.17.1 Features 7.18 I2S-bus serial controllers 7.18.1 Features 7.19 General purpose 32-bit timers/external event counters 7.19.1 Features 7.20 Pulse width modulator 7.20.1 Features 7.21 Watchdog timer 7.21.1 Features 7.22 battery 7.22.1 Features 7.23 Clocking power control 7.23.1 Crystal oscillators 7.23.1.1 Internal oscillator 7.23.1.2 Main oscillator 7.23.1.3 oscillator. 7.23.2 PLL. 7.23.3 Wake-up timer 7.23.4 Power control 7.23.4.1 Idle mode 7.23.4.2 Sleep mode 7.23.4.3 Power-down mode 7.23.4.4 Power domains. 7.24 System control 7.24.1 Reset 7.24.2 Brownout detection 7.24.3 Code security (Code Read Protection CRP) 7.24.4 7.24.5 External interrupt inputs 7.24.6 Memory mapping control 7.25 Emulation debugging. 7.25.1 EmbeddedICE 7.25.2 Embedded trace. 7.25.3 RealMonitor Limiting values Static characteristics Dynamic characteristics 10.1 Timing Application information 11.1 Suggested interface solutions Package outline Abbreviations Revision history Legal information 15.1 Data sheet status 15.2 Definitions 15.3 Disclaimers. 15.4 Trademarks
continued
LPC2361_62_3
B.V. 2008. rights reserved.
Product data sheet
Rev. November 2008
Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit
Contact information. Contents
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2008.
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more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: November 2008 Document identifier: LPC2361_62_3
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