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16/32-bit microcontrollers; ISP/IAP flash with CAN, 10-bit external me


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LPC2292/LPC2294
16/32-bit microcontrollers; ISP/IAP flash with CAN, 10-bit external memory interface
Rev. December 2008 Product data sheet
LPC2292/LPC2294 microcontrollers based 16/32-bit ARM7TDMI-S with real-time emulation embedded trace support, together with embedded high-speed flash memory. 128-bit wide memory interface unique accelerator architecture enable 32-bit code execution maximum clock rate. critical code size applications, alternative 16-bit Thumb mode reduces code more than with minimal performance penalty. With their 144-pin package, power consumption, various 32-bit timers, 8-channel 10-bit ADC, (LPC2294) advanced channels, channels nine external interrupt pins these microcontrollers particularly suitable automotive industrial control applications well medical systems fault-tolerant maintenance buses. number available GPIOs ranges from (with external memory) through (single-chip). With wide range additional serial communications interfaces, they also suited communication gateways protocol converters well many other general-purpose applications. Remark: Throughout data sheet, term LPC2292/LPC2294 will apply devices with without suffix. suffixes will used differentiate from other devices only when necessary.
Features
features brought LPC2292/LPC2294/01 devices
Fast GPIO ports enable port toggling times faster than original device. They also allow port read time regardless function. Dedicated result registers ADC(s) reduce interrupt overhead. pads tolerant when configured digital function(s). UART0/1 include fractional baud rate generator, auto-bauding capabilities handshake flow-control fully implemented hardware. Buffered serial controller supporting SPI, 4-wire SSI, Microwire formats. programmable data length master mode enhancement. Diversified Code Read Protection (CRP) enables different security levels implemented. This feature available LPC2292/LPC2294/00 devices well. General purpose timers operate external event counters.
features common devices
16/32-bit ARM7TDMI-S microcontroller LQFP144 package.
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
on-chip static on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed operation. In-System Programming/In-Application Programming (ISP/IAP) on-chip bootloader software. Single flash sector full chip erase programming EmbeddedICE-RT Embedded Trace interfaces offer real-time debugging with on-chip RealMonitor software well high-speed real-time tracing instruction execution. Two/four (LPC2292/LPC2294) interconnected interfaces with advanced acceptance filters. Additional serial interfaces include UARTs (16C550), Fast I2C-bus (400 kbit/s) SPIs. Eight channel 10-bit with conversion time 2.44 32-bit timers (with four capture four compare channels), unit (six outputs), Real-Time Clock (RTC), watchdog. Vectored Interrupt Controller (VIC) with configurable priorities vector addresses. Configurable external memory interface with four banks, each 8/16/32-bit data width. general purpose pins tolerant). nine edge/level sensitive external interrupt pins available. maximum clock available from programmable on-chip with settling time on-chip crystal oscillator should have operating range MHz. Power saving modes include Idle Power-down. Processor wake-up from Power-down mode external interrupt. Individual enable/disable peripheral functions power optimization. Dual power supply: operating voltage range 1.65 1.95 (1.8 0.15 power supply range (3.3 with tolerant pads.
Ordering information
Table Ordering information Package Name LPC2292FBD144 LPC2292FBD144/00 LPC2292FBD144/01 LPC2292FET144/00 LPC2292FET144/01 LPC2292FET144/G LQFP144 LQFP144 LQFP144 TFBGA144 TFBGA144 TFBGA144 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic thin fine-pitch ball grid array package; balls; body plastic thin fine-pitch ball grid array package; balls; body plastic thin fine-pitch ball grid array package; balls; body Version SOT486-1 SOT486-1 SOT486-1 SOT569-2 SOT569-2 SOT569-2 Type number
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Ordering information .continued Package Name Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT486-1 SOT486-1 SOT486-1 LQFP144 LQFP144 LQFP144
Table
Type number LPC2294HBD144 LPC2294HBD144/00 LPC2294HBD144/01
Ordering options
Table Ordering options Flash memory Fast GPIO/ SSP/ Enhanced UART, ADC, Timer Temperature range Type number
LPC2292FBD144
channels channels channels channels channels channels channels channels channels
+125 +125 +125
LPC2292FBD144/00 LPC2292FBD144/01 LPC2292FET144/00 LPC2292FET144/01 LPC2292FET144/G LPC2294HBD144
LPC2294HBD144/00 LPC2294HBD144/01
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Block diagram
TMS(1) TDI(1) TRST(1) TCK(1) TDO(1) XTAL2 XTAL1 RESET
EMULATION TRACE MODULE
LPC2292 LPC2294
HIGH-SPEED GPIO(4) PINS TOTAL
TEST/DEBUG INTERFACE
system clock
SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER
ARM7TDMI-S
BRIDGE
ARM7 local INTERNAL SRAM CONTROLLER INTERNAL FLASH CONTROLLER
AMBA (Advanced High-performance Bus)
DECODER BRIDGE DIVIDER CS0(2) A0(2) BLS3 BLS0(2) WE(2) D0(2) SCK1 SPI1/SSP(4) SERIAL INTERFACE MOSI1 MISO1 SSEL1
SRAM
FLASH
EXTERNAL MEMORY CONTROLLER
EINT3 EINT0
EXTERNAL INTERRUPTS
(advanced peripheral bus) I2C-BUS SERIAL INTERFACE
CAP0 CAP1 MAT0 MAT1
CAPTURE/ COMPARE TIMER 0/TIMER
AIN3 AIN0 CONVERTER AIN7 AIN4 P0[30:0] P1[31:16], P1[1:0] P2[31:0] P3[31:0] PWM6 PWM1 PWM0 REAL-TIME CLOCK GENERAL PURPOSE UART0/UART1 SPI0 SERIAL INTERFACE
SCK0 MOSI0 MISO0 SSEL0 TXD0, TXD1 RXD0, RXD1 DSR1, CTS1, DCD1, TD2, RD2, TD4, TD3(3) RD4, RD3(3)
SYSTEM CONTROL
WATCHDOG TIMER
002aad184
When test/debug interface used, GPIO/other functions sharing these pins available. Pins shared with GPIO. Available LPC2294 only. interface high-speed GPIO available LPC2292/2294/01 only.
Block diagram
LPC2292_2294_7 B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Pinning information
Pinning
002aad185
LPC2292FBD LPC2294HBD(1)
configuration identical devices with without suffixes.
LQFP144 pinning
ball index area
LPC2292FET144(1)
002aad191
Transparent view
configuration identical devices with without suffixes.
TFBGA144 pinning
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
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Product data sheet Rev. December 2008
B.V. 2008. rights reserved. LPC2292_2294_7
Semiconductors
Table
Ball allocation VDDA(1V8) P1[27]/ P1[28]/ XTAL2 P2[21]/ VSSA(PLL) P2[18]/ P2[19]/ P2[14]/ P2[15]/ P1[29]/ P2[12]/ P2[11]/ P0[20]/ MAT1[3]/ SSEL1/ EINT3 P0[19]/ MAT1[2]/ MOSI1/ CAP1[2] P0[18]/ CAP1[3]/ MISO1/ MAT1[3] P2[10]/ VDD(3V3) P2[7]/D7 P2[6]/D6 VDD(3V3) VDD(1V8) P2[3]/D3 P2[4]/D4
Column P2[22]/ VDD(3V3)
P0[21]/ PWM5/ CAP1[3] P0[24]/
XTAL1
VSSA
RESET
P2[16]/
P2[13]/
P2[9]/D9
P2[5]/D5
P2[2]/D2
P2[1]/D1
VDD(3V3)
P1[19]/ TRACE PKT3 P2[24]/
P0[23]/
P0[22]/ CAP0[0]/ MAT0[0]
P2[20]/
P2[17]/
P2[8]/D8
P1[30]/
P1[20]/ TRACE SYNC P2[0]/D0
P0[17]/ CAP1[2]/ SCK1/ MAT1[2] P3[30]/ BLS1
16/32-bit microcontrollers with external memory interface
P2[25]/
P2[23]
P0[16]/ EINT0/ MAT0[2]/ CAP0[2] P3[31]/ BLS0 P0[14]/ DCD1/ EINT1 P0[13]/ DTR1/ MAT1[1] P3[3]/A3
P0[15]/ RI1/ EINT2 P1[21]/ PIPE STAT0
P2[27]/ D27/ BOOT1 P2[29]/ P0[25]/
P1[18]/ TRACE PKT2 P2[28]/
VDDA(3V3)
P2[26]/ D26/ BOOT0
VDD(3V3)
P2[30]/ P2[31]/ D30/AIN4 D31/AIN5 P0[27]/ AIN0/ CAP0[1]/ MAT0[1] P3[29]/ BLS2/ AIN6 VDD(3V3) P1[17]/ TRACE PKT1 P3[28]/ BLS3/ AIN7 P3[22]/ P3[20]/ P0[1]/ RXD0/ PWM3/ EINT0 P3[14]/ P1[25]/ EXTIN0 P3[11]/
P1[0]/CS0 P3[0]/A0
P1[1]/OE
LPC2292/LPC2294
P1[22]/ PIPE STAT1 P1[23]/ PIPE STAT2 P0[10]/ RTS1/ CAP1[0]
P3[2]/A2
P3[1]/A1
P0[28]/ AIN1/ CAP0[2]/ MAT0[2] P3[27]/
P0[11]/ CTS1/ CAP1[1]
P0[12]/ DSR1/ MAT1[0] P3[4]/A4
P3[26]/
VDD(3V3)
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Table P0[29]/ AIN2/ CAP0[3]/ MAT0[3] P3[25]/ Ball allocation .continued P0[30]/ AIN3/ EINT3/ CAP0[0] P3[24]/ P1[16]/ TRACE PKT0 VDD(3V3) P0[0]/ TXD0/ PWM1 P1[31]/ TRST P3[19]/ P0[2]/ SCL/ CAP0[0] VDD(3V3) P3[15]/ P0[4]/ SCK0/ CAP0[1] P0[3]/ SDA/ MAT0[0]/ EINT1 VDD(3V3) P3[12]/ P1[24]/ TRACE P0[7]/ SSEL0/ PWM2/ EINT2 P0[6]/ MOSI0/ CAP0[2] P0[8]/ TXD1/ PWM4 P3[7]/A7 P0[9]/ RXD1/ PWM6/ EINT3 P3[5]/A5
Product data sheet Rev. December 2008
B.V. 2008. rights reserved. LPC2292_2294_7
Semiconductors
Column
P3[18]/
P3[16]/
P3[13]/
P3[9]/A9
VDD(1V8)
P3[23]/ A23/ XCLK
P3[21]/
P3[17]/
P1[26]/ RTCK
P0[5]/ MISO0/ MAT0[1]
P3[10]/
P3[8]/A8
P3[6]/A6
16/32-bit microcontrollers with external memory interface
LPC2292/LPC2294
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
description
Table Symbol P0[0] P0[31] description (LQFP) (TFBGA)[1] Type Description Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins port available. P0[0]/TXD0/ PWM1 P0[1]/RXD0/ PWM3/EINT0 42[2] 49[4] L4[2] K6[4] P0[2]/SCL/ CAP0[0] P0[3]/SDA/ MAT0[0]/EINT1 50[5] L6[5] 58[5] M8[5] P0[4]/SCK0/ CAP0[1] P0[5]/MISO0/ MAT0[1] P0[6]/MOSI0/ CAP0[2] P0[7]/SSEL0/ PWM2/EINT2 59[2] L8[2] 61[2] N9[2] 68[2] N11[2] 69[4] M11[4] P0[8]/TXD1/ PWM4 P0[9]/RXD1/ PWM6/EINT3 75[2] 76[4] L12[2] L13[4] P0[10]/RTS1/ CAP1[0] P0[11]/CTS1/ CAP1[1] 78[2] 83[2] K11[2] J12[2] TXD0 Transmitter output UART0. PWM1 Pulse Width Modulator output RXD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input I2C-bus clock input/output. Open-drain output (for I2C-bus compliance). CAP0[0] Capture input Timer channel I2C-bus data input/output. Open-drain output (for I2C-bus compliance). MAT0[0] Match output Timer channel EINT1 External interrupt input. SCK0 Serial clock SPI0. clock output from master input slave. CAP0[1] Capture input Timer channel MISO0 Master Slave SPI0. Data input master data output from slave. MAT0[1] Match output Timer channel MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0[2] Capture input Timer channel SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. TXD1 Transmitter output UART1. PWM4 Pulse Width Modulator output RXD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input. RTS1 Request Send output UART1. CAP1[0] Capture input Timer channel CTS1 Clear Send input UART1. CAP1[1] Capture input Timer channel
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table Symbol
description .continued (LQFP) 84[2] (TFBGA)[1] J13[2] Type 85[2] H10[2] 92[4] G10[4] Description DSR1 Data Ready input UART1. MAT1[0] Match output Timer channel CAN4 receiver input (LPC2294 only). DTR1 Data Terminal Ready output UART1. MAT1[1] Match output Timer channel CAN4 transmitter output (LPC2294 only). DCD1 Data Carrier Detect input UART1. EINT1 External interrupt input. Note: this while RESET forces on-chip bootloader take over control part after reset.
P0[12]/DSR1/ MAT1[0]/RD4
P0[13]/DTR1/ MAT1[1]/TD4
P0[14]/DCD1/ EINT1
P0[15]/RI1/ EINT2 P0[16]/EINT0/ MAT0[2]/ CAP0[2]
99[4] 100[4]
E11[4] E10[4]
Ring Indicator input UART1. EINT2 External interrupt input. EINT0 External interrupt input. MAT0[2] Match output Timer channel CAP0[2] Capture input Timer channel CAP1[2] Capture input Timer channel SCK1 Serial Clock SPI1/SSP[3]. clock output from master input slave. MAT1[2] Match output Timer channel CAP1[3] Capture input Timer channel MISO1 Master Slave SPI1/SSP[3]. Data input master data output from slave. MAT1[3] Match output Timer channel MAT1[2] Match output Timer channel MOSI1 Master Slave SPI1/SSP[3]. Data output from master data input slave. CAP1[2] Capture input Timer channel MAT1[3] Match output Timer channel SSEL1 Slave Select SPI1/SSP[3]. Selects interface slave. EINT3 External interrupt input. PWM5 Pulse Width Modulator output CAN3 receiver input (LPC2294 only). CAP1[3] Capture input Timer channel CAN3 transmitter output (LPC2294 only). CAP0[0] Capture input Timer channel MAT0[0] Match output Timer channel CAN2 receiver input. CAN2 transmitter output. CAN1 receiver input.
P0[17]/CAP1[2]/ 101[2] SCK1/MAT1[2]
D13[2]
P0[18]/CAP1[3]/ MISO1/MAT1[3]
121[2]
D8[2]
P0[19]/MAT1[2]/ MOSI1/CAP1[2]
122[2]
C8[2]
P0[20]/MAT1[3]/ SSEL1/EINT3
123[4]
B8[4]
P0[21]/PWM5/ RD3/CAP1[3]
4[2]
C1[2]
P0[22]/TD3/ CAP0[0]/ MAT0[0] P0[23]/RD2 P0[24]/TD2 P0[25]/RD1
5[2]
D4[2]
6[2] 8[2] 21[2]
D3[2] D1[2] H1[2]
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table Symbol
description .continued (LQFP) 23[6] (TFBGA)[1] H3[6] Type 25[6] J1[6] 32[6] L1[6] 33[6] L2[6] Description AIN0 ADC, input This analog input always connected pin. CAP0[1] Capture input Timer channel MAT0[1] Match output Timer channel AIN1 ADC, input This analog input always connected pin. CAP0[2] Capture input Timer channel MAT0[2] Match output Timer channel AIN2 ADC, input This analog input always connected pin. CAP0[3] Capture input Timer Channel MAT0[3] Match output Timer channel AIN3 ADC, input This analog input always connected pin. EINT3 External interrupt input. CAP0[0] Capture input Timer channel Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins through port available. LOW-active Chip Select signal. (Bank addresses range 0x8000 0000 0x80FF FFFF) LOW-active Output Enable signal. TRACEPKT0 Trace Packet, Standard port with internal pull-up. TRACEPKT1 Trace Packet, Standard port with internal pull-up. TRACEPKT2 Trace Packet, Standard port with internal pull-up. TRACEPKT3 Trace Packet, Standard port with internal pull-up. TRACESYNC Trace Synchronization. Standard port with internal pull-up. Note: this while RESET LOW, enables pins P1[25:16] operate Trace port after reset.
P0[27]/AIN0/ CAP0[1]/ MAT0[1]
P0[28]/AIN1/ CAP0[2]/ MAT0[2]
P0[29]/AIN2/ CAP0[3]/ MAT0[3]
P0[30]/AIN3/ EINT3/CAP0[0]
P1[0] P1[31]
P1[0]/CS0 P1[1]/OE P1[16]/ TRACEPKT0 P1[17]/ TRACEPKT1 P1[18]/ TRACEPKT2 P1[19]/ TRACEPKT3 P1[20]/ TRACESYNC
91[7] 90[7] 34[7] 24[7] 15[7] 7[7] 102[7]
G11[7] G13[7] L3[7] H4[7] F2[7] D2[7] D12[7]
P1[21]/ PIPESTAT0 P1[22]/ PIPESTAT1 P1[23]/ PIPESTAT2 P1[24]/ TRACECLK
95[7] 86[7] 82[7] 70[7]
F11[7] H11[7] J11[7] L11[7]
PIPESTAT0 Pipeline Status, Standard port with internal pull-up. PIPESTAT1 Pipeline Status, Standard port with internal pull-up. PIPESTAT2 Pipeline Status, Standard port with internal pull-up. TRACECLK Trace Clock. Standard port with internal pull-up.
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table Symbol
description .continued (LQFP) 60[7] 52[7] (TFBGA)[1] K8[7] N6[7] Type Description EXTIN0 External Trigger Input. Standard with internal pull-up. RTCK Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional with internal pull-up. Note: this while RESET LOW, enables pins P1[31:26] operate Debug port after reset.
P1[25]/EXTIN0 P1[26]/RTCK
P1[27]/TDO P1[28]/TDI P1[29]/TCK
144[7] 140[7] 126[7]
B2[7] A3[7] A7[7]
Test Data JTAG interface. Test Data JTAG interface. Test Clock JTAG interface. This clock must slower than clock (CCLK) JTAG interface operate. Test Mode Select JTAG interface. TRST Test Reset JTAG interface. Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line
B.V. 2008. rights reserved.
P1[30]/TMS P1[31]/TRST P2[0] P2[31]
113[7] 43[7]
D10[7] M4[7]
P2[0]/D0 P2[1]/D1 P2[2]/D2 P2[3]/D3 P2[4]/D4 P2[5]/D5 P2[6]/D6 P2[7]/D7 P2[8]/D8 P2[9]/D9 P2[10]/D10 P2[11]/D11 P2[12]/D12 P2[13]/D13 P2[14]/D14 P2[15]/D15 P2[16]/D16 P2[17]/D17 P2[18]/D18 P2[19]/D19 P2[20]/D20 P2[21]/D21 P2[22]/D22 P2[23]/D23
LPC2292_2294_7
98[7] 105[7] 106[7] 108[7] 109[7] 114[7] 115[7] 116[7] 117[7] 118[7] 120[7] 124[7] 125[7] 127[7] 129[7] 130[7] 131[7] 132[7] 133[7] 134[7] 136[7] 137[7] 1[7] 10[7]
E12[7] C12[7] C11[7] B12[7] A13[7] C10[7] B10[7] A10[7] D9[7] C9[7] A9[7] A8[7] B7[7] C7[7] A6[7] B6[7] C6[7] D6[7] A5[7] B5[7] D5[7] A4[7] A1[7] E3[7]
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table Symbol P2[24]/D24 P2[25]/D25
description .continued (LQFP) 11[7] 12[7] 13[7] (TFBGA)[1] E2[7] E1[7] F4[7] Type Description External memory data line External memory data line External memory data line BOOT0 While RESET low, together with BOOT1 controls booting internal operation. Internal pull-up ensures high state left unconnected. External memory data line BOOT1 While RESET low, together with BOOT0 controls booting internal operation. Internal pull-up ensures high state left unconnected. BOOT1:0 selects 8-bit memory boot. BOOT1:0 selects 16-bit memory boot. BOOT1:0 selects 32-bit memory boot. BOOT1:0 selects internal flash memory.
P2[26]/D26/ BOOT0
P2[27]/D27/ BOOT1
16[7]
F1[7]
P2[28]/D28 P2[29]/D29 P2[30]/D30/ AIN4 P2[31]/D31/ AIN5 P3[0] P3[31]
17[7] 18[7] 19[6]
G2[7] G1[7] G3[6]
External memory data line External memory data line External memory data line AIN4 ADC, input This analog input always connected pin. External memory data line AIN5 ADC, input This analog input always connected pin. Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line
B.V. 2008. rights reserved.
20[6]
G4[6]
P3[0]/A0 P3[1]/A1 P3[2]/A2 P3[3]/A3 P3[4]/A4 P3[5]/A5 P3[6]/A6 P3[7]/A7 P3[8]/A8 P3[9]/A9 P3[10]/A10 P3[11]/A11 P3[12]/A12 P3[13]/A13 P3[14]/A14 P3[15]/A15 P3[16]/A16
LPC2292_2294_7
89[7] 88[7] 87[7] 81[7] 80[7] 74[7] 73[7] 72[7] 71[7] 66[7] 65[7] 64[7] 63[7] 62[7] 56[7] 55[7] 53[7]
G12[7] H13[7] H12[7] J10[7] K13[7] M13[7] N13[7] M12[7] N12[7] M10[7] N10[7] K9[7] L9[7] M9[7] K7[7] L7[7] M7[7]
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table Symbol P3[17]/A17 P3[18]/A18 P3[19]/A19 P3[20]/A20 P3[21]/A21 P3[22]/A22
description .continued (LQFP) 48[7] 47[7] 46[7] 45[7] 44[7] 41[7] 40[7] 36[7] 35[7] 30[7] 29[7] 28[6] (TFBGA)[1] N5[7] M5[7] L5[7] K5[7] N4[7] K4[7] N3[7] M2[7] M1[7] K2[7] K1[7] J4[6] Type 27[6] J3[6] 97[7] 96[7] 22[7] 135[8] E13[7] F10[7] H2[7] C5[8] Description External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line XCLK Clock output. LOW-active Chip Select signal. (Bank addresses range 0x8300 0000 0x83FF FFFF) LOW-active Chip Select signal. (Bank addresses range 0x8200 0000 0x82FF FFFF) LOW-active Chip Select signal. (Bank addresses range 0x8100 0000 0x81FF FFFF) LOW-active Write enable signal. BLS3 LOW-active Byte Lane Select signal (Bank AIN7 ADC, input This analog input always connected pin. BLS2 LOW-active Byte Lane Select signal (Bank AIN6 ADC, input This analog input always connected pin. BLS1 LOW-active Byte Lane Select signal (Bank BLS0 LOW-active Byte Lane Select signal (Bank TD1: CAN1 transmitter output. External Reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Ground: reference.
P3[23]/A23/ XCLK P3[24]/CS3 P3[25]/CS2 P3[26]/CS1 P3[27]/WE P3[28]/BLS3/ AIN7 P3[29]/BLS2/ AIN6 P3[30]/BLS1 P3[31]/BLS0 RESET
XTAL1 XTAL2
142[9] 141[9] 103, 107, 111,
C3[9] B3[9] L10, K12, F13, D11, B13, B11,
VSSA
Analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. core power supply: This power supply voltage internal circuitry.
B.V. 2008. rights reserved.
VSSA(PLL)
VDD(1V8)
LPC2292_2294_7
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table Symbol VDDA(1V8)
description .continued (LQFP) (TFBGA)[1] Type Description Analog core power supply: This power supply voltage internal circuitry. This should nominally same voltage VDD(1V8) should isolated minimize noise error. power supply: This power supply voltage ports.
VDD(3V3)
K10, 104, 112, F12, C13, A11,
VDDA(3V3)
Analog power supply: This should nominally same voltage VDD(3V3) should isolated minimize noise error.
LPC2294 only. tolerant providing digital functions with levels hysteresis slew rate control. interface available LPC2292/2294/01 only. tolerant providing digital functions with levels hysteresis slew rate control. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than Open-drain tolerant digital I2C-bus specification compatible pad. requires external pull-up provide output functionality. Open-drain configuration applies output functions this pin. tolerant providing digital (with levels hysteresis slew rate control) analog input function. configured digital input function, this utilizes built-in glitch filter that blocks pulses shorter than When configured input, digital section disabled. tolerant with built-in pull-up resistor providing digital functions with levels hysteresis slew rate control. pull-up resistor's value ranges from tolerant providing digital input (with levels hysteresis) function only. provides special analog functionality.
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Functional description
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based RISC principles, instruction related decode mechanism much simpler than those microprogrammed CISC. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit 16-bit Thumb
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-chip flash program memory
LPC2292/LPC2294 incorporate flash memory system respectively. This memory used both code data storage. Programming flash memory accomplished several ways. programmed System serial port. application program also erase and/or program flash while application running, allowing great degree flexibility data storage field firmware upgrades, etc. When on-chip bootloader used, flash memory available user code. LPC2292/LPC2294 flash memory provides minimum 100000 erase/write cycles years data retention. On-chip bootloader revision 1.64) provides Code Read Protection (CRP) LPC2292/LPC2294 on-chip flash memory. When enabled, JTAG debug port, external memory boot commands accessing either on-chip flash memory disabled. However, flash erase command executed time matter whether off). Removal achieved erasure full on-chip user flash. With off, full access chip JTAG and/or restored.
LPC2292_2294_7 B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
On-chip SRAM
On-chip SRAM used code and/or data storage. SRAM accessed 8-bit, 16-bit, 32-bit. LPC2292/LPC2294 provide SRAM.
Memory
LPC2292/LPC2294 memory maps incorporate several distinct regions, shown Figure addition, interrupt vectors re-mapped allow them reside either flash memory (the default) on-chip static RAM. This described Section 6.19 "System control".
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
RESERVED ADDRESS SPACE
0xC000 0000
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY)
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4000 4000 0x4000 3FFF ON-CHIP STATIC 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0004 0000 0x0003 FFFF ON-CHIP FLASH MEMORY 0x0000 0000
002aaa754
LPC2292/LPC2294 memory
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Interrupt controller
accepts interrupt request inputs categorizes them Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt. Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active.
6.5.1 Interrupt sources
Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected VIC, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core Timer Timer UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only EmbeddedICE, DbgCommRx EmbeddedICE, DbgCommTx Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Line Status (RLS) Transmit Holding Register Empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Auto-baud time-out (ABTO)[1] auto-baud (ABEO)[1] channel
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Interrupt sources .continued Flag(s) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) Auto-baud time-out (ABTO)[1] auto-baud (ABEO)[1] channel
Table Block UART1
PWM0 SPI0 System Control
Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) (state change) SPIF, MODF Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt (EINT0) External Interrupt (EINT1) External Interrupt (EINT2) External Interrupt (EINT3)
28,29
SPI1 SSP[1] SPIF, MODF TXRIS, RXRIS, RTRIS, RORRIS
ORed Acceptance Filter CAN1/2 CAN2/3 (LPC2294 only) reserved CAN1/2 CAN3/4 (LPC2294 only)
interface UART0/1 auto-baud control available LPC2292/2294/01 only.
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined.
External memory controller
external Static Memory Controller module which provides interface between system external (off-chip) memory devices. provides support four independently configurable memory banks each with byte lane enable control) simultaneously. Each memory bank capable supporting SRAM, ROM, flash EPROM, burst memory, some external devices. Each memory bank 8-bit, 16-bit, 32-bit wide.
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
General purpose parallel (GPIO) Fast
Device pins that connected specific peripheral function controlled parallel registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins.
6.8.1 Features
Bit-level clear registers allow single instruction clear number
bits port.
Direction control individual bits. Separate control output clear. default inputs after reset.
6.8.2 Features added with Fast GPIO registers available LPC2292/LPC2294/01 only
Fast GPIO registers relocated local fastest possible
timing, enabling port toggling times faster than earlier LPC2000 devices.
Mask registers allow treating sets port bits group, leaving other bits
unchanged.
Fast GPIO registers byte addressable. Entire port value written instruction. Ports accessible either legacy group registers (GPIOs) group
registers providing accelerated port access (Fast GPIOs).
10-bit
LPC2292/LPC2294 each contain single 10-bit successive approximation with four multiplexed channels.
6.9.1 Features
Measurement range Capable performing more than 400000 10-bit samples second. Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal.
6.9.2 features available LPC2292/LPC2294/01 only
Every analog input dedicated result register reduce interrupt overhead. Every analog input generate interrupt once conversion completed. pads tolerant when configured digital function(s).
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
6.10 controllers acceptance filter
LPC2292/LPC2294 each contain two/four controllers. serial communications protocol which efficiently supports distributed real-time control with very high level security. domain application ranges from high-speed networks cost multiplex wiring.
6.10.1 Features
Data rates Mbit/s each bus. 32-bit register access. Compatible with specification 2.0B, 11898-1. Global Acceptance Filter recognizes 11-bit 29-bit identifiers buses. Acceptance Filter provide FullCAN-style automatic reception selected Standard identifiers.
6.11 UARTs
LPC2292/LPC2294 each contain UARTs. addition standard transmit receive data lines, UART1 also provides full modem control handshake interface.
6.11.1 Features
Receive Transmit FIFOs. Register locations conform 16C550 industry standard. Receiver FIFO trigger points Built-in fractional baud rate generator covering wide range baud rates without need external crystals particular values. control both UARTs.
Transmission FIFO control enables implementation software (XON/XOFF) flow UART1 equipped with standard modem interface signals. This module also
provides full support hardware flow control (auto-CTS/RTS).
6.11.2 UART features available LPC2292/LPC2294/01 only
Compared previous LPC2000 microcontrollers, UARTs LPC2292/LPC2294/01 introduce fractional baud rate generator both UARTs, enabling these microcontrollers achieve standard baud rates such 115200 with crystal frequency above MHz. addition, auto-CTS/RTS flow-control functions fully implemented hardware.
Fractional baud rate generator enables standard baud rates such 115200
achieved with crystal frequency above MHz.
Auto-bauding. Auto-CTS/RTS flow-control fully implemented hardware. 6.12 I2C-bus serial controller
I2C-bus bidirectional, inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver transmitter with
LPC2292_2294_7 B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master bus, controlled more than master connected I2C-bus implemented LPC2292/LPC2294 supports rate kbit/s (Fast I2C-bus).
6.12.1 Features
Compliant with standard I2C-bus interface. Easy configure master, slave, master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. 6.13 serial controller
LPC2292/LPC2294 each contain SPIs. full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master.
6.13.1 Features
Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex communication. Combined master slave. Maximum data rate input clock rate.
6.13.2 Features available LPC2292/LPC2294/01 only
Eight bits frame. When interface used Master mode, SSELn needed (can
used different function).
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
6.14 controller (LPC2292/94/01 only)
controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. Only single master single slave communicate during given data transfer. Data transfers principle full duplex, with frames four bits data flowing from master slave from slave master. While SPI1 peripherals share same physical pins, possible have both these peripherals active same time. Application switch from SPI1 back.
6.14.1 Features
Compatible with Motorola's SPI, Texas Instrument's 4-wire SSI, National
Semiconductor's Microwire buses.
Synchronous serial communication. Master slave operation. 8-frame FIFOs both transmit receive. Four bits frame.
6.15 General purpose timers
Timer/Counter designed count cycles peripheral clock (PCLK) externally supplied clock optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them.
6.15.1 Features
32-bit Timer/Counter with programmable 32-bit Prescaler. Timer external event counter operation Four 32-bit capture channels timer that take snapshot timer value
when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer corresponding match registers, with following
capabilities: match. HIGH match. Toggle match. nothing match.
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
6.15.2 Features available LPC2292/LPC2294/01 only
LPC2292/LPC2294/01 count external events capture inputs external pulse lasts least half period PCLK. this configuration, unused capture lines selected regular timer capture inputs, used external interrupts.
Timer count cycles either peripheral clock (PCLK) externally supplied
clock.
When counting cycles externally supplied clock, only timer's capture
inputs selected timer's clock. rate such clock limited PCLK Duration HIGH/LOW levels selected input cannot shorter than (2PCLK).
6.16 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
6.16.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(PCLK) (Tcy(PCLK) multiples Tcy(PCLK)
6.17 Real-time clock
Real-Time Clock (RTC) designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode).
6.17.1 Features
Measures passage time maintain calendar clock. Ultra-low power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Programmable Reference Clock Divider allows adjustment match
various crystal frequencies.
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
6.18 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2292/LPC2294. Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. function also based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
6.18.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
LPC2292_2294_7 B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit prescaler. 6.19 System control
6.19.1 Crystal oscillator
oscillator supports crystals range MHz. oscillator output frequency called fosc processor clock frequency referred CCLK purposes rate equations, etc. fosc CCLK same value unless running connected. Refer Section 6.19.2 "PLL" additional information.
6.19.2
accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle.The turned bypassed following chip reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time
6.19.3 Reset wake-up timer
Reset sources LPC2292/LPC2294: RESET watchdog reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip reset source starts Wake-up Timer (see Wake-up Timer description below), causing internal chip reset remain asserted until external reset de-asserted, oscillator running, fixed number clocks have passed, on-chip flash controller completed initialization. When internal reset removed, processor begins executing address which reset vector. that point, processor peripheral registers have been initialized predetermined values. Wake-up Timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power-on, types reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes Wake-up Timer.
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Wake-up Timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power-on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
6.19.4 Code security (Code Read Protection CRP)
This feature LPC2292/LPC2294/01 allows user enable different levels security system that access on-chip flash JTAG restricted. When needed, invoked programming specific pattern into dedicated flash location. commands affected CRP. There three levels Code Read Protection. CRP1 disables access chip JTAG allows partial flash update (excluding flash sector using limited commands. This mode useful when required flash field updates needed sectors erased. CRP2 disables access chip JTAG only allows full flash erase update using reduced commands. Running application with level CRP3 selected fully disables access chip JTAG pins ISP. This mode effectively disables override using P0[14] pin, too. user's application provide needed) flash update mechanism using calls call reinvoke command enable flash update UART0.
CAUTION level three Code Read Protection (CRP3) selected, future factory testing performed device.
Remark: Devices without name have only security level equivalent CRP2 available.
6.19.5 External interrupt inputs
LPC2292/LPC2294 include nine edge level sensitive External Interrupt Inputs selectable functions. When pins combined, external events processed four independent interrupt signals. External Interrupt Inputs optionally used wake processor from Power-down mode.
6.19.6 Memory mapping control
Memory Mapping Control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom on-chip flash memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
6.19.7 Power control
LPC2292/LPC2294 support reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses. Power-down mode, oscillator shut down, chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode, logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings.
6.19.8
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside bus), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.20 Emulation debugging
LPC2292/LPC2294 support emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs Port This means that communication, timer interface peripherals residing Port available during development debugging phase they when application embedded system itself.
6.20.1 EmbeddedICE
Standard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol converter. EmbeddedICE protocol converter converts remote debug protocol commands JTAG data needed access core. core Debug Communication Channel function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed co-processor program running ARM7TDMI-S core. debug
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic. JTAG clock (TCK) must slower than clock (CCLK) JTAG interface operate.
6.20.2 Embedded trace
Since LPC2292/LPC2294 have significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Embedded Trace Macrocell (ETM) provides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code cannot traced because this restriction.
6.20.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real-time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using Debug Communications Channel (DCC), which present EmbeddedICE logic. LPC2292/LPC2294 contain specific configuration RealMonitor software programmed into on-chip flash memory.
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) VDDA(3V3) Tstg Ptot(pack) Parameter supply voltage (1.8 supply voltage (3.3 analog supply voltage (3.3 analog input voltage input voltage supply current ground current junction temperature storage temperature total power dissipation (per package) electrostatic discharge voltage based package heat transfer, device power consumption human body model pins
[11] [10]
Conditions
-0.5 -0.5 -0.5 -0.5
+2.5 +3.6 +4.6 +5.1 +6.0 VDD(3V3) +150
Unit
tolerant pins other pins
[4][5] [4][6] [7][8] [8][9]
-0.5 -0.5
Vesd
-2000
+2000
following applies Table This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Internal rail. External rail. Including voltage outputs 3-state mode. Only valid when VDD(3V3) supply voltage present. exceed supply pin. peak current limited times corresponding maximum current. ground pin.
[10] Dependent package type. [11] Human body model: equivalent discharging capacitor through series resistor.
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Static characteristics
Table Static characteristics Tamb +125 unless otherwise specified. Symbol VDD(1V8) VDD(3V3) Parameter supply voltage (1.8 supply voltage (3.3 Conditions
1.65
Typ[1]
1.95
Unit
VDDA(3V3) analog supply voltage (3.3 Standard port pins, RESET, RTCK Ilatch Vhys IOHS IOLS LOW-level input current HIGH-level input current OFF-state output current latch-up current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short-circuit output current LOW-level short-circuit output current pull-down current pull-up current VDD(3V3) VDD(3V3) VDD(3V3) Power consumption LPC2292, LPC2292/00, LPC2294, LPC2294/00 IDD(act) active mode supply current VDD(1V8) CCLK MHz; Tamb code
pull-up VDD(3V3); pull-down VDD(3V3); pull-up/down -(0.5VDD(3V3)) (1.5VDD(3V3));
[4][5]
VDD(3V3)
output active
VDD(3V3)
[10]
while(1){}
executed from flash; peripherals enabled PCONP[11] register configured
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table Static characteristics .continued Tamb +125 unless otherwise specified. Symbol IDD(pd) Parameter Power-down mode supply current Conditions VDD(1V8) Tamb VDD(1V8) Tamb VDD(1V8) Tamb Power consumption LPC2292/01 LPC2294/01 IDD(act) active mode supply current VDD(1V8) CCLK MHz; Tamb code Typ[1] 1000 Unit
while(1){}
executed from flash; peripherals enabled PCONP[11] register configured IDD(idle) Idle mode supply current VDD(1V8) CCLK MHz; Tamb executed from flash; peripherals enabled PCONP[11] register configured IDD(pd) Power-down mode supply current VDD(1V8) Tamb VDD(1V8) Tamb VDD(1V8) Tamb I2C-bus pins Vhys HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS VDD(3V3)
[12]
11.5
0.7VDD(3V3)
0.3VDD(3V3)
0.5VDD(3V3)
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table Static characteristics .continued Tamb +125 unless otherwise specified. Symbol Vi(XTAL1) Vo(XTAL2) Parameter input voltage XTAL1 output voltage XTAL2 Conditions Typ[1] Unit Oscillator pins
Typical ratings guaranteed. values listed room temperature (+25 °C), nominal supply voltages. Internal rail. External rail. Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded. Accounts voltage drop supply lines. Allowed long current limit does exceed maximum current allowed device. Minimum condition maximum condition
[10] Applies P1[25:16]. [11] LPC2119/2129/2194/2292/2294 User Manual. [12] VSS.
Table static characteristics VDDA Tamb +125 unless otherwise specified. frequency MHz. Symbol EL(adj)
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error
Conditions
[1][2][3] [1][4] [1][5] [1][6] [1][7]
VDDA ±0.5
Unit
Conditions: VSSA VDDA monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute voltage error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
(LSBideal) offset error
VDDA VSSA 1024
002aaa668
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Power consumption measurements LPC2292/01 LPC2294/01
power consumption measurements represent typical values given conditions. peripherals were enabled through PCONP register, these measurements, peripherals were configured run. Peripherals were disabled through PCONP register. description PCONP register bits, refer LPC2119/2129/2194/2292/2294 User Manual.
IDD(act) (mA) peripherals enabled peripherals disabled
002aad102
frequency (MHz)
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb core voltage
Typical LPC2292/01 IDD(act) measured different frequencies
IDD(act) (mA)
002aad103
1.65
1.80
voltage
1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb peripherals enabled active.
Typical LPC2292/01 IDD(act) measured different core voltages
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
IDD(act) (mA)
002aad104
temperature (°C)
Test conditions: Active mode entered executing code on-chip flash; PCLK CCLK/4; core voltage peripherals disabled.
Typical LPC2292/01 IDD(act) measured different temperatures
10.0 IDD(idle) (mA) peripherals enabled peripherals disabled
002aad105
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb core voltage
Typical LPC2292/01 IDD(idle) measured different frequencies
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
10.0 IDD(idle) (mA)
002aad106
1.65 1.80 1.95
voltage
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb peripherals enabled active.
Typical LPC2292/01 IDD(idle) measured different core voltages
IDD(idle) (mA)
002aad107
temperature (°C)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Core voltage peripherals disabled.
Typical LPC2292/01 IDD(idle) measured different temperatures
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
IDD(pd) (µA) 1.95 1.65
002aad108
temperature (°C)
Test conditions: Power-down mode entered executing code from on-chip flash.
Typical LPC2292/01 core power-down current IDD(pd) measured different temperatures
50.0 IDD(act) (mA) 40.0 peripherals enabled peripherals disabled
002aad109
30.0
20.0
10.0
frequency (MHz)
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb core voltage
Typical LPC2294/01 IDD(act) measured different frequencies
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
55.0 IDD(act) (mA) 45.0 35.0
002aad110
25.0
15.0
1.65
1.80
voltage
1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb peripherals enabled active.
Typical LPC2294/01 IDD(act) measured different core voltages
45.0 IDD(act) (mA) 35.0
002aad111
25.0
15.0
temperature (°C)
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; core voltage peripherals disabled.
Typical LPC2294/01 IDD(act) measured different temperatures
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
002aad112
15.0 IDD(idle) (mA)
10.0 peripherals enabled
peripherals disabled
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb core voltage
Typical LPC2294/01 IDD(idle) measured different frequencies
15.0
002aad113
IDD(idle) (mA) 10.0
1.65
1.80
voltage
1.95
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb peripherals enabled active.
Typical LPC2294/01 IDD(idle) measured different core voltages
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
6.50 IDD(idle) (mA) 5.50
002aad114
4.50
3.50
2.50 1.50
0.50 temperature (°C)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; core voltage peripherals disabled.
Typical LPC2294/01 IDD(idle) measured different temperatures
IDD(pd) (µA) 1.95 1.65
002aad115
temperature (°C)
Test conditions: Power-down mode entered executing code from on-chip flash.
Typical LPC2294/01 core power-down current IDD(pd) measured different temperatures
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
45.0 IDD(act) (mA) 35.0
002aad116
25.0
15.0
1.65
1.80
voltage
1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb peripherals disabled.
Typical LPC2292/01 LPC2294/01 IDD(act) measured different core voltages
10.0
002aad117
IDD(idle) (mA)
1.65
1.80
voltage
1.95
Test conditions: Idle mode entered executing code from on-chip flash; PCLK CCLK/4; Tamb peripherals disabled.
Typical LPC2292/01 LPC2294/01 IDD(idle) measured different core voltages Table Typical LPC2292/01 peripheral power consumption active mode Core voltage Tamb measurements PCLK CCLK/4; peripherals enabled. Peripheral Timer0 Timer1 UART0 UART1
LPC2292_2294_7
CCLK
CCLK
CCLK
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table Typical LPC2292/01 peripheral power consumption active mode .continued Core voltage Tamb measurements PCLK CCLK/4; peripherals enabled. Peripheral PWM0 I2C-bus SPI0/1 PCEMC CAN1/2 CCLK CCLK CCLK 1205
Table Typical LPC2294/01 peripheral power consumption active mode Core voltage Tamb measurements PCLK CCLK/4; peripherals enabled. Peripheral Timer0 Timer1 UART0 UART1 PWM0 I2C-bus SPI0/1 PCEMC CAN1/2/3/4 CCLK CCLK CCLK 1205
Dynamic characteristics
Table Dynamic characteristics Tamb +125 VDD(1V8), VDD(3V3) over specified ranges.[1] Symbol External clock fosc oscillator frequency supplied external oscillator (signal generator) external clock frequency supplied external crystal oscillator external clock frequency on-chip used external clock frequency on-chip bootloader used initial code download Tcy(clk) tCHCX tCLCX
LPC2292_2294_7
Parameter
Conditions
Unit
clock cycle time clock HIGH time clock time
Tcy(clk) Tcy(clk)
1000
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table Dynamic characteristics .continued Tamb +125 VDD(1V8), VDD(3V3) over specified ranges.[1] Symbol tCLCH tCHCL I2C-bus
Parameter clock rise time clock fall time rise time fall time pins (P0[2] P0[3]) fall time
Conditions
Unit
Port pins (except P0[2] P0[3])
Parameters valid over operating temperature range unless otherwise specified. capacitance from
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table External memory interface dynamic characteristics Tamb Symbol tCHAV tCHCSL tCHCSH tCHANV Parameter XCLK HIGH address valid time XCLK HIGH time XCLK HIGH HIGH time XCLK HIGH address invalid time address valid time address valid time time memory access time memory access time (initial burst-ROM) memory access time (subsequent burst-ROM) data input hold time HIGH HIGH time HIGH address invalid time XCLK HIGH time XCLK HIGH HIGH time address valid time data valid time time time data valid time data valid time HIGH time HIGH time HIGH address invalid time HIGH data invalid time HIGH address invalid time
[2][3]
Conditions
Unit
Common read write cycles
Read cycle parameters tCSLAV tOELAV tCSLOEL tam(ibr) tam(sbr) th(D) tCSHOEH tOEHANV tCHOEL tCHOEH (Tcy(CCLK) WST1)) (-20) (Tcy(CCLK) WST1)) (-20) Tcy(CCLK) (-20)
[2][3]
[2][4]
Write cycle parameters tAVCSL tCSLDV tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tBLSLBLSH tWEHANV tWEHDNV tBLSHANV Tcy(CCLK) Tcy(CCLK) WST2) Tcy(CCLK) WST2) Tcy(CCLK) Tcy(CCLK)) Tcy(CCLK) Tcy(CCLK) WST2) Tcy(CCLK) WST2) Tcy(CCLK)
Tcy(CCLK)) Tcy(CCLK)
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Table External memory interface dynamic characteristics .continued Tamb Symbol tBLSHDNV tCHDV tCHWEL tCHBLSL tCHWEH tCHBLSH tCHDNV Parameter HIGH data invalid time XCLK HIGH data valid time XCLK HIGH time XCLK HIGH time XCLK HIGH HIGH time XCLK HIGH HIGH time XCLK HIGH data invalid time Conditions
Tcy(CCLK))
Unit
Tcy(CCLK))
Except initial access, which case address Tcy(CCLK) earlier. Tcy(CCLK) 1/CCLK. Latest address valid, LOW, data valid. Address valid data valid. Earliest HIGH, HIGH, address change data invalid.
Table
Standard read access specifications frequency WST[1] setting round integer Memory access time requirement
Access cycle
standard read
WRITE INIT
CCLK WRITE CCLK INIT CCLK
CCLK WRITE CCLK INIT CCLK CCLK
standard write
burst read initial
burst read subsequent
LPC2119/2129/2194/2292/2294 User Manual description WSTn bits.
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Timing
XCLK tCSLAV tCSHOEH
addr data tCSLOEL tOELAV tCHOEL tCHOEH
002aaa749
th(D)
tOEHANV
External memory read access
XCLK tCSLDV
tAVCSL tWELWEH tBLSLBLSH tWEHANV tCSLBLSL tWELDV tBLSHANV
tCSLWEL BLS/WE
addr tCSLDV data tWEHDNV tBLSHDNV
002aaa750
External memory write access
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
External clock timing (with amplitude least Vi(RMS)
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Package outline
LQFP144: plastic profile quad flat package; leads; body SOT486-1
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.75 0.45 0.08 0.08 D(1) E(1)
22.15 22.15 21.85 21.85
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT486-1 REFERENCES 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-03-14 03-02-20
Package outline SOT486-1 (LQFP144)
LPC2292_2294_7 B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
TFBGA144: plastic thin fine-pitch ball grid array package; balls
SOT569-2
ball index area
detail
ball index area
scale
DIMENSIONS original dimensions) UNIT 1.20 1.05 0.95 0.40 0.35 0.30 0.80 0.70 0.65 0.50 0.45 0.40 12.1 12.0 11.9 12.1 12.0 11.9 0.15 0.05 0.08
OUTLINE VERSION SOT569-2
REFERENCES JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 08-01-29 08-03-14
Package outline SOT569-2 (TFBGA144)
LPC2292_2294_7 B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Abbreviations
Table Acronym AMBA CISC FIFO GPIO JTAG RISC SRAM UART Acronym list Description Analog-to-Digital Converter Advanced High-performance Advanced Microcontroller Architecture Advanced Peripheral Controller Area Network Complex Instruction Computer First First General Purpose Input/Output Input/Output Joint Test Action Group Least Significant Phase-Locked Loop Pulse Width Modulator Reduced Instruction Computer Serial Peripheral Interface Static Random Access Memory Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Revision history
Table Revision history Release date 20081204 Data sheet status Product data sheet Change notice Supersedes LPC2292_2294_6 Document LPC2292_2294_7 Modifications:
Figure "Block diagram": corrected high-speed GPIO ports pins; P0/P1 only. Figure "External clock timing (with amplitude least Vi(RMS) mV)": removed figure note "VDD updated graphic. Table "Pin description": descriptions corrected pins P2[30], P2[31], P3[28], P3[30], P3[31]. Table "Interrupt sources": UART0/1 interrupt sources corrected. Table "Static characteristics": Vhys, moved from column. Maximum frequency fosc external oscillator external crystal updated. Changed SOT569-1 SOT569-2. Added overbar indicate LOW-active BLSn, CSn, Product data sheet LPC2292_2294_5 Type number LPC2292FBD144/01 been added. Type number LPC2292FET144/01 been added. Type number LPC2294HBD144/01 been added. Details introduced with devices peripherals/features (Fast ports, SSP, CRP) enhancements existing ones (UART0/1, Timers, ADC, SPI) added. Power consumption measurements LPC2292/2294/01 added. Description JTAG been updated. Product data sheet Product data sheet Product data sheet Product data Preliminary data LPC2292_2294_4 LPC2292_2294_3 LPC2292_2294-02 LPC2292_2294-01
LPC2292_2294_6 Modifications:
20071210
LPC2292_2294_5 LPC2292_2294_4 LPC2292_2294_3 LPC2292_2294-02 LPC2292_2294-01
20070215 20060711 20051101 20041223 20040205
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Legal information
13.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
13.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
13.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected
13.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
LPC2292_2294_7
B.V. 2008. rights reserved.
Product data sheet
Rev. December 2008
Semiconductors
LPC2292/LPC2294
16/32-bit microcontrollers with external memory interface
Contents
6.5.1 6.8.1 6.8.2 General description Features features brought LPC2292/ LPC2294/01 devices. features common devices Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-chip flash program memory On-chip SRAM Memory map. Interrupt controller Interrupt sources. connect block External memory controller. General purpose parallel (GPIO) Fast Features Features added with Fast GPIO registers available LPC2292/ LPC2294/01 only 10-bit Features features available LPC2292/ LPC2294/01 only controllers acceptance filter Features UARTs Features UART features available LPC2292/ LPC2294/01 only I2C-bus serial controller Features serial controller. Features Features available LPC2292/LPC2294/ only controller (LPC2292/94/01 only). Features General purpose timers Features 6.15.2 6.16 6.16.1 6.17 6.17.1 6.18 6.18.1 6.19 6.19.1 6.19.2 6.19.3 6.19.4 6.19.5 6.19.6 6.19.7 6.19.8 6.20 6.20.1 6.20.2 6.20.3 13.1 13.2 13.3 13.4 Features available LPC2292/ LPC2294/01 only Watchdog timer Features Real-time clock. Features Pulse width modulator Features System control Crystal oscillator. PLL. Reset wake-up timer Code security (Code Read Protection CRP) External interrupt inputs Memory mapping control Power control Emulation debugging. EmbeddedICE Embedded trace. RealMonitor Limiting values Static characteristics Power consumption measurements LPC2292/01 LPC2294/01 Dynamic characteristics Timing Package outline Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers. Trademarks Contact information Contents.
6.9.1 6.9.2 6.10 6.10.1 6.11 6.11.1 6.11.2 6.12 6.12.1 6.13 6.13.1 6.13.2 6.14 6.14.1 6.15 6.15.1
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2008.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: December 2008 Document identifier: LPC2292_2294_7

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