Single-chip 16-bit/32-bit microcontrollers; flash, with segment driver

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Single-chip 16-bit/32-bit microcontrollers; flash, with segment driver

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LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers; flash, with segment driver
Rev. October 2008 Product data sheet
LPC2157/2158 multi-chip module consisting LPC2138/2148 single-chip microcontroller combined with PCF8576D Universal driver low-cost 100-pin package. driver provides segments supports from backplanes. Display overhead minimized on-chip display with auto-increment addressing. Refer respective LPC2148 LPC2138 user manual details.
Features
128-bit wide interface/accelerator enables high-speed operation. on-chip static on-chip flash memory. Full-speed compliant device controller with endpoint RAM. additional on-chip accessible (LPC2158 only). segment backplane controller supports from backplanes. Single 10-bit provides variable analog output. power Real-Time Clock (RTC) with independent power clock input. Multiple serial interfaces including UARTs (16C550), Fast I2C-bus (400 kbit/s), with buffering variable data length capabilities. High-accuracy internal oscillator option allows operation without external oscillator components. oscillator option selectable fine tunable. operating range. pins tolerant (may pulled driven 100-pin LQFP package with microcontroller pins minimum. Individual enable/disable peripheral functions well peripheral clock scaling additional power optimization.
Ordering information
Table Ordering information Package Name LPC2157FBD100 LPC2158FBD100 LQFP100 LQFP100 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT407-1 SOT407-1 Type number
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Block diagram
S[31:0] P1[31:25], P1[17:16] P0[31:28], P0[27:26](1), P0[25], P0[23:0]
LPC2157/ LPC2158
PCF8576D
CONTROLLER
BP[3:0]
VLCD A[2:0]
002aad382
B.V. 2008. rights reserved.
LPC2157 only.
Block diagram LPC2157/2158
LPC2157_2158_1
Product data sheet
Rev. October 2008
SCL_LCD, SDA_LCD
SCL,
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
TMS(1) TDI(1) TRST(1) TCK(1) TDO(1)
XTAL2 XTAL1 RESET
EMULATION TRACE MODULE
LPC2157/2158
P1[31:25], P1[17:16] P0[31:28], P0[27:26](3) P0[25], P0[23:0]
TEST/DEBUG INTERFACE
PLL0 system clock PLL1 clock VECTORED INTERRUPT CONTROLLER SYSTEM FUNCTIONS
FAST GENERAL PURPOSE
ARM7TDMI-S
BRIDGE
ARM7 local
AMBA (Advanced High-performance Bus) INTERNAL SRAM CONTROLLER INTERNAL FLASH CONTROLLER SHARED WITH DMA(2) DECODER
SRAM
FLASH
BRIDGE
DIVIDER
(advanced peripheral bus) EINT3 EINT0 EXTERNAL INTERRUPTS
FULL-SPEED DEVICE CONTROLLER WITH DMA(2)
UP_LED CONNECT VBUS SCL0, SCL1
CAP0 CAP1 MAT0 MAT1 AD0[7:6], AD0[5](3) AD0[0](3) AD0[4:1] AD1[7:0]
CAPTURE/COMPARE (W/EXTERNAL CLOCK) TIMER 0/TIMER
I2C-BUS SERIAL INTERFACES
SDA0, SDA1
SCK0, SCK1 CONVERTERS SERIAL INTERFACES MOSI0, MOSI1 MISO0, MISO1 SSEL0, SSEL1 TXD0, TXD1
AOUT
CONVERTER
UART0/UART1
RXD0, RXD1
P0[31:28] P0[25:0] P1[31:16]
GENERAL PURPOSE
REAL-TIME CLOCK
DSR1,CTS1, RTS1, DTR1, DCD1,RI1 RTCX1 RTCX2 VBAT
PWM[6:1]
PWM0
WATCHDOG TIMER SYSTEM CONTROL
002aad384
Pins shared with GPIO. controller with accessible general purpose and/or available LPC2158 only. LPC2157 only.
Microcontroller section block diagram
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
S[31:0]
VDD(LCD) BACKPLANE OUTPUTS VOLTAGE SELECTOR BIAS GENERATOR VLCD SHIFT REGISTER DISPLAY SEGMENT OUTPUTS
DISPLAY LATCH
SYNC
TIMING
BLINKER DISPLAY CONTROLLER
INPUT BANK SELECTOR
DISPLAY BITS
OUTPUT BANK SELECTOR
OSCILLATOR
POWERON RESET COMMAND DECODER
DATA POINTER
SCL_LCD SDA_LCD INPUT FILTERS I2C-BUS CONTROLLER
SUBADDRESS COUNTER
002aad449
display controller block diagram
Pinning information
Pinning
LPC2157FBD
002aad385
configuration LPC2157
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
LPC2158FBD
002aad444
configuration LPC2158
description
Table Symbol P0[0] P0[31] description LPC2157 Type Description Port Port 32-bit port with individual direction controls each bit. Total pins Port used general purpose bidirectional digital I/Os while P0[31] output only pin. operation port pins depends upon function selected connect block. P0[24] available. P0[0]/TXD0/ PWM1 7[1] P0[1]/RXD0/ PWM3/EINT0 9[2] P0[2]/SCL0/ CAP0[0] 10[3] P0[3]/SDA0/ MAT0[0]/EINT1 14[3] P0[4]/SCK0/ CAP0[1]/AD0[6] 15[4] P0[5]/MISO0/ MAT0[1]/AD0[7] 17[4]
LPC2157_2158_1
P0[0] General purpose input/output digital (GPIO). TXD0 Transmitter output UART0. PWM1 Pulse Width Modulator output P0[1] General purpose input/output digital (GPIO). RXD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input. P0[2] General purpose input/output digital (GPIO). SCL0 I2C0 clock input/output. Open-drain output (for I2C-bus compliance). CAP0[0] Capture input Timer channel P0[3] General purpose input/output digital (GPIO). SDA0 I2C0 data input/output. Open-drain output (for I2C-bus compliance). MAT0[0] Match output Timer channel EINT1 External interrupt input. P0[4] General purpose input/output digital (GPIO). SCK0 Serial clock SPI0. clock output from master input slave. CAP0[1] Capture input Timer channel AD0[6] input P0[5] General purpose input/output digital (GPIO). MISO0 Master Slave SPI0. Data input master data output from slave. MAT0[1] Match output Timer channel AD0[7] input
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Table Symbol
description LPC2157 .continued 18[4] Type Description P0[6] General purpose input/output digital (GPIO). MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0[2] Capture input Timer channel AD1[0] input P0[7] General purpose input/output digital (GPIO). SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. P0[8] General purpose input/output digital (GPIO). TXD1 Transmitter output UART1. PWM4 Pulse Width Modulator output AD1[1] input P0[9] General purpose input/output digital (GPIO). RXD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input. P0[10] General purpose input/output digital (GPIO). RTS1 Request Send output UART1. CAP1[0] Capture input Timer channel AD1[2] input P0[11] General purpose input/output digital (GPIO). CTS1 Clear Send input UART1. CAP1[1] Capture input Timer channel SCL1 I2C1 clock input/output. Open-drain output (for I2C-bus compliance) P0[12] General purpose input/output digital (GPIO). DSR1 Data Ready input UART1. MAT1[0] Match output Timer channel AD1[3] input P0[13] General purpose input/output digital (GPIO). DTR1 Data Terminal Ready output UART1. MAT1[1] Match output Timer channel AD1[4] input P0[14] General purpose input/output digital (GPIO). DCD1 Data Carrier Detect input UART1. EINT1 External interrupt input. SDA1 I2C1 data input/output. Open-drain output (for I2C-bus compliance). Note: this while RESET forces on-chip bootloader take over control part after reset.
P0[6]/MOSI0/ CAP0[2]/AD1[0]
P0[7]/SSEL0/ PWM2/EINT2
19[2]
P0[8]/TXD1/ PWM4/AD1[1]
20[4]
P0[9]/RXD1/ PWM6/EINT3
21[2]
P0[10]/RTS1/ CAP1[0]/AD1[2]
22[4]
P0[11]/CTS1/ CAP1[1]/SCL1
23[3]
P0[12]/DSR1/ MAT1[0]/AD1[3]
24[4]
P0[13]/DTR1/ MAT1[1]/AD1[4]
25[4]
P0[14]/DCD1/ EINT1/SDA1
26[3]
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Table Symbol
description LPC2157 .continued 28[4] Type Description P0[15] General purpose input/output digital (GPIO). Ring Indicator input UART1. EINT2 External interrupt input. AD1[5] input P0[16] General purpose input/output digital (GPIO). EINT0 External interrupt input. MAT0[2] Match output Timer channel CAP0[2] Capture input Timer channel P0[17] General purpose input/output digital (GPIO). CAP1[2] Capture input Timer channel SCK1 Serial Clock SSP. Clock output from master input slave. MAT1[2] Match output Timer channel P0[18] General purpose input/output digital (GPIO). CAP1[3] Capture input Timer channel MISO1 Master Slave SSP. Data input master data output from slave. MAT1[3] Match output Timer channel P0[19] General purpose input/output digital (GPIO). MAT1[2] Match output Timer channel MOSI1 Master Slave SSP. Data output from master data input slave. CAP1[2] Capture input Timer channel P0[20] General purpose input/output digital (GPIO). MAT1[3] Match output Timer channel SSEL1 Slave Select SSP. Selects interface slave. EINT3 External interrupt input. P0[21] General purpose input/output digital (GPIO). PWM5 Pulse Width Modulator output AD1[6] input CAP1[3] Capture input Timer channel P0[22] General purpose input/output digital (GPIO). AD1[7] input CAP0[0] Capture input Timer channel MAT0[0] Match output Timer channel P0[23] General purpose input/output digital (GPIO). P0[25] General purpose input/output digital (GPIO). AD0[4] input AOUT output. P0[26] General purpose input/output digital (GPIO). AD0[5] input This analog input always connected pin.
P0[15]/RI1/ EINT2/AD1[5]
P0[16]/EINT0/ MAT0[2]/CAP0[2]
29[2]
P0[17]/CAP1[2]/ SCK1/MAT1[2]
30[1]
P0[18]/CAP1[3]/ MISO1/MAT1[3]
79[1]
P0[19]/MAT1[2]/ MOSI1/CAP1[2]
80[1]
P0[20]/MAT1[3]/ SSEL1/EINT3
81[2]
P0[21]/PWM5/ AD1[6]/CAP1[3]
91[4]
P0[22]/AD1[7]/ CAP0[0]/ MAT0[0]
92[4]
P0[23] P0[25]/AD0[4]/ AOUT
84[1] 97[5]
P0[26]/AD0[5]
98[7]
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Table Symbol
description LPC2157 .continued 99[7] Type Description P0[27] General purpose input/output digital (GPIO). AD0[0] input This analog input always connected pin. CAP0[1] Capture input Timer channel MAT0[1] Match output Timer channel P0[28] General purpose input/output digital (GPIO). AD0[1] input CAP0[2] Capture input Timer channel MAT0[2] Match output Timer channel P0[29] General purpose input/output digital (GPIO). AD0[2] input CAP0[3] Capture input Timer channel MAT0[3] Match output Timer channel P0[30] General purpose input/output digital (GPIO). AD0[3] input EINT3 External interrupt input. CAP0[0] Capture input Timer channel P0[31] General purpose output only digital pin. Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins through through port available. P1[16] General purpose input/output digital (GPIO). P1[17] General purpose input/output digital (GPIO). P1[25] General purpose input/output digital (GPIO). EXTIN0 External Trigger Input. Standard with internal pull-up. P1[26] General purpose input/output digital (GPIO). RTCK Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional with internal pull-up. Note: RTCK while RESET enables pins P1[31:26] operate Debug port after reset.
P0[27]/AD0[0]/ CAP0[1]/MAT0[1]
P0[28]/AD0[1]/ CAP0[2]/MAT0[2]
1[4]
P0[29]/AD0[2]/ CAP0[3]/MAT0[3]
2[4]
P0[30]/AD0[3]/ EINT3/CAP0[0]
3[4]
P0[31] P1[0] P1[31]
5[6]
P1[16] P1[17] P1[25]/EXTIN0 P1[26]/RTCK
4[6] 100[6] 16[6] 12[6]
P1[27]/TDO P1[28]/TDI P1[29]/TCK P1[30]/TMS P1[31]/TRST
90[6] 86[6] 82[6] 78[6] 8[6]
P1[27] General purpose input/output digital (GPIO). Test Data JTAG interface. P1[28] General purpose input/output digital (GPIO). Test Data JTAG interface. P1[29] General purpose input/output digital (GPIO). Test Clock JTAG interface. P1[30] General purpose input/output digital (GPIO). Test Mode Select JTAG interface. P1[31] General purpose input/output digital (GPIO). TRST Test Reset JTAG interface.
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Table Symbol RESET
description LPC2157 .continued 83[8] Type Description External reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input from oscillator amplifier. Output oscillator circuit internal clock generator circuits. Input oscillator circuit. Output from oscillator circuit. Ground: reference.
XTAL1 XTAL2 RTCX1 RTCX2
88[9] 87[9] 93[9] 94[9]
VDDA
power supply: This power supply voltage core ports. Analog power supply: This should nominally same voltage should isolated minimize noise error. This voltage only used power on-chip ADC(s) DAC. power supply: Power supply voltage PCF8576D. power supply: voltage. reference voltage: This should nominally less than equal voltage should isolated minimize noise error. Level this used reference ADC(s) DAC. power supply voltage: this supplies power RTC. I2C-bus data signal controller. I2C-bus clock signal controller. SYNC cascade synchronization input/output external clock input/output BP3: backplane outputs. S31: segment outputs.
VDD(LCD) VLCD VREF
VBAT SDA_LCD SCL_LCD SYNC
tolerant providing digital functions with levels hysteresis slew rate control. tolerant providing digital functions with levels hysteresis slew rate control. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than Open-drain tolerant digital I2C-bus specification compatible pad. requires external pull-up provide output functionality. tolerant providing digital (with levels hysteresis slew rate control) analog input function. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than When configured input, digital section disabled. tolerant providing digital (with levels hysteresis slew rate control) analog output function. When configured output, digital section disabled. tolerant with built-in pull-up resistor providing digital functions with levels hysteresis slew rate control. pull-up resistor's value typically ranges from designed accordance with Universal Serial (USB) specification, revision (Full-speed Low-speed mode only). tolerant providing digital input (with levels hysteresis) function only. provides special analog functionality.
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Table Symbol
description LPC2158 Type Description Port Port 32-bit port with individual direction controls each bit. Total pins Port used general purpose bidirectional digital I/Os while P0[31] output only pin. operation port pins depends upon function selected connect block. Pins P0[24], P0[26] P0[27] available. P0[0] General purpose input/output digital (GPIO). TXD0 Transmitter output UART0. PWM1 Pulse Width Modulator output P0[1] General purpose input/output digital (GPIO). RXD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input. P0[2] General purpose input/output digital (GPIO). SCL0 I2C0 clock input/output. Open-drain output (for I2C-bus compliance). CAP0[0] Capture input Timer channel P0[3] General purpose input/output digital (GPIO). SDA0 I2C0 data input/output. Open-drain output (for I2C-bus compliance). MAT0[0] Match output Timer channel EINT1 External interrupt input. P0[4] General purpose input/output digital (GPIO). SCK0 Serial clock SPI0. clock output from master input slave. CAP0[1] Capture input Timer channel AD0[6] input P0[5] General purpose input/output digital (GPIO). MISO0 Master Slave SPI0. Data input master data output from slave. MAT0[1] Match output Timer channel AD0[7] input P0[6] General purpose input/output digital (GPIO). MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0[2] Capture input Timer channel AD1[0] input P0[7] General purpose input/output digital (GPIO). SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. P0[8] General purpose input/output digital (GPIO). TXD1 Transmitter output UART1. PWM4 Pulse Width Modulator output AD1[1] input
P0[0] P0[31]
P0[0]/TXD0/ PWM1
7[1]
P0[1]/RXD0/ PWM3/EINT0
9[2]
P0[2]/SCL0/ CAP0[0]
10[3]
P0[3]/SDA0/ MAT0[0]/EINT1
14[3]
P0[4]/SCK0/ CAP0[1]/AD0[6]
15[4]
P0[5]/MISO0/ MAT0[1]/AD0[7]
17[4]
P0[6]/MOSI0/ CAP0[2]/AD1[0]
18[4]
P0[7]/SSEL0/ PWM2/EINT2
19[2]
P0[8]/TXD1/ PWM4/AD1[1]
20[4]
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Table Symbol
description LPC2158 .continued 21[2] Type Description P0[9] General purpose input/output digital (GPIO). RXD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input. P0[10] General purpose input/output digital (GPIO). RTS1 Request Send output UART1. CAP1[0] Capture input Timer channel AD1[2] input P0[11] General purpose input/output digital (GPIO). CTS1 Clear Send input UART1. CAP1[1] Capture input Timer channel SCL1 I2C1 clock input/output. Open-drain output (for I2C-bus compliance) P0[12] General purpose input/output digital (GPIO). DSR1 Data Ready input UART1. MAT1[0] Match output Timer channel AD1[3] input P0[13] General purpose input/output digital (GPIO). DTR1 Data Terminal Ready output UART1. MAT1[1] Match output Timer channel AD1[4] input P0[14] General purpose input/output digital (GPIO). DCD1 Data Carrier Detect input UART1. EINT1 External interrupt input. SDA1 I2C1 data input/output. Open-drain output (for I2C-bus compliance). Note: this while RESET forces on-chip bootloader take over control part after reset.
P0[9]/RXD1/ PWM6/EINT3
P0[10]/RTS1/ CAP1[0]/AD1[2]
22[4]
P0[11]/CTS1/ CAP1[1]/SCL1
23[3]
P0[12]/DSR1/ MAT1[0]/AD1[3]
24[4]
P0[13]/DTR1/ MAT1[1]/AD1[4]
25[4]
P0[14]/DCD1/ EINT1/SDA1
26[3]
P0[15]/RI1/ EINT2/AD1[5]
28[4]
P0[15] General purpose input/output digital (GPIO). Ring Indicator input UART1. EINT2 External interrupt input. AD1[5] input P0[16] General purpose input/output digital (GPIO). EINT0 External interrupt input. MAT0[2] Match output Timer channel CAP0[2] Capture input Timer channel P0[17] General purpose input/output digital (GPIO). CAP1[2] Capture input Timer channel SCK1 Serial Clock SSP. Clock output from master input slave. MAT1[2] Match output Timer channel
P0[16]/EINT0/ MAT0[2]/CAP0[2]
29[2]
P0[17]/CAP1[2]/ SCK1/MAT1[2]
30[1]
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Table Symbol
description LPC2158 .continued 79[1] Type Description P0[18] General purpose input/output digital (GPIO). CAP1[3] Capture input Timer channel MISO1 Master Slave SSP. Data input master data output from slave. MAT1[3] Match output Timer channel P0[19] General purpose input/output digital (GPIO). MAT1[2] Match output Timer channel MOSI1 Master Slave SSP. Data output from master data input slave. CAP1[2] Capture input Timer channel P0[20] General purpose input/output digital (GPIO). MAT1[3] Match output Timer channel SSEL1 Slave Select SSP. Selects interface slave. EINT3 External interrupt input. P0[21] General purpose input/output digital (GPIO). PWM5 Pulse Width Modulator output AD1[6] input CAP1[3] Capture input Timer channel P0[22] General purpose input/output digital (GPIO). AD1[7] input CAP0[0] Capture input Timer channel MAT0[0] Match output Timer channel P0[23] General purpose input/output digital (GPIO). VBUS Indicates presence power. Note: This signal must HIGH reset occur. P0[25] General purpose input/output digital (GPIO). AD0[4] input AOUT output. P0[28] General purpose input/output digital (GPIO). AD0[1] input CAP0[2] Capture input Timer channel MAT0[2] Match output Timer channel P0[29] General purpose input/output digital (GPIO). AD0[2] input CAP0[3] Capture input Timer channel MAT0[3] Match output Timer channel P0[30] General purpose input/output digital (GPIO). AD0[3] input EINT3 External interrupt input. CAP0[0] Capture input Timer channel
P0[18]/CAP1[3]/ MISO1/MAT1[3]
P0[19]/MAT1[2]/ MOSI1/CAP1[2]
80[1]
P0[20]/MAT1[3]/ SSEL1/EINT3
81[2]
P0[21]/PWM5/ AD1[6]/CAP1[3]
91[4]
P0[22]/AD1[7]/ CAP0[0]/ MAT0[0]
92[4]
P0[23]/VBUS
84[1]
P0[25]/AD0[4]/ AOUT
97[5]
P0[28]/AD0[1]/ CAP0[2]/MAT0[2]
1[4]
P0[29]/AD0[2]/ CAP0[3]/MAT0[3]
2[4]
P0[30]/AD0[3]/ EINT3/CAP0[0]
3[4]
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Table Symbol
description LPC2158 .continued 5[6] Type Description P0[31] General purpose output only digital pin. UP_LED GoodLink indicator. when device configured (non-control endpoints enabled). HIGH when device configured during global suspend. CONNECT Signal used switch external resistor under software control. Used with SoftConnect feature. Important: This digital output only pin. This MUST externally pulled when RESET JTAG port will disabled.
P0[31]/UP_LED/ CONNECT
P1[0] P1[31]
Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins through through port available. P1[16] General purpose input/output digital (GPIO). P1[17] General purpose input/output digital (GPIO). P1[25] General purpose input/output digital (GPIO). EXTIN0 External Trigger Input. Standard with internal pull-up. P1[26] General purpose input/output digital (GPIO). RTCK Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional with internal pull-up. Note: RTCK while RESET enables pins P1[31:26] operate Debug port after reset.
P1[16] P1[17] P1[25]/EXTIN0 P1[26]/RTCK
4[6] 100[6] 16[6] 12[6]
P1[27]/TDO P1[28]/TDI P1[29]/TCK P1[30]/TMS P1[31]/TRST RESET
90[6] 86[6] 82[6] 78[6] 8[6] 98[7] 99[7] 83[8]
P1[27] General purpose input/output digital (GPIO). Test Data JTAG interface. P1[28] General purpose input/output digital (GPIO). Test Data JTAG interface. P1[29] General purpose input/output digital (GPIO). Test Clock JTAG interface. P1[30] General purpose input/output digital (GPIO). Test Mode Select JTAG interface. P1[31] General purpose input/output digital (GPIO). TRST Test Reset JTAG interface. bidirectional line. bidirectional line. External reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input from oscillator amplifier. Output oscillator circuit internal clock generator circuits. Input oscillator circuit. Output from oscillator circuit. Ground: reference.
XTAL1 XTAL2 RTCX1 RTCX2
88[9] 87[9] 93[9] 94[9]
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Table Symbol VDDA
description LPC2158 .continued Type Description power supply: This power supply voltage core ports. Analog power supply: This should nominally same voltage should isolated minimize noise error. This voltage only used power on-chip ADC(s) DAC. power supply: Power supply voltage PCF8576D. power supply: voltage. reference voltage: This should nominally less than equal voltage should isolated minimize noise error. Level this used reference ADC(s) DAC. power supply voltage: this supplies power RTC. I2C-bus data signal controller. I2C-bus clock signal controller. SYNC cascade synchronization input/output external clock input/output BP3: backplane outputs. S31: segment outputs.
VDD(LCD) VLCD VREF
VBAT SDA_LCD SCL_LCD SYNC
tolerant providing digital functions with levels hysteresis slew rate control. tolerant providing digital functions with levels hysteresis slew rate control. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than Open-drain tolerant digital I2C-bus specification compatible pad. requires external pull-up provide output functionality. tolerant providing digital (with levels hysteresis slew rate control) analog input function. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than When configured input, digital section disabled. tolerant providing digital (with levels hysteresis slew rate control) analog output function. When configured output, digital section disabled. tolerant with built-in pull-up resistor providing digital functions with levels hysteresis slew rate control. pull-up resistor's value typically ranges from designed accordance with Universal Serial (USB) specification, revision (Full-speed Low-speed mode only). tolerant providing digital input (with levels hysteresis) function only. provides special analog functionality.
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Functional description
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers (CISC). This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-chip flash program memory
LPC2157/2158 incorporate flash memory system. This memory used both code data storage. Programming flash memory accomplished several ways. programmed System serial port. application program also erase and/or program flash while application running, allowing great degree flexibility data storage field firmware upgrades, etc. architectural solution chosen on-chip bootloader, flash memory available user's code LPC2157/2158 respectively. LPC2157/2158 flash memory provides minimum 400000 erase/write cycles years data-retention.
On-chip static
On-chip static used code and/or data storage. SRAM accessed 8-bit, 16-bit, 32-bit. LPC2157/2158 provide static RAM.
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Single-chip 16-bit/32-bit microcontrollers
case LPC2158 only, SRAM block intended utilized mainly also used general purpose data storage code storage execution.
Memory
LPC2157/2158 memory incorporates several distinct regions, shown Figure addition, interrupt vectors remapped allow them reside either flash memory (the default) on-chip static RAM. This described Section 6.19 "System control".
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xE000 0000
RESERVED ADDRESS SPACE
0xC000 0000
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY RESERVED ADDRESS SPACE
0x8000 0000 0x7FFF FFFF 0x7FFF D000 0x7FFF CFFF 0x4001 8000 0x4000 7FFF
ON-CHIP STATIC (LPC2157/2158) RESERVED ADDRESS SPACE ON-CHIP NON-VOLATILE MEMORY (LPC2157/2158)
0x4000 4000 0x0008 0000 0x0007 FFFF
0x0001 0000
002aad402
LPC2157/2158 memory
Interrupt controller
Vectored Interrupt Controller (VIC) accepts interrupt request inputs categorizes them Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted.
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highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine does need branch into interrupt service routine from interrupt vector location. more than request assigned class, service routine will read word from that identifies which source(s) (are) requesting interrupt. Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs pending, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active.
6.5.1 Interrupt sources
Each peripheral device interrupt line connected Vectored Interrupt Controller, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined. Control Module with select registers defines functionality microcontroller given hardware environment. After reset pins Port Port configured input with following exceptions: debug enabled, JTAG pins will assume their JTAG functionality. pins associated with I2C0 I2C1 interface open drain.
Fast general purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins. LPC2157/2158 introduce accelerated GPIO functions over prior LPC2000 devices:
GPIO registers relocated local fastest possible timing.
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Single-chip 16-bit/32-bit microcontrollers
Mask registers allow treating sets port bits group, leaving other bits
unchanged.
GPIO registers byte addressable. Entire port value written instruction.
6.7.1 Features
Bit-level clear registers allow single instruction clear number
bits port.
Direction control individual bits. Separate control output clear. default inputs after reset. 10-bit
LPC2157/2158 contain single 10-bit successive approximation ADCs. While ADC0 eight channels (six channels LPC2158), ADC1 eight channels. Therefore, total number available inputs LPC2157 LPC2158
6.8.1 Features
10-bit successive approximation ADC. Measurement range VREF (2.0 VREF VDDA). Each converter capable performing more than 400000 10-bit samples second. Every analog input dedicated result register reduce interrupt overhead. Burst conversion mode single multiple inputs. Optional conversion transition input timer match signal. Global Start command both converters.
10-bit
enables LPC2157/2158 generate variable analog output. maximum output voltage VREF voltage.
6.9.1 Features
10-bit DAC. Buffered output. Power-down mode available. Selectable speed versus power.
6.10 device controller (LPC2158 only)
4-wire serial that supports communication between host number (127 max) peripherals. host controller allocates bandwidth attached devices through token based protocol. supports plugging, unplugging, dynamic configuration devices. transactions initiated host controller.
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Single-chip 16-bit/32-bit microcontrollers
LPC2158 equipped with device controller that enables Mbit/s data exchange with host controller. consists register interface, serial interface engine, endpoint buffer memory controller. serial interface engine decodes data stream writes data appropriate point buffer memory. status completed transfer error condition indicated status registers. interrupt also generated enabled. controller transfer data between endpoint buffer RAM.
6.10.1 Features
Fully compliant with Full-speed specification. Supports physical logical) endpoints. Supports control, bulk, interrupt isochronous endpoints. Scalable realization endpoints time. Endpoint maximum packet size selection maximum specification) software time.
message buffer size based endpoint realization maximum packet size. Supports SoftConnect GoodLink indicator. These functions sharing
pin.
Supports bus-powered capability with suspend current. Supports transfer non-control endpoints. duplex channel serves endpoints. Allows dynamic switching between controlled modes. Double buffer implementation bulk isochronous endpoints.
6.11 UARTs
LPC2157/2158 each contain UARTs. addition standard transmit receive data lines, UART1 also provides full modem control handshake interface. Compared previous LPC2000 microcontrollers, UARTs LPC2157/2158 introduce fractional baud rate generator both UARTs, enabling these microcontrollers achieve standard baud rates such 115200 with crystal frequency above MHz. addition, auto-CTS/RTS flow-control functions fully implemented hardware.
6.11.1 Features
Receive Transmit FIFOs. Register locations conform 16C550 industry standard. Receiver FIFO trigger points Built-in fractional baud rate generator covering wide range baud rates without need external crystals particular values. control both UARTs.
Transmission FIFO control enables implementation software (XON/XOFF) flow LPC2158 UART1 equipped with standard modem interface signals. This module also
provides full support hardware flow control (auto-CTS/RTS).
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Product data sheet
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Semiconductors
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Single-chip 16-bit/32-bit microcontrollers
6.12 I2C-bus serial controller
LPC2157/2158 each contain I2C-bus controllers. I2C-bus bidirectional, inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver transmitter with capability both receive send information (such memory)). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master bus, controlled more than master connected I2C-bus implemented LPC2157/2158 supports rates kbit/s (Fast I2C-bus).
6.12.1 Features
Compliant with standard I2C-bus interface. Easy configure master, slave, master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. 6.13 serial controller
LPC2157/2158 each contain controller. full duplex serial interface, designed handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master.
6.13.1 Features
Compliant with specification. Synchronous, Serial, Full Duplex, Communication. Combined master slave. Maximum data rate eighth input clock rate.
6.14 serial controller
LPC2157/2158 each contain Serial Synchronous Port controller (SSP). controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. However, only single master single
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Single-chip 16-bit/32-bit microcontrollers
slave communicate during given data transfer. supports full duplex transfers, with data frames bits bits data flowing from master slave from slave master. Often only these data flows carries meaningful data.
6.14.1 Features
Compatible with Motorola's SPI, TI's 4-wire National Semiconductor's
Microwire buses.
Synchronous serial communication. Master slave operation. 8-frame FIFOs both transmit receive. Four bits bits frame.
6.15 General purpose timers/external event counters
Timer/Counter designed count cycles peripheral clock (PCLK) externally supplied clock optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them. LPC2157/2158 count external events capture inputs minimum external pulse equal longer than period PCLK. this configuration, unused capture lines selected regular timer capture inputs, used external interrupts.
6.15.1 Features
32-bit timer/counter with programmable 32-bit prescaler. External event counter timer operation. Four 32-bit capture channels timer/counter that take snapshot timer
value when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer/counter corresponding match registers, with
following capabilities: match. HIGH match. Toggle match. nothing match.
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Single-chip 16-bit/32-bit microcontrollers
6.16 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
6.16.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(PCLK) (Tcy(PCLK) multiples Tcy(PCLK)
6.17 Real-time clock
designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode).
6.17.1 Features
Measures passage time maintain calendar clock. Ultra-low power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
either dedicated oscillator input clock derived from
external crystal/oscillator input XTAL1. Programmable reference clock divider allows fine adjustment RTC.
Dedicated power supply connected battery main 6.18 Pulse width modulator
based standard timer block inherits features, although only function pinned LPC2157/2158. timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. function also based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions.
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Single-chip 16-bit/32-bit microcontrollers
match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
6.18.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit prescaler.
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6.19 System control
6.19.1 Crystal oscillator
On-chip integrated oscillator operates with external crystal range MHz. oscillator output frequency called fosc processor clock frequency referred CCLK purposes rate equations, etc. fosc CCLK same value unless running connected. Refer Section 6.19.2 "PLL" additional information.
6.19.2
accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle. turned bypassed following chip reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time
6.19.3 Reset wake-up timer
Reset sources LPC2157/2158: RESET watchdog reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip reset source starts Wake-up Timer (see Wake-up Timer description below), causing internal chip reset remain asserted until external reset de-asserted, oscillator running, fixed number clocks have passed, on-chip flash controller completed initialization. When internal reset removed, processor begins executing address which reset vector. that point, processor peripheral registers have been initialized predetermined values. Wake-up Timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power types reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes Wake-up Timer. Wake-up Timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
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6.19.4 Brownout detector
LPC2157/2158 include 2-stage monitoring voltage pins. this voltage falls below asserts interrupt signal VIC. This signal enabled interrupt; not, software monitor signal reading dedicated register. second stage voltage detection asserts reset inactivate LPC2157/2158 when voltage pins falls below This reset prevents alteration flash operation various elements chip would otherwise become unreliable voltage. circuit maintains this reset down below which point circuitry maintains overall reset. Both thresholds include some hysteresis. normal operation, this hysteresis allows detection reliably interrupt, regularly-executed event loop sense condition.
6.19.5 Code security
This feature LPC2157/2158 allow application control whether debugged protected from observation. after reset on-chip bootloader detects valid checksum flash reads 0x8765 4321 from address 0x1FC flash, debugging will disabled thus code flash will protected from observation. Once debugging disabled, enabled only performing full chip erase using ISP.
6.19.6 External interrupt inputs
LPC2157/2158 include nine edge level sensitive external interrupt inputs selectable functions. When pins combined, external events processed four independent interrupt signals. external interrupt inputs optionally used wake-up processor from Power-down mode. Additionally capture input pins also used external interrupts without option wake device from Power-down mode.
6.19.7 Memory mapping control
Memory Mapping Control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom on-chip flash memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
6.19.8 Power control
LPC2157/2158 supports reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses.
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Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Selecting external clock instead PCLK clock-source on-chip will enable microcontroller have active during Power-down mode. Power-down current increased with active. However, significantly lower than Idle mode. Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings during active Idle mode.
6.19.9
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside bus), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.20 Emulation debugging
LPC2157/2158 supports emulation debugging JTAG serial port. Debugging functions multiplexed with GPIOs Port This means that communication, timer interface peripherals residing Port available during development debugging phase they when application embedded system itself.
6.20.1 EmbeddedICE
Standard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts remote debug protocol commands JTAG data needed access core. core Debug Communications Channel (DCC) function built-in. allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. accessed co-processor program running ARM7TDMI-S core. allows JTAG port used sending receiving data without affecting normal program flow. data control registers mapped addresses EmbeddedICE logic.
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6.20.2 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real-time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using DCC, which present EmbeddedICE logic. LPC2157/2158 contain specific configuration RealMonitor software programmed into on-chip flash memory.
6.21 driver
6.21.1 General description
segment driver LPC2157/2158 interface most LCDs using multiplex rates. generates drive signals static multiplexed LCDs containing four backplanes segments. controller communicates host using I2C-bus. I2C-bus clock data signals both microcontroller driver available LPC2157/2158 providing system flexibility. Communication overhead manage display minimized on-chip display with auto-increment addressing, hardware subaddressing, display memory switching (static duplex drive modes). Please refer PCF8576D data sheet electrical data.
6.21.2 Functional description
controller versatile peripheral device designed interface microcontrollers wide variety LCDs. directly drive static multiplexed containing four backplanes segments. display configurations possible with controller depend number active backplane outputs required. selection display configurations shown Table these configurations implemented typical system. microcontroller communicates controller using I2C-bus.The appropriate biasing voltages multiplexed waveforms generated internally. only other connections required complete system power supplies (VDD(LCD), VLCD) panel chosen application.
Table Number Backplanes Segments Selection display configurations 7-segments numeric Digits Indicator symbols 14-segments alphanumeric Characters Indicator symbols matrix
6.21.3 bias voltages
biasing voltages obtained from internal voltage divider consisting three series resistors connected between VLCD VSS. voltage temperature compensated externally supply VLCD. voltage selector drives multiplexing based programmable configurations.
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6.21.4 Oscillator
6.21.4.1 Internal clock internal oscillator provides clock signals internal logic controller drive signals. After power-up, must HIGH guarantee that clock starts.
6.21.5 Timing
controller timing controls internal data flow device. This includes transfer display data from display display segment outputs. timing also generates frame signal whose frequency derived from clock frequency. frame signal frequency fixed division clock frequency from either internal external clock. Frame frequency fosc(ctrl)LCD/24.
6.21.6 Display register
display latch holds display data while corresponding multiplex signals generated. There one-to-one relationship between data display latch, segment outputs, each column display RAM.
6.21.7 Segment outputs
drive section includes segment outputs S31. segment output signals generated according multiplexed backplane signals display latch data. When less than segment outputs required, unused segment outputs should left open-circuit.
6.21.8 Backplane outputs
drive section four backplane outputs BP3. backplane output signals generated accordance with selected drive mode. less than four backplane outputs required, unused outputs left open-circuit. multiplex drive mode, carries same signal BP1, therefore these adjacent outputs tied together give enhanced drive capabilities. multiplex drive mode, BP2, respectively carry same signals also paired increase drive capabilities. static drive mode same signal carried four backplane outputs they connected parallel very high drive requirements.
6.21.9 Display
display static 4-bit which stores data. There one-to-one correspondence between addresses segment outputs, between individual bits word backplane outputs. first column corresponds segments backplane (BP0). multiplexed applications segment data second, third fourth column display time-multiplexed with BP1, respectively.
6.21.10 Data pointer
Display addressed using data pointer. Either single byte series display bytes loaded into location display RAM.
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6.21.11 Output bank selector
controller includes bank switching feature static drive modes. static drive mode, BANK SELECT command request contents selected display instead contents mode, contents bits selected instead bits This allows display information prepared alternative bank then selected display when assembled.
6.21.12 Input bank selector
input bank selector loads display data into display based selected drive configuration. BANK SELECT command used load display data static drive mode bits mode. input bank selector functions independent output bank selector.
6.21.13 Blinker
controller very versatile display blinking capability. whole display blink frequency selected BLINK command. Each blink frequency multiple integer value clock frequency; ratio between clock frequency blink frequency depends blink mode selected, shown Table additional feature allows arbitrary selection segments blinked static drive modes. This implemented without communication overheads output bank selector which alternates displayed data between data display bank data alternative bank blink frequency. This mode also implemented BLINK command. entire display blinked frequency other than nominal blink frequency sequentially resetting setting display enable required rate using MODE command.
Table Blinking frequencies Normal operating mode ratio Normal blink frequency fosc(ctrl)LCD/768 fosc(ctrl)LCD/1536 fosc(ctrl)LCD/3072 blinking
Blink mode
Blink modes nominal blink frequencies correspond oscillator frequency (fosc(ctrl)LCD) 1536 CLK. oscillator frequency range 3046 6.21.13.1 I2C-bus controller controller acts I2C-bus slave receiver. LPC2157/2158 hardware subaddress inputs tied setting hardware subaddress
6.21.14 Input filters
enhance noise immunity electrically adverse environments, low-pass filters provided lines.
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6.21.15 I2C-bus slave addresses
I2C-bus slave address 0111 0000. controller write-only device will respond read access.
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Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDDA Vi(VBAT) Vi(VREF) Parameter supply voltage (core external rail) analog supply voltage input voltage VBAT input voltage VREF analog input voltage input voltage related pins tolerant pins; only valid when supply voltage present other pins Tstg Ptot(pack) supply current ground current storage temperature total power dissipation (per package) based package heat transfer, device power consumption supply ground
Conditions
-0.5 -0.5
+3.6 +4.6 +4.6 +4.6 +5.1 +6.0
Unit
-0.5 -0.5 -0.5 -0.5
[2][3]
-0.5
+150
following applies Limiting values: This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Including voltage outputs 3-state mode. exceed peak current limited times corresponding maximum current. Dependent package type.
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Static characteristics
Table Static characteristics Tamb commercial applications, unless otherwise specified. Symbol VDDA Vi(VBAT) Vi(VREF) Parameter supply voltage analog supply voltage input voltage VBAT input voltage VREF LOW-level input current OFF-state output current latch-up current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short-circuit output current LOW-level short-circuit output current pull-down current pull-up current VDDA
Conditions
Typ[1]
VDDA
Unit
Standard port pins, RESET, RTCK Ilatch Vhys IOHS IOLS pull-up VDD; pull-up/down -(0.5VDD) (1.5VDD); configured provide digital function output active
[4][5][6]
HIGH-level input current VDD; pull-down
[10]
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Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol IDD(act) Parameter active mode supply current Conditions Tamb code Typ[1] Unit
while(1){}
executed from flash, active peripherals CCLK CCLK Tamb code executed from flash; enabled active; other peripherals disabled CCLK CCLK IDD(pd) IBATpd Power-down mode supply current Power-down mode battery supply current Tamb Tamb clock (from RTCX pins); Tamb Vi(VBAT) Vi(VBAT) IBATact active mode battery supply current CCLK MHz; PCLK MHz; PCLK enabled RTCK; clock (from RTCX pins); Tamb Vi(VBAT) IBATact(opt) optimized active mode battery supply current PCLK disabled RTCK PCONP register; clock (from RTCX pins); Tamb Vi(VBAT) CCLK CCLK I2C-bus Vhys pins HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS Oscillator pins Vi(XTAL1) input voltage XTAL1
[11][12] [11] [11]
0.7VDD
0.5VDD
0.3VDD
[13]
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Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol Vo(XTAL2) Vi(RTCX1) Vo(RTCX2) pins VBUS Vth(rs)se OFF-state output current supply voltage differential input sensitivity voltage differential common mode voltage range single-ended receiver switching threshold voltage LOW-level output voltage HIGH-level output voltage transceiver capacitance
[14]
Parameter output voltage XTAL2 input voltage RTCX1 output voltage RTCX2
Conditions
Typ[1]
Unit
5.25
|(D+) (D-)| includes range
Ctrans ZDRV
driver output impedance steady state drive driver which high-speed capable pull-up resistance SoftConnect
Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. Core external rail. typically fails when Vi(VBAT) drops below Including voltage outputs 3-state mode. supply voltages must present. 3-state outputs into 3-state mode when grounded. Accounts voltage drop supply lines. Allowed long current limit does exceed maximum current allowed device. Minimum condition maximum condition
[10] Applies P1[16] P1[31]. [11] VBAT. [12] Optimized battery consumption. [13] VSS. [14] Includes external resistors
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Table static characteristics VDDA Tamb unless otherwise specified; frequency MHz. Symbol EL(adj) Rvsi Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance
monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure Figure
Conditions
VDDA ±0.5
Unit
VSSA VDDA VSSA VDDA VSSA VDDA VSSA VDDA VSSA VDDA
[1][2]
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
offset error (LSBideal)
VDDA VSSA 1024
002aac046
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
LPC2XXX
ADx[y]SAMPLE
ADx[y]
Rvsi
VEXT
002aad458
Suggested interface LPC2157/2158 ADx[y]
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Dynamic characteristics
Table Dynamic characteristics pins (full-speed) VDD, unless otherwise specified. Symbol tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise fall time matching output signal crossover voltage source interval source jitter differential transition transition receiver jitter next transition receiver jitter paired transitions width receiver must reject EOP; Figure must accept EOP; Figure
Conditions (tr/tf)
+18.5
Unit
Figure Figure
-18.5
tEOPR2
width receiver
Characterized implemented production test. Guaranteed design.
Table Dynamic characteristics Tamb commercial applications, over specified ranges[1] Symbol External clock fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL tr(o) tf(o) I2C-bus tf(o)
Parameter oscillator frequency clock cycle time clock HIGH time clock time clock rise time clock fall time output rise time output fall time pins (P0[2], P0[3], P0[11], P0[14]) output fall time
Conditions
Tcy(clk) Tcy(clk)
Typ[2]
Unit
Port pins (P0[2], P0[3], P0[11], P0[14])
Cb[3]
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. capacitance from
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Timing
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
External clock timing (with amplitude least Vi(RMS)
tPERIOD crossover point differential data lines
crossover point extended
source width: tFEOPT differential data SE0/EOP skew tPERIOD tFDEOP
receiver width: tEOPR1, tEOPR2
002aab561
Differential data-to-EOP transition skew width
Application information
10.1 Suggested interface solutions
CONNECT soft-connect switch
LPC2158
VBUS
002aad410
USB-B connector
LPC2158 interface using CONNECT function
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
LPC2158
UP_LED VBUS
USB-B connector
002aad411
LPC2158 interface using UP_LED function
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Package outline
LQFP100: plastic profile quad flat package; leads; body SOT407-1
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.75 0.45 0.08 0.08 1.15 0.85 1.15 0.85
16.25 16.25 15.75 15.75
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT407-1 REFERENCES 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-02-01 03-02-20
Package outline SOT407-1 (LQFP100)
LPC2157_2158_1 B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Abbreviations
Table Acronym AMBA FIFO GPIO JTAG UART Abbreviations Description Analog-to-Digital Converter Advanced High-performance Advanced Microcontroller Architecture Advanced Peripheral Brown-Out Detection Digital-to-Analog Converter Debug Communications Channel Direct Memory Access First First General Purpose Input/Output Input/Output In-System Programming Joint Test Action Group Microcontroller Unit Phase-Locked Loop Power-On Reset Pulse Width Modulator Resistance-Capacitance Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Revision history
Table Revision history Release date 20081015 Data sheet status Product data sheet Change notice Supersedes Document LPC2157_2158_1
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
14.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
14.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental
14.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V. GoodLink trademark B.V. SoftConnect trademark B.V.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
LPC2157_2158_1
B.V. 2008. rights reserved.
Product data sheet
Rev. October 2008
Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
Contents
6.5.1 6.7.1 6.8.1 6.9.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 6.18 6.18.1 6.19 6.19.1 6.19.2 6.19.3 6.19.4 6.19.5 6.19.6 General description Features Ordering information Block diagram Pinning information Pinning description Functional description Architectural overview. On-chip flash program memory On-chip static RAM. Memory map. Interrupt controller Interrupt sources. connect block Fast general purpose parallel Features 10-bit Features 10-bit Features device controller (LPC2158 only) Features UARTs Features I2C-bus serial controller Features serial controller. Features serial controller Features General purpose timers/external event counters Features Watchdog timer. Features Real-time clock Features Pulse width modulator Features System control Crystal oscillator Reset wake-up timer Brownout detector. Code security External interrupt inputs 6.19.7 Memory mapping control 6.19.8 Power control 6.19.9 6.20 Emulation debugging. 6.20.1 EmbeddedICE 6.20.2 RealMonitor 6.21 driver 6.21.1 General description 6.21.2 Functional description 6.21.3 bias voltages 6.21.4 Oscillator 6.21.4.1 Internal clock 6.21.5 Timing 6.21.6 Display register. 6.21.7 Segment outputs 6.21.8 Backplane outputs 6.21.9 Display RAM. 6.21.10 Data pointer 6.21.11 Output bank selector 6.21.12 Input bank selector. 6.21.13 Blinker 6.21.13.1 I2C-bus controller 6.21.14 Input filters 6.21.15 I2C-bus slave addresses Limiting values Static characteristics Dynamic characteristics Timing Application information 10.1 Suggested interface solutions Package outline Abbreviations Revision history Legal information 14.1 Data sheet status 14.2 Definitions 14.3 Disclaimers. 14.4 Trademarks Contact information Contents.
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2008.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: October 2008 Document identifier: LPC2157_2158_1

Single-chip 16-bit/32-bit microcontrollers; flash, with segment driver

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