August 2008 LM26003 Switching Regulator with High Efficiency Slee

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August 2008 LM26003 Switching Regulator with High Efficiency Slee

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LM26003 Switching Regulator with High Efficiency Sleep Mode
August 2008
LM26003 Switching Regulator with High Efficiency Sleep Mode
LM26003 switching regulator designed high efficiency requirements applications with stand-by modes. device features low-current sleep mode maintain efficiency under light-load conditions current-mode control accurate regulation over wide input voltage range. Quiescent current reduced 10.8 typically shutdown mode less than sleep mode. Forced mode also available disable sleep mode. LM26003 deliver continuous load current with fixed current limit, through internal N-channel switch. part wide input voltage range 4.0V operate with input voltages during line transients. Operating frequency adjustable from with single resistor synchronized external clock. Other features include Power good, adjustable soft-start, enable pin, input under-voltage protection, internal bootstrap diode reduced component count.
Features
High efficiency sleep mode typical sleep mode 10.8 typical shutdown mode 3.0V minimum input voltage 4.0V continuous input range 1.5% reference accuracy Cycle-by-cycle current limit Adjustable Frequency (150 kHz) Synchronizable external clock Power Good Flag Forced function Adjustable Soft-start TSSOP-20 exposed package Thermal Shut Down
Applications
Automotive Telematics Navigation systems In-Dash Instrumentation Battery Powered Applications Stand-by power home gateways/set-top boxes
Typical Application Circuit
30067601
2008 National Semiconductor Corporation
300676
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LM26003
Connection Diagram
30067602
View 20-Lead Exposed TSSOP Package
Ordering Information
Order Number LM26003MH LM26003MHX Package Type TSSOP-20EXP Package Drawing MXA20A Package Marking LM26003MH LM26003MH Supplied Units Rail 2500 Units Tape Reel
Descriptions
Name AVIN PGOOD COMP AGND PGND FREQ FPWM SYNC VBIAS BOOT Description Power supply input high side Power supply input high side Power supply input high side Power supply input supply Power Good pin. open drain output which goes high when output voltage greater than nominal. Enable analog level input pin. When pulled below 0.8V, device enters shutdown mode. Soft-start pin. Connect capacitor from this soft-start time. Compensation pin. Connect resistor capacitor pair compensate control loop. Feedback pin. Connect resistor divider between VOUT output voltage. Analog reference Power switching stage regulator Frequency adjust pin. Connect resistor from this operating frequency. FPWM logic level input pin. normal operation, connect GND. When pulled high, sleep mode operation disabled. Frequency synchronization pin. Connect external clock signal synchronized operation. SYNC must pulled non-synchronized operation. Connect external greater supply bypass internal regulator improved efficiency. used, VBIAS should tied GND. output internal regulator. Bypass with minimum capacitor. Bootstrap capacitor pin. Connect minimum ceramic capacitor from this generate gate drive bootstrap voltage. Switch pin. source internal N-channel switch. Switch pin. source internal N-channel switch. Switch pin. source internal N-channel switch. Exposed thermal connection. Connect GND.
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LM26003
Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Voltages from indicated pins GND: -0.3V (Note -0.3V VBIAS -0.3V -0.3V BOOT VSW-0.3V VSW+7V PGOOD -0.3V FREQ -0.3V SYNC -0.3V
FPWM Storage Temperature Power Dissipation (Note Recommended Lead Temperature Vapor Phase (70s) Infrared (15s) Susceptibility (Note Human Body Model
-0.3V -0.3V -65°C +150°C 3.1W
215°C 220°C (Note -40°C 125°C 3.0V
Operating Ratings
Operating Junction Temp. Supply Voltage (Note
Electrical Characteristics
Symbol System (Note IqSleep_VB (Note IqSleep_VDD IqPWM_VB IqPWM_VDD IBIAS_Sleep (Note IBIAS_PWM VOUT/VIN VOUT/IOUT ISS_Source Vbias_th Switching RDS(ON) Isw_off VFREQ range VSYNC Shutdown Current Quiescent Current Quiescent Current Quiescent Current Quiescent Current Bias Current Bias Current Feedback Voltage Bias Current
Specifications standard type 25°C only, limits boldface type apply over junction temperature (TJ) range -40°C +125°C. Unless otherwise stated, 12V. Minimum Maximum limits guaranteed through test, design, statistical correlation. Parameter Conditions (Note 10.8 0.16 0.65 1.217 1.236 0.00025 0.08 5.50 Specified IBIAS 92.5% full value 38V, RFREQ 62k, 124k, 240k SYNC rising SYNC falling Sync Hysteresis ISYNC FSYNC_UP FSYNC_DN SYNC Leakage Current Upper Frequency Synchronization Range Lower Frequency Synchronization Range compared nominal compared nominal 1.23 1.10 2.64 5.99 6.50 3.07 Unit
Sleep mode, VBIAS Sleep mode, VBIAS mode, VBIAS FPWM mode, VBIAS FPWM Sleep mode, VBIAS mode, VBIAS 1.20V 0.8V VCOMP 1.15V IVDD=
0.23 0.85 1.255 ±200
Output Voltage Line Regulation Output Voltage Load Regulation Output Voltage Soft-start Source Current VBIAS Voltage
Switch Resistance Switch State Leakage Current Switching Frequency FREQ Voltage Switching Frequency Range Sync Threshold
0.040
0.095 0.002
0.200
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LM26003
Symbol TOFFMIN TONMIN THSLEEP_HYS THWAKE IBOOT Protection ILIMPK VFB_SC F_min_sc VTH_PGOOD
Parameter Minimum Off-time Minimum On-time Sleep Mode Threshold Hysteresis Wake Threshold BOOT Leakage Current Peak Current Limit Short Circuit Frequency Foldback Threshold Frequency Foldback Power Good Threshold PGOOD Hysteresis
Conditions
(Note
Unit
rising, THWAKE Measured falling COMP 0.6V BOOT 3.15 Measured falling 0.3V Measured PGOOD rising PGOOD PGOOD sink current falling shutdown, rising, soft-start, 2.70 3.70
101.3 1.236 0.001 0.87 1.25 2.96 3.99 3.30 4.30 6.05
IPGOOD_HI RDS_PGOOD VUVLO
PGOOD Leakage Current PGOOD Resistance Under-voltage Lock-Out Threshold
Logic VthEN IEN_Source VTH_FPWM IFPWM ICOMP VCOMP
Thermal Shutdown Threshold Thermal Resistance Power dissipation lfpm flow Enable rising FPWM VCOMP 0.9V VCOMP 0.9V 0.575
°C/W
Enable Threshold Voltage Enable Hysteresis Source Current FPWM Threshold FPWM Leakage Current Error Trans-conductance COMP Source Current COMP Sink Current COMP Voltage Range
1.18 4.85 1.24
1000
µmho
1.365
Note Absolute Maximum Ratings indicate limits beyond which damage device occur, including inoperability degradation device reliability and/or performance. Functional operation device and/or non-degradation Absolute Maximum Ratings other conditions beyond those indicated recommended Operating Ratings implied. recommended Operating Ratings indicate conditions which device functional should operated beyond such conditions. Note maximum allowable power dissipation function maximum junction temperature, TJ_MAX, junction-to-ambient thermal resistance, ambient temperature, maximum allowable power dissipation ambient temperature calculated using: PD_MAX (TJ_MAX /JA. maximum power dissipation 3.1W determined using 25°C, 32°C/W, TJ_MAX 125°C. Note human body model capacitor discharged through resistor into each pin. Note Below 4.0V input, power dissipation increase increased RDS(ON). Therefore, minimum input voltage 4.0V required operate continuously within specification. minimum 3.9V (typical) also required startup. Note limits 100% production tested 25°C. Limits over operating temperature range guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits used calculate National's Average Outgoing Quality Level (AOQL). Note specify current into AVIN pins. IBIAS current into VBIAS when VBIAS voltage greater than quiescent current specifications apply non-switching operation. Note absolute maximum specification applies voltage. extended negative voltage limit applies pulse pulse
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LM26003
Typical Performance Characteristics
12V, 25°C. Efficiency Load Current (300 kHz)
Unless otherwise specified following conditions apply:
Efficiency Load Current (500 kHz)
30067637
30067639
Temperature
(IDC
30067634 30067636
IVBIAS Temperature (Sleep Mode)
IVBIAS Temperature (PWM Mode)
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30067638
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LM26003
Startup Waveforms
Peak Current Limit Temperature
30067647
30067641
Load Transient Response
Normalized Switching Frequency Temperature (300kHz)
30067646
30067643
UVLO Threshold Temperature (VDD VIN)
30067645
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LM26003
Block Diagram
30067603
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LM26003
Operation Description
GENERAL LM26003 current mode buck regulator. beginning each clock cycle, internal high-side switch turns allowing current ramp-up inductor. inductor current internally monitored during each switching cycle. control signal derived from inductor current compared voltage control signal COMP pin, derived from feedback voltage. When inductor current reaches threshold, high-side switch turned inductor current ramps-down. While switch off, inductor current supplied through catch diode. This cycle repeats next clock cycle. this way, duty-cycle output voltage controlled regulating inductor current. Current mode control provides superior line load regulation. Other benefits include cycle-by-cycle current limiting simplified compensation scheme. Typical waveforms shown Figure
30067605
FIGURE Sleep Mode Waveforms Load, sleep mode, quiescent current reduced less than (typical) when switching. sleep mode threshold roughly calculated according equation below:
Where Imin Ilim/16 (4.7A/16 typically) duty-cycle, defined (Vout+Vdiode)/Vin. When load current increases above this limit, LM26003 forced back into operation. sleep mode threshold varies with frequency, inductance, duty-cycle shown Figure
30067604
FIGURE Waveforms Load, SLEEP MODE light load conditions, LM26003 automatically switches into sleep mode improved efficiency. loading decreases, voltage increases COMP voltage decreases. When COMP voltage reaches 0.6V (typical) clamp threshold voltage rises above nominal, sleep mode enabled switching stops. regulator remains sleep mode until voltage falls reset threshold, which point switching resumes. This window limits corresponding output ripple requirement approximately nominal output voltage. sleep cycle will repeat until load current increased. Figure shows typical switching output voltage waveforms sleep mode.
30067607
FIGURE Sleep Mode Threshold Vout 3.3V FPWM Pulling FPWM high disables sleep mode forces LM26003 always operate mode. Light load efficiency reduced mode, switching frequency remains stable. FPWM connected pull high. FPWM mode, under light load conditions, regulator operates discontinuous conduction mode (DCM) discontinuous conduction mode, current through
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LM26003
inductor starts zero ramps-up peak, then ramps-down zero again. Until next cycle, inductor current remains zero. nominal load currents, FPWM mode, device operates continuous conduction mode, where positive current always flows inductor. Typical discontinuous operation waveforms shown below.
Where desired soft-start time soft-start source current. During soft-start, current limit synchronization remain effect, while sleep mode frequency foldback disabled. Soft-start mode ends when voltage reaches 1.23V typical. this point, output voltage control transferred discharged. CURRENT LIMIT peak current limit internally directly measuring peak inductor current through internal switch. ensure accurate current sensing, AVIN should bypassed with minimum ceramic capacitor close possible AVIN pins. Also PVIN should bypassed with least ensure jitter operation. When inductor current reaches current limit threshold, internal turns immediately allowing inductor current ramp-down until next cycle. This reduction dutycycle corresponds reduction output voltage. current limit comparator disabled less than leading edge increased immunity switching noise. Because current limit monitors peak inductor current, load current limit threshold varies with inductance frequency. Assuming minimum current limit 3.15A, maximum load current calculated follows:
30067608
FIGURE Discontinuous Mode Waveforms Load, very light load, FPWM mode, LM26003 enter sleep mode. This prevent over-voltage condition from occurring. However, FPWM sleep threshold much lower than normal operation. ENABLE LM26003 provides shutdown function disable device when output voltage does need maintained. analog level input with typically hysteresis. device active when above 1.18V (typical) shutdown mode when below this threshold. When goes high, internal regulator turns charges capacitor. When reaches 3.9V (typical), soft-start begins source current. shutdown mode, regulator shuts down total quiescent current reduced 10.8 (typical). Because sources 4.85 (typical) pull-up current, this left open always-on operation. When open, will pulled VIN. connected VIN, must connected through resistor limit noise spikes. also driven externally with maximum voltage 15V, whichever lower. SOFT-START soft-start feature provides controlled output voltage ramp-up startup. This reduces inrush current eliminates output overshoot turn-on. soft-start pin, must connected through capacitor. power-on, enable, UVLO recovery, internal (typical) current charges soft-start capacitor. During soft-start, error amplifier output voltage controlled both soft-start voltage feedback loop. voltage rampsup, duty-cycle increases proportional soft-start ramp, causing output voltage ramp-up. rate which duty-cycle increases depends capacitance soft-start capacitor. higher capacitance, slower output voltage ramps-up. soft-start capacitor value calculated with following equation:
Where Iripple peak-to-peak inductor ripple current, calculated shown below:
find worst case (lowest) current limit threshold, maximum input voltage minimum current limit specification. During high over-current conditions, such output short circuit, LM26003 employs frequency foldback second level protection. feedback voltage falls below short circuit threshold 0.9V, operating frequency reduced, thereby reducing average switch current. This especially helpful short circuit conditions, when inductor current rise very high during minimum on-time. Frequency reduction begins below nominal frequency setting. minimum operating frequency foldback mode typical. voltage falls below frequency foldback threshold during frequency synchronized operation, SYNC function disabled. Operating frequency versus voltage short circuit conditions shown typical performance characteristics section. conditions where on-time close minimum (less than typically), such high input voltage high switching frequency, current limit function properly. This because current limit circuit cannot reduce on-time below minimum which prevents entry into frequency foldback mode. There ways ensure proper current limit foldback operation under high input voltage conditions. First,
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LM26003
operating frequency reduced increase nominal on-time. Second, inductor value increased slow current ramp reduce peak over-current. FREQUENCY ADJUSTMENT SYNCHRONIZATION switching frequency LM26003 adjusted between using single external resistor. This resistor connected from FREQ ground shown typical application. resistor value calculated with following empirically derived equation: RFREQ (6.25 1010) fSW-1.042
VBIAS VBIAS used bypass internal regulator which provides bias voltage LM26003. When VBIAS connected voltage greater than internal regulator automatically switches over VBIAS input. This reduces current into (Iq) increases system efficiency. Using VBIAS added benefit reducing power dissipation within device. most applications where Vout 10V, VBIAS connected VOUT. used, VBIAS should tied GND. VBIAS drops below 2.9V (typical), device automatically switches over supply internal bias voltage from Vin. Total device input current gate drive current, VBIAS current, plus some negligible current into pin. Total minimum input supply current calculated shown below:
Where gate drive current, calculated (9.2 10-9) Total supply input current varies according load, system efficiency, operating frequency. calculate minimum input current during sleep mode, IqSleep_VB, IBIAS_SLEEP. input current mode, same equation, with IqPWM_VB, IBIAS_PWM. VBIAS connected ground, same equation with Ibias term eliminated either IqSleep_VDD IqPWM_VDD. When LM26003 powered with circuit's output voltage through VBIAS, especially output voltages such 3.3V, output ripple noise couple through Vbias causing some falling edge jitter switch node. avoid this, additional bypassing close VBIAS with capacitor implemented. circuit diagram Figure shows this bypass capacitor OPERATION UVLO LM26003 designed remain operational during short line transients when input voltage drop 3.0V. Minimum nominal operating input voltage 4.0V. Below this voltage, switch RDS(ON) increases, lower gate drive voltage from VDD. minimum voltage required approximately 3.5V normal operation within specification. also used pull-up voltage functions such PGOOD FPWM. Note that used externally, recommended loads greater than input voltage approaches nominal output voltage, duty-cycle maximized hold output voltage. this mode operation, once duty-cycle reaches maximum, LM26003 skip maximum seven pulses, effectively increasing duty-cycle thus minimizing dropout from input output. Typical off-pulse skipping waveforms shown below.
30067612
FIGURE Switching Frequency RFREQ switching frequency also synchronized external clock signal using SYNC pin. SYNC allows operating frequency varied above below nominal frequency setting. adjustment range from above nominal below nominal. External synchronization requires 1.23V minimum (typical) peak signal level SYNC pin. FREQ resistor must always connected initialize nominal operating frequency. operating frequency synchronized falling edge SYNC input. When SYNC goes low, high-side switch turns This allows duty-cycle used sync signal when synchronizing frequency higher than nominal. When synchronizing lower frequency, however, there minimum duty-cycle requirement SYNC signal, given equation below:
Where fnom nominal switching frequency FREQ resistor, fsync square wave. SYNC used, must pulled normal operation. pull-down resistor recommended protect against missing sync signal. Although LM26003 designed operate kHz, maximum load current limited higher frequencies increased temperature rise. Thermal Considerations section.
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LM26003
PGOOD power good pin, PGOOD, available monitor output voltage status. internally connected open drain MOSFET, which remains open while output voltage within operating range. PGOOD goes (low impedance ground) when output falls below nominal pulled low. When output voltage returns within nominal, measured pin, PGOOD returns high state. improved noise immunity, there delay between PGOOD threshold PGOOD going low.
Design Information
30067615
FIGURE Off-Pulse Skipping Waveforms 3.5V, Vnom 3.3V, fnom UVLO sensed both VDD, activated when either voltage falls below 2.96V (typical). Although typically less than below VIN, will discharge through VIN. Therefore when voltage drops rapidly, remain high, especially sleep mode. fast line voltage transients, using larger capacitor help hold UVLO shutdown extending discharge time. holding VDD, larger also reduce RDS(ON) (and dropout voltage) conditions. Alternately, under heavy loading voltage fall several hundred below VIN. this case, UVLO triggered even though voltage above UVLO threshold. When UVLO activated LM26003 enters standby state which remains charged. input voltage voltage rise above 3.99V (typical) device will restart from soft-start mode.
EXAMPLE CIRCUIT Figure shows complete typical application schematic. components have been selected based design criteria given following sections. SETTING OUTPUT VOLTAGE output voltage ratio voltage divider shown typical application. resistor values determined following equation:
Where 1.236V typically. maximum value recommended input voltage decreases towards nominal output voltage, LM26003 skip seven off-pulses described Operation section. output voltage applications, on-time reaches TonMIN, device will skip on-pulses maintain regulation. There limit number pulses that skipped. this mode operation, however, output ripple voltage increase slightly.
30067616
FIGURE Example Circuit
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LM26003
INDUCTOR output inductor should selected based inductor ripple current. amount inductor ripple current compared load current, ripple content, defined Iripple/ Iload. Ripple content should less than 40%. Inductor ripple current, Iripple, calculated shown below:
Larger ripple content increases losses inductor reduces effective current limit. Larger inductance values result lower output ripple voltage higher efficiency, slightly degraded transient response. Lower inductance values allow smaller case size, increased ripple lowers effective current limit threshold. Remember that inductor value also affects sleep mode threshold shown Figure When choosing inductor, saturation current rating must higher than maximum peak inductor current current rating should higher than maximum load current. Peak inductor current, Ipeak, calculated
Where allowed voltage excursion during load transient, maximum expected load transient. total high, load transient requirement cannot met, matter large output capacitance. criteria ripple voltage transient excursion cannot met, more capacitors should used parallel. non-ceramic capacitors, minimum output capacitance secondary importance, determined only load transient requirement. there enough capacitance, output voltage excursion will exceed maximum allowed value even maximum requirement met. minimum capacitance calculated follows:
assumed total ESR, greater than ReMAX. Also, assumed that already been selected. Generally speaking, output capacitance requirement decreases with typical value greater than works well most applications. INPUT CAPACITOR switching converter, very fast switching pulse currents drawn from input rail. Therefore, input capacitors required reduce noise, EMI, ripple input LM26003. Capacitors must selected that handle both maximum ripple current highest ambient temperature well maximum input voltage. equation calculating input ripple current shown below:
example, maximum load ripple content 10%, peak inductor current equal 3.15A which safely minimum current limit 3.15A. increasing inductor size, ripple content peak inductor current lowered, which increases current limit margin. size output inductor also determined using desired output ripple voltage, Vrip. equation determine minimum inductance value based Vrip follows:
Where output capacitors, Vrip peak-to-peak value. This equation assumes that output capacitors have some amount ESR. does apply ceramic output capacitors. this method used, ripple content should still verified less than that peak currents exceed minimum current threshold. OUTPUT CAPACITOR primary criterion selecting output capacitor equivalent series resistance, ESR. (Re) selected based requirements output ripple voltage transient response. Once inductor value been selected, ripple voltage calculated given using equation above LMIN. Lower values result lower output ripple. also calculated from following equation:
noise suppression, ceramic capacitor range should placed close possible PVIN pin. AVIN also some decoupling necessary. very important that decoupled with such capacitor close AGND avoid switching noise couple into Also some input filtering implemented using small resistor between PVIN AVIN. figure resistor value selected increased filter with different time constants depending capacitor value used. When using resistor, keep mind that resistance will increase minimum input voltage threshold voltage drop across resistor. PVIN decoupling should implemented minimize trace length between capacitor Schottky diode gnd. larger, high input capacitor should also used. This capacitor recommended damping input voltage spikes during power holding input voltage during transients. input voltage applications, line transients fall below UVLO threshold there enough input capacitance. Both tantalum electrolytic type capacitors suitable bulk capacitor. However, large tantalums available high input voltages their working voltage must derated least
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LM26003
BOOTSTRAP drive voltage internal switch supplied BOOT pin. This must connected ceramic capacitor, Cboot, from switch node, shown typical application. LM26003 provides voltage internally, external diode needed. minimum value recommended Cboot. Smaller values result insufficient hold time drive voltage increased power dissipation. During operation, when on-time extended, bootstrap capacitor risk discharging. Cboot capacitor discharged below approximately 2.5V, LM26003 enters high frequency re-charge mode. Cboot re-charged synchronous shown block diagram. Switching returns normal when Cboot been recharged. CATCH DIODE When internal switch off, output current flows through catch diode. Alternately, when switch diode sees reverse voltage equal Vin. Therefore, important parameters selecting catch diode peak current peak inverse voltage. average current through diode given IDAVE Iload (1-D) Where duty-cycle, defined Vout/Vin. catch diode conducts largest currents during lowest dutycycle. Therefore IDAVE should calculated assuming maximum input voltage. diode should rated handle this current continuously. over-current short circuit conditions, catch diode should rated handle peak currents equal peak current limit. peak inverse voltage rating diode must greater than maximum input voltage. Schottky diode must used. It's forward voltage maximizes efficiency BOOT voltage, while also protecting against large negative voltage spikes. When selecting catch diode high efficiency output load applications, select Schottky diode with reverse leakage current. Also keep mind that reverse leakage current Schottky diode increases with temperature with reverse voltage. Reverse voltage equals roughly input voltage buck converter. hot, diode reverse leakage current larger than current consumption LM26003. COMPENSATION purpose loop compensation ensure stable operation while maximizing dynamic performance. Stability analyzed with loop gain measurements, while dynamic performance analyzed with both loop gain load transient response. Loop gain equal product control-output transfer function (power stage) feedback transfer function (the compensation network). stability purposes, target have loop gain slope that -20dB /decade from very frequency beyond crossover frequency. Also, crossover frequency should exceed one-fifth switching frequency, i.e. case switching frequency. dynamic purposes, higher bandwidth, faster load transient response. downside high bandwidth that increases regulators susceptibility board noise which ultimately leads excessive falling edge jitter switch node voltage.
large gain means high regulation accuracy (i.e. voltage changes little with load line variations). achieve this loop gain, compensation components should according shape control-output bode plot. typical plot shown Figure below.
30067624
FIGURE Control-Output Transfer Function control-output transfer function consists pole (fp), zero (fz), double pole (half switching frequency). Referring Figure following should done create -20dB /decade roll-off loop gain: Place pole (fpc) Place zero (fzc) Place second pole (fpc1) resulting feedback (compensation) bode plot shown below Figure Adding control-output response feedback response will then result nearly continuous -20db/decade slope.
30067625
FIGURE Feedback Transfer Function control-output corner frequencies determined approximately following equations:
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LM26003
second pole (fpc1) also placed This pole created with single capacitor, minimum value this capacitor calculated
Where output capacitance, load resistance, output capacitor ESR, switching frequency. effects slope compensation current sense gain included this equation. However, equation approximation intended simplify loop compensation calculations. Since determined output network, shifts with loading. Determine range frequencies (fpmin/max) across expected load range. Then determine compensation values described below shown Figure
necessary applications. However operating frequency being synchronized below nominal frequency, recommended. Although required stability, very helpful suppressing noise. phase lead capacitor also added increase phase gain margins. phase lead capacitor most helpful high input voltage applications when synchronizing frequency greater than nominal. This capacitor, shown Figure should placed parallel with feedback resistor, introduces additional zero pole compensation network. These frequencies calculated shown below:
phase lead capacitor will boost loop phase around region zero frequency, fzff. fzff should placed somewhat below fpz1 frequency However, large, will have effect.
Layout
30067627
FIGURE Compensation Network compensation network automatically introduces frequency pole (fpc), which close Once range determined, should calculated using:
Where desired feedback gain between transconductance error amplifier. gain value around (3.3v/v) generally good starting point. Bandwidth increases with increasing values Next, place zero (fzc) near using determined with following equation:
selected value should place within decade above below fpmax less than fpmin. higher value (closer fpmin) generally provides more stable loop, high value will slow transient response time. Conversely, smaller value will result faster transient response, lower phase margin.
Good board layout critical switching regulators such LM26003. First, ground plane area must sufficient thermal dissipation purposes, second, appropriate guidelines must followed reduce effects switching noise. Switch mode converters very fast switching devices. such devices, rapid increase input current combined with parasitic trace inductance generates unwanted Ldi/dt noise spikes node also node. magnitude this noise tends increase output current increases. This parasitic spike noise turn into electromagnetic interference (EMI) also cause problems device performance. Therefore, care must taken layout minimize effect this switching noise. current sensing circuit current mode devices easily affected switching noise. This noise cause dutycycle jitter which leads increased spectrum noise. Although LM26003 blanking time beginning every cycle ignore this noise, some noise remain after blanking time. Following important guidelines below will help minimize switching noise effect current sensing. switch node area should small possible. catch diode, input capacitors, output capacitors should grounded same local ground, with bulk input capacitor grounded close possible catch diode anode. Additionally, ground area between catch diode bulk input capacitor very noisy should somewhat isolated from rest ground plane.
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LM26003
ceramic input capacitor must connected close possible AVIN well PVIN pin. capacitor between AVIN ground should grounded close pins LM26003 PVIN capacitor should grounded close Schottky diode ground. Often, AVIN bypass capacitor most easily located bottom side PCB. increases trace inductance vias, reduces trace length however. above layout recommendations illustrated below Figure
inductor switch node. Application Note AN-1229 more information regarding layout switching regulators.
Thermal Considerations
Although LM26003 built current limit, ambient temperatures above 80°C, device temperature rise limit actual maximum load current. Therefore, temperature rise must taken into consideration determine maximum allowable load current. Temperature rise function power dissipation within device. following equations used calculate power dissipation (PD) temperature rise, where total switching losses, losses, drive losses, VBIAS losses: PDTOTAL PswAC PswDC PVBIAS
PswDC Iload2 (0.095 0.00065 25)) 10-9 PVBIAS Vbias IVBIAS Given this total power dissipation, junction temperature calculated follows: (PDTOTAL Where 32°C/W (typically) when using multi-layer board with large copper plane area. varies with board type metallization area. calculate maximum allowable power dissipation, assume 125°C. ensure that junction temperature does exceed maximum operating rating 125°C, power dissipation should verified maximum expected operating frequency, maximum ambient temperature, minimum maximum input voltage. calculated maximum load current based continuous operation exceeded during transient conditions. power dissipation remains above maximum allowable level, device temperature will continue rise. When junction temperature exceeds maximum, LM26003 engages Thermal Shut Down (TSD). TSD, part remains shutdown state until junction temperature falls within normal operating limits. this point, device restarts soft-start mode.
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FIGURE Example Layout good practice connect pin, small signal components (COMP, FREQ) separate ground plane, shown Figure GND, schematics signal ground symbol. Both exposed must connected ground. This quieter plane should connected high current ground plane quiet location, preferably near Vout ground shown dashed line Figure plane should made large possible, since also used thermal dissipation. Several vias placed directly below increase heat flow other layers when they available. recommended hole diameter 0.3mm. trace from resistor divider should short entire feedback trace must kept away from
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LM26003
Physical Dimensions inches (millimeters) unless otherwise noted
eTSSOP-20 Package 20-Lead Exposed TSSOP Package Package Number MXA20A
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LM26003
Notes
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LM26003 Switching Regulator with High Efficiency Sleep Mode
Notes
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August 2008 LM26003 Switching Regulator with High Efficiency Slee

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