L74VHC1GT14 L74VHC1GT14 single gate CMOS Schmitt-trigger inverter

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L74VHC1GT14 L74VHC1GT14 single gate CMOS Schmitt-trigger inverter

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Schmitt-Trigger Inverter/ CMOS Logic Level Shifter
L74VHC1GT14
L74VHC1GT14 single gate CMOS Schmitt-trigger inverter fabricated with silicon gate CMOS technology. achieves high speed operation similar equivalent Bipolar Schottky while maintaining CMOS power dissipation. internal circuit composed three stages, including buffer output which provides high noise immunity stable output. device input compatible with TTL-type input thresholds output full CMOS level output swing. input protection circuitry this device allows overvoltage tolerance input, allowing device used logic-level translator from CMOS logic CMOS Logic from CMOS logic CMOS Logic while operating high-voltage power supply. L74VHC1GT14 input structure provides protection when voltages applied, regardless supply voltage. This allows L74VHC1GT14 used interface circuits circuits. output structures also provide protection when These input output structures help prevent device destruction caused supply voltage input/output voltage mismatch, battery backup, insertion, etc. LMC74VHC1GT14 used enhance noise immunity square slowly changing waveforms. High Speed: (Typ) Power Dissipation: (Max) 25°C TTL-Compatible Inputs: CMOS-Compatible Outputs: Load Power Down Protection Provided Inputs Outputs Balanced Propagation Delays Function Compatible with Other Standard Logic Families Chip Complexity: FETs 100; Equivalent Gates
MARKING DIAGRAMS
SC-70/SC-88A/SOT-353 SUFFIX Date Code
Figure Pinout (Top View)
Figure Logic Symbol
Date Code
SOT-23/TSOP-5/SC-59 SUFFIX
ASSIGNMENT
FUNCTION TABLE
Inputs Output
ORDERING INFORMATION
detailed ordering shipping information package dimensions section page this data sheet.
L74VHC1GT14
MAXIMUM RATINGS
Value Unit +7.0 CC=0 +7.0 High State -0.5 Input Diode Current Output Diode Current GND; Output Current, Supply Current, Power dissipation still SC-88A, TSOP-5 Thermal resistance SC-88A, TSOP-5 °C/W Lead Temperature, from Case Junction Temperature Under Bias Storage temperature +150 Withstand Voltage Human Body Model (Note >2000 Machine Model (Note Charged Device Model (Note LATCH-UP Latch-Up Performance Above Below 125°C (Note Maximum Ratings those values beyond which damage device occur. Exposure these conditions conditions beyond those indicated adversely affect device reliability. Functional operation under absolute-maximum-rated conditions implied. Functional operation should restricted Recommended Operating Conditions. Tested EIA/JESD22-A114-A Tested EIA/JESD22-A115-A Tested JESD22-C101-A Tested EIA/JESD78 Supply Voltage Input Voltage Output Voltage RECOMMENDED OPERATING CONDITIONS Symbol Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Range Input Rise Fall Time Symbol Parameter
High State NORMALIZED FAILURE RATE
Unit ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME 0.1% BOND FAILURES
Junction Temperature Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4
1000
TIME, YEARS
Figure Failure Rate Time Junction Temperature
L74VHC1GT14
ELECTRICAL CHARACTERISTICS Symbol Parameter Positive Threshold Voltage Negative Threshold Voltage Hysteresis Voltage Test Conditions 25°C 85°C -55°C<TA<125°C Unit 1.20 1.40 1.60 1.60 1.58 1.74 2.00 Minimum High-Level Output Voltage Maximum Low-Level Output Voltage MinL 1.79 1.94 0.35 0.76 0.30 0.40 2.58 3.94 0.36 0.36 ±0.1 1.35 1.01 1.13 0.64 0.73 2.10 0.93 1.18 1.29 1.20 1.40 1.60 0.35 0.35 0.30 1.20 0.30 0.40 1.40 0.40 0.50 1.60 0.50 2.48 3.80 0.44 0.44 ±1.0 1.50 2.34 3.66 0.52 0.52 ±1.0 1.65
1.20 1.40 1.60
0.50 0.81
Maximum Input Leakage Current Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current
to5.5 Input:
ELECTRICAL CHARACTERISTICS load Input 25°C Symbol Parameter Maximum Propagation Delay, Input Test Conditions 3.3± 5.0± Maximum Input Capacitance Power Dissipation Capacitance (Note 12.8 16.3 10.6
85°C -55°C<TA<125°C 15.0 18.5 10.0 12.0
Unit 17.0 20.5 11.5 13.5
Typical 25°C,
defined value internal equivalent capacitance which calculated from operating current consumption without load. Average operating current obtained equation: CC(OPR) used determine load dynamic power consumption;
L74VHC1GT14
3.0V
Figure Switching Waveforms
*Includes probe capacitance
Figure Test Circuit
DEVICE ORDERING INFORMATION Device Nomenclature
Device Temp Order Number Circuit Device Range Technology Indicator Function Identifier L74VHC1GT14DFT1 L74VHC1GT14DFT2 L74VHC1GT14DTT1 VHC1G VHC1G VHC1G Package Suffix Tape Reel Suffix Package Type (Name/SOT#/ Common Name) Tape Reel Size
SC-70/SC-88A/ SOT-353 SC-70/SC-88A/ SOT-353 SOT-23/TSOPS/ SC-59
3000 Unit 3000 Unit 3000 Unit
L74VHC1GT14
PACKAGE DIMENSIONS
SC70-5/SC-88A/SOT-353 SUFFIX
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. 419A-01 OBSOLETE. STANDARD 419A-02. DIMENSIONS INCLUDE MOLD FLASH, PROTRUSIONS, GATE BURRS. INCHES 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 0.004 0.004 0.010 0.004 0.012 0.008 0.079 0.087 MILLIMETERS 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 0.10 0.10 0.25 0.10 0.30 0.20 2.00 2.20
(0.008)
SOLDERING FOOTPRINT*
0.50 0.0197
0.65 0.025 0.65 0.025 0.40 0.0157
0.0748
SCALE 20:1
inches
L74VHC1GT14
PACKAGE DIMENSIONS
SOT23-5/TSOP-5/SC59-5 SUFFIX
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS MINIMUM THICKNESS BASE MATERIAL. DIMENSIONS INCLUDE MOLD FLASH, PROTRUSIONS, GATE BURRS. MILLIMETERS 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 2.50 3.00 INCHES 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0.0985 0.1181
0.05 (0.002)
SOLDERING FOOTPRINT*
0.074
0.95 0.037
0.094 0.039 0.028
SCALE 10:1
inches

L74VHC1GT14 L74VHC1GT14 single gate CMOS Schmitt-trigger inverter

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