LTC2285IUP#3CGPBF 14-bit 135Msps, power dual 3.3V converter designed d
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LTC2285IUP#3CGPBF Dual 14-Bit, 135Msps Power 3.3V DESCRIPTION
LTC2285IUP#3CGPBF 14-bit 135Msps, power dual 3.3V converter designed digitizing high frequency, wide dynamic range signals. LTC2285IUP#3CGPBF perfect demanding imaging communications applications with performance that includes 72.2dB 82dB SFDR signals Nyquist frequency. Typical specs include ±1.5LSB INL, ±0.6LSB DNL. transition noise 1.3LSBRMS. single 3.3V supply allows power operation. separate output supply allows outputs drive 0.5V 3.6V logic. single-ended input controls converter operation. optional clock duty cycle stabilizer allows high performance full speed wide range clock duty cycles. data ready output clock (CLKOUT) used latch output data.
Lare registered trademarks Linear Technology Corporation. other trademarks property their respective owners.
Integrated Dual 14-Bit ADCs Sample Rate: 135Msps Single 3.3V Supply (2.85V 3.4V) Power: 954mW 72.4dB SNR, 88dB SFDR 110dB Channel Isolation 100MHz Flexible Input: 1VP-P 2VP-P Range 640MHz Full Power Bandwidth Clock Duty Cycle Stabilizer Shutdown Modes Data Ready Output Clock Compatible Family 125Msps: LTC2283 (12-Bit), LTC2285 (14-Bit) 105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit) 80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit) 65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit) 40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit) 64-Pin (9mm 9mm) Package
APPLICATIONS
Wireless Wired Broadband Communication Imaging Systems Spectral Analysis Portable Instrumentation
TYPICAL APPLICATION
ANALOG INPUT INPUT OVDD 14-BIT PIPELINED CORE OUTPUT DRIVERS D13A OGND (dBFS)
Input Frequency, -1dB, Range
CLOCK/DUTY CYCLE CONTROL CLOCK/DUTY CYCLE CONTROL
CLKOUT
OVDD
ANALOG INPUT INPUT
14-BIT PIPELINED CORE
OUTPUT DRIVERS
D13B OGND
2285 TA01
2285 TA01b INPUT FREQUENCY (MHz)
2285iup#3cgpbf
LTC2285IUP#3CGPBF ABSOLUTE MAXIMUM RATINGS
OVDD (Notes
CONFIGURATION
VIEW SENSEA VCMA MODE SHDNA DA13 DA12 DA11 DA10 OGND OVDD AINA+ AINA- REFHA REFHA REFLA REFLA CLKA CLKB REFLB REFLB REFHB REFHB AINB- AINB+ CLKOUT DB13 DB12 DB11 DB10 PACKAGE 64-LEAD (9mm 9mm) PLASTIC TJMAX 150°C, 20°C/W EXPOSED (PIN MUST SOLDERED
Supply Voltage (VDD) Digital Output Ground Voltage (OGND) -0.3V Analog Input Voltage (Note .-0.3V (VDD 0.3V) Digital Input Voltage.-0.3V (VDD 0.3V) Digital Output Voltage -0.3V (OVDD 0.3V) Power Dissipation .1500mW Operating Temperature Range LTC2285IUP#3CGPBF -20°C 85°C Storage Temperature Range. -65°C 150°C
ORDER INFORMATION
LEAD FREE FINISH LTC2285IUP#3CGPBF PART MARKING LTC2285UP PACKAGE DESCRIPTION 64-Lead (9mm 9mm) Plastic TEMPERATURE RANGE -20°C 85°C Consult Marketing parts specified with wider operating temperature ranges. more information lead free part marking, http://www.linear.com/leadfree/ more information tape reel specifications,
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise SENSE Internal Reference External Reference External Reference Differential Analog Input (Note Differential Analog Input (Note External Reference CONDITIONS
CONVERTER CHARACTERISTICS
SENSEB VCMB SHDNB OGND OVDD
±1.5
UNITS Bits
-2.5
±0.6 ±0.5 ±0.3
V/°C ppm/°C ppm/°C LSBRMS
2285iup#3cgpbf
LTC2285IUP#3CGPBF ANALOG INPUT
SYMBOL VIN,CM ISENSE IMODE tJITTER CMRR PARAMETER Analog Input Range (AIN+ -AIN-) Analog Input Common Mode (AIN+ +AIN-)/2 Analog Input Leakage Current SENSEA, SENSEB Input Leakage MODE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth Figure Test Circuit
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS 2.85V 3.4V (Note Differential Input Drive (Note Single Ended Input Drive (Note AIN+, AIN- SENSEA, SENSEB MODE
±0.5V
UNITS psRMS
DYNAMIC ACCURACY
SYMBOL PARAMETER Signal-to-Noise Ratio
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. -1dBFS. (Note
CONDITIONS 5MHz Input 30MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range Harmonic 5MHz Input 30MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range Harmonic Higher 5MHz Input 30MHz Input 70MHz Input 140MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input Intermodulation Distortion Crosstalk 40MHz, 41MHz 100MHz
72.4 72.3
UNITS
72.2 71.7
72.2
71.9 70.2 -110
2285iup#3cgpbf
LTC2285IUP#3CGPBF INTERNAL REFERENCE CHARACTERISTICS
PARAMETER Output Voltage Output Tempco Line Regulation Output Resistance 2.85V 3.4V CONDITIONS IOUT
(Note
1.475 1.500 1.525 UNITS ppm/°C mV/V
|IOUT|
DIGITAL INPUTS DIGITAL OUTPUTS
SYMBOL LOGIC OUTPUTS OVDD 3.3V ISOURCE ISINK OVDD 2.5V OVDD 1.8V High Level Output Voltage Level Output Voltage -200A 1.6mA High Level Output Voltage Level Output Voltage -200A 1.6mA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Level Output Voltage High (Note VOUT VOUT 3.3V -10A -200A 1.6mA PARAMETER High Level Input Voltage Level Input Voltage Input Current Input Capacitance CONDITIONS 3.3V 3.3V (Note LOGIC INPUTS (CLK, SHDN, MUX)
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
UNITS
3.29 3.25 0.005 0.09 2.49 0.09 1.79 0.09
2285iup#3cgpbf
LTC2285IUP#3CGPBF
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
SYMBOL OVDD IVDD PDISS PSHDN PNAP PARAMETER Analog Supply Voltage Output Supply Voltage Supply Current Power Dissipation Shutdown Power (Each Channel) Mode Power (Each Channel) CONDITIONS (Note (Note Both ADCs fS(MAX) Both ADCs fS(MAX) SHDN SHDN
POWER REQUIREMENTS
2.85
1072
UNITS
TIMING CHARACTERISTICS
SYMBOL PARAMETER Sampling Frequency Time High Time Sample-and-Hold Aperture Delay DATA Delay CLKOUT Delay DATA CLKOUT Skew DATA Delay Data Access Time After Relinquish Time Pipeline Latency
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS (Note Duty Cycle Stabilizer (Note Duty Cycle Stabilizer (Note Duty Cycle Stabilizer (Note Duty Cycle Stabilizer (Note (Note (Note (Note (Note (Note (Note
-0.6
UNITS Cycles
Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Rating condition extended periods affect device reliability lifetime. Note voltage values with respect ground with OGND wired together (unless otherwise noted). Note When these voltages taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below above without latchup. Note 3.3V, fSAMPLE 135MHz, input range 2VP-P with differential drive, unless otherwise noted.
Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Offset error offset voltage measured from -0.5 when output code flickers between 0000 0000 0000 1111 1111 1111. Note Guaranteed design, subject test. Note 3.3V, fSAMPLE 135MHz, input range 1VP-P with differential drive. supply current power dissipation total both channels with both channels active. Note Recommended operating conditions.
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LTC2285IUP#3CGPBF TYPICAL PERFORMANCE CHARACTERISTICS
Crosstalk Input Frequency
-100 -105 -110 -115 -120 -125 -130 INPUT FREQUENCY (MHz)
2285
Typical INL, Range, 125Msps
ERROR (LSB) ERROR (LSB) -0.2 -0.4 -0.6 -0.8 -1.0 4096 8192 CODE 12288 16384
2285
Typical DNL, Range, 125Msps
CROSSTALK (dB)
-0.5 -1.0 -1.5 -2.0
4096
8192 CODE
12288
16384
2285
8192 Point FFT, 5MHz, -1dB, Range, 125Msps
AMPLITUDE (dB) AMPLITUDE (dB) -100 -110 -120 FREQUENCY (MHz)
2285
8192 Point FFT, 30MHz, -1dB, Range, 125Msps
-100 -110 -120 FREQUENCY (MHz)
2285
8192 Point FFT, 70MHz, -1dB, Range, 125Msps
AMPLITUDE (dB) -100 -110 -120 FREQUENCY (MHz)
2285
8192 Point FFT, 140MHz, -1dB, Range, 125Msps
AMPLITUDE (dB) -100 -110 -120 FREQUENCY (MHz)
2285
8192 Point 2-Tone FFT, 28.2MHz 26.8MHz, -1dB, Range, 125Msps
AMPLITUDE (dB) COUNT -100 -110 -120 FREQUENCY (MHz)
2285
Grounded Input Histogram, 125Msps
20000 18000 16000 14000 12000 10000 8000 6000 4000 2000 3380 8183 8185 8187 8189 CODE 3316 8191 8193
2285
17646 18027
11299
10516
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LTC2285IUP#3CGPBF TYPICAL PERFORMANCE CHARACTERISTICS
Input Frequency, -1dB, Range, 125Msps
SFDR (dBRS) (dBFS) 2285 INPUT FREQUENCY (MHz) 2285 INPUT FREQUENCY (MHz) 2285 SAMPLE RATE (Msps) SFDR (dBFS)
SFDR Input Frequency, -1dB, Range, 125Msps
SFDR Sample Rate, Range, 5MHz, -1dB
SFDR
Input Level, 70MHz, Range, 125Msps
SFDR (dBc dBFS) (dBc dBFS) INPUT LEVEL (dBFS) dBFS
SFDR Input Level, 70MHz, Range, 125Msps
dBFS IVDD (mA)
IVDD Sample Rate, 5MHz Sine Wave Input, -1dB
RANGE RANGE
2285
2285 INPUT LEVEL (dBFS)
SAMPLE RATE (Msps)
2285
IOVDD Sample Rate, 5MHz Sine Wave Input, -1dB, 0VDD 1.8V
(dBFS) IOVDD (mA) SAMPLE RATE (Msps)
2285
SENSE, 5MHz, -1dB
SENSE
2285
2285iup#3cgpbf
LTC2285IUP#3CGPBF FUNCTIONS
AINA+ (Pin Channel Positive Differential Analog Input. AINA- (Pin Channel Negative Differential Analog Input. REFHA (Pins Channel High Reference. Short together bypass Pins with 0.1F ceramic chip capacitor close possible. Also bypass Pins with additional 2.2F ceramic chip capacitor ground with ceramic chip capacitor. REFLA (Pins Channel Reference. Short together bypass Pins with 0.1F ceramic chip capacitor close possible. Also bypass Pins with additional 2.2F ceramic chip capacitor ground with ceramic chip capacitor. (Pins 63): Analog 3.3V Supply. Bypass with 0.1F ceramic chip capacitors. CLKA (Pin Channel Clock Input. input sample starts positive edge. CLKB (Pin Channel Clock Input. input sample starts positive edge. REFLB (Pins 12): Channel Reference. Short together bypass Pins with 0.1F ceramic chip capacitor close possible. Also bypass Pins with additional 2.2F ceramic chip capacitor ground with ceramic chip capacitor. REFHB (Pins 14): Channel High Reference. Short together bypass Pins with 0.1F ceramic chip capacitor close possible. Also bypass Pins with additional 2.2F ceramic chip capacitor ground with ceramic chip capacitor. AINB- (Pin 15): Channel Negative Differential Analog Input. AINB+ (Pin 16): Channel Positive Differential Analog Input. (Pins 64): Power Ground. SENSEB (Pin 19): Channel Reference Programming Pin. Connecting SENSEB VCMB selects internal reference ±0.5V input range. selects internal reference input range. external reference greater than 0.5V less than applied SENSEB selects input range ±VSENSEB. largest valid input range. VCMB (Pin 20): Channel 1.5V Output Input Common Mode Bias. Bypass ground with 2.2F ceramic chip capacitor. connect VCMA. (Pin 21): Digital Output Multiplexer Control. High, Channel comes DA0-DA13; Channel comes DB0-DB13. Low, output busses swapped Channel comes DB0-DB13; Channel comes DA0-DA13. multiplex both channels onto single output bus, connect MUX, CLKA CLKB together. (This recommended clock frequencies above 80Msps.) SHDNB (Pin 22): Channel Shutdown Mode Selection Pin. Connecting SHDNB results normal operation with outputs enabled. Connecting SHDNB results normal operation with outputs high impedance. Connecting SHDNB results mode with outputs high impedance. Connecting SHDNB results sleep mode with outputs high impedance. (Pin 23): Channel Output Enable Pin. Refer SHDNB function. DB13 (Pins 39): Channel Digital Outputs. DB13 MSB. OGND (Pins 50): Output Driver Ground. OVDD (Pins 49): Positive Supply Output Drivers. Bypass ground with 0.1F ceramic chip capacitor. CLKOUT (Pin 40): Data Ready Clock Output. Latch data falling edge CLKOUT. CLKOUT derived from CLKB. CLKA CLKB simultaneous operation. DA13 (Pins 56): Channel Digital Outputs. DA13 MSB. (Pin 57): Overflow/Underflow Output. High when overflow underflow occurred either channel channel (Pin 58): Channel Output Enable Pin. Refer SHDNA function.
2285iup#3cgpbf
LTC2285IUP#3CGPBF FUNCTIONS
SHDNA (Pin 59): Channel Shutdown Mode Selection Pin. Connecting SHDNA results normal operation with outputs enabled. Connecting SHDNA results normal operation with outputs high impedance. Connecting SHDNA results mode with outputs high impedance. Connecting SHDNA results sleep mode with outputs high impedance. MODE (Pin 60): Output Format Clock Duty Cycle Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE selects offset binary output format turns clock duty cycle stabilizer off. selects offset binary output format turns clock duty cycle stabilizer selects complement output format turns clock duty cycle stabilizer selects complement output format turns clock duty cycle stabilizer off. VCMA (Pin 61): Channel 1.5V Output Input Common Mode Bias. Bypass ground with 2.2F ceramic chip capacitor. connect VCMB. SENSEA (Pin 62): Channel Reference Programming Pin. Connecting SENSEA VCMA selects internal reference ±0.5V input range. selects internal reference input range. external reference greater than 0.5V less than applied SENSEA selects input range ±VSENSEA. largest valid input range. (Exposed Pad) (Pin 65): Power Ground. Exposed bottom package needs soldered ground.
FUNCTIONAL BLOCK DIAGRAM
AIN+ INPUT FIRST PIPELINED STAGE SECOND PIPELINED STAGE THIRD PIPELINED STAGE FOURTH PIPELINED STAGE FIFTH PIPELINED STAGE SIXTH PIPELINED STAGE AIN-
2.2F
1.5V REFERENCE
SHIFT REGISTER CORRECTION
RANGE SELECT
REFH SENSE
REFL
INTERNAL CLOCK SIGNALS OVDD
DIFF
CLOCK/DUTY CYCLE CONTROL
CONTROL LOGIC
OUTPUT DRIVERS
CLKOUT*
REFH
0.1F
REFL MODE SHDN
2285
OGND
2.2F CLKOUT SHARED BETWEEN BOTH CHANNELS.
Figure Functional Block Diagram (Only Channel Shown)
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LTC2285IUP#3CGPBF TIMING DIAGRAMS
Dual Digital Output Timing (Only Channel Shown)
ANALOG INPUT CLKA CLKB D0-D13, CLKOUT
2285 TD01
Multiplexed Digital Output Timing
tAPA ANALOG INPUT tAPB ANALOG INPUT CLKA CLKB
D0A-D13A
D0B-D13B
2285 TD02
CLKOUT
2285iup#3cgpbf
LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio signal-to-noise plus distortion ratio [S/(N ratio between amplitude fundamental input frequency amplitude other frequency components output. output band limited frequencies above below half sampling frequency. Signal-to-Noise Ratio signal-to-noise ratio (SNR) ratio between amplitude fundamental input frequency amplitude other frequency components except first five harmonics Total Harmonic Distortion Total harmonic distortion ratio harmonics input signal fundamental itself. out-of-band harmonics alias into frequency band between half sampling frequency. expressed 20log (V22 .Vn2 )/V1 where amplitude fundamental frequency through amplitudes second through harmonics. calculated this data sheet uses harmonics fifth. Intermodulation Distortion input signal consists more than spectral component, transfer function nonlinearity produce intermodulation distortion (IMD) addition THD. change sinusoidal input caused presence another sinusoidal input different frequency. pure sine waves frequencies applied input, nonlinearities transfer function create distortion products difference frequencies nfb, where etc. order intermodulation products intermodulation distortion defined ratio value either input tone value largest order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range peak harmonic spurious noise that largest spectral component excluding input signal This value expressed decibels relative value full-scale input signal. Input Bandwidth input bandwidth that input frequency which amplitude reconstructed fundamental reduced full scale input signal. Aperture Delay Time time from when reaches midsupply instant that input signal held sample hold circuit. Aperture Delay Jitter variation aperture delay time from conversion conversion. This random variation will result noise when sampling input. signal noise ratio jitter alone will SNRJITTER -20log tJITTER) Crosstalk Crosstalk coupling from channel (being driven full-scale signal) onto other channel (being driven -1dBFS signal). CONVERTER OPERATION shown Figure LTC2285IUP#3CGPBF dual CMOS pipelined multistep converter. converter pipelined stages; sampled analog input will result digitized value five cycles later (see Timing Diagram section). optimal performance analog inputs should driven differentially. cost sensitive applications, analog inputs driven single-ended
2285iup#3cgpbf
LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
with slightly worse harmonic distortion. input single-ended. LTC2285IUP#3CGPBF phases operation, determined state input pin. Each pipelined stage shown Figure contains ADC, reconstruction interstage residue amplifier. operation, quantizes input stage quantized value subtracted from input produce residue. residue amplified output residue amplifier. Successive stages operate phase that when stages outputting their residue, even stages acquiring that residue vice versa. When low, analog input sampled differentially directly onto input sample-and-hold capacitors, inside "Input S/H" shown Block Diagram. instant that transitions from high, sampled input held. While high, held input voltage buffered amplifier which drives first pipelined stage. first stage acquires output during this high phase CLK. When goes back low, first stage produces residue which acquired second stage. same time, input goes back acquiring analog input. When goes back high, second stage produces residue which acquired third stage. identical process repeated third, fourth fifth stages, resulting fifth stage residue that sent sixth stage final evaluation. Each stage following first additional range accommodate flash amplifier offset errors. Results from stages digitally synchronized such that results properly combined correction logic before being sent output buffer. SAMPLE/HOLD OPERATION INPUT DRIVE Sample/Hold Operation Figure shows equivalent circuit LTC2285IUP# 3CGPBF CMOS differential sample-and-hold. analog inputs connected sampling capacitors (CSAMPLE) through NMOS transistors. capacitors shown attached each input (CPARASITIC) summation other capacitance associated with each input. During sample phase when low, transistors connect analog inputs sampling capacitors they charge track differential input voltage. When transitions from high, sampled input voltage held sampling capacitors. During hold phase when high, sampling capacitors disconnected
LTC2285IUP#3CGPBF AIN+ CPARASITIC
CSAMPLE 3.5pF
CSAMPLE 3.5pF CPARASITIC
AIN-
2285
Figure Equivalent Input Circuit
2285iup#3cgpbf
LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
from input held voltage passed core processing. transitions from high low, inputs reconnected sampling capacitors acquire sample. Since sampling capacitors still hold previous sample, charging glitch proportional change voltage between samples will seen this time. change between last sample sample small, charging glitch seen input will small. input change large, such change seen with input frequencies near Nyquist, then larger charging glitch will seen. Single-Ended Input cost sensitive applications, analog inputs driven single-ended. With single-ended input harmonic distortion will degrade, will remain unchanged. single-ended input, AIN+ should driven with input signal AIN- should connected 1.5V VCM. Common Mode Bias optimal performance analog inputs should driven differentially. Each input should swing ±0.5V range ±0.25V range, around common mode voltage 1.5V. output used provide common mode bias level. tied directly center transformer input level reference level differential driver circuit. must bypassed ground close with 2.2F greater capacitor. Input Drive Impedance with high performance, high speed ADCs, dynamic performance LTC2285IUP#3CGPBF influenced input drive circuitry, particularly second third harmonics. Source impedance reactance influence SFDR. falling edge CLK, sample-and-hold circuit will connect 3.5pF sampling capacitor input start sampling period. sampling period ends when rises, holding sampled input sampling capacitor. Ideally input circuitry should fast enough fully charge sampling capacitor during sampling period 1/(2FENCODE); however, this always possible incomplete settling degrade SFDR. sampling glitch been designed linear possible minimize effects incomplete settling. best performance, recommended have source impedance less each input. source impedance should matched differential inputs. Poor matching will result higher even order harmonics, especially second. Input Drive Circuits Figure shows LTC2285IUP#3CGPBF being driven transformer with center tapped secondary. secondary center biased with VCM, setting input signal optimum level. Terminating transformer secondary desirable, this provides common mode path charging glitches caused sample hold. Figure shows turns ratio transformer. Other turns ratios used source impedance seen does exceed each input. disadvantage using transformer loss frequency response. Most small transformers have poor performance frequencies below 1MHz.
2.2F 0.1F ANALOG INPUT MA/COM ETC1-1T RESISTORS, CAPACITORS 0402 PACKAGE SIZE 0.1F 12pF AIN-
2285
AIN+
LTC2285IUP #3CGPBF
Figure Single-Ended Differential Conversion Using Transformer
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LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
HIGH SPEED DIFFERENTIAL AMPLIFIER ANALOG INPUT 2.2F
2.2F 0.1F LTC2285IUP #3CGPBF ANALOG INPUT 0.1F 0.1F AIN-
2285
AIN+
12pF
LTC2285IUP #3CGPBF
AIN-
2285
MA/COM, 1-1-13 RESISTORS, CAPACITORS 0402 PACKAGE SIZE
Figure Differential Drive with Amplifier
0.1F ANALOG INPUT 2.2F AIN+ LTC2285IUP #3CGPBF 0.1F ANALOG INPUT
2285
Figure Recommended Front Circuit Input Frequencies Between 70MHz 170MHz
2.2F
12pF 0.1F AIN-
AIN+ 0.1F
LTC2285IUP #3CGPBF
0.1F MA/COM, 1-1-13 RESISTORS, CAPACITORS 0402 PACKAGE SIZE AIN-
2285
Figure Single-Ended Drive
Figure demonstrates differential amplifier convert single ended input signal into differential input signal. advantage this method that provides frequency input response; however, limited gain bandwidth most amps will limit SFDR high input frequencies. Figure shows single-ended input circuit. impedance seen analog inputs should matched. This circuit recommended distortion required. resistors 12pF capacitor analog inputs serve purposes: isolating drive circuitry from sample-and-hold charging glitches limiting wideband noise converter input. input frequencies above 70MHz, input circuits Figure recommended. balun transformer gives better high frequency response than flux coupled center tapped transformer. coupling capacitors allow analog inputs biased 1.5V. Figure series inductors impedance matching elements that maximize bandwidth.
Figure Recommended Front Circuit Input Frequencies Between 170MHz 300MHz
2.2F 0.1F ANALOG INPUT 0.1F 8.2nH
2285
8.2nH 0.1F
AIN+
LTC2285IUP #3CGPBF
MA/COM, 1-1-13 RESISTORS, CAPACITORS, INDUCTORS 0402 PACKAGE SIZE
Figure Recommended Front Circuit Input Frequencies Above 300MHz
2285iup#3cgpbf
LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
Reference Operation Figure shows LTC2285IUP#3CGPBF reference circuitry consisting 1.5V bandgap reference, difference amplifier switching control circuit. internal voltage reference configured selectable input ranges (±1V differential) (±0.5V differential). Tying SENSE selects range; tying SENSE selects range. 1.5V bandgap reference serves functions: output provides bias point setting common mode voltage external input circuitry; additionally, reference used with difference amplifier generate differential reference levels needed internal circuitry. external bypass capacitor required 1.5V reference output, VCM. This provides high frequency impedance path ground internal external circuitry.
LTC2285IUP#3CGPBF 1.5V 2.2F RANGE DETECT CONTROL SENSE
2285
difference amplifier generates high reference ADC. High speed switching circuits connected these outputs they must externally bypassed. Each output pins. multiple output pins needed reduce package inductance. Bypass capacitors must connected shown Figure Each channel independent reference with bypass capacitors. channels used with same different input ranges. Other voltage ranges between selectable ranges programmed with external resistors shown Figure external reference used applying output directly through resistor divider SENSE. recommended drive SENSE with logic device. SENSE should tied appropriate level close converter possible. SENSE driven externally, should bypassed ground close device possible with ceramic capacitor. best channel matching, connect external reference SENSEA SENSEB.
1.5V 2.2F 0.75V SENSE LTC2285IUP #3CGPBF
1.5V BANDGAP REFERENCE 0.5V
RANGE; RANGE; RANGE VSENSE 0.5V VSENSE
BUFFER INTERNAL HIGH REFERENCE REFH
Figure 1.5V Range
Input Range
DIFF
2.2F
0.1F
REFL INTERNAL REFERENCE
2285
input range based application. input range will provide best signal-to-noise performance while maintaining excellent SFDR. input range will have better SFDR performance, will degrade 5.7dB. Typical Performance Characteristics section. Driving Clock Input inputs driven directly with CMOS level signal. sinusoidal clock also used along with jitter squaring circuit before (Figure 11).
2285iup#3cgpbf
Figure Equivalent Reference Circuit
LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
4.7F FERRITE BEAD 0.1F SINUSOIDAL CLOCK INPUT 0.1F NC7SVU04
2285 2285
CLEAN SUPPLY
4.7F FERRITE BEAD 0.1F
CLEAN SUPPLY
LTC2285IUP #3CGPBF
LTC2285IUP #3CGPBF
LVDS FIN1002 FIN1018. PECL, AZ1000ELT21 SIMILAR
Figure Sinusoidal Single-Ended Drive
Figure Drive Using LVDS PECL CMOS Converter
noise performance LTC2285IUP#3CGPBF depend clock signal quality much analog input. noise present clock signal will result additional aperture jitter that will summed with inherent aperture jitter. applications where jitter critical, such when digitizing high input frequencies, large amplitude possible. Also, clocked with sinusoidal signal, filter signal reduce wideband noise distortion products generated source. recommended that CLKA CLKB shorted together driven same clock source. small time delay desired between when channels sample analog inputs, CLKA CLKB driven different signals. this delay exceeds 1ns, performance part degrade. CLKA CLKB should driven asynchronous signals. Figures show alternatives converting differential clock single-ended input. transformer provides incremental contribution phase noise. LVDS PECL CMOS translators provide little degradation below 70MHz, 140MHz will degrade compared transformer solution. nature received signals also large bearing much degradation will experienced. high crest factor signals such WCDMA OFDM, where nominal power level must least below full scale, these translators will have lesser impact.
ETC1-1T 5pF-30pF DIFFERENTIAL CLOCK INPUT
LTC2285IUP #3CGPBF
2285
0.1F
FERRITE BEAD
Figure LVDS PECL Drive Using Transformer
transformer example terminated with appropriate termination signaling use. transformer with impedance ratio desirable cases where lower voltage differential signals considered. center bypassed ground through capacitor close differential signals originate different plane. capacitor input result peaking, depending transmission line length require series resistor both pass filter high frequency noise that induced into clock line neighboring digital signals, well damping mechanism reflections. Maximum Minimum Conversion Rates maximum conversion rate LTC2285IUP#3CGPBF 135Msps. lower limit LTC2285IUP#3CGPBF sample rate determined droop sample-and-hold circuits. pipelined architecture this relies
2285iup#3cgpbf
LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
storing analog signals small valued capacitors. Junction leakage will discharge capacitors. specified minimum operating frequency LTC2285IUP#3CGPBF 1Msps. Clock Duty Cycle Stabilizer optional clock duty cycle stabilizer circuit ensures high performance even input clock duty cycle. Using clock duty cycle stabilizer recommended most applications. clock duty cycle stabilizer, MODE should connected 1/3VDD 2/3VDD using external resistors. This circuit uses rising edge sample analog input. falling edge ignored internal falling edge generated phase-locked loop. input clock duty cycle vary from clock duty cycle stabilizer will maintain constant internal duty cycle. clock turned long period time, duty cycle stabilizer circuit will require hundred clock cycles lock onto input clock. applications where sample rate needs changed quickly, clock duty cycle stabilizer disabled. duty cycle stabilizer disabled, care should taken make sampling clock have (±5%) duty cycle. DIGITAL OUTPUTS Table shows relationship between analog input voltage, digital data bits, overflow bit. Note that high when overflow underflow occurred either channel channel
Table Output Codes Input Voltage
AIN+ AIN- Range) >+1.000000V +0.999878V +0.999756V +0.000122V 0.000000V -0.000122V -0.000244V -0.999878V -1.000000V <-1.000000V (Offset Binary) 1111 1111 1111 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 (2's Complement) 1111 1111 1111 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000
Digital Output Buffers Figure shows equivalent circuit single output buffer. Each buffer powered OVDD OGND, isolated from power ground. additional N-channel transistor output driver allows operation down voltages. internal resistor series with output makes output appear external circuitry eliminate need external damping resistors. with high speed/high resolution converters, digital output loading affect performance. digital outputs LTC2285IUP#3CGPBF should drive minimal capacitive load avoid possible interaction between digital outputs sensitive input circuitry. full speed operation capacitive load should kept under 10pF Lower OVDD voltages will also help reduce interference from digital outputs.
LTC2285IUP#3CGPBF OVDD 0.5V 3.6V 0.1F OVDD DATA FROM LATCH OGND PREDRIVER LOGIC TYPICAL DATA OUTPUT
2285
Figure Digital Output Buffer
Data Format Using MODE pin, LTC2285IUP#3CGPBF parallel digital output selected offset binary complement format. Connecting MODE 1/3VDD selects offset binary output format. Connecting MODE 2/3VDD selects complement output format. external resistor divider used 1/3VDD 2/3VDD logic values. Table shows logic states MODE pin.
2285iup#3cgpbf
LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
Table MODE Function
MODE 1/3VDD 2/3VDD OUTPUT FORMAT Offset Binary Offset Binary Complement Complement CLOCK DUTY CYCLE STABILIZER
Sleep Modes converter placed shutdown modes conserve power. Connecting SHDN results normal operation. Connecting SHDN results sleep mode, which powers down circuitry including reference typically dissipates 1mW. When exiting sleep mode will take milliseconds output data become valid because reference capacitors have recharge stabilize. Connecting SHDN results mode, which typically dissipates 30mW. mode, on-chip reference circuit kept that recovery from mode faster than that from sleep mode, typically taking clock cycles. both sleep modes, digital outputs disabled enter Hi-Z state. Channels have independent SHDN pins (SHDNA, SHDNB). Channel controlled SHDNA OEA, channel controlled SHDNB OEB. nap, sleep output enable modes channels completely independent, possible have channel operating while other channel sleep mode. Digital Output Multiplexer digital outputs LTC2285IUP#3CGPBF multiplexed onto single data sample rate 80Msps less. digital input that swaps data busses. High, channel comes DA0-DA13; channel comes DB0-DB13. Low, output busses swapped channel comes DB0-DB13; channel comes DA0DA13. multiplex both channels onto single output bus, connect MUX, CLKA CLKB together (see Timing Diagram multiplexed mode). multiplexed data available either data bus-the unused data disabled with pin. Grounding Bypassing LTC2285IUP#3CGPBF requires printed circuit board with clean, unbroken ground plane. multilayer board with internal ground plane recommended. Layout printed circuit board should ensure that digital analog signal lines separated much possible.
2285iup#3cgpbf
Overflow When outputs logic high converter either overranged underranged channel channel Note that both channels share common pin, which case slower compatible parts such LTC2284 LTC2299. disabled when channel sleep mode. Output Clock delayed version CLKB input available digital output, CLKOUT. falling edge CLKOUT used latch digital output data. CLKOUT disabled when channel sleep mode. Output Driver Power Separate output power ground pins allow output drivers isolated from analog circuitry. power supply digital output buffers, OVDD, should tied same power supply logic being driven. example, converter driving powered 1.8V supply, then OVDD should tied that same 1.8V supply. OVDD powered with voltage from 500mV 3.6V. OGND powered with voltage from must less than OVDD. logic outputs will swing between OGND OVDD. Output Enable outputs disabled with output enable pin, high disables data outputs including data access relinquish times slow allow outputs enabled disabled during full speed operation. output Hi-Z state intended during long periods inactivity. Channels have independent output enable pins (OEA, OEB).
LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
particular, care should taken digital track alongside analog signal track underneath ADC. High quality ceramic bypass capacitors should used VDD, OVDD, VCM, REFH, REFL pins. Bypass capacitors must located close pins possible. particular importance 0.1F capacitor between REFH REFL. This capacitor should placed close device possible (1.5mm less). size 0402 ceramic capacitor recommended. large 2.2F capacitor between REFH REFL somewhat further away. traces connecting pins bypass capacitors must kept short should made wide possible. LTC2285IUP#3CGPBF differential inputs should parallel close each other. input traces should short possible minimize capacitance minimize noise pickup. Heat Transfer Most heat generated LTC2285IUP#3CGPBF transferred from through bottom-side Exposed package leads onto printed circuit board. good electrical thermal performance, Exposed should soldered large grounded board. critical that ground pins connected ground plane sufficient area. Clock Sources Undersampling Undersampling especially demanding clock source, higher input frequency, greater sensitivity clock jitter phase noise. clock source that degrades full-scale signal 70MHz will degrade 140MHz, 4.5dB 190MHz. cases where absolute clock frequency accuracy relatively unimportant only single required, canned oscillator from vendors such Saronix Vectron placed close simply connected directly ADC. there distance ADC, some source termination reduce ringing that occur even over fraction inch advisable. must allow clock overshoot supplies performance will suffer. filter clock signal with narrow band filter unless have sinusoidal clock source, rise fall time artifacts present typical digital clock signals will translated into phase noise. lowest phase noise oscillators have single-ended sinusoidal outputs, these devices filter close beneficial. This filter should close both reduce roundtrip reflection times, well reduce susceptibility traces between filter ADC. circuit sensitive closein phase noise, power supply oscillators buffers must very stable, propagation delay variation with supply will translate into phase noise. Even though these clock sources regarded digital devices, operate them digital supply. your clock also used drive digital devices such FPGA, should locate oscillator, clock fan-out devices close ADC, give routing precedence. clock signals FPGA should have series termination driver prevent high frequency noise from FPGA disturbing substrate clock fan-out device. FPGA programmable divider, must re-time signal using original oscillator, re-timing flip-flop well oscillator should close ADC, powered with very quiet supply. cases where there multiple ADCs, where clock source originates some distance away, differential clock distribution advisable. This advisable both from perspective EMI, also avoid receiving noise from digital sources both radiated, well propagated waveguides that exist between layers multilayer PCBs. differential pairs must close together distanced from other signals. differential pair should guarded both sides with copper distanced least distance between traces, grounded with vias more than inch apart.
2285iup#3cgpbf
2.2F LTC2285IUP#3CGPBF OVDD QDVDD 0.1F SENSEA VCMA MODE SHDNA DA13 DA12 DA11 DA10 OGND OVDD
LTC2285IUP#3CGPBF
APPLICATIONS INFORMATION
SENSEB VCMB SHDNB OGND OVDD
Evaluation Circuit Schematic LTC2285IUP#3CGPBF
OVDD EDGE-CON-100 MODE 0.1F 0.1F 0.1F OVDD OVDD QDVDD 2.2F 1/3VDD 2/3VDD 0.1F 24.9 24.9 QDVDD OVDD FXLH42245MPX VCCA VCCB VCCB EXPOSED 2.2F 2.2F OVDD VCMB 24.9 SENSEB VCMB 0.1F 105k OVDD 0.01F 6.3V 105k QDVDD OVDD 24.9 0.1F 0.1F 0.1F 0.1F FXLH42245MPX VCCA VCCB VCCB EXPOSED AINA+ AINA- REFHA REFHA REFLA REFLA CLKA CLKB REFLB REFLB REFHB REFHB AINB- AINB+ CLKOUT DB13 DB12 DB11 DB10 FXLH42245MPX VCCA VCCB VCCB EXPOSED OVDD QDVDD
SENSEA
VCMA
ANALOG INPUT
0.1F
0.1F
BEAD
4.7F 6.3V
VCMA
0.1F
0.1F
0.1F
CLOCK INPUT
0.1F
0.1F
49.9
NC7SVU04
ANALOG INPUT
0.1F
ENABLE QDVDD NC7SV86P5X 4.7k VCCIN 0.1F 100k 0.1F 4.99k VCCIN
0.1F
VCMB
QDVDD 4.7k
0.1F QDVDD 0.1F 0.1F 0.1F
100F 6.3V
4.7F
LT1761ES5-BYP
FXLH42245MPX VCCA VCCB VCCB EXPOSED
0.1F
0.1F
0.1F
0.1F
LT1761ES5-BYP
0.01F
105k
6.3V 100k
24LC025
4.99k
4.99k
2285 AI01
*VERSION TABLE 12pF 12pF 12pF MABAES0060 MABAES0060 MABAES0060 MABA-007159-000000 MABA-007159-000000 MABA-007159-000000 INPUT FREQUENCY 1MHz 70MHz 1MHz 70MHz 1MHz 70MHz 70MHz 140MHz 70MHz 140MHz 70MHz 140MHz
ASSEMBLY TYPE DC1098A-A DC1098A-B DC1098A-C DC1098A-D DC1098A-E DC1098A-F
LTC2281IUP LTC2283IUP LTC2285IUP LTC2281IUP LTC2283IUP LTC2285IUP
BITS
Msps
R18, 24.9 24.9 24.9 12.4 12.4 12.4
2285iup#3cgpbf
LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
Silkscreen
Side
2285iup#3cgpbf
LTC2285IUP#3CGPBF APPLICATIONS INFORMATION
Inner Layer Inner Layer Power
Bottom Side
2285iup#3cgpbf
LTC2285IUP#3CGPBF PACKAGE DESCRIPTION
Package 64-Lead Plastic (9mm 9mm)
(Reference 05-08-1705)
0.70 ±0.05
7.15 ±0.05
7.50 8.10 ±0.05 9.50 ±0.05 SIDES)
7.15 ±0.05
PACKAGE OUTLINE 0.25 ±0.05 0.50 RECOMMENDED SOLDER PITCH DIMENSIONS APPLY SOLDER MASK AREAS THAT SOLDERED 0.10 SIDES) 0.75 0.05 0.115
0.10
0.40 0.10 CHAMFER 0.35
MARK (SEE NOTE
7.15 0.10 7.50 (4-SIDES)
7.15 0.10
(UP64) 0406
0.200 0.00 0.05 NOTE: DRAWING CONFORMS JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 DIMENSIONS MILLIMETERS DIMENSIONS EXPOSED BOTTOM PACKAGE INCLUDE MOLD FLASH. MOLD FLASH, PRESENT, SHALL EXCEED 0.20mm SIDE, PRESENT EXPOSED SHALL SOLDER PLATED SHADED AREA ONLY REFERENCE LOCATION BOTTOM PACKAGE DRAWING SCALE
0.25 0.05 0.50 BOTTOM VIEW-EXPOSED
2285iup#3cgpbf
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC2285IUP#3CGPBF TYPICAL APPLICATION
PART NUMBER LTC1748 LTC1750 LTC1993-2 LTC1994 LTC2208 LTC2220 LTC2224 LTC2242-12 LTC2254 LTC2255 LTC2280 LTC2282 LTC2284 LTC2286 LTC2287 LTC2288 LTC2289 LTC2290 LTC2291 LTC2292 LTC2293 LTC2294 LTC2295 LTC2296 LTC2297 LTC2298 LTC2299 LT5512 LT5514 LT5515 LT5516 LT5517 LT5522 DESCRIPTION 14-Bit, 80Msps, 14-Bit, 80Msps, Wideband High Speed Differential Noise, Distortion Fully Differential Input/Output Amplifier/Driver 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 12-Bit, 170Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, High Sampling 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs 14-Bit, 105Msps, ADC, Lowest Power 14-Bit, 125Msps ADC, ADC, Lowest Power 10-Bit, Dual, 105Msps, ADC, Crosstalk 12-Bit, Dual, 105Msps, ADC, Crosstalk 14-Bit, Dual, 105Msps, ADC, Crosstalk 10-Bit, Dual, 25Msps, ADC, Crosstalk 10-Bit, Dual, 40Msps, ADC, Crosstalk 10-Bit, Dual, 65Msps, ADC, Crosstalk 10-Bit, Dual, 80Msps, ADC, Crosstalk 12-Bit, Dual, 10Msps, ADC, Crosstalk 12-Bit, Dual, 25Msps, ADC, Crosstalk 12-Bit, Dual, 40Msps, ADC, Crosstalk 12-Bit, Dual, 65Msps, ADC, Crosstalk 12-Bit, Dual, 80Msps, ADC, Crosstalk 14-Bit, Dual, 10Msps, ADC, Crosstalk 14-Bit, Dual, 25Msps, ADC, Crosstalk 14-Bit, Dual, 40Msps, ADC, Crosstalk 14-Bit, Dual, 65Msps, ADC, Crosstalk 14-Bit, Dual, 80Msps, ADC, Crosstalk DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion Amplifier/ADC Driver with Digitally Controlled Gain 1.5GHz 2.5GHz Direct Conversion Quadrature Demodulator 800MHz 1.5GHz Direct Conversion Quadrature Demodulator 40MHz 900MHz Direct Conversion Quadrature Demodulator 600MHz 2.7GHz High Linearity Downconverting Mixer COMMENTS 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package 500MHz Undersampling, 90dB SFDR 800MHz 70dBc Distortion 70MHz, Gain Distortion: -94dB 1MHz 1250mW, 77.1dB SNR, 100dB SFDR, 64-Pin Package 890mW, 67.7dB SNR, 84dB SFDR, 64-Pin Package 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin Package 740mW, 65.4dB SNR, 84dB SFDR, 64-Pin Package 320mW, 72.4dB SNR, 88dB SFDR, 32-Pin Package 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin Package 320mW, 61.6dB SNR, 85dB SFDR, 64-Pin Package 540mW, 70.1dB SNR, 88dB SFDR, 64-Pin Package 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin Package 150mW, 61.8dB SNR, 85dB SFDR, 64-Pin Package 235mW, 61.8dB SNR, 85dB SFDR, 64-Pin Package 400mW, 61.8dB SNR, 85dB SFDR, 64-Pin Package 422mW, 61.6dB SNR, 90dB SFDR, 64-Pin Package 120mW, 71.3dB SNR, 90dB SFDR, 64-Pin Package 150mW, 71.4dB SNR, 90dB SFDR, 64-Pin Package 235mW, 71.4dB SNR, 90dB SFDR, 64-Pin Package 400mW, 71.3dB SNR, 90dB SFDR, 64-Pin Package 422mW, 70.6dB SNR, 90dB SFDR, 64-Pin Package 120mW, 74.4dB SNR, 90dB SFDR, 64-Pin Package 150mW, 74.5dB SNR, 90dB SFDR, 64-Pin Package 235mW, 74.4dB SNR, 90dB SFDR, 64-Pin Package 400mW, 74.3dB SNR, 90dB SFDR, 64-Pin Package 444mW, 73dB SNR, 90dB SFDR, 64-Pin Package 3GHz, 21dBm IIP3, Integrated Buffer 450MHz 47dB OIP3, Digital Gain Control 10.5dB 33dB 1.5dB/Step High IIP3: 20dBm 1.9GHz, Integrated Quadrature Generator High IIP3: 21.5dBm 900MHz, Integrated Quadrature Generator High IIP3: 21dBm 800MHz, Integrated Quadrature Generator 4.5V 5.25V Supply, 25dBm IIP3 900MHz, 12.5dB, Single Ended Ports
2285iup#3cgpbf
Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1008 PRINTED
1630 McCarthy Blvd., Milpitas, 95035-7417
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2006
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