LTC1408-12 12-bit, 600ksps with simultaneously sampled differential in

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LTC1408-12 12-bit, 600ksps with simultaneously sampled differential in

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LTC1408-12 Channel, 12-Bit, 600ksps Simultaneous Sampling with Shutdown DESCRIPTIO
LTC1408-12 12-bit, 600ksps with simultaneously sampled differential inputs. device draws only from single supply, comes tiny (5mm 5mm) package. SLEEP shutdown feature further reduces power consumption 6µW. combination power tiny package makes LTC1408-12 suitable portable applications. LTC1408-12 contains separate differential inputs that sampled simultaneously rising edge CONV signal. These sampled inputs then converted rate 100ksps channel. 83dB common mode rejection allows users eliminate ground loops common mode noise measuring signals differentially from source. device converts 2.5V unipolar inputs differentially, ±1.25V bipolar inputs also differentially, depending state pin. analog input swing rail-to-rail long differential input range maintained. conversion sequence abbreviated convert fewer than channels, depending logic state SEL2, SEL1 SEL0 inputs. serial interface sends conversion results clocks compatibility with standard serial interfaces.
600ksps with Simultaneously Sampled Differential Inputs 100ksps Throughput Channel 72dB SINAD Power Dissipation: 15mW Single Supply Operation 2.5V Internal Bandgap Reference, Overdriven with External Reference 3-Wire SPI-Compatible Serial Interface 2.5V Unipolar, ±1.25V Bipolar Differential Input Range SLEEP (6µW) Shutdown Mode (3.3mW) Shutdown Mode Internal Conversion Triggered CONV 83dB Common Mode Rejection Tiny 32-Pin (5mm 5mm) Package
APPLICATIO
Multiphase Power Measurement Multiphase Motor Control Data Acquisition Systems Uninterruptable Power Supplies
Lare registered trademarks Linear Technology Corporation. other trademarks property their respective owners. Protected U.S. Patents including 6084440, 6522187.
BLOCK DIAGRA
CH5- CH5+ CH4- CH4+
CH3-
CH3+
CH2-
CH2+
CH1-
CH1+
CH0-
CH0+
10µF
600ksps 12-BIT
TIMING LOGIC VREF 10µF
235114 TA01
2.5V REFERENCE
12-BIT LATCH 12-BIT LATCH 12-BIT LATCH 12-BIT LATCH 12-BIT LATCH 12-BIT LATCH OVDD 0.1µF OGND
THREESTATE SERIAL OUTPUT PORT
CONV DGND
SEL2 SEL1 SEL0
140812f
LTC1408-12 ABSOLUTE
(Notes
RATI
PACKAGE/ORDER ATIO
VIEW
DGND CONV SEL0 SEL1 SEL2
Supply Voltage (VDD, VCC, OVDD) Analog VREF Input Voltages (Note 0.3V (VDD 0.3V) Digital Input Voltages 0.3V (VDD 0.3V) Digital Output Voltage 0.3V (VDD 0.3V) Power Dissipation 100mW Operation Temperature Range LTC1408C-12 70°C LTC1408I-12 40°C 85°C Storage Temperature Range 65°C 125°C
ORDER PART NUMBER
VREF CH5- CH5+ CH4- CH4+
OGND OVDD CH0+ CH0- CH1+ CH1-
CH2+ CH2- CH3+ CH3-
LTC1408CUH-12 LTC1408IUH-12
PART MARKING
1408-12
TJMAX 125°C, 34°C/ EXPOSED (PAD MUST SOLDERED
PACKAGE 32-PIN (5mm 5mm) PLASTIC
Order Options Tape Reel: Lead Free: #PBF Lead Free Tape Reel: #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/
Consult Marketing parts specified with wider operating temperature ranges.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Offset Error Offset Match from Range Error Range Match from Range Tempco
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With internal reference,
CONDITIONS
-4.5
±0.25 ±0.5
UNITS Bits ppm/°C ppm/°C
(Note (Note (Note Internal Reference (Note External Reference
ALOG
SYMBOL PARAMETER tACQ tJITTER CMRR
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With internal reference,
CONDITIONS 2.7V 3.3V (Note
UNITS
Analog Differential Input Range (Notes Analog Common Mode Differential Input Range Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Channel Channel Aperture Skew Analog Input Common Mode Rejection Ratio
(Note
100kHz, 10MHz,
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LTC1408-12
ACCURACY
SYMBOL SINAD SFDR PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise Full Power Bandwidth Full Linear Bandwidth
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With internal reference,
CONDITIONS 100kHz Input Signal 300kHz Input Signal 100kHz First Harmonics 300kHz First Harmonics 100kHz Input Signal 300kHz Input Signal 0.625VP-P, 833kHz into CH0+, 0.625VP-P, 841kHz into CH0-. Bipolar Mode. Also Applicable Other Channels VREF 2.5V (Note 2.5VP-P, 11585LSBP-P (-3dBFS) (Note S/(N 68dB, Bipolar Differential Input
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance VREF Settling Time External VREF Input Range CONDITIONS IOUT
DIGITAL PUTS DIGITAL OUTPUTS
SYMBOL ISOURCE ISINK PARAMETER High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT Output Short-Circuit Source Current Output Short-Circuit Sink Current VOUT VOUT CONDITIONS 3.3V 2.7V
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C.
UNITS LSBRMS
25°C.
2.55 UNITS ppm/°C µV/V
2.7V 3.6V, VREF 2.5V Load Current 0.5mA CREF 10µF
UNITS
IOUT 200µA 2.7V, IOUT 160µA 2.7V, IOUT 1.6mA VOUT
0.05
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LTC1408-12
POWER REQUIRE
SYMBOL VDD, PARAMETER Supply Voltage Supply Current
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With internal reference, VCC=
CONDITIONS Active Mode, fSAMPLE 600ksps Mode Sleep Mode Active Mode with SCK, fSAMPLE 600ksps
Power Dissipation
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C.
SYMBOL fSAMPLE(MAX) tTHROUGHPUT tSCK tCONV PARAMETER Maximum Sampling Rate Channel (Conversion Rate) Minimum Sampling Period (Conversion Acquisiton Period) Clock Period Conversion Time Minimum High SCLK Pulse Width CONV Setup Time Before CONV Minimum High CONV Pulse Width Sample Mode CONV Hold Mode 96th CONV Interval (Affects Acquisition Period) Delay from Valid Bits Through Hi-Z Previous Remains Valid After VREF Settling Time After Sleep-to-Wake Transition (Note (Notes (Note (Notes (Note (Note (Note (Notes (Notes (Notes (Notes (Notes (Notes CONDITIONS
CHARACTERISTICS
Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Rating condition extended periods affect device reliabilty lifetime. Note voltage values with respect ground GND. Note When these pins taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below greater than without latchup. Note Offset range specifications apply single-ended CH0+ CH5+ input with CH5- grounded using internal 2.5V reference. Note Integral linearity tested with external 2.55V reference defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Linearity tested only. Note Guaranteed design, subject test. Note Recommended operating conditions. Note analog input range defined voltage difference between CHx+ CHx-, 0-5.
UNITS
UNITS
10000 10000
SCLK cycles
Note absolute voltage CHx+ CHx- must within this range. Note less than allowed, output data will appear clock cycle later. best CONV rise half clock before SCK, when running clock rated speed. Note same aperture delay. Aperture delay (1ns) difference between 2.2ns delay through sample-and-hold 1.2ns CONV Hold mode delay. Note rising edge guaranteed catch data coming into storage latch. Note time period acquiring input signal started 96th rising clock ended rising edge CONV. Note internal reference settles after wakes from Sleep mode with more cycles 10µF capacitive load. Note full power bandwidth frequency where output code swing drops with 2.5VP-P input sine wave. Note Maximum clock period guarantees analog performance during conversion. Output data read with arbitrarily long clock period. Note conversion process takes clocks each channel that enabled, clocks channels.
140812f
LTC1408-12 TYPICAL PERFOR CHARACTERISTICS
SINAD Input Frequency
THD, 2nd, (dB)
THD, 2nd, (dB)
SINAD (dB)
FREQUENCY (MHz)
SFDR Input Frequency
SFDR (dB)
MAGNITUDE (dB)
(dB)
FREQUENCY (MHz)
100kHz Bipolar Sine Wave 8192 Point Plot
DIFFERENTIAL LINEARITY (LSB) MAGNITUDE (dB) -100 -110 -120 FREQUENCY (KHZ)
140812
INTEGRAL LINEARITY (LSB)
140814
25°C THD, Input Frequency
BIPOLAR SINGLE-ENDED
THD, Input Frequency
-104
UNIPOLAR SINGLE-ENDED
-104
-110
FREQUENCY (MHz)
140812
-110
FREQUENCY (MHz)
140812
Input Frequency
-100
100kHz Unipolar Sine Wave 8192 Point Plot
-110 -120
FREQUENCY (MHz)
140812
140814
FREQUENCY (kHz)
140812
Differential Linearity Output Code, CH0, Unipolar Mode
-0.2 -0.4 -0.6 -0.8 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
140812
Integral Linearity Output Code, CH0, Unipolar Mode
-0.2 -0.4 -0.6 -0.8 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
140812
140812f
LTC1408-12 TYPICAL PERFOR CHARACTERISTICS
Full Scale Signal Response
MAGNITUDE (dB)
FREQUENCY (MHz) 1000
1408
CMRR (dB)
Crosstalk Frequency
CROSSTALK (dB)
PSRR (dB)
-100
-120 100k 100M FREQUENCY (Hz)
1408
25°C
CMRR Frequency
-100 -120
100k 100M FREQUENCY (Hz)
1408
PSRR Frequency
-100 -120
100k 100M FREQUENCY (Hz)
1408
140812f
LTC1408-12
CTIO
(Pin Three-State Serial Data Output. Each output data words represent analog input channels start previous conversion. Data comes first data comes last. Each data word comes first. OGND (Pin Ground Return Currents. Connect solid ground plane. OVDD (Pin Power Supply Pin. OVDD must more than 300mV higher than brought lower voltage interface voltage logic families. unloaded high state potential OVDD. CH0+ (Pin Non-Inverting Channel CH0+ operates fully differentially with respect CH0- with 2.5V, ±1.25V differential swing absolute input range. CH0- (Pin Inverting Channel CH0- operates fully differentially with respect CH0+ with -2.5V ±1.25V differential swing absolute input range. (Pins 19): Analog Grounds. These ground pins must tied directly solid ground plane under part. Analog signal currents flow through these connections. CH1+ (Pin Non-Inverting Channel CH1+ operates fully differentially with respect CH1- with 2.5V, ±1.25V differential swing absolute input range. CH1- (Pin Inverting Channel CH1- operates fully differentially with respect CH1+ with -2.5V ±1.25V differential swing absolute input range. CH2+ (Pin 10): Non-Inverting Channel CH2+ operates fully differentially with respect CH2- with 2.5V, ±1.25V differential swing absolute input range. CH2- (Pin 11): Inverting Channel CH2- operates fully differentially with respect CH2+ with -2.5V ±1.25V differential swing absolute input range. CH3+ (Pin 14): Non-Inverting Channel CH3+ operates fully differentially with respect CH3- with 2.5V, ±1.25V differential swing absolute input range. CH3- (Pin 15): Inverting Channel CH3- operates fully differentially with respect CH3+ with -2.5V ±1.25V differential swing absolute input range. CH4+ (Pin 17): Non-Inverting Channel CH4+ operates fully differentially with respect CH4- with 2.5V, ±1.25V differential swing absolute input range. CH4- (Pin 18): Inverting Channel CH4- operates fully differentially with respect CH4+ with -2.5V ±1.25V differential swing absolute input range. CH5+ (Pin 20): Non-Inverting Channel CH5+ operates fully differentially with respect CH5- with 2.5V, ±1.25V differential swing absolute input range. CH5- (Pin 21): Inverting Channel CH5- operates fully differentially with respect CH5+ with -2.5V ±1.25V differential swing absolute input range. (PIN 22): Analog Ground Reference. Analog ground must tied directly solid ground plane under part. Analog signal currents flow through this connection. 10µF reference bypass capacitor should returned this pad. VREF (Pin 23): 2.5V Internal Reference. Bypass solid analog ground plane with 10µF ceramic capacitor 10µF tantalum parallel with 0.1µF ceramic). overdriven external reference voltage between 2.55V VDD, VCC. (Pin 24): Positive Analog Supply. This supplies analog section. Bypass solid analog ground plane with 10µF ceramic capacitor 10µF tantalum) parallel with 0.1µF ceramic. Care should taken place 0.1µF bypass capacitor close possible. must tied
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LTC1408-12
CTIO
(Pin 25): Positive Digital Supply. This supplies logic section. Bypass DGND solid analog ground plane with 10µF ceramic capacitor 10µF tantalum parallel with 0.1µF ceramic). Keep mind that internal digital output signal currents flow through this pin. Care should taken place 0.1µF bypass capacitor close possible. must tied SEL2 (Pin 26): Most significant controlling number channels being converted. combination with SEL1 SEL0, selects just first channel (CH0) conversion. Incrementing SELx selects additional channels(CH0-CH5) conversion. 101, select channels conversion. Must kept fixed state during conversion during subsequent conversion read data. SEL1 (Pin 27): Middle significance controlling number channels being converted. combination with SEL0 SEL2, selects just first channel (CH0) conversion. Incrementing SELx selects additional channels conversion. 101, select channels (CH0-CH5) conversion. Must kept fixed state during conversion during subsequent conversion read data. SEL0 (Pin 28): Least significant controlling number channels being converted. combination with SEL1 SEL2, selects just first channel (CH0) conversion. Incrementing SELx selects additional channels conversion. 101, select channels (CH0-CH5) conversion. Must kept fixed state during conversion during subsequent conversion read data. (Pin 29): Bipolar/Unipolar Mode. input differential range 2.5V when LOW, ±1.25V when HIGH. Must kept fixed state during conversion during subsequent conversion read data. When changing between conversions full acquisition time must allowed before starting next conversion. output data complement format bipolar mode straight binary format unipolar mode. CONV (Pin 30): Convert Start. Holds analog input signals starts conversion CONV's rising edge. CONV pulses with fixed high fixed state starts mode. Four more CONV pulses with fixed high fixed state starts Sleep mode. DGND (Pin 31): Digital Ground. This ground must tied directly solid ground plane. Digital input signal currents flow through this pin. (Pin 32): External Clock Input. Advances conversion process sequences output data (Pin1) rising edge. more pulses wake from sleep power saving modes. clock cycles needed each channels that activated SELx (Pins 28), total clock cycles needed convert read channels. EXPOSED (Pin 33): GND. Must tied directly solid ground plane.
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LTC1408-12
BLOCK DIAGRA
CH0+
CH0-
CH1+
CH1-
CH2-
CH3+
CH3-
CH4+
CH4-
CH5-
0.1µF 10µF
600ksps 12-BIT
12-BIT LATCH 12-BIT LATCH 12-BIT LATCH 12-BIT LATCH 12-BIT LATCH 12-BIT LATCH
OVDD THREESTATE SERIAL OUTPUT PORT OGND 0.1µF
TIMING LOGIC CONV
2.5V REFERENCE EXPOSED 10µF SEL2 SEL1 SEL0 VREF DGND
1408
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LTC1408-12
CONV
HOLD
Back SAMPLE mode SELx Back
INTERNAL STATUS
REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION
SAMPLE
REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION
12-BIT DATA WORD
DIAGRA
12-BIT DATA WORD
Hi-Z
Hi-Z
tCONV
tTHROUGHPUT
SAMPLE mode SELx
Back SAMPLE mode SELx
REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION
12-BIT DATA WORD
REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION
12-BIT DATA WORD
tCONV
tTHROUGHPUT
Back SAMPLE mode SELx
Back SAMPLE mode SELx
SAMPLE
REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION
12-BIT DATA WORD
REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION
12-BIT DATA WORD
Hi-Z
tCONV
tTHROUGHPUT
1408 TD01
LTC1408-12 Timing Diagram
140812f
LTC1408-12
DIAGRA
Mode Sleep Mode Waveforms
CONV
SLEEP
VREF
NOTE: SLEEP INTERNAL SIGNALS
1408 TD02
Delay
1408 TD03
Hi-Z
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LTC1408-12
APPLICATIO ATIO
SELECTING NUMBER CONVERTED CHANNELS (SEL2, SEL1, SEL0) These three control pins select number channels being converted (see Table selects only first channel (CH0) conversion. Incrementing SELx selects additional channels conversion, channels. 101, select channels conversion. These pins must kept fixed state during conversion during subsequent conversion read data. When changing modes between conversions, keep mind that output data particular channel will remain unchanged until after that channel converted again. example: convert sequence channels (CH0, CH1, CH2, CH3) with SELx 011, then, after these channels converted change SELx convert just CH1. During conversion first channels will able read data from same channels converted part previous group channels. Later, could convert more channels read back unread data that converted first channels. These pins often hardwired enable right number channels particular application. Choosing convert fewer channels conversion results faster throughput those channels. example, channels converted 100ksps/ch, while channels converted 200ksps/ch.
Table Conversion Sequence Control ("acquire" represents simultaneous sampling channels; represents conversion channels) SEL2 SEL1 SEL0 CHANNEL ACQUISITION CONVERSION SEQUENCE acquire, CH0, acquire, CH0. acquire, CH0, CH1, acquire, CH0, CH1. acquire, CH0, CH1, CH2, acquire, CH0, CH1, CH2. acquire, CH0, CH1, CH2, CH3, acquire, CH0, CH1, CH2, CH3. acquire, CH0, CH1, CH2, CH3, CH4, acquire, CH0,CH1,CH2, CH3, CH4. acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5. acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5. acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5.
BIPOLAR/UNIPOLAR MODE input voltage range each input differential pairs UNIPOLAR 2.5V when LOW, BIPOLAR ±1.25V when HIGH. This must kept fixed state during conversion during subsequent conversion read data. When changing between conversions full acquisition time must allowed before starting next conversion. After changing modes from BIPOLAR UNIPOLAR, from UNIPOLAR BIPOLAR, still read first channels mode, inverting read these channels mode that they were converted DRIVING ANALOG INPUT differential analog inputs LTC1408-12 driven differentially single-ended input (i.e., CHx- input grounded). twelve analog inputs differential analog input pairs, CH0+ CH0-, CH1+ CH1-, CH2+ CH2-, CH3+ CH3-, CH4+ CH4- CH5+ CH5-, sampled same instant. unwanted signal that common both inputs each input pair will reduced common mode rejection sample-and-hold circuit. inputs draw only small current spike while charging sample-and-hold capacitors conversion. During conversion, analog inputs draw only small leakage current. source impedance driving circuit low, then
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LTC1408-12
APPLICATIO ATIO
LTC1408-12 inputs driven directly. source impedance increases, will acquisition time. minimum acquisition time with high source impedance, buffer amplifier must used. main requirement that amplifier driving analog input(s) must settle after small current spike before next conversion starts (the time allowed settling must least 39ns full throughput rate). Also keep mind while choosing input amplifier amount noise harmonic distortion added amplifier. CHOOSING INPUT AMPLIFIER Choosing input amplifier easy requirements taken into consideration. First, limit magnitude voltage spike seen amplifier from charging sampling capacitor, choose amplifier that output impedance 100) closed-loop bandwidth frequency. example, amplifier used gain unity-gain bandwidth 50MHz, then output impedance 50MHz must less than 100. second requirement that closed-loop bandwidth must greater than 40MHz ensure adequate smallsignal settling full throughput rate. slower amps used, more time settling provided increasing time between conversions. best choice drive LTC1408-12 depends application. Generally, applications fall into categories: applications where dynamic specifications most critical time domain applications where accuracy settling time most critical. following list summary amps that suitable driving LTC1408-12. (More detailed information available Linear Technology Databooks website www.linear.com.)
LinearView trademark Linear Technology Corporation.
LTC1566-1: Noise 2.3MHz Continuous Time Lowpass Filter. LT®1630: Dual 30MHz Rail-to-Rail Voltage Amplifier. 2.7V ±15V supplies. Very high AVOL, 500µV offset 520ns settling 0.5LSB swing. noise 93dB 40kHz below 1LSB 320kHz 2VP-P into 5V), making part excellent applications Nyquist) where rail-to-rail performance desired. Quad version available LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage Amplifier. 2.7V ±15V supplies. Very high AVOL, 1.5mV offset 400ns settling 0.5LSB swing. suitable applications with single supply. noise 93dB 40kHz below 1LSB 800kHz 2VP-P into 5V), making part excellent applications where rail-to-rail performance desired. Quad version available LT1633. LT1801: 80MHz GBWP, -75dBc 500kHz, 2mA/amplifier, 8.5nV/Hz. LT1806/LT1807: 325MHz GBWP, -80dBc distortion 5MHz, unity gain stable, rail-to-rail out, 10mA/amplifier, 3.5nV/Hz. LT1810: 180MHz GBWP, -90dBc distortion 5MHz, unity gain stable, rail-to-rail out, 15mA/amplifier, 16nV/Hz. LT1818/LT1819: 400MHz, 2500V/µs, 9mA, Single/Dual Voltage Mode Operational Amplifier. LT6200: 165MHz GBWP, -85dBc distortion 1MHz, unity gain stable, rail-to-rail out, 15mA/amplifier, 0.95nV/Hz. LT6203: 100MHz GBWP, -80dBc distortion 1MHz, unity gain stable, rail-to-rail out, 3mA/amplifier, 1.9nV/Hz. LT6600: Amplifier/Filter Differential In/Out with 10MHz Cutoff frequency.
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LTC1408-12
APPLICATIO ATIO
INPUT FILTERING SOURCE IMPEDANCE
noise distortion input amplifier other circuitry must considered since they will LTC1408-12 noise distortion. small-signal bandwidth sample-and-hold circuit 50MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient many applications. example, Figure shows 47pF capacitor from CHO+ ground source resistor limit input bandwidth 30MHz. 47pF capacitor also acts charge reservoir input sampleand-hold isolates input from sampling-glitch sensitive circuitry. High quality capacitors resistors should used since these components distortion. silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors generate distortion from self heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems. When high amplitude unwanted signals close frequency desired signal frequency multiple pole filter required. High external source resistance, combined with 13pF input capacitance, will reduce rated 50MHz input bandwidth increase acquisition time beyond 39ns.
ANALOG INPUT
47pF*
CH0+ CH0- LTC1408-12
10µF ANALOG INPUT 47pF*
VREF
3.5V
CH1+ CH1-
1408
*TIGHT TOLERANCE REQUIRED AVOID APERTURE SKEW DEGRADATION
Figure Input Filter
INPUT RANGE analog inputs LTC1408-12 driven fully differentially with single supply. Either input swing VCC, provided differential swing greater than 2.5V with (Pin Low, ±1.25V with (BIP High. 2.5V range also ideally suited singleended input with single supply applications. common mode range inputs extend from ground supply voltage VCC. difference between input pair exceeds 2.5V (unipolar) 1.25V (bipolar), output code will stay fixed positive fullscale, this difference goes below (unipolar) 1.25V (bipolar), output code will stay fixed negative full-scale. INTERNAL REFERENCE LTC1408-12 on-chip, temperature compensated, bandgap reference that factory trimmed 2.5V obtain precise 2.5V input span. reference amplifier output VREF, (Pin must bypassed with capacitor ground. reference amplifier stable with capacitors greater. best noise performance, 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic recommended. VREF overdriven with external reference shown Figure voltage external reference must higher than 2.5V open-drain P-channel output internal reference. recommended range external reference 2.55V VDD. external reference 2.55V will quiescent load 0.75mA much during conversion.
LT1790-3 10µF VREF LTC2351-12
1408
Figure Overdriving VREF with External Reference
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LTC1408-12
APPLICATIO ATIO
INPUT SPAN VERSUS REFERENCE VOLTAGE
differential input range unipolar voltage span that equals difference between voltage reference buffer output VREF (Pin voltage ground. differential input range 2.5V when using internal reference. internal referenced these nodes. This relationship also holds true with external reference. DIFFERENTIAL INPUTS will always convert difference minus CH-, independent common mode voltage pair inputs. common mode rejection holds high frequencies (see Figure only requirement that both inputs below ground exceed VDD.
STRAIGHT BINARY OUTPUT CODE
CMRR (dB)
-100
-120 100k 100M FREQUENCY (Hz)
1408
Figure CMRR Frequency
COMPLEMENT OUTPUT CODE
Integral nonlinearity errors (INL) differential nonlinearity errors (DNL) largely independent common mode voltage. However, offset error will vary. CMRR typically better than -90dB.
Figure shows ideal input/output characteristics LTC1408-12 unipolar mode (BIP Low). code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, 1.5LSB). output code straight binary with 1LSB 2.5V/4096 610µV LTC1408-12. LTC1408-12 Gaussian white noise.
111.111 111.110 111.101 000.010 000.001 000.000 INPUT VOLTAGE
1408
1LSB
Figure LTC1408-12 Transfer Characteristic Unipolar Mode (BIP Low)
Figure shows ideal input/output characteristics LTC1408-12 bipolar mode (BIP High). code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, 1.5LSB). output code complement with 1LSB 2.5V/4096 610µV LTC1408-12. LTC1408-12 Gaussian white noise.
011.111 011.110 011.101
100.010 100.001 100.000 INPUT VOLTAGE
1408
1LSB
Figure LTC1408-12 Transfer Characteristic Bipolar Mode (BIP High)
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LTC1408-12
APPLICATIO ATIO
POWER-DOWN MODES
Upon power-up, LTC1408-12 initialized active state ready conversion. Sleep mode waveforms show power down modes LTC1408-12. CONV inputs control power down modes (see Timing Diagrams). rising edges CONV, without intervening rising edges SCK, LTC1408-12 mode power consumption drops from 15mW 3.3mW. internal reference remains powered mode. more rising edges wake LTC1408-12 very quickly CONV start accurate conversion within clock cycle. Four rising edges CONV, without intervening rising edges SCK, LTC1408-12 Sleep mode power consumption drops from 15mW 6µW. more rising edges wake LTC1408-12 operation. internal reference (VREF takes slew settle with 10µF load. Using sleep mode more frequently compromises accuracy output data. Note that slower conversion rates, Sleep modes used substantial reductions power consumption. DIGITAL INTERFACE LTC1408-12 3-wire (Serial Peripheral Interface) interface. CONV inputs output implement this interface. CONV inputs accept swings from logic compatible, logic swing does exceed VDD. detailed description three serial port signals follows:
Conversion Start Input (CONV) rising edge CONV starts conversion, subsequent rising edges CONV ignored LTC1408-12 until following rising edges have occurred. duty cycle CONV arbitrarily chosen used frame sync signal processor serial port. simple approach generate CONV create pulse that wide drive LTC1408-12 then buffer this signal drive frame sync input processor serial port. good practice drive LTC1408-12 CONV input first avoid digital noise interference during sample-to-hold transition triggered CONV start conversion. also good practice keep width portion CONV signal greater than 15ns avoid introducing glitches front just before sample-and-hold goes into Hold mode rising edge CONV. Minimizing Jitter CONV Input high speed applications where high amplitude sine waves above 100kHz sampled, CONV signal must have little jitter possible (10ps less). square wave output common crystal clock module usually meets this requirement. challenge generate CONV signal from this crystal clock without jitter corruption from other digital circuits system. clock divider gates signal path from crystal clock CONV input should share same integrated circuit with other parts system. CONV inputs should driven first, with digital buffers
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LTC1408-12
APPLICATIO ATIO
used drive serial port interface. Also note that master clock already corrupted with jitter, even comes directly from crystal. Another problem with high speed processor clocks that they often cost, speed crystal (i.e., 10MHz) generate fast, jittery, phase-locked-loop system clock (i.e., 40MHz). jitter these PLL-generated high speed clocks several nanoseconds. Note that choose frame sync signal generated port, this signal will have same jitter DSP's master clock. Typical Application Figure page shows circuit level-shifting squaring output from signal generator other low-jitter source. single D-type flip flop used generate CONV signal LTC1408-12. Re-timing master clock signal eliminates clock jitter introduced controlling device (DSP, FPGA, etc.) Both inverter flip flop must treated analog components should powered from clean analog supply. Serial Clock Input (SCK) rising edge advances conversion process also udpates each data stream. After CONV rises, third rising edge sends sets data bits, with sent first. simple approach generate drive LTC1408-12 first then buffer this signal with appropriate number inverters drive serial clock input processor serial port. falling edge clock latch data from Serial Data Output (SDO) into your processor serial port. 12-bit Serial Data will received 16-bit words with more clocks frame sync. fewer than channels selected SEL0-SEL2 conversion, then clocks needed channel convert analog inputs read resulting data
after next convert pulse. good practice drive LTC1408-12 input first avoid digital noise interference during internal comparison decision internal high speed comparator. Unlike CONV input, input sensitive jitter because input signal already sampled held constant. Serial Data Output (SDO) Upon power-up, output automatically reset high impedance state. output remains high impedance until conversion started. sends sets bits output data stream after third rising edge after start conversion with rising edge CONV. fewer 12-bit words separated don't care bits clock cycles high impedance mode. Please note delay specification from valid SDO. always guaranteed valid next rising edge SCK. 96-bit output data stream compatible with 16-bit 32-bit serial port most processors. BOARD LAYOUT BYPASSING Wire wrap boards recommended high resolution and/or high speed converters. obtain best performance from LTC1408-12, printed circuit board with ground plane required. Layout printed circuit board should ensure that digital analog signal lines separated much possible. particular, care should taken digital track alongside analog signal track. optimum phase match between inputs desired, length twelve input wires input channels should kept matched. each pair input wires input channels should kept separated ground trace avoid high frequency crosstalk between channels.
140812f
LTC1408-12
APPLICATIO ATIO
High quality tantalum ceramic bypass capacitors should used VCC, VREF pins shown Block Diagram first page this data sheet. optimum performance, 10µF surface mount tantalum capacitor with 0.1µF ceramic recommended VCC, VREF pins. Alternatively, 10µF ceramic chip capacitors such used. capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible. bypass capacitor returns ground plane VREF bypass capacitor returns Care should taken place 0.1µF bypass capacitor close Pins possible. Figure shows recommended system ground connections. analog circuitry grounds should terminated LTC1408-12 Exposed Pad. ground return from LTC1408-12 power supply should impedance noise-free operation. Exposed 32pin package also internally tied ground pads. Exposed should soldered board reduce ground connection inductance. ground pins (GND, DGND, OGND) must connected directly same ground plane under LTC1408-12.
OVDD BYPASS, 0.1µF, 0402
BYPASS, 0.1µF, 0402 BYPASS, 0.1µF, 0402 10µF, 0805
VREF BYPASS, 10µF, 0805
Figure Recommended Layout
HARDWARE INTERFACE TMS320C54x LTC1408-12 serial output whose interface been designed high speed buffered serial ports fast digital signal processors (DSPs). Figure shows example this interface using TMS320C54X. buffered serial port TMS320C54x direct access segment memory. ADC's serial data collected alternating segments, real time, full 600ksps conversion rate LTC1408-12. assembly code sets frame sync mode BFSR accept external positive going pulse serial clock BCLKR accept external positive edge clock. Buffers near LTC1408-12 added drive long tracks prevent corruption signal LTC1408-12. This configuration adequate traverse typical system board, source resistors buffer outputs termination resistors DSP, needed match characteristic impedance very long transmission lines. need terminate transmission line, buffer first with 74ACxx gates. threshold inputs port respond properly swing used with LTC1408-12.
LTC1408-12 OVDD CONV TMS320C54x BFSR OGND DGND CONV 3-WIRE SERIAL INTERFACE LINK
1408
BCLKR
LOGIC SWING
Figure Serial Interface TMS320C54x
140812f
LTC1408-12
PACKAGE DESCRIPTIO
Package 32-Lead Plastic (5mm 5mm)
(Reference 05-08-1693)
0.70 ±0.05 PACKAGE OUTLINE 0.25 0.05 0.50 RECOMMENDED SOLDER LAYOUT APPLY SOLDER MASK AREAS THAT SOLDERED 5.00 0.10 SIDES) MARK (NOTE 0.75 0.05 0.05 0.00 0.05 BOTTOM VIEW-EXPOSED 0.115 0.40 0.10 3.45 0.10 NOTCH 0.30 0.35 CHAMFER 3.50 (4-SIDES) 3.45 0.10
(UH32) 0406
5.50 ±0.05 4.10 ±0.05 3.50 SIDES) 3.45 0.05
3.45 0.05
0.200 NOTE: DRAWING PROPOSED JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) APPROVED) DRAWING SCALE DIMENSIONS MILLIMETERS DIMENSIONS EXPOSED BOTTOM PACKAGE INCLUDE MOLD FLASH. MOLD FLASH, PRESENT, SHALL EXCEED 0.20mm SIDE EXPOSED SHALL SOLDER PLATED SHADED AREA ONLY REFERENCE LOCATION BOTTOM PACKAGE
0.25 0.05 0.50
140812f
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC1408-12 RELATED PARTS
PART NUMBER ADCs LTC1402 LTC1403/LTC1403A LTC1405 LTC1407/LTC1407A LTC1408 LTC1411 LTC1412 LTC1420 LTC1608 LTC1609 LTC1864/LTC1865 LTC1864L/LTC1865L DACs LTC1592 LTC1666/LTC1667 LTC1668 References LT1460-2.5 LT1461-2.5 LT1790-2.5 Micropower Series Voltage Reference Precision Voltage Reference Micropower Series Reference SOT-23 0.10% Initial Accuracy, 10ppm Drift 0.04% Initial Accuracy, 3ppm Drift 0.05% Initial Accuracy, 10ppm Drift 16-Bit, Serial SoftSpanIOUT 12-/14-/16-Bit, 50Msps ±1LSB INL/DNL, Software Selectable Spans 87dB SFDR, 20ns Settling Time 12-Bit, 2.2Msps Serial 12-/14-Bit, 2.8Msps Serial 12-Bit, 5Msps Parallel 12-/14-Bit, 3Msps Simultaneous Sampling 14-Bit, 600ksps Simultaneous Sampling 14-Bit, 2.5Msps Parallel 12-Bit, 3Msps Parallel 12-Bit, 10Msps Parallel 16-Bit, 500ksps Parallel 16-Bit, 250ksps Serial 16-Bit, 250ksps 1-/2-Channel Serial ADCs Supply, 4.096V ±2.5V Span 15mW, Unipolar Inputs, MSOP Package 15mW, Bipolar Inputs, MSOP Package Selectable Spans, 115mW 14mW, 2-Channel Unipolar Input Range 14mW, 2-Channel Bipolar Input Range 15mW, Selectable Bipolar (Unipolar Input, Differential Inputs) Selectable Spans, 80dB SINAD Supply, ±2.5V Span, 72dB SINAD Selectable Spans, 72dB SINAD Supply, ±2.5V Span, 90dB SINAD Configurable Bipolar/Unipolar Inputs (L-Version), Micropower, MSOP Package DESCRIPTION COMMENTS
LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial
LTC1407-1/LTC1407A-1 12-/14-Bit, 3Msps Simultaneous Sampling
SoftSpan trademark Linear Technology Corporation.
TYPICAL APPLICATIO
Low-Jitter Clock Timing with Sine Generator Using Clock Squaring/Level Shifting Circuit Re-Timing Flip-Flop
NC7SVU04P5X MASTER CLOCK CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) CONV NL17SZ74 CONVERT ENABLE
1408 TA02
0.1µF
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408) 432-1900
FAX: (408) 434-0507 www.linear.com
1408-12
140812f LT/LWI 1006 PRINTED LINEAR TECHNOLOGY CORPORATION 2006

LTC1408-12 12-bit, 600ksps with simultaneously sampled differential in

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