Data Sheet December 2008 FN6814.0 10-Bit, 275/210/170/105MSPS Con
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KAD2710C
Data Sheet December 2008 FN6814.0
10-Bit, 275/210/170/105MSPS Converter
KAD2710C industry's lowest power, 10-bit, 275MSPS, high performance Analog-to-Digital converter. designed with Intersil's proprietary FemtoChargetechnology standard CMOS process. KAD2710C offers high dynamic performance (55.6dBFS 138MHz) while consuming less than 265mW. Features include over-range indicator selectable divide-by-2 input clock divider. KAD2710C member pin-compatible family offering 10-bit ADCs with sample rates from 350MSPS LVDS-compatible LVCMOS outputs (Table This family products available 68-pin RoHS-compliant packages with exposed paddle. Performance specified over full industrial temperature range (-40°C +85°C).
CLKDIV AVDD2 AVDD3 OVDD
Features
On-Chip Reference Internal Sample Hold 1.5VP-P Differential Input Voltage 600MHz Analog Input Bandwidth Two's Complement Binary Output Over-Range Indicator Selectable Clock Input LVCMOS Outputs Pb-Free (RoHS Compliant)
Applications
High-Performance Data Acquisition Portable Oscilloscope Medical Imaging Cable Head Ends
CLK_P CLK_N
Clock Generation
CLKOUTP CLKOUTN
Power-Amplifier Linearization Radar Satellite Antenna Array Processing Broadband Communications Point-to-Point Microwave Systems
VREF
10-bit 275MSPS
1.21V
LVCMOS Drivers
Communications Test Equipment
Specs
55.6dBFS 275MSPS, 138MHz SFDR 68.5dBc 275MSPS, 138MHz Power consumption <265mW 275MSPS
VREFSEL
OVSS
AVSS
Pin-Compatible Family
TABLE PIN-COMPATIBLE PRODUCTS RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS Bits 350MSPS Bits 275MSPS Bits 210MSPS Bits 170MSPS Bits 105MSPS Bits 275MSPS Bits 210MSPS Bits 170MSPS Bits 105MSPS KAD2708L-35 KAD2708L-27 KAD2708L-21 KAD2708L-17 KAD2708L-10 KAD2710L-27 KAD2710L-21 KAD2710L-17 KAD2710L-10 KAD2708C-27 KAD2708C-21 KAD2708C-17 KAD2708C-10 KAD2710C-27 KAD2710C-21 KAD2710C-17 KAD2710C-10
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. FemtoCharge trademark Kenet Inc. Copyright Intersil Americas Inc. 2008. Rights Reserved other trademarks mentioned property their respective owners.
KAD2710C Ordering Information
PART NUMBER (Note) KAD2710C-27Q68 KAD2710C-21Q68 KAD2710C-17Q68 KAD2710C-10Q68 SPEED (MSPS) TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. L68.10x10B L68.10x10B L68.10x10B L68.10x10B
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, 100% matte plate plus anneal termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations). Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
FN6814.0 December 2008
KAD2710C Table Contents
Absolute Maximum Ratings Thermal Information. Electrical Specifications Digital Specifications Timing Diagram Timing Specifications Thermal Impedance. Descriptions Pinout Typical Performance Curve Functional Description Reset Voltage Reference. Analog Input Clock Input Jitter. Digital Outputs
Equivalent Circuits. Layout Considerations Split Ground Power Planes Clock Input Considerations. Bypass Filtering LVCMOS Outputs. Unused Inputs
Definitions. Package Outline Drawing L68.10x10B
FN6814.0 December 2008
KAD2710C
Absolute Maximum Ratings
AVDD2 AVSS. -0.4V 2.1V AVDD3 AVSS. -0.4V 3.7V OVDD2 OVSS -0.4V 2.1V Analog Inputs AVSS. -0.4V AVDD3 0.3V Clock Inputs AVSS. -0.4V AVDD2 0.3V Logic Inputs AVSS (VREFSEL, CLKDIV) -0.4V AVDD3 0.3V Logic Inputs OVSS (RST, 2SC) -0.4V OVDD2 0.3V VREF AVSS -0.4V AVDD3 0.3V Analog Output Currents 10mA Logic Output Currents 10mA LVDS Output Currents 20mA
Thermal Information
Operating Temperature .-40°C +85°C Storage Temperature .-65°C +150°C Junction Temperature +150°C
CAUTION: operate near maximum ratings listed extended periods time. Exposure such conditions adversely impact product reliability result failures covered warranty.
Electrical Specifications specifications apply under following conditions unless otherwise noted: AVDD2 1.8V, AVDD3 3.3V,
OVDD 1.8V, -40°C +85°C (typical specifications +25°C), fSAMPLE 350MSPS, 270MSPS, 210MSPS, 170MSPS 105MSPS, Nyquist -0.5dBFS. KAD2710C-27 PARAMETER SPECIFICATIONS Analog Input Full-Scale Analog Input Range Full Scale Range Temp. Drift Common-Mode Output Voltage Power Requirements 1.8V Analog Supply Voltage 3.3V Analog Supply Voltage 1.8V Digital Supply Voltage 1.8V Analog Supply Current 3.3V Analog Supply Current 1.8V Digital Supply Current Power Dissipation SPECIFICATIONS Maximum Conversion Rate Minimum Conversion Rate Differential Nonlinearity Integral Nonlinearity Signal-to-Noise Ratio 10MHz Nyquist 430MHz Signal-to-Noise Distortion SINAD 10MHz Nyquist 430MHz -1.0 ±0.8 -2.5 ±1.0 55.7 53.5 55.6 55.2 55.3 52.5 55.2 54.4 -1.0 ±0.8 -2.5 ±1.0 56.4 53.5 56.2 54.8 56.1 52.5 56.0 53.7 -1.0 ±0.8 -2.5 ±1.0 56.6 53.5 56.5 54.6 56.3 52.5 56.2 53.4 -1.0 ±0.8 -2.5 ±1.0 56.6 53.5 56.5 54.5 56.3 52.5 56.2 53.2 MSPS MSPS dBFS dBFS dBFS dBFS dBFS dBFS AVDD2 AVDD3 OVDD IAVDD2 IAVDD3
OVDD
KAD2710C-21
KAD2710C-17
KAD2710C-10
SYMBOL
CONDITIONS
UNITS
AVTC Full Temp
VP-P ppm/°C
3.15
3.45
3.45 3.15
3.45 3.15
3.45 3.15
FN6814.0 December 2008
KAD2710C
Electrical Specifications specifications apply under following conditions unless otherwise noted: AVDD2 1.8V, AVDD3 3.3V,
OVDD 1.8V, -40°C +85°C (typical specifications +25°C), fSAMPLE 350MSPS, 270MSPS, 210MSPS, 170MSPS 105MSPS, Nyquist -0.5dBFS. (Continued) KAD2710C-27 PARAMETER Effective Number Bits SYMBOL ENOB CONDITIONS 10MHz Nyquist 430MHz Spurious-Free Dynamic Range SFDR 10MHz Nyquist 430MHz Two-Tone SFDR Word Error Rate Full Power Bandwidth 2TSFDR 133MHz, 135MHz FPBW KAD2710C-21 KAD2710C-17 KAD2710C-10
UNITS 68.5 68.5 63.8 10-12 71.1 62.6 10-12 60.1 10-12 60.9 10-12 Bits Bits Bits
Digital Specifications
PARAMETER INPUTS Input Voltage High (VREFSEL) Input Voltage (VREFSEL) Input Current High (VREFSEL) Input Current (VREFSEL) Input Voltage High (CLKDIV) Input Voltage (CLKDIV) Input Current High (CLKDIV) Input Current (CLKDIV) Input Voltage High (RST,2SC) Input Voltage (RST,2SC) Input Current High (RST,2SC) Input Current (RST,2SC) Input Capacitance CLKP, CLKN Differential Input Voltage CLKP, CLKN Differential Input Resistance CLKP, CLKN Common-Mode Input Voltage LVCMOS OUTPUTS Output Voltage High Output Voltage Output Rise Time Output Fall Time VCDI RCDI VCCI OVDD OVSS AVDD3 AVSS 0.8*OVDD2 0.2*OVDD2 AVDD3 AVSS 0.8*AVDD3 0.2*AVDD3 0.8*AVDD3 0.2*AVDD3 VP-P SYMBOL CONDITIONS UNITS
FN6814.0 December 2008
KAD2710C Timing Diagram
Sample
CLKN CLKP
tPID
CLKOUT
tPCD
D[9:0]
Data invalid
Data N-L+1
Data
FIGURE LVCMOS TIMING DIAGRAM
Timing Specifications
PARAMETER Aperture Delay Aperture Jitter Input Clock Data Propagation Delay Data Hold Time Output Clock Data Propagation Delay Latency (Pipeline Delay) Overvoltage Recovery SYMBOL tPID tPCD tOVR -300 UNITS cycles cycle
Thermal Impedance
PARAMETER Junction Paddle (Note NOTE: Paddle soldered ground plane. SYMBOL UNIT °C/W
Electrostatic charge accumulates humans, tools equipment discharge through metallic package contacts (pins, balls, exposed paddle, etc.) integrated circuit. Industry-standard protection techniques have been utilized design this product. However, reasonable care must taken storage handling sensitive products. Contact Intersil specific sensitivity rating this product.
FN6814.0 December 2008
KAD2710C Descriptions
NUMBER 11-13, 29-33, 64-66 Exposed Paddle AVSS NAME AVDD2 AVSS VREF VREFSEL AVDD3 INP, CLKDIV CLKN, CLKP OVSS OVDD2 CLKOUT 1.8V Analog Supply Analog Supply Return Reference Voltage Out/In Reference Voltage Select (0:Int 1:Ext) Common-Mode Voltage Output 3.3V Analog Supply Analog Input Positive, Negative Connect Clock Divide (Active Low) Clock Input Complement, True Output Supply Return 1.8V LVCMOS Supply Power Reset (Active Low) LVCMOS (LSB) Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Clock Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS (MSB) Output Over-Range Connect OVDD2 Two's Complement Select (Active Low) Analog Supply Return FUNCTION
FN6814.0 December 2008
KAD2710C Pinout
KAD2710C QFN) VIEW
AVDD2 AVSS VREF VREFSEL AVDD3 AVSS AVSS AVDD2 AVDD3 AVDD3 CLKDIV
OVDD2 OVDD2 OVDD2 OVSS OVDD2
KAD2710C
View Scale
OVSS OVDD2 CLKOUT OVDD2
AVDD2 AVSS AVDD2 AVSS CLKN CLKP AVSS AVDD3 OVSS OVDD2
FIGURE CONFIGURATION
FN6814.0 December 2008
KAD2710C Typical Performance Curves
SNR(dBFS), SFDR(dBc) SFDR
HD2, (dBc
AVDD2 OVDD2 1.8V, AVDD3 3.3V, +25°C, fSAMPLE 275MSPS, 137MHz, -0.5dBFS unless noted.
(MHz)
-100 (MHz)
FIGURE SFDR
FIGURE
SNR(dBFS), SFDR(dBc)
HD2, (dBc)
SFDR
(dBFS)
(dBFS)
FIGURE SFDR
FIGURE
SFDR SNR(dBFS), SFDR(dBc)
HD2, HD3(dBc)
fSAMPLE (MSPS)
-100 SAMPLE (fS) (MSPS)
FIGURE SFDR fSAMPLE
FIGURE fSAMPLE
FN6814.0 December 2008
KAD2710C Typical Performance Curves
Power Dissipation (PD) (mW)
(LSBs) 0.75 0.25 -0.25 -0.5 -0.75
AVDD2 OVDD2 1.8V, AVDD3 3.3V, +25°C, fSAMPLE 275MSPS, 137MHz, -0.5dBFS unless noted. (Continued)
fSAMPLE (fS) (MSPS)
FIGURE POWER DISSIPATION fSAMPLE
CODE
1023
FIGURE DIFFERENTIAL NONLINEARITY OUTPUT CODE
(LSBs)
-0.5
CODE
1023
FIGURE INTEGRAL NONLINEARITY OUTPUT CODE
FIGURE NOISE HISTOGRAM
-0.49dBFS
-0.49dBFS
AMPLITUDE (dB)
56.5dBFS
AMPLITUDE (dB)
56.5dBF 71.0dBc SINAD 55.7dBc -84.8dBc -71.0dBc
70.0dBc INAD 55.7dBc -94.3dBc -70.5dBc
-100 -120
-100 -120
FREQUENCY (MHz)
FREQUE (MHz)
FIGURE OUTPUT SPECTRUM; 10MHz
FIGURE OUTPUT SPECTRUM; 134MHz
FN6814.0 December 2008
KAD2710C Typical Performance Curves
-0.50dBFS
AVDD2 OVDD2 1.8V, AVDD3 3.3V, +25°C, fSAMPLE 275MSPS, 137MHz, -0.5dBFS unless noted. (Continued)
-7dBFS
56.0dBFS
AMPLITUDE (dB) -100 -120
RELATIVE POWER (dB)
2TSFDR 71dBc IMD3 -78dBFS
63.6dBc SINAD 55.1dBc -67.8dBc 63.6dBc
-100 -120
FREQ UENCY (MHz)
FREQUENCY (MHz)
FIGURE OUTPUT SPECTRUM; 300MHz
FIGURE TWO-TONE SPECTRUM; 69MHz, 70MHz
RELATIVE POWER (dB) -100 -120
-7dBFS
RELATIVE POWER (dB) -100 -120
-7dBFS 2TSFDR 63dBc IMD3 -75dBFS
2TSFDR 74.7dBc IMD3 -84.5dBFS
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE TWO-TONE SPECTRUM; 140MHz, 141MHz
FIGURE TWO-TONE SPECTRUM; 300MHz, 305MHz
SNR(dBFS), SFDR(dBc)
SFDR
tCAL(ms)
Ambient Temperature deg.C
SAMPLE (MSPS)
FIGURE TEMPERATURE
FIGURE CALIBRATION TIME
FN6814.0 December 2008
KAD2710C Functional Description
KAD2710 bit, 275MSPS converter pipelined architecture. input voltage captured sample hold circuit converted unit charge. Proprietary charge-domain techniques used compare input series reference charges. These comparisons determine digital code each input value. converter pipeline requires sample clocks produce result. Digital error correction also applied, resulting total latency clock cycles. This evident user latency between start conversion data being available digital outputs. power-up, self-calibration performed minimize gain offset errors. reset (RST) held internally power-up will remain that state until calibration complete. clock frequency should remain fixed during this time. Calibration accuracy maintained sample rate which performed, therefore should repeated clock frequency changed more than 10%. Recalibration initiated pin, power cycling, time.
Voltage Reference
VREF reference voltage which sets fullscale input voltage chip. This requires bypass capacitor 0.1uF minimum. internally generated bandgap reference voltage provided on-chip voltage buffer.buffer sink source 50µA externally. external voltage applied this provide more accurate reference than internally generated bandgap voltage, match full-scale reference multiple KAD2710C chips.One option latter configuration KAD2710C's internally generated reference external reference voltage other chips system. Additionally, externally provided reference changed from nominal value adjust full-scale input voltage within limited range. select whether full-scale reference internally generated externally provided, digital input VREFSEL internal, high external.This internal pull-up.use internally generated reference VREFSEL tied directly AVSS, external reference VREFSEL left unconnected.
Analog Input
core contains fully differential input (INP/INN) sample hold circuit. ideal full-scale input voltage 1.50V, centered voltage 0.86V shown Figure
-0.75V 0.75V 0.86V
Reset
Recalibration initiated time driving minimum clock cycle. open-drain driver recommended. calibration sequence initiated rising edge RST, shown Figure over-range output (OR) high once pulled low, remains that state until calibration complete. output returns normal operation that time, important that analog input within converter's full-scale range order observe transition. input over-range state will stay high will possible detect calibration cycle. While low, output clock (CLKOUT) stops toggling low. Normal operation output clock resumes next input clock edge (CLKP/CLKN) after deasserted. 275MSPS nominal calibration time ~240ms.
CLKN CLKP Calibration Time Calibration Begins Calibration Complete CLKOUTP
FIGURE ANALOG INPUT RANGE
Best performance obtained when analog inputs driven differentially. common-mode output voltage, VCM, should used properly bias inputs shown Figures transformer will give best noise distortion performance wideband and/or high intermediate frequency (IF) inputs. different transformer input schemes shown Figures
FIGURE CALIBRATION TIMING
FN6814.0 December 2008
KAD2710C
0.01µF Analog
ADT1-1WT ADT1-1WT
KAD2710
recommended drive circuit shown Figure clock driven single-ended, this will reduce edge rate impact performance.
AVDD2
0.1µF
FIGURE TRANSFORMER INPUT GENERAL APPLICATIONS
CLKP 200O CLKN
Clock Input TC4-1W
ADTL1-12 Analog Input
ADTL1-12 KAD2710
FIGURE RECOMMENDED CLOCK DRIVE
0.1µF
FIGURE TRANSMISSION-LINE TRANSFORMER INPUT HIGH APPLICATIONS
back-to-back transformer scheme used improve common-mode rejection, which keeps common-mode level input matched VCM. value shunt resistor should determined based desired load impedance. sample hold circuit design uses switched capacitor input stage, which creates current spikes when sampling capacitance reconnected input voltage. This creates disturbance input which must settle before next sampling point. Lower source impedance will result faster settling improved performance. Therefore transformer shunt resistance recommended optimal performance. differential amplifier used applications that require coupling. this configuration amplifier will typically determine achievable distortion. typical differential amplifier circuit shown Figure
348O 69.8O
100O Analog Input 49.9O 0.22µF
clock divider optional. KAD2710C's requires clock with duty cycle optimum performance. such clock available, option generate twice desired sampling rate KAD2710C's divide-by-2 setting. This frequency divider uses rising edge clock, clock duty cycle assured. Table describes CLKDIV connection.
TABLE CLKDIV SETTINGS CLKDIV AVSS AVDD DIVIDE RATIO
CLKDIV internally pulled low, pull-up resistor logic driver must connected undivided clock.
Jitter
sampled data system, clock jitter directly impacts achievable performance. theoretical relationship between clock jitter (tJ) shown Equation illustrated Figure
(EQ.
Where uncertainty sampling instant.
217O
KAD2710
tj=0.1p Bits
100O
69.8O 348O
0.1µF
tj=1
tj=1
Bits
FIGURE DIFFERENTIAL AMPLIFIER INPUT
Bits
tj=1
Clock Input
sample clock input circuit differential pair (see Figure 29). Driving these inputs with high level 1.8VP-P each input) sine square wave will provide lowest jitter performance.
Input Frequency
FIGURE CLOCK JITTER
FN6814.0 December 2008
KAD2710C
This relationship shows that would achieved clock jitter were only non-ideal factor. reality, achievable limited internal factors such linearity, aperture jitter thermal noise. Internal aperture jitter uncertainty sampling instant shown Figure internal aperture jitter combines with input clock jitter root-sum-square fashion, since they statistically correlated, this determines total jitter system. total jitter, combined with other noise sources, then determines achievable SNR.
Digital Outputs
Data output parallel with LVCMOS drivers. output format (Binary Two's Complement) selected shown Table
TABLE SETTINGS AVSS AVDD unconnected) MODE Two's Complement Binary
Equivalent Circuits
AVDD2
AVDD3 Charge Pipeline
AVDD3
Csamp 0.3pF
AVDD2
Clock Generation
CLKP
Csamp 0.3pF
Charge Pipeline
AVDD2
CLKN
FIGURE ANALOG INPUTS
FIGURE CLOCK INPUTS
OVDD OVDD
DATA
D[9:0]
FIGURE LVCMOS OUTPUTS
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
FN6814.0 December 2008
KAD2710C Layout Considerations
Split Ground Power Planes
Data converters operating high sampling frequencies require extra care board layout. analog digital ground planes separate, analog supply ground planes should laid under signal clock inputs digital planes under outputs logic pins. Grounds should joined under chip. Effective Number Bits (ENOB) alternate method specifying Signal Noise-and-Distortion Ratio (SINAD). calculated ENOB (SINAD 1.76)/6.02 Gain Error ratio difference between voltages that cause lowest highest code transitions full-scale voltage (less LSB). typically expressed percent. Integral Non-Linearity (INL) deviation each individual code from line drawn from negative full-scale (1/2 below first code transition) through positive full-scale (1/2 above last code transition). deviation given code from this line measured from center that code. Least Significant (LSB) that smallest value weight digital word. value terms input voltage VFS/(2N where resolution bits. Missing Codes output codes that skipped will never appear output. These codes cannot reached with input value. Most Significant (MSB) that largest value weight. Pipeline Delay number clock cycles between initiation conversion appearance output pins data. Power Supply Rejection Ratio (PSRR) ratio change input voltage necessary correct change output code that results from change power supply voltage. Signal Noise-and-Distortion (SINAD) ratio signal amplitude other spectral components below half clock frequency, including harmonics excluding Signal-to-Noise Ratio (SNR) (without Harmonics) ratio signal amplitude other spectral components below one-half sampling frequency, excluding harmonics SINAD either given units carrier) when power level fundamental used reference, dBFS full scale) when converter's full-scale input power used reference. Spurious-Free-Dynamic Range (SFDR) ratio signal amplitude value peak spurious spectral component. peak spurious spectral component harmonic. Two-Tone SFDR ratio value lowest power input tone value peak spurious component, which product.
Clock Input Considerations
matched transmission lines inputs analog input clock signals. Locate transformers, drivers terminations close chip possible.
Bypass Filtering
Bulk capacitors should have equivalent series resistance. Tantalum recommended. Keep ceramic bypass capacitors very close device pins. Longer traces will increase inductance, resulting diminished dynamic performance accuracy. Make sure that connections ground direct, impedance.
LVCMOS Outputs
Output traces connections must designed characteristic impedance. Keep trace lengths equal, minimize bends where possible. Avoid crossing ground power-plane breaks with signal traces.
Unused Inputs
inputs internally pulled left open-circuit used. CLKDIV internally pulled low, which divides input clock two. VREFSEL must held internal reference, left open external reference.
Definitions
Analog Input Bandwidth analog input frequency which spectral output power fundamental frequency determined analysis) reduced from full-scale low-frequency value. This also referred Full Power Bandwidth. Aperture Delay Sampling Delay time required after rise clock input sampling switch open, which time signal held conversion. Aperture Jitter variation aperture delay samples. Clock Duty Cycle ratio time clock wave logic high total time clock period. Differential Non-Linearity (DNL) deviation code width from ideal step.
FN6814.0 December 2008
KAD2710C
Package Outline Drawing
L68.10x10B
LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE 11/08
INDEX AREA 10.00
8.00
INDEX AREA 0.50
10.00
Exp. 7.70
0.15 (4X)
VIEW
0.55
BOTTOM VIEW
0.25
0.10
0.90 8.00
DETAIL 0.10
0.50
SIDE VIEW
0.08 SEATING PLANE
0.25 9.65
7.70
MIN. MAX. 0.75
DETAIL
TYPICAL RECOMMENDED LAND PATTERN
NOTES: Dimensions millimeters. Dimensions Reference Only.
Dimensioning tolerancing conform AMSEY14.5m-1994. Unless otherwise specified, tolerance Decimal 0.05 Dimension applies metallized terminal measured between 0.15mm 0.30mm from terminal tip. Tiebar shown present) non-functional feature. configuration identifier optional, must located within zone indicated. identifier either mold mark feature.
FN6814.0 December 2008
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