Data Sheet December 2008 FN6812.0 8-Bit, 275/210/170/105MSPS Conv

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Data Sheet December 2008 FN6812.0 8-Bit, 275/210/170/105MSPS Conv

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KAD2708C
Data Sheet December 2008 FN6812.0
8-Bit, 275/210/170/105MSPS Converter
KAD2708C industry's lowest power, 8-bit, 275MSPS, high performance Analog-to-Digital converter. designed with Intersil's proprietary FemtoChargetechnology standard CMOS process. KAD2708C offers high dynamic performance (49.2dBFS 138MHz) while consuming less than 265mW. Features include over-range indicator selectable divide-by-2 input clock divider. KAD2708C member pin-compatible family offering 10-bit ADCs with sample rates from 105MSPS 350MSPS LVCMOS LVDS-compatible outputs (Table This family products available 68-pin RoHS-compliant packages with exposed paddle. Performance specified over full industrial temperature range (-40°C +85°C).
AVDD3 CLKDIV AVDD2 OVDD
Features
On-Chip Reference Internal Track Hold 1.5VP-P Differential Input Voltage 600MHz Analog Input Bandwidth Two's Complement Binary Output Over-Range Indicator Selectable Clock Input LVCMOS Outputs
Applications
High-Performance Data Acquisition Portable Oscilloscope Medical Imaging Cable Head Ends Power-Amplifier Linearization
CLK_P CLK_N
Clock Generation
CLKOUT
Radar Satellite Antenna Array Processing Broadband Communications
Point-to-Point Microwave Systems Communications Test Equipment
VREF VREFSEL
8-bit 275MSPS
LVCMOS Drivers
Specifications
1.21
49.2dBFS 275MSPS, 138MHz SFDR 66.6dBc 275MSPS, 138MHz Power Consumption 265mW 275MSPS
OVSS
AVSS
Pin-Compatible Family
TABLE PIN-COMPATIBLE PRODUCTS RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS PKG. DWG. Bits 350MSPS Bits 275MSPS Bits 275MSPS Bits 210MSPS Bits 210MSPS Bits 170MSPS Bits 170MSPS Bits 105MSPS Bits 105MSPS KAD2708L-35 KAD2710L-27 KAD2708L-27 KAD2710L-21 KAD2708L-21 KAD2710L-17 KAD2708L-17 KAD2710L-10 KAD2708L-10 KAD2710C-27 KAD2708C-27 KAD2710C-21 KAD2708C-21 KAD2710C-17 KAD2708C-17 KAD2710C-10 KAD2708C-10
Ordering Information
PART NUMBER KAD2708C-27Q68 KAD2708C-21Q68 KAD2708C-17Q68 KAD2708C-10Q68 SPEED (MSPS) TEMP. RANGE (°C) PACKAGE
L68.10x10B L68.10x10B L68.10x10B L68.10x10B
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, 100% matte plate plus anneal termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations). Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. FemtoCharge trademark Kenet Inc. Copyright Intersil Americas Inc. 2008. Rights Reserved other trademarks mentioned property their respective owners.
KAD2708C Table Contents
Absolute Maximum Ratings Thermal Information. Electrical Specifications Digital Specifications Timing Diagram Timing Specifications Thermal Impedance. Description Configuration Typical Performance Curves Functional Description Reset Voltage Reference. Analog Input Clock Input Jitter. Digital Outputs
Equivalent Circuits. Layout Considerations Split Ground Power Planes Clock Input Considerations. Bypass Filtering LVCMOS Outputs. Unused Inputs
Definitions. Package Outline Drawing L68.10x10B
FN6812.0 December 2008
KAD2708C
Absolute Maximum Ratings
AVDD2 AVSS. -0.4V 2.1V AVDD3 AVSS. -0.4V 3.7V OVDD2 OVSS -0.4V 2.1V Analog Inputs AVSS. -0.4V AVDD3 0.3V Clock Inputs AVSS. -0.4V AVDD2 0.3V Logic Inputs AVSS (VREFSEL, CLKDIV) -0.4V AVDD3 0.3V Logic Inputs OVSS (RST, 2SC) -0.4V OVDD2 0.3V VREF AVSS -0.4V AVDD3 0.3V Analog Output Currents 10mA Logic Output Currents 10mA CMOS Output Currents 20mA
Thermal Information
Operating Temperature .-40°C +85°C Storage Temperature .-65°C +150°C Junction Temperature +150°C
CAUTION: operate near maximum ratings listed extended periods time. Exposure such conditions adversely impact product reliability result failures covered warranty.
Electrical Specifications specifications apply under following conditions unless otherwise noted: AVDD2 1.8V, AVDD3 3.3V,
OVDD 1.8V, -40°C +85°C (typical specifications +25°C), fSAMPLE 275MSPS, 210MSPS, 170MSPS 105MSPS, Nyquist -0.5dBFS. KAD2708C-27 PARAMETER SPECIFICATIONS Analog Input Full-Scale Analog Input Range Full Scale Range Temp. Drift Common-Mode Output Voltage Power Requirements 1.8V Analog Supply Voltage 3.3V Analog Supply Voltage 1.8V Digital Supply Voltage 1.8V Analog Supply Current 3.3V Analog Supply Current 1.8V Digital Supply Current Power Dissipation SPECIFICATIONS Maximum Conversion Rate Minimum Conversion Rate Differential Nonlinearity Integral Nonlinearity Signal-to-Noise Ratio 10MHz Nyquist 430MHz 46.5 -0.3 -0.8 ±0.2 ±0.2 50.4 49.2 49.0 46.5 -0.3 -0.8 ±0.2 ±0.2 49.5 49.2 49.1 46.5 -0.3 -0.8 ±0.2 ±0.2 49.5 49.2 49.1 46.5 -0.3 -0.8 ±0.2 ±0.2 49.5 49.2 49.1 MSPS MSPS dBFS dBFS dBFS AVDD2 AVDD3 OVDD IAVDD2 IAVDD3
OVDD
KAD2708C-21
KAD2708C-17
KAD2708C-10 UNITS
SYMBOL CONDITIONS
AVTC Full Temp
VP-P ppm/°C
3.15
3.45
3.45 3.15
3.45 3.15
3.45 3.15
FN6812.0 December 2008
KAD2708C
Electrical Specifications specifications apply under following conditions unless otherwise noted: AVDD2 1.8V, AVDD3 3.3V,
OVDD 1.8V, -40°C +85°C (typical specifications +25°C), fSAMPLE 275MSPS, 210MSPS, 170MSPS 105MSPS, Nyquist -0.5dBFS. (Continued) KAD2708C-27 PARAMETER Signal-to-Noise Distortion SYMBOL CONDITIONS SINAD 10MHz Nyquist 430MHz Effective Number Bits ENOB 10MHz Nyquist 430MHz Spurious-Free Dynamic Range SFDR 10MHz Nyquist 430MHz Two-Tone SFDR Word Error Rate Full Power Bandwidth 2TSFDR 133MHz, 135MHz FPBW 46.5 49.2 49.2 48.9 67.6 66.6 66.1 10-12 46.5 KAD2708C-21 49.5 49.2 48.9 69.1 69.1 69.0 10-12 46.5 KAD2708C-17 49.5 49.2 49.0 69.1 69.1 69.0 10-12 46.5 KAD2708C-10 49.5 49.2 48.9 69.1 69.1 68.9 10-12 UNITS dBFS dBFS dBFS Bits Bits Bits
Digital Specifications
PARAMETER INPUTS High Input Voltage (VREFSEL) Input Voltage (VREFSEL) Input Current High (VREFSEL) Input Current (VREFSEL) High Input Voltage (CLKDIV) Input Voltage (CLKDIV) Input Current High (CLKDIV) Input Current (CLKDIV) High Input Voltage (RST,2SC) Input Voltage (RST,2SC) Input Current High (RST,2SC) Input Current (RST,2SC) Input Capacitance CLKP, CLKN Differential Input Voltage CLKP, CLKN Differential Input Resistance CLKP, CLKN Common-Mode Input Voltage LVCMOS OUTPUTS Voltage Output High Voltage Output Output Rise Time Output Fall Time VREFSEL VREFSEL VREFSEL VREFSEL CLKDIV CLKDIV CLKDIV CLKDIV RST,2SC RST,2SC RST,2SC RST,2SC VCDI RCDI VCCI OVDD OVSS AVDD3 AVSS 0.8*OVDD2 0.2*OVDD2 AVDD3 AVSS 0.8*AVDD3 0.2*AVDD3 0.8*AVDD3 0.2*AVDD3 VP-P SYMBOL CONDITIONS UNITS
FN6812.0 December 2008
KAD2708C Timing Diagram
Sample
CLKN CLKP
tPID
CLKOUT
tPCD
D[7:0]
Data invalid
Data N-L+1
Data
FIGURE LVCMOS TIMING DIAGRAM
Timing Specifications
PARAMETER Aperture Delay Aperture Jitter Input Clock Data Propagation Delay Data Hold Time Output Clock Data Propagation Delay Latency (Pipeline Delay) Overvoltage Recovery SYMBOL tPID tPCD tOVR -300 UNITS cycles cycle
Thermal Impedance
PARAMETER Junction Paddle (Note NOTE: Paddle soldered ground plane. SYMBOL UNIT °C/W
Electrostatic charge accumulates humans, tools equipment discharge through metallic package contacts (pins, balls, exposed paddle, etc.) integrated circuit. Industry-standard protection techniques have been utilized design this product. However, reasonable care must taken storage handling sensitive products. Contact Intersil specific sensitivity rating this product.
FN6812.0 December 2008
KAD2708C Description
NUMBER 11-13, 29-36, 64-66 Exposed Paddle AVSS NAME AVDD2 AVSS VREF VREFSEL AVDD3 INP, CLKDIV CLKN, CLKP OVSS OVDD2 CLKOUT 1.8V Analog Supply Analog Supply Return Reference Voltage Out/In Reference Voltage Select (0:Int 1:Ext) Common-Mode Voltage Output 3.3V Analog Supply Analog Input Positive, Negative Connect Clock Divide (Active Low) Clock Input Complement, True Output Supply Return 1.8V CMOS Supply Power Reset (Active Low) LVCMOS (LSB) Output LVCMOS Output LVCMOS Clock Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Output Over-Range Connect OVDD2 Two's Complement Select (Active Low) Analog Supply Return FUNCTION
FN6812.0 December 2008
KAD2708C Configuration
OVDD2 OVDD2 OVDD2 OVDD2 OVSS
AVDD2 AVSS VREF VREFSEL AVDD3 AVSS AVSS AVDD2 AVDD3 AVDD3 CLKDIV
OVSS OVDD2 CLKOUT OVDD2
KAD2708C
View Scale
AVDD2
AVDD2
AVDD3
OVDD2
AVSS
AVSS
AVSS
CLKN
OVSS
CLKP
FIGURE CONFIGURATION
FN6812.0 December 2008
KAD2708C Typical Performance Curves
AVDD2 OVDD2 1.8V, AVDD3 3.3V, +25°C, fSAMPLE 275MSPS, 137MHz, -0.5dBFS unless noted.
(dBc)
SFDR
(dBc) HD3(
MHz)
FIGURE SFDR
FIGURE
(dBc)
HD2, (dBc)
SFDR
Input Amplitude (dBFS)
FIGURE
FIGURE SFDR
SFDR
HD2, HD3(dBc)
SNR(dBFS), SFDR (dBc)
(MSPS)
fSAMPLE (MHz)
FIGURE SFDR fSAMPLE
FIGURE fSAMPLE
FN6812.0 December 2008
KAD2708C Typical Performance Curves
Power Dissipation (PD) (mW) SAMPLE (MSPS)
CODE
AVDD2 OVDD2 1.8V, AVDD3 3.3V, +25°C, fSAMPLE 275MSPS, 137MHz, -0.5dBFS unless noted. (Continued)
-0.5
FIGURE POWER DISSIPATION fSAMPLE
FIGURE DIFFERENTIAL NONLINEARITY OUTPUT CODE
-0.2 -0.5 -0.7
50,000 45,000 40,000 35,000 CODE COUNT 30,000 25,000 20,000 15,000 10,000 5,000
CODE
SBs)
CODE
FIGURE INTEGRAL NONLINEARITY OUTPUT CODE
-0.47dBFS 49.4dBFS SFDR 68.4dBc AMPLITUDE (dB) SINAD 49.3dBFS -86dBc -69dBc AMPLITUDE (dB)
FIGURE NOISE HISTOGRAM
-0.47dBFS 49.4dBFS SFDR 69.2dBc SINAD 49.4dBFS -81dBc -91dBc
-100
-100
-120
FREQUENCY (MHz)
-120
FREQUENCY (MHz)
FIGURE OUTPUT SPECTRUM 9.865MHz
FIGURE OUTPUT SPECTRUM 133.805MHz
FN6812.0 December 2008
KAD2708C Typical Performance Curves
-0.48dBFS 49.3dBFS SFDR 63dBc SINAD 49.1dBFS -63dBc -67dBc AMPLITUDE (dB)
AVDD2 OVDD2 1.8V, AVDD3 3.3V, +25°C, fSAMPLE 275MSPS, 137MHz, -0.5dBFS unless noted. (Continued)
-7.1dBFS 2TSFDR 67dBc IMD3 -74dBF
AMPLITUDE (dB)
-100
-100
-120
FREQUENCY (MHz)
-120
FREQUENCY (MHz)
FIGURE OUTPUT SPECTRUM 299.645MHz
-7dBFS 2TSF 73dBc IMD3 -81dBFS AMPLIT (dB)
FIGURE TWO-TONE SPECTRUM 69MHz, 70MHz
-7dBFS 2TSFDR 63dBc IMD3 -76dBFS AMPLITUDE (dB)
-100
-100
-120
FREQ UENCY (MHz)
-120
FREQUENCY (MHz)
FIGURE TWO-TONE SPECTRUM 140MHz, 141MHz
FIGURE TWO-TONE SPECTRUM 300MHz, 305MHz
tCAL (ms)
SNR(dBFS), SFDR(dBc) AMBIENT TEMPERATURE,
SFDR
SAMPLE (MSPS)
FIGURE SFDR TEMPERATURE
FIGURE CALIBRATION TIME
FN6812.0 December 2008
KAD2708C Functional Description
KAD2708 eight bit, 275MSPS converter pipelined architecture. input voltage captured sample hold circuit converted unit charge. Proprietary charge domain techniques used compare input series reference charges. These comparisons determine digital code each input value. converter pipeline requires sample clocks produce result. Digital error correction also applied, resulting total latency clock cycles. This evident user latency between start conversion data being available digital outputs. start-up, self-calibration performed minimize gain offset errors. reset (RST) initially held internally power-up will remain that state until calibration complete. clock frequency should remain fixed during this time. Calibration accuracy maintained sample rate which performed, therefore should repeated clock frequency changed more than 10%. Recalibration initiated pin, power cycling, time.
Voltage Reference
VREF full-scale reference, which sets full-scale input voltage chip requires bypass capacitor 0.1µF larger. internally generated reference voltage provided from bandgap voltage buffer. This buffer sink source 50µA externally. external voltage applied this provide more accurate reference than internally generated bandgap voltage match full-scale reference among system KAD2708C chips. option latter configuration KAD2708C's internally generated reference external reference voltage other chips system. Additionally, externally provided reference changed from nominal value adjust full-scale input voltage within limited range. select whether full-scale reference internally generated externally provided, digital input port VREFSEL should appropriately, internal high external.This also internal pull-up resistor. internally generated reference, VREFSEL tied directly AVSS, external reference, VREFSEL left unconnected.
Reset
Recalibration initiated time driving minimum clock cycle. open-drain driver recommended. calibration sequence initiated rising edge RST, shown Figure over-range output (OR) high once pulled low, remains that state until calibration complete. output returns normal operation that time, important that analog input within converter's full-scale range order observe transition. input over-range state will stay high will possible detect calibration cycle. While low, output clock (CLKOUT) stops toggling low. Normal operation output clock resumes next input clock edge (CLKP/CLKN) after deasserted. 275MSPS nominal calibration time ~240ms.
CLKN CLKP Calibration Time Calibration Begins Calibration Complete CLKOUT
Analog Input
fully differential input (INP/INN) connects sample hold circuit. ideal full-scale input voltage 1.5VPP, centered voltage 0.86V shown Figure
-0.75V 0.75V 0.86V
FIGURE ANALOG INPUT RANGE
Best performance obtained when analog inputs driven differentially ac-coupled configuration. common-mode output voltage, VCM, should used properly bias each input shown Figures transformer will give best noise distortion performance wideband and/or high intermediate frequency (IF) inputs. recommended biasing shown Figures
FIGURE CALIBRATION TIMING
FN6812.0 December 2008
KAD2708C
Clock Input
0.01µF Analog
ADT1-1WT ADT1-1WT
KAD2708
0.1µF
clock input circuit differential pair (see Figure 29). Driving these inputs with high level 1.8VPP each input) sine square wave will provide lowest jitter performance. recommended drive circuit shown Figure clock driven single-ended, this will reduce edge rate impact performance.
AVDD2 CLKP 200O CLKN
FIGURE TRANSFORMER INPUT, GENERAL APPLICATION
ADTL1-12 Analog Input
ADTL1-12
KAD2708
Clock Input TC4-1W
0.1µF
FIGURE TRANSFORMER INPUT, HIGH APPLICATION
FIGURE RECOMMENDED CLOCK DRIVE
back-to-back transformer scheme used improve common-mode rejection, which keeps common-mode level input matched VCM. value termination resistor should determined based desired impedance. sample hold circuit design uses switched capacitor input stage, which creates current spikes when sampling capacitance reconnected input voltage. This creates disturbance input which must settle before next sampling point. Lower source impedance will result faster settling improved performance. Therefore transformer shunt resistance recommended optimal performance. differential amplifier used applications that require coupling, expense reduced dynamic performance. this configuration amplifier will typically reduce achievable distortion performance. typical differential amplifier configuration shown Figure
348O 69.8O
100O 0.22µF
clock divider optional. KAD2708C's requires clock with duty cycle optimum performance. such clock available, option generate twice desired sampling rate, then KAD2708C's divide-by-2 generate 50%-duty-cycle clock. This frequency divider uses rising edge clock, clock duty cycle assured. Table describes CLKDIV connection.
TABLE CLKDIV SETTINGS CLKDIV AVSS AVDD DIVIDE RATIO
CLKDIV internally pulled low, pull-up resistor logic driver must connected undivided clock.
Jitter
sampled data system, clock jitter directly impacts achievable performance. theoretical relationship between clock jitter maximum shown Equation illustrated Figure
(EQ.
151O
KAD2708
100O 49.9O 69.8O 348O
0.1µF
Where uncertainty sampling instant. This relationship shows that would achieved clock jitter were only non-ideal factor. reality, achievable limited internal factors such differential nonlinearity, aperture jitter thermal noise.
FIGURE DIFFERENTIAL AMPLIFIER INPUT
FN6812.0 December 2008
KAD2708C
tj=0.1 Bits
tj=1 tj=10
tj=1
Bits
internal aperture jitter combines with input clock jitter, root-sum-square fashion since they statistically correlated, this determines total jitter system. total jitter, combined with other noise sources, then determines achievable SNR.
Digital Outputs
Bits
Data output parallel with LVDS-compatible drivers.
equen
output format (Binary Two's Complement) selected shown Table
TABLE SETTINGS AVSS AVDD MODE Two's Complement Binary
FIGURE CLOCK JITTER
Equivalent Circuits
AVDD2
AVDD3 Charge Pipeline
CLKP
AVDD2
AVDD3
Csamp 0.3pF
Clock Generation
Csamp 0.3pF
Charge Pipeline
CLKN
AVDD2
FIGURE ANALOG INPUTS
FIGURE CLOCK INPUTS
OVDD OVDD
DATA
D[9:0]
FIGURE LVCMOS OUTPUT
FN6812.0 December 2008
KAD2708C Layout Considerations
Split Ground Power Planes
Data converters operating high sampling frequencies require extra care board layout. Many complex board designs benefit from isolating analog digital sections. Analog supply ground planes should laid under signal clock inputs. Locate digital planes under outputs logic pins. Grounds should joined under chip. Aperture Jitter variation aperture delay samples. Clock Duty Cycle ratio time clock wave logic high total time clock period. Differential Non-Linearity (DNL) deviation code width from ideal step. Effective Number Bits (ENOB) alternate method specifying Signal Noise-and-Distortion Ratio (SINAD). calculated ENOB (SINAD 1.76)/6.02. Integral Non-Linearity (INL) deviation each individual code from line drawn from negative full-scale (1/2 below first code transition) through positive full-scale (1/2 above last code transition). deviation given code from this line measured from center that code. Least Significant (LSB) that smallest value weight digital word. value terms input voltage VFS/(2N where resolution bits. Missing Codes output codes that skipped will never appear output. These codes cannot reached with input value. Most Significant (MSB) that largest value weight. value terms input voltage VFS/2. Pipeline Delay number clock cycles between initiation conversion appearance output pins corresponding data. Power Supply Rejection Ratio (PSRR) ratio change power supply voltage input voltage necessary negate resultant change output code. Signal Noise-and-Distortion (SINAD) ratio signal amplitude other spectral components below half clock frequency, including harmonics excluding Signal-to-Noise Ratio (SNR) (without Harmonics) ratio signal amplitude other spectral components below one-half sampling frequency, excluding harmonics Spurious-Free-Dynamic Range (SFDR) ratio signal amplitude value peak spurious spectral component. peak spurious spectral component harmonic. Two-Tone SFDR ratio value either input tone value peak spurious component. peak spurious component product.
Clock Input Considerations
matched transmission lines inputs analog input clock signals. Locate transformers, drivers terminations close chip possible.
Bypass Filtering
Bulk capacitors should have equivalent series resistance. Tantalum good choice. best performance, keep ceramic bypass capacitors very close device pins. Longer traces will increase inductance, resulting diminished dynamic performance accuracy. Make sure that connections ground direct impedance.
LVCMOS Outputs
Output traces connections must designed characteristic impedance. Avoid crossing ground power-plane breaks with signal traces.
Unused Inputs
inputs internally pulled left open-circuit used. CLKDIV internally pulled low, which divides input clock two. VREFSEL internally pulled must held internal reference, left open external reference.
Definitions
Analog Input Bandwidth analog input frequency which spectral output power fundamental frequency determined analysis) reduced from full-scale low-frequency value. This also referred Full Power Bandwidth. Aperture Delay Sampling Delay time required after rise clock input sampling switch open, which time signal held conversion.
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
FN6812.0 December 2008
KAD2708C
Package Outline Drawing
L68.10x10B
LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE 11/08
INDEX AREA 10.00
8.00
INDEX AREA 0.50
10.00
Exp. 7.70
0.15 (4X)
VIEW
0.55
BOTTOM VIEW
0.25
0.10
0.90 8.00
DETAIL 0.10
0.50
SIDE VIEW
0.08 SEATING PLANE
0.25 9.65
7.70
MIN. MAX. 0.75
DETAIL
TYPICAL RECOMMENDED LAND PATTERN
NOTES: Dimensions millimeters. Dimensions Reference Only.
Dimensioning tolerancing conform AMSEY14.5m-1994. Unless otherwise specified, tolerance Decimal 0.05 Dimension applies metallized terminal measured between 0.15mm 0.30mm from terminal tip. Tiebar shown present) non-functional feature. configuration identifier optional, must located within zone indicated. identifier either mold mark feature.
FN6812.0 December 2008

Data Sheet December 2008 FN6812.0 8-Bit, 275/210/170/105MSPS Conv

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