Input References Hitless Switch Over CMOS output 77.76 Output Fast Acq
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Stratum Timing Module STL-S3
Input References Hitless Switch Over CMOS output 77.76 Output Fast Acquisition Mode Manual/ Autonomous Operation Master/Slave Configuration Revertive/Nonrevertive Modes
Application
Connor-Winfield Stratum Simplified Control Timing Module acts complete system clock module Stratum timing applications accordance with GR-1244CORE, Issue GR-253-CORE, Issue ITU-T G.812, Option Connor-Winfield's Stratum Timing module helps reduce cost your design minimizing your development time maximizing your control system clock with simplified design.
Bulletin Page Revision Date Issued
TM055 MBATTS
General
Connor-Winfield's timing module provides Stratum synchronization complete system clock solution single module accordance with GR-1244-CORE Issue GR253-CORE Issue ITU-T G.812 Option III. provides reliable network element clock reference line cards used TDM, PDH, SONET, application environments. Typical applications include digital cross connects, DSLAMs, ADMs, multiservice platforms, switches routers. meets 0.37 Hold Over requirements over 70°C temperature range. 3.3V power requirement will draw maximum during initial start-up period then drop typical current 0.5A during normal operating conditions. accepts input references supply CMOS outputs (see Tables specific information).
Diagram
Figure
View
Hold Over Ref. Indicator Ref. Indicator Ref. Indicator Ref. Indicator Ref. Indicator Free Indicator Ref. Indicator Reset Alarm Output CNTRL CNTRL CNTRL Enable Lock Ext. Ref. Ext. Ref. Ext. Ref. Ext. Ref. Ext. Ref. Ext. Ref. Slave Input Output SPI_IN SPI_CLK Output SPI_OUT
Functional Block Diagram
Figure
Reference Indicators
Reset SPI_ENBL
Reference Reference Reference Reference Reference Reference
Port
SPI_CLK SPI_IN SPI_OUT CNTRL External Detect CNTRL CNTRL External
Status Indicators
Control Refence Primary Qualification Loop Loop
Alarm Lock Hold Over Free
External
External
Frequency Control
Output
External
OCXO
Output
External
Output
Slave Input
Table
Symbol Parameter Power Supply Voltage Input Voltage Storage Temperature
Absolute Maximum Rating
Minimum -0.5 -0.5 Nominal Maximum Units Volts Volts deg. Notes
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Table
Symbol tPULSE tRST tHLD Parameter Power Supply Voltage High level input voltage CMOS level input voltage CMOS
Recommended Operating Conditions
Minimum 3.135 Nominal Maximum 3.465 5.25 Units Volts Volts Volts sec. Notes
Minimum pulse width, positve/negative external references Input signal transistion time Time module re-configure after reset (manual POR) Time hold reset high
Table
Symbol Parameter High level output voltage, -4.0mA, min. level output voltage, 8.0mA, max.
Characteristics
Minimum Nominal Maximum Units Volts Volts Notes
Table
Parameter Frequency Range Output Output Output Supply Current Timing Reference Inputs Slave Input Jitter, Wander Phase Transient Tolerances Wander Generation Wander Transfer Jitter Generation Jitter Transfer Phase Transients Output Free Accuracy Hold Over Stability Inital Offset Temperature Drift Maximum Hold Over History Minimum Time Hold Over Lock Time Lock Accuracy Environmental Characteristics Shock Vibration
Specifications
Specifications 77.76 77.76 77.76 0.5A typical @25°C, during warm-up (Maximum) 77.76 GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6 GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2 GR-1244-CORE GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3 GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1 GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3 ±4.6 over temperature range ±0.370 ±0.050 ±0.280 ±0.040 1049 seconds seconds after reference rearrangement sec. Notes
100G's, 6mS, halfsine MIL-STD-202F, Method 2138, Test Condition 0.06" D.A. peak MIL-STD-202F, Method 204D, Test Condition
4.0: 5.0: 6.0: Hold Over stability cumulative fractional frequency offset described GR-1244-CORE, After seconds stable temperature (±5° Frequencies must specified time order.
NOTES: 1.0: Stresses beyond those listed under Absolute Maximum Rating cause damage device. Operation beyond Recommended Conditons implied. 2.0: 3.0: Inputs 3.3V CMOS,5V tolerant Logic 3.3V CMOS
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Description
Table
Connection
Hold Over Reference Reference Reference Reference Reference Free Reference Reset Alarm Output CNTRL CNTRL CNTRL Enable Lock SPI_OUT Output SPI_SCLK SPI_IN Output Slave Input External Reference External Reference External Reference External Reference External Reference External Reference
Description
Indicator when module Hold Over Indicator when module locking locked external reference Indicator when module locking locked external reference Indicator when module locking locked external reference Indicator when module locking locked external reference Indicator when module locking locked external reference Indicator when module Free Indicator when module locking locked external reference Ground Reset Indicator when module alarm condition output derived from system clock Mode control input manual operation. Mode control input manual operation. Mode control input manual operation. Enable communication Indicator when module locked selected reference. Ground Serial data output communication System clock output Input clock communication. Ground Serial data input communication output derived from system clock Input synchronizing module slave configuration. Ground External reference input External reference input External reference input Ground External reference input External reference input External reference input +3.3Vcc power supply required
Internal pull-up Internal pull-down Internal pull-up/pull-down resistors range from pull-down resistor
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Functional Truth Table
Table
Reference# Alarm Lock Hold Over Free Condition Locking selected reference phase error 20µs Tracking selected reference phase error 20µs Auto Mode There valid references module entered Hold Over. Manual Mode Module Hold Over mode. Auto Mode There valid references there valid Hold Over history module entered Free Run. Manual Mode Module Free mode. Slave Mode Module locked master module phase error 20µs Slave Mode Module locked master module phase error 20µs Slave Mode Module unable track master module Loss Reference condition frequency range.
Control Inputs
Table
CNTRL3/CF3 CNTRL2/CF2 CNTRL1/CF1 Mode Operation Free Locked Locked Hold Over Locked Locked Locked Locked
Module Restabilization Times
Table given off-time, time required meet daily aging, short term stability TDEV requirements:
Time Hour Hour Hour Days Days Restabilization Time Hours Hours Hours Hours Time Days
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Operation Overview
offers both manual autonomous modes operation, option revertive non-revertive reference switching during autonomous mode. manual mode, user control module using pins CNTRL determine whether module should lock specific reference, enter Free enter Hold Over. autonomous mode, module determines proper operating behavior depending state external references, which frequency qualified module. further details autonomous operation, state diagram Figure also offers master slave modes incorporates reference qualification external references Slave Input. When module locked valid reference, appropriate external indicator will asserted that reference. When internal phase error less than 20µs, Lock signal will asserted. takes seconds obtain complete phase lock qualified reference. assure that will always lock valid frequency offset within seconds, module goes into Fast Acquisition mode immediately after switching reference. module experiences Lock alarm after phase-locked selected reference, module will re-enter Fast Acquisition stage filtering reference been disqualified. Once locked, filtering will return filter. filtering during Fast Acquisition mode will allow frequency movement faster than second frequency step 9.2ppm. Fast Acquisition mode further described fast start mode GR-1244-CORE, Issue section 3.6. current status accessed port register 0Eh. manual reset called Reset provided device. This will reset DSP, FPGA, causing disruption programmable devices same type reset, though software controlled, described Table device will treat this reset were following power-up; registers reset their default values. Resetting unit cycling power requires more time restablization internal ovenized oscillator recommended. Hold Over mode provides stable frequency that guaranteed within ±0.370ppm over entire temperature range first hours after entry into Hold Over. module establishes Hold Over history within seconds after reference selected continues running average every seconds next 1049 seconds. Long-term Hold Over values based 1049 second moving window average. Hold Over values updated when reference disqualified during Fast Acquisition mode. Hold Over values buffered least seconds allow enough time respond alarms frequency qualification status. Free mode operation which module locked reference output frequency solely dependent initial frequency setting internal oscillator. output frequency Free guaranteed ±4.6ppm nominal frequency. Reference qualification continually monitors input references, well Slave Input. references monitored both frequency accuracy presence. Although loss presence detected almost immediately being continually monitored, delay approximately seconds occur before out-of-band frequency detected. This delay caused fact that reference qualification done reference time, round robin fashion. Each reference takes just over second qualify, cycle time cause delay. module provides three output frequencies. Output primary synchronized output. phase locked input reference during normal operation fixed frequency when operating Hold Over Free Run. Output Output derived from Output module provides variety alarm status information alert user multiple conditions that affect overall performance their system. Some this information brought external pins, while other information accessible through port internal memory-mapped registers. Status information from reference qualification, including frequency offsets, contained these registers; information regarding phase build valid Hold Over also stored here. Additionally, current mode operation status available. Certain features programmable user. complete details memory-mapped registers, please Timing Operation section. timing, Figures 7-8. master mode, module will experience alarm condition (Alarm=1) when module Hold Over Free Run. manual mode, alarm condition will occur user selects Hold Over, Free reference that disqualified. reference disqualified after module starts track module will enter holdover valid holdover history available, unit will enter Free (see figure 19). autonomous mode, module will experience alarm condition when there available references. This caused references being disqualified off-frequency condition references unavailable priority table. these cases, module will enter holdover there valid holdover history available, module will enter Free Run. slave mode, module will experience alarm condition module able lock master because master frequency exceeded pull-in range slave, master. Lock indicator will de-asserted (Lock=1) when internal phase error greater than 20us from final, locked value (See figure 20). This alarm occur when unit initially locking reference, occur after lock module loses lock. This alarm will de-asserted (Lock=1) during holdover freerun modes.
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Phase build operation inter nally enabled disabled through internal memory-mapped registers. initially disabled. Internal circuitry monitors input reference greater than 3.4µs change over second interval. When this occurs, internal buffers reset that phase change ignored, allowing phase shift between input output. phase shift smaller than 3.4µs over seconds will followed re-establish original input/output phase relationship, unless rate change causes reference disqualified. Refer Reference Qualification section (pg. more details disqualification. meets requirements wander generation wander transfer required GR-1244, sections 5.4. also complies with phase transient requirements during Reference Rearrangement, Entry into Hold Over, transient. Input jitter attenuated about dB/decade minimize jitter noise passed other network elements clocks. Figure illustrates STL's typical roll attenuated jitter.
Autonomous Mode
During autonomous mode, unit makes decision about which reference track based priority qualification status. goal module lock onto highest priority qualified reference. revertive option selected, module will switch current reference, even when that reference still qualified, soon higher priority qualified reference becomes available. module will also switch into highest priority qualified reference when current reference disqualified. non-revertive option selected, module will only switch into another reference when current reference disqualified. current reference disqualified, there other qualified references switch module will enter last valid Hold Over value. soon reference qualified, module will begin track Hold Over value been calculated, then unit will revert into Free until reference available. multiple references same priority priority table, module will select lowest reference number highest priority. example, Reference Reference both priority module will consider Reference higher priority than Reference (assuming both qualified references).
Autonomous Mode State Diagram Figure
Fast Acquisition
eference isqualified anothe eference valid
reference Vali Fast Acquisit vailab phase-locn able
Valid refe
availa
Lock
lifie isqu
eren lifie
Hold Over
Free
sets Hold Over
*Note: During autonomous, revertive operation, valid reference higher priority available, module will switch from reference that still qualified.
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Manual Mode
During manual operation, mode operation determined user through either external control pins CNTRL3:1 internal configuration bits CF3:1 (see Table default configuration have external control, this changed internal control setting memory-mapped registers port. During manual operation, user select Free Run, Hold Over, locked operation. input references selected unit track. module locked reference that reference becomes disqualified, module will automatically into Hold Over. module been phase-locked current reference least seconds final stage filter indicated register 0Eh), Hold Over value will derived from data from current reference. module been phase-locked current reference less than seconds, then last valid Hold Over value will used. control bits/pins remain same selection that caused unit into Hold Over, unit will remain Hold Over until reference re-qualified. that time, after minimum soak time, unit will attempt relock same reference. external user control pins select reference that module qualified, module will switch into last valid Hold Over value. module established valid Hold Over, module will return pre-programmed Free value. soon module qualifies selected reference, will begin locking process. time during manual mode will unit attempt lock reference that selected external pins/internal bits. only mode that unit will enter automatically into Hold Over Free Run, that disqualification selected reference.
Manual Mode State Diagram Figure
Fast Acquisition
ref. been acqu ired selected Lock
cted ref. chang Sele cted ref. Sele
ects
reference fied uali
Free
User
selects Hold Over User
Lock
efer
Hold Over
Free
Free resets
elects Hold Over
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Master/Slave Operation
During master operation, master pays attention Slave Input reference other than monitoring qualification purposes. slave unit removed, there behavioral change master. During slave operation, slave module locks Slave Input reference from master, continually qualifies slave module determines that master input gone range, slave continues lock master until reaches pull-in/hold-in range, which approximately ±125 ppm. slave determines that Slave Input frequency from master been removed, slave will internal priority table (which should configured same master module) configuration registers begin locking highest priority qualified reference selected input reference master unit manual mode). soon Slave Input from master returns, (after sec. minimum soak time) slave will begin locking When module slave mode, external indicator pins (Reference 1-Reference Free Run, Hold Over) will remain low, regardless mode. module locked attempting lock master, alarm indicator will low. LOCK alarm works normally long module tracking master. master lost (due tracking range), module enters another mode, alarm LOCK indicators will both remain high (=1). internal status register (0Eh) must read determine current mode operation module. goal slave maintain zero-phase error with Slave Input from master. order accomplish this, during slave mode increased that slave respond very quickly change master's frequency minimize phase difference between master slave.
Master/Slave State Diagram Figure
Master Mode Slave mode selected
Master mode selected Slave Mode
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Reference Qualification
Reference qualification requires that reference both present within required frequency limits minimum seconds. time reference disqualified loss signal frequency offset, second window will start over. active reference also disqualified there phase-time movement input that greater than allowable movement jitter tolerance frequency hold-in range. active reference disqualified faster than allowed phase-time change (phase hit), module will immediately into Hold Over Free Hold Over valid) minimum 2ms, after which module will though reference disqualified off-frequency condition.
Reference Frequency Qualification Test
Figure
Reference qualified
Reference qualified
(3ppm minimum)
Reference qualified Reference qualified
(3ppm minimum)
Reference qualified
Frequency Rejection Limit
Frequency Qualification Limit
Nominal
Frequency Qualification Limit
Frequency Rejection Limit
Timing Operation
port communication. address bytes bits length, reads return bits writes require bits. each address byte read/write bit. lower bits lowest bits specified address. example, read from address would require byte 1000 0001b sent module, first.
Table
Bit0
Format Address Byte R/W: Read=1/Write=0 Address Information Send First
Table
Format Data Byte Data Information Receive/Send First
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Timing Diagrams
Figure
Write Cycle
tclk SPI_SCLK SPI_IN tpause-w
SPI_OUT
Enable Figure tclk SPI_SCLK
Read Cycle
tpause-r
SPI_IN
SPI_OUT
Enable
*See tables specific information.
Parameter tCLK tpause-w tpause-r Description rising edge rising edge Setup time, Valid data rising edge Hold time, Valid data following rising edge Minimum time between address data byte, Write only Minimum time between address data byte, Read only Setup time, Enable first rising edge Hold time, Enable following last rising edge Pulse width, (tCLK (tCLK (tCLK
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Memory Mapped Registers
internal memory-mapped registers accessible through port module. Some registers read-only, while others accessible read write operation. registers contain status information, alarm information, configuration tables, registers. access registers, please read write timing diagrams Figures 7-8.
Table Register
Addrs Description Priority Selection Table Reserved
Reference Measurement
Slave Reference Measurement Reserved Qualification Status References Slave Input Phase-Locked Loop Status Reserved Reference Qualification Limits Configuration Reserved Bandwidth Selection Status Identification Reserved
Table Priority Selection Table Read/Write
Addrs Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description Priority register References Priority register References Priority register References
P13,P12,P11,P10 Priority Reference 1(Default 0110) P23,P22,P21,P20 Priority Reference 2(Default 0101) P33,P32,P31,P30 Priority Reference 3(Default 0100) P43,P42,P41,P40 Priority Reference 4(Default 0011) P53,P52,P51,P50 Priority Reference 5(Default 0010) P63,P62,P61,P60 Priority Reference 6(Default 0001)
Priority Selection Table registers contain default information priority references, these registers overwritten user. lowest priority 0000 highest priority 0110. reference given priority 0000, then that reference will evaluated frequency presence, will considered unavailable reference autonomous mode.
Preliminary Data Sheet TM055
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multiple references assigned same priority, module autonomous, revertive mode, module will select lowest reference number highest priority. priorities with binary number greater than 0110 will treated though their priority 0110. 4-bit binary combinations will considered invalid.
Table Reference Measurement Qualification Status Read only
Addrs Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description Reference Frequency offset from Free Reference Frequency offset from Free Reference Frequency offset from Free Reference Frequency offset from Free Reference Frequency offset from Free Reference Frequency offset from Free Slave Input frequency offset from Free Status indicators References
Status indicators References Fx7,Fx6,Fx5,Fx4,Fx3,Fx2,Fx1,Fx0 Frequency offset Reference (Default 1111 1111) R#1,R#0 Describes status Reference Table (Default Reserved future (Default Reference Measurement Qualification Status registers hold information regarding specified reference's frequency offset from nominal (accurate within actual frequency) status information regarding presence qualification status. Frequency Offset registers have resolution ppm, complement form. maximum frequency offset +63.5 shown these registers. reference determined have frequency offset past these limits, register will only show maximum. Status Indicator registers show qualification status each reference.
Table Phase-Locked Loop Status Read only
Addrs Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description Reference used Status when Holdover history available (Default R2,R1,R0 Describes reference use, Table (Default 000) S3,S2,S1,S0 Describes state PLL, Table (Default 1001)
HA=1 when holdover history current reference available. will remain high when switched directly from current reference into holdover mode. Changing references, switching into free run, setting register will clear bit. However, valid holdover history will remain module's memory until either overwritten history from reference, until cleared HOR. When module detects second phase-time change 0.1s, unable determine whether this actual phase higher) frequency step. phase build triggered higher) frequency step, module will into continuous phase build out. phase frequency varies with phase internal reference from degrees degrees then back phase build status register (0Eh) will blink. frequency this blinking will depend actual size frequency step prevent module from going into continuous phase build state, attempt greater) frequency step unless phase build disabled.
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Table Reference Qualification Limits Read/Write
Addrs Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description Frequency rejection limit
Frequency qualification limit RJ7,RJ6,RJ5,RJ4,RJ3,RJ2,RJ1,RJ0 Limit beyond which references always rejected (Default 0001 1111 (+/-15.5 ppm)) FQ7,FQ6,FQ5,FQ4,FQ3,FQ2,FQ1,FQ0 Limit below which references always qualified (Default 0001 1001 (+/-12.5 ppm)) Reference Qualification Limits registers hold information used determine always reject always qualify regions references. proper module operation, minimum space between these numbers should ppm. each these registers ppm, ppm, number 127.5 ppm. format complement, positive numbers. Note that qualification rejection ranges symmetrical that +15.5 register gives frequency rejection limit 15.5 ppm. Figure further details.
Table Configuration Read/Write
Addrs Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description Mode configuration register
Feature configuration register When selects internal user configuration data over exter CNFG pins. (Default When module slave mode. (Default CF3,CF2,CF1 Internal configuration pins, Table (Default 000) When Phase Build disabled. (Default When will choose priority reference based frequency offset rather than priority table. (Default Will internally reset module when (Default Will reset Hold Over history when Holdover history defaults Free value when reset. (Default Selects revertive reference switching when Revertive switching only occurs while autonomous mode. (Default Select autonomous mode. When enables autonomous selection modes. (Default Reserved future use. (Default Configuration registers read/write registers that hold configuration options device. high, external pins CNTRL3:1 ignored, full user control maintained through these registers. Bits CF3:1 mimic pins CNTRL3:1 operation, mode configuration register controls whether unit acts master slave module. complete master/slave operation, Figure feature configuration register turns optional features device such phase build out, revertive switching, autonomous operation. Bits also provided judge priority references (applicable during autonomous mode only) based their frequency offset (see registers 04h-09h) priority table (see registers 00h-02h). module also allows reset Hold Over history (HOR), well complete module reset (RST). used initiate complete software reset. proper procedure reset device write then wait device re-boot. This will reset DSP, well FPGA DDS. complete reset, output frequencies will temporarily disrupted while programmable chips reinitialize then Free value will reestablished. previous histories will cleared. registers will initialize though following power-up. Please note that there will increase current device reinitializes, current increase will stay below stated datasheet maximum. optimal performance during master/slave operation, slave unit should configured same master unit. This will allow proper selection input reference slave module event signal from master module lost.
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Table Bandwidth Selection Read/Write
Addrs Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description Primary Bandwidth selection Slave mode Bandwidth selection
FB3,FB2,FB1,FB0 Selected bandwidth. Table (Default 0011) SF3,SF2,SF1,SF0 Slave bandwidth. (Default 0101, Reserved future use. (Default
bandwidth changed time during operation, even when device locked. However, module experience phase filters change bandwidth recommended only change bandwidth upon initialization, when Free Hold Over modes. bandwidth changed undefined selection, change operation will occur. initial bandwidth will remain effect until valid bandwidth selected. Slave mode bandwidth selection will take effect only when unit configured slave mode. Slave Input reference lost (LOR), unit uses configuration data determine which reference lock this bandwidth remains same. purpose slave mode operation lock master; master lost, then next best reference used.
Table Status Read only
Addrs Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description Error status ER7,ER6,ER5,ER4,ER3,ER2,ER1 Error Status. Table (Default 0000 0000) Status register holds state last communication. overrun error occurs when many bytes information have been sent quickly module able process address information before clock started data byte. Both reads writes invalid this error follows their communication sequence. address error shows this register, then address that sent module invalid. read write will occur this case. invalid address sent module, module will still expect Enable line active line pulsed times before next read/write cycle. communication cycles expected bytes wide, whether there error not. invalid data error displayed Status register, means that either write attempted read-only address, invalid data word written address. either case, data will written into memory.
Table Identification Read only
Addrs Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description Customer Identification Software Model/Version Identification Hardware Model/Version Identification
CI7, CI6, CI5, CI4, CI3, CI2, CI1, SI7, SI6, SI5, SI4, SI3, SI2, SI1, HI7, HI6, HI5, HI4, HI3, HI2, HI1,
Customer Identification Software Model/Version Identification Hardware Model/Version Identification
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Table Reference Status Table
Description Reference present. Reference present frequency disqualified. Reference qualified unavailable.*
Reference present frequency qualified. Reference unavailable autonomous mode when priority register =0000 that reference (register 13h)
Table Active Reference Table
Description reference. Module Free Hold Over Tracking reference Tracking reference Tracking reference Tracking reference Tracking reference Tracking reference Module locked Slave input. (Valid only Slave mode)
Table Primary State
Description Loss Lock Acquisition Filter Future Future Future Future Final Filter Phase Build-Out Hold Over Free
Table Bandwidth Selecton
Description compatible)
Table Status
Status overrun error address error invalid data
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Wander Generation TDEV
Figure
GR-1244-CORE, Fig. 5-4, GR-253-CORE, 5-8, Wander Generation TDEV Wander Generation TDEV
TDEV (ns) 1000 10000 Integration Time (sec)
Wander Generation MTIE
Figure
1000
GR-1244-CORE, 5-5, Wander Generation-MTIE GR-253-CORE, 5-17, MTIE SONET clock Wander Generation MTIE
MTIE (ns) 1000 10000 Observation Time (sec)
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Wander Transfer TDEV
Figure
10000
GR-1244-CORE, 5-6, Stratum Wander Transfer Stratum Calibrated Wander Transfer TDEV
1000
TDEV (ns) 0.01
1000
Integration Time (sec)
MTIE During Reference Rearrangement
Figure
10000
GR-1244-CORE, Fig. 5-7, Stratum 3/4E, Phase Transient during rearrangement GR-253-CORE, 5-19, MTIE Phase Transients from SONET Clocks, Objective GR-1244-CORE, Fig. 5-7,Stratum 2/3E, Phase Transient during Rearrangment Stratum Reference Switch MTIE
1000
MTIE (ns)
0.001
0.01
Observation Time (sec)
1000
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Entry into Hold Over MTIE
Figure
1000
GR-1244-CORE, 5-8, Phase Transient Entry into Hold Over MTIE
MTIE (ns) 0.01
1000
Observation Time (sec)
Phase Transient MTIE
Figure
10000
GR-1244-CORE, 5-9, MTIE mask Phase Transient GR-253-CORE, 5-19, MTIE Phase Transients from SONET Clocks, Requirement Phase Transient MTIE
1000
MTIE (ns)
0.001
0.01
Observation Time (sec)
1000
10000
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Jitter Attenuation
Figure
Jitter attenuation (-dB)
Slave Mode
Master Mode
0.001
0.01
*See Table Table Bandwidth selections
INPUT Jitter frequency (Hz)
Hold Over Stability over Temperature
Figure
Temperature (°C)
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Typical Current Consumption Over Temperature
Figure 0.700
0.600
0.500
Currnet (Amps)
0.400
0.300
0.200
0.100
0.000 0.00
10.00
20.00
30.00
40.00
50.00
60.00
70.00
Temperature (°C)
Typical Phase Build MTIE
Figure
100.0E-9
(Disabled default Stratum compliance)
10.0E-9
MTIE (ns) 1.0E-9 100.0E-12 1.0E-3
10.0E-3
100.0E-3 1.0E+0 Observation Window (Tau)
10.0E+0
100.0E+0
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Mode Alarm Timing Diagram
Figure
State Change Control Input Pins
(CNTRL1-3)
Operational Mode Indicators
(Ref1-Ref6, Hold Over Free Run)
Alarm Indicator
(See Operation Overview details Alarm Operation)
LOCK Timing Diagram
Figure
Internal 8kHz
(Derived from Sync_Out)
External 8kHz
(Derived from Active Reference)
Internal Phase Error Signal
tdelay Lock Indicator
tdelay
tdelay
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Package Dimensions
Figure
.110 [2.80mm]
1.820 [46.23mm] SQUARE MAX.
1.600 [40.64mm]
.160 ±0.008 [4.06mm]
.700 [17.78] MAX.
.075 [1.90] MIN. .110 [2.81mm] .020 [.51mm]
.100 [2.54mm]
*Please consult factory alternate connector lengths.
Footprint Keepout Dimensions
Figure
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Revision
Revision Date 05/17/04
Notes Preliminary informational release
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