STC5230 single chip solution timing source SDH, SONET, Synchronous Eth

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STC5230 single chip solution timing source SDH, SONET, Synchronous Eth

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Synchronous Clock SETS Data Sheet Description
STC5230 single chip solution timing source SDH, SONET, Synchronous Ethernet network elements. device fully compliant with ITU-T G.813, Telcordia GR1244, GR253. STC5230 accepts reference inputs generates independent synchronized output clocks. Reference input frequencies automatically detected, inputs individually monitored quality. Active reference selection manual automatic. reference switches hitless. Synchronized outputs programmed wide variety SONET well Synchronous Ethernet frequencies. independent timing generators, provide essential functions Synchronous Equipment Timing Source (SETS). Each timing generator includes DPLL (Digital Phase-Locked Loop), which operate Freerun, Synchronized, Holdover modes. Both timing generators support master/slave operation redundant applications. proprietary SyncLinkcross-couple data link provides master/slave phase information state data ensure seamless side switches. standard serial interface provide access STC5230's comprehensive, simple internal control status registers. device operates with external OCXO TCXO MCLK MHz. STC5230 capable field upgrade with optional external EEPROM interface.
STC5230
Functional Specification
SETS, SONET Stratum SMC, Synchronous Ethernet timing generators, SETS Complies with ITU-T G.813, Telcordia GR1244 GR253 Supports Master/Slave redundant application with SyncLinkcross-couple data links Accepts individual clock reference inputs Reference clock inputs automatically frequency detected; each monitored quality Support manual automatic reference selection have independent reference lists priority tables automatic reference selection Output synchronized clocks Could compensate phase delay crosscouple links, 0.1ns steps 409.5ns Capable trace round-trip phase delay master/slave cross-couple links. Hit-less reference master/slave switching Phase rebuild re-lock reference switches Programmable loop bandwidth each DPLL timing generator, from 90mHz 107Hz Supports interface Field upgrade capability IEEE 1149.1 JTAG boundary scan Available TQFP100 package
T0_MASTER_SLAVE T0_XSYNC_IN Phase Detector Digital Filter LVPECL 155.52/125 Active Selector Reference
1.544 2.048 19.44 38.88 77.76 6.48 8.192 16.384
Clock Synthesizer
1.544/3.088/6.176/12.352/24.704 2.048/4.096/8.192/16.384/32.768 44.736 MHz/34.368 LVPECL 155.52/125 (2nd)
Activity Frequency Offset Monitor Active Selector
STC5230
T0_XSYNC_OUT
Phase Detector
Digital Filter
Clock Synthesizer
1.544 MHz/2.048 T4_Xsync_Out
T4_XSYNC_In T4_Master_Slave OCXO TCXO
20MHz
Serial Interface
Control Status Registers
IEEE 1194.1 JTAG
Figure Functional Block Diagram
Preliminary
Data Sheet TM102
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Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet Table Contents
STC5230 Diagram (Top View) STC5230 Description Absolute Maximum Ratings Operating Conditions Electrical Characteristics General Description Detailed Description Chip Master Clock Input Operating Mode General Description Operating Mode Details Freerun/Master Mode Holdover/Master Mode Synchronized/Master Mode Slave Mode Operating Mode Transition Details History Accumulation Details Phase-Locked Loop Status Details Reference Input Monitoring Qualification Active Reference Selection Manual Reference Selection Mode Automatic Reference Selection Mode Output Clocks Master/Slave Configuration Master/Slave Operation Event Interrupts Field Upgrade Feature Load mode configuration pins Load Process EEPROM Load Process EEPROM: Read Write Processor Interface Descriptions Serial Timing Register Descriptions Operation General Register Operation Multibyte register reads Multibyte register writes Clearing bits Interrupt Status Register Noise Transfer Functions Application Notes General Power Ground Mechanical Specifications Ordering Information Revision History
STC5230
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
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Synchronous Clock SETS Data Sheet Table Figures
Figure Functional Block Diagram Figure Operating mode transition automatic reference selection (Master mode). Figure Activity Monitor Figure Reference Qualification Scheme. Figure Output Clocks. Figure clock output Phase Alignment. Figure Master/Slave Pair Figure CLK0-6,8 Phase Alignment Master/Slave skew Control Figure CLK7 Master/Slave Skew Control. Figure EEPROM Configuration Figure Serial Timing, Read access Figure Serial Timing, Write access. Figure Noise Transfer Functions Figure Powers Grounds
STC5230
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet STC5230 Diagram (Top View)
STC5230
Vdd33 CLK0_N CLK0_P Vdd18 CLK1 CLK2 Vdd33 CLK3 CLK4 AVdd18
Vdd33 TRST Vdd18
AVss MCLK
AVdd18 Ref1 Ref2 Ref3 Vdd33 Ref4 Vdd18 Ref5 Test_Pin Ref6 Ref7 Ref8 Ref9 Vdd18 Ref10 Ref11 Vdd33 Ref12 T0_MS T0_XSYNC_IN
Connor-Winfield STC5230
AVss CLK5 CLK6 T0_XSYNC_OUT Vdd33 CLK7 T4_XSYNC_OUT Vdd18 CLK8_N CLK8_P Vdd33 Vdd18 Vdd33 Vdd18 SPI_SDO
T4_XSYNC_IN Vdd18 T4_MS
RESET Vdd33 EVENT_INTR EEP_CS EEP_SCK EEP_SI EEP_SO Vdd18 Vdd33 SPI_CS SPI_SCK Vdd18 Test_Pin
Page Rev:
Note: Pins labeled "Test Pin" must grounded.
Preliminary
Data Sheet TM102
SPI_SDI
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet STC5230 Description
LVCMOS, except CLK0 CLK8, which LVPECL.
STC5230
Table Description
Name Vdd33 6,22,31, 44,59,61, 69,80, 87,97 9,18,27, 38,47,53, 60,65,84, 3,13,15, 20,29,35, 41,56,64, 67,71,78, 82,88,95 3.3V power input Description
Vdd18
1.8V power input
Digital ground
AVdd18 AVss TRST RESET MCLK SPI_CS SPI_SCK SPI_SDI SPI_SDO EEP_SO EEP_SI EEP_SCK EEP_CS EVENT_INTR REF1 REF2 REF3 REF4 REF5 REF6
1.8V analog power input Analog ground JTAG boundary scan reset, active JTAG boundary scan clock JTAG boundary scan mode selection JTAG boundary scan data input JTAG boundary scan data output Active reset chip Master clock input, chip select (CS) clock input (SCLK) data input (SDI) data output (SDO) Optional external EEPROM Optional external EEPROM Optional external EEPROM Optional external EEPROM event interrupt Reference input Reference input Reference input Reference input Reference input Reference input Page Rev: Date: August 2007
Preliminary
Data Sheet TM102
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
Table Description
Name REF7 REF8 REF9 REF10 REF11 REF12 T0_M/S T4_M/S T0_XSYNC_IN T0_XSYNC_OUT T4_XSYNC_IN T4_XSYNC_OUT CLK0_P CLK0_N CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8_P CLK8_N 39,40,42, 43,48,52, 54,55,57, 73,98 11,49
STC5230
Description Reference input Reference input Reference input Reference input Reference input Reference input Select master slave mode Master, Slave Select master slave mode Master, Slave Cross-couple SyncLinkdata link input master/slave redundant applications Cross-couple SyncLinkdata link output master/slave redundant applications 8kHz cross-couple link input master/slave redundant applications 8kHz cross-couple link output master/slave redundant applications 155.52/125 LVPECL output (T0) 155.52/125 LVPECL output (T0) (T0) (T0) frame pulse duty cycle clock (T0) frame pulse duty cycle clock (T0) 44.736/34.368 (T0) (T0) 1.544/2.048 (T4) 155.52/125 LVPECL output (T0) 155.52/125 LVPECL output (T0) Hardware firmware configuration data load mode Hardware firmware configuration data load mode connection. Pins recommented tied ground
Test_Pin
connection. Pins left open, floating, tied grounded Test pins, must grounded normal operation
Note CLK0 CLK8, which LVPECL
Preliminary
Data Sheet TM102
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Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet Absolute Maximum Ratings
Table Absolute Maximum Ratings
Symbol Vdd33 Vdd18 AVdd18 TSTG Parameter Logic power supply voltage, 3.3V Logic power supply voltage, 1.8V Analog power supply voltage, 1.8V Logic input voltage Storage Temperature Min. -0.5 -0.5 -0.5 -0.5 Units volts volts volts volts Notes
STC5230
Note Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions.
Operating Conditions Electrical Characteristics
Table Recommended Operating Conditions Electrical Characteristics
Symbol Vdd33 Vdd18 AVdd18 TRIP TRIN (Vcc) (AVcc) (3.3V) (3.3V) (3.3V) (3.3V) LVCMOS Parameter 3.3V digital power supply voltage 1.8V digital power supply voltage 1.8V analog power supply voltage Input capacitance Input reference signal positive pulse width Input reference signal negative pulse width Operating Ambient Temperature Range (Commercial) Operating Ambient Temperature Range (Industrial) 3.3V digital supply current 3.3V analog supply current Device power dissipation High level input voltage level input voltage High level output voltage (IOH -12mA) level output voltage (IOL =12mA) Threshold point Input Leakage Current 1.45 1.58 -0.3 1.74 Min. 1.65 1.65 Nominal Max. 1.95 1.95 Units Volts Volts Volts Volts Volts Volts Volts Volts Notes
Preliminary
Data Sheet TM102
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Synchronous Clock SETS Data Sheet
Table Recommended Operating Conditions Electrical Characteristics
Symbol LVPECL Parameter Output voltage high Output voltage Output differential voltage Min. Vdd33 1.11 Vdd33 Nominal Max. Vdd33 0.67 Vdd33 2.66 Units Volts Volts Volts Notes
STC5230
Note LVCMOS compatible Note ohms termination Vdd33 2.0) volts
Preliminary
Data Sheet TM102
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Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet Register
Table Register
Addr 0x00 0x02 0x03 0x04 0x05 0x07 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x10 0x12 0x14 0x15 0x16 0x18 0x1a 0x1c 0x1d 0x1e 0x1f 0x20 0x24 0x28 0x2c 0x30 Chip_ID Chip_Rev Chip_Sub_Rev T0_T4_MS_Sts T0_Slave_Phase_Adj T4_Slave_Phase_Adj Fill_Obs_Window Leak_Obs_Window Bucket_Size Assert_Threshold De_Assert_Threshold Freerun_Cal Disqualification_Range Qualification_Range Qualification_Timer Ref_Selector Ref_Frq_Offset Refs_Activity Refs_Qual T0_Control_Mode T0_Bandwidth T0_Auto_Active_Ref T0_Manual_Active_Ref T0_Device_Holdover_History T0_Long_Term_Accu_History T0_Short_Term_Accu_History T0_User_Accu_History T0_History_Ramp Name Bits 15-0 11-0 11-0 10-0 15-0 13-0 11-0 31-0 31-0 31-0 31-0 Type Chip 0x5230 Chip revision number Chip sub-revision Indicates master/slave state Adjust slave phase from 409.5 steps Adjust slave phase from 409.5 steps Leaky bucket fill observation window, Leaky bucket leak observation window, times Fill_Obs_Window Leaky bucket size, Leaky bucket alarm assert threshold, Leaky bucket alarm de-assert threshold, Freerun calibration, 102.4 102.3 Reference disqualification range (pull-in range), 102.3 Reference qualification range, 102.3 Reference qualification timer, Determines which reference data shown register 0x16 Reference frequency frequency offset reference selected register 0x15 Reference cross reference activity Reference qualification -Follow/Don't Follow, Manual/Auto, Revertive, HO_Usage, PhaseAlignMode Loop bandwidth selection Indicates automatically selected reference Selects active reference manual mode Device Holdover History relative MCLK Long term Accumulated History relative MCLK Short term Accumulated History relative MCLK User Holdover data relative MCLK Bits 6-4, Long term history accumulation bandwidth: 9.7, 4.9, 2.4, 1.2, 0.61, 0.03 Bits3-2, Short term history accumulation bandwidth: 2.5, 1.24, 0.62, 0.31 Bits 1-0, Ramp control: none, 1.5, ppm/s REF1-12 selection priority automatic mode, bits/reference OOP, LOL, LOS, Sync, HHA, AHR, Flush/reset long-term history, Flush/reset both longterm device holdover history -Follow/Don't Follow, Manual/Auto, Revertive, HO_Usage, PhaseAlignMode Loop bandwidth selection Indicates automatically selected reference Selects active reference manual mode Device Holdover History relative MCLK Description
STC5230
0x31 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d
T0_Priority_Table T0_PLL_Status T0_Accu_Flush T4_Control_Mode T4_Bandwidth T4_Auto_Active_Ref T4_Manual_Active_Ref T4_Device_Holdover_History
47-0 31-0
Preliminary
Data Sheet TM102
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Synchronous Clock SETS Data Sheet
Table Register
Addr 0x41 0x45 0x49 0x4d Name T4_Long_Term_Accu_History T4_Short_Term_Accu_History T4_User_Accu_History T4_History_Ramp Bits 31-0 31-0 31-0 Type Description Long term Accumulated History relative MCLK Short term Accumulated History relative MCLK User Holdover data relative MCLK Bits 6-4, Long term history accumulation bandwidth: 9.7, 4.9, 2.4, 1.2, 0.61, 0.03 Bits3-2, Short term history accumulation bandwidth: 2.5, 1.24, 0.62, 0.31 Bits 1-0, Ramp control: none, 1.5, ppm/s REF1-12 selection priority automatic mode, bits/reference OOP, LOL, LOS, Sync, HHR, AHR, Flush/reset long-term history, Flush/reset both longterm device holdover history 155.52/125 clock select disable CLK0 disable select CLK1 disable select CLK2 8kHz output duty cycle pulse width selection CLK3 2kHz output duty cycle pulse width selection CLK4 DS3/E3 select CLK5 selector CLK6 DS1/E1 selector CLK7 Interrupt event Interrupt enable Round-trip phase delay T0's cross-couple data links 155.52/125 clock select disable CLK8
STC5230
0x4e 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x60 0x62 0x65
T4_Priority_Table T4_PLL_Status T4_Accu_Flush CLK0_Sel CLK1_Sel CLK2_Sel CLK3_Sel CLK4_Sel CLK5_Sel CLK6_Sel CLK7_Sel Intr_Event Intr_Enable T0_MS_PHE CLK8_Sel
47-0 19-0
Extra Registers configured BUS_LOAD_MODE 0x70 0x71 0x72 Bus_Loader_Status Bus_Loader_Data Bus_Loader_Counter 13-0 Status loader configuration data Data port loader configuration data Data counter loader configuration data
Extra Registers configured EEP_LOAD_MODE 0x70 0x71 0x72 0x73 0x74 EEP_Loader_Checksum EEP_Controller_Mode EEP_Controller_Cmd EEP_Controller_Page EEP_Controller_Data Checksum status EEPROM loader configuration data Mode EEPROM controller Command EEPROM controller Page number EEPROM controller Data port EEPROM controller
Preliminary
Data Sheet TM102
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Synchronous Clock SETS Data Sheet General Description
STC5230 integrated single chip solution synchronous clock (SETS), SONET, Synchronous Ethernet network elements. highly integrated design implements necessary reference selection, monitoring, filtering, synthesis, control functions. external OCXO TCXO completes system level solution (see Functional Block Diagram, Figure STC5230 comes with timing generators, implement essential functions Synchronous Equipment Timing Source (SETS). Each timing generator could either external-timing self-timing. external timing, timing generator individually select external reference inputs active reference individual Digital PhaseLocked Loop (DPLL). self-timing, clock outputs just synthesized from local oscillator (the external TCXO/OCXO). provides chip's clock outputs while provides clock output. Additionally, both provide cross reference output master/slave applications. Each timing generator individually operate Freerun, Synchronized, Holdover modes. synchronized mode, DPLL phase-locks selected external reference. Phase lock arbitrary zero phase offset between active reference clock outputs. Each DPLL's loop bandwidth programmed individually vary DPLL's filtering function. Oppositely, both freerun holdover modes self-timing. freerun mode, clock outputs synthesized calibrated from local oscillator. holdover mode, clock outputs synthesized with given frequency offset. This frequency offset could either frequency history previously accumulated STC5230, user supplied frequency offset. stability freerun holdover simply determined local oscillator. Reference frequencies auto-detected. Each reference input continuously monitored activity frequency offset. activity monitoring implemented with leaky bucket accumulator. reference desiganted "qualified" active frequency offset within programmed range pre-programmed time. Active references selected manually automatically, individually selectable manual mode, active reference selected under application control, Functional Specification independant it's qualification status. automatic mode, active reference selected according revertivity status, each reference's priority qualification. Reference priorities individually programmable. each have their priority tables. While current active reference qualified, revertivity determines whether higher priority qualified reference should preempt current active reference. reference switches performed hitless manner. When references switched, device will minimize phase transitions output clocks. frequency ramp control feature also ensures smooth frequency transitions in/out both freerun holdover mode. Both timing generators, support master/ slave operation redundant applications. sends both phase reference selection information other paired STC5230 proprietary SyncLinkcross-couple data link. provides only phase information sending 8kHz signal cross-couple path. STC5230 capable trace report T0's round-trip phase delay cross-couple data links. phase slave's clock outputs programmed adjust 0.1ns step compensate propagation re-transmission delay crosscouple path. This could minimize phase hits downstream devices while doing master/slave switches. device comes with serial interface (SPI). application could access STC5230's internal control status registers interface. STC5230 also capable field upgrading. initialization registers detailed behavior defined hardware firmware configuration data. configuration data provided internal externally. When externally sourced, data pumped either over interface, from optional external EEPROM.
STC5230
Preliminary
Data Sheet TM102
Page
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Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet Detailed Description
Chip Master Clock Input
device operates with external 20MHz OCXO TCXO master clock, connected MCLK input, freerun clock digitally calibrated from MCLK writing offset Freerun_Cal register, (0x0e/0f), from -102.4 +102.3 ppm, 0.1ppm steps, two's complement form. (See Register Descriptions section details regarding register references this section.)
STC5230
Operating Mode Details
Functional smooth clock outSTC5230 designed provide Specification puts downstream devices, even under change operating mode reference switch. Both phase frequency transition will continuous. transfer into self-timing mode (freerun holdover) designed free frequency bump. frequency ramp control limits rate frequency change when transferring self-timing mode.
Freerun/Master Mode CLK(0-6,8) (CLK7 clock outputs synthesized calibrated from MCLK have stability external TCXO/OCXO. calibration offset programmed application writing Freerun_Cal register, (0x0e/0f). calibration offset programmed from -102.4 +102.3 ppm, 0.1ppm steps. transitions into freerun back from freerun, application programmable maximum slew rate 1.5, ppm/second slew rate limit) applied, written T(0/4)_History_Ramp registers (0x30/ 0x4d). Holdover/Master Mode Holdover Mode analogous freerun mode. CLK(0-6,8) (CLK7 clock outputs synthesized from MCLK with given frequency offset, which centered digitally calibrated freerun clock. clock outputs will have stability external TCXO/OCXO. application select source frequency offset from either device accumulated holdover history user supplied frequency offset writing "HO_Usage" T(0/4)_Control_Mode register (0x1c/0x39). Device Accumulated History Holdover Mode, DPLL will device accumulated device holdover history synthesize clock outputs. User Supplied History Mode, DPLL outputs synthesized according application supplied frequency offset, provided T(0/4)_User_Accu_History registers (0x2c/ 0x49). facilitate user's accumulation holdover history, user read short-term history current clock outputs from T(0/ 4)_Short_Term_Accu_History register (0x28-0x2b/ 0x45-0x48).
Rev: Date: August 2007
Operating Mode General Description
STC5230 includes both timing generators. Each timing generator DPLL. general, each timing generator could either external-timing self-timing mode individually. external-timing, timing generator select external references active reference DPLL. active reference either input reference clocks, reference from T(0/4)_XSYNC_IN cross-couple links slave mode. addition, select clock output active reference. self-timing, clock outputs synthesized from MCLK (the external TCXO/ OCXO) with certain calibration given frequency offset. master mode, timing generators each operates Freerun, Synchronized, Holdover mode. Slave mode analogous synchronized/ master. Both external-timing. synchronized/ master mode, phase relation between reference clock outputs could configured arbitrary aligned. User could also program DPLL's loop bandwidth vary noise transfer function. slave mode, clock outputs phase-align cross-reference. Unlike master mode, loop bandwidth fixed (107 slave mode. Holdover mode analogous freerun mode. Both self-timing. clock outputs synthesized from local oscillator with certain calibration given frequency offset. stability these modes simply determined local oscillator.
Preliminary
Data Sheet TM102
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Synchronous Clock SETS Data Sheet
transitions into holdover back from holdover, application programmable maximum slew rate 1.5, ppm/second slew rate limit) applied, written T(0/4)_History_Ramp registers (0x30/ 0x4d). Synchronized/Master Mode synchronized mode, DPLL phase-locks track selected input reference. timing generator external-timing. CLK(0-6,8) (CLK7 clock outputs synchronized selected input reference. this mode, "Phase Align Mode" T(0/ 4)_Control_Mode registers (0x1c, 0x39) determines output clock input reference phase alignment mode. Arbitrary mode, DPLL will frequency locking stage initially. When synchronization achieved, clock output phase relationship relative reference input will reset locked (phase rebuild). Phase Align mode, output clocks phase aligned selected reference. should noted that output-to-reference phase alignment meaningful only those cases where output frequency reference same related integer ratio.) After reference switch re-lock (due loss signal loss lock), DPLL will pull-in process initially. phase mode arbitrary, pullin process will frequency-locking only until synchronization achieved. When synchronization achieved, clock output phase relationship relative reference input will reset locked. phase mode aligned, pull-in process will phase-locking mode since beginning. pull-in process prologue seconds normal situation. DPLL's loop bandwidth independently. Loop bandwidth programmable from 90mHz 107Hz writing T(0/4)_Bandwidth registers (0x1d/ 0x3a). There special cases synchronized mode: Zombie mode signal active reference lost, DPLL output generated according short-term history last moment; Pull-in Range mode selected reference exceeds pull-in range programmed application, DPLL output Functional Specification programmed stay pull-in range limit, follow reference. This programmed writing "OOP" T(0/4)_Control_Mode registers (0x1c/ 0x39), specifying whether follow follow reference that exceeded pull-in range. frequency offset centered digitally calibrated freerun clock. Slave Mode slave mode analogous synchronized/ master mode. timing generators will enter this mode bring T(0/4)_M/S low. Different synchronized/master mode, phase mode aligned loop bandwidth fixed DPLL's clock outputs will follow cross-reference matter "OOP" T(0/ 4)_Control_Mode registers. DPLL will lock phase align T0_XSYNC_IN input 8kHz signal T4_XSYNC_IN input.
STC5230
Operating Mode Transition Details
When reference selection manual mode, operating mode could selected writing T(0/4)_Manual_Active_Ref registers (0x1f/0x3c). This could force timing generator into freerun, synchronized, holdover mode. When reference selection automatic mode, automatic reference selector only picks active reference, also decides operating mode. DPLL will enter synchronized mode least reference qualified elected active reference. Otherwise, operating mode will either freerun mode holdover mode, depending existence holdover history. Figure shows phase locked loop states transitions operation with automatic reference selection Master mode. transfer into holdover mode designed smooth free hits with frequency ramp control. transitions into freerun back from freerun, application programmable maximum slew rate 1.5, ppm/second slew rate limit) applied, written T(0/4)_History_Ramp registers (0x30/ 0x4d).
Rev: Date: August 2007
Preliminary
Data Sheet TM102
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Synchronous Clock SETS Data Sheet
reference. weighted single-pole low-pass filter programmed -3dB point 9.7, 4.9, Functional Specification 2.4, 1.2, 0.61, 0.31 writing T(0/ 4)_History_Ramp register (0x30/0x4d). Internally, express mode used after reset applying lower time constant first minutes speed history accumulation process. This accumulation process will reset whenever selected reference switched loss lock occurs. accumulation process will then resume after synchronization achieved assertion "SYNC" T(0/ 4)_DPLL_Status register (0x37/0x54). Additionally, application flush/rebuild this long-term history writing either T(0/ 4)_Accu_Flush register (0x38/0x55). long-term history read from T(0/ 4)_Long_Term_Accu_History registers (0x24-0x27/ 0x41-0x44). Device Holdover History When timing generator enters holdover mode with history usage programmed Device Accumulated History Holdover Mode, this history determines CLK(0-6,8) (CLK7 clock outputs. initial history will begin continuously being updated long-term history after minute express mode time completed. Updating will stop long term history accumulation process reset result reference switch loss lock. Thus, previous holdover history will persist until long term history accumulated following reference switch attendant re-building long term history after loss lock. "AHR" T(0/4)_DPLL_Status registers (0x37/0x54) during updating, will revert when updating stops. Additionally, application reset this holdover history writing T(0/ 4)_Accu_Flush register (0x38/0x55).
STC5230
Freerun
Reference Available Available
Reference Available
Locking
Switch active reference
Frequency Locked Locked Synchronized Reference Available Available Reference Available
Holdover
Figure Operating mode transition automatic reference selection (Master mode)
History Accumulation Details
Three holdover histories built maintained each timing generator: short-term history, long-term history, device holdover history. Short-Term History This short-term average frequency DPLL's clock outputs time. weighted single-pole low-pass filter programmed -3dB point 2.5, 1.24, 0.62, 0.31 writing T(0/ 4)_History_Ramp register (0x30/0x4d). shortterm history used zombie sub-mode. This history read from T(0/ 4)_Short_Term_Accu_History registers (0x28-0x2b/ 0x45-0x48). Long-Term History This long-term average frequency DPLL's clock outputs, while synchronized selected exter-
Phase-Locked Loop Status Details
T(0/4)_PLL_Status registers (0x37/0x54) contain detailed status DPLL, including signal activity active reference, synchronization status, availability holdover histories. Applications program Intr_Enable register enable/disable interrupts (pin EVENT_INTR) trigged status change T(0/4)_PLL_Status registers.
Rev: Date: August 2007
Preliminary
Data Sheet TM102
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Synchronous Clock SETS Data Sheet
SYNC external-timing mode (e.g., slave synchronized/master modes), this indicates achievement synchronization. This won't asserted self-timing mode (e.g., freerun holdover modes). external-timing mode (e.g., slave synchronized/master modes), this indicates loss signal active reference. This won't asserted self-timing mode (e.g., freerun holdover modes). external-timing mode (e.g., slave synchronized/master modes), DPLL will raise event loss lock fails achieve maintain lock active reference. This won't asserted self-timing mode (e.g., freerun holdover modes). This also complemented SYNC bit. Both bits won't asserted when DPLL still pull-in process. This indicates pull-in range active reference external-timing mode (e.g., slave synchronized/master modes). This won't asserted self-timing mode (e.g., freerun holdover modes). frequency offset centered digitally calibrated freerun clock. This indicates whether DPLL's output clocks stop following active reference because frequency offset active reference pull-in range. application write T(0/ 4)_Control_Mode register program whether DPLL shall follow active reference specified pull-in range. This indicates whether device holdover history tracking current active reference (updating long-term history). This indicates availability holdover history, which could either user provided history device holdover history.
Data Sheet TM102
STC5230
Reference Input Monitoring QualifiFunctional Specification cation
STC5230 accepts external reference inputs 8kHz, 64kHz, 1.544MHz, 2.048MHz, 19.44MHz, 38.88MHz, 77.76MHz, 6.48MHz, 8.192MHz, 16.384MHz, 25MHz, 50MHz, 125MHz. Input frequencies detected automatically. autodetected frequency reference read selecting reference Ref_Selector register (0x15) then reading frequency from register Ref_Frq_Offset (0x17). Each input monitored qualified activity frequency offset. Activity monitoring accomplished with leaky bucket accumulation algorithm, shown figure "leaky bucket" accumulator fill observation window that from where signal abnormality multiple hits) during window increments bucket count one. leak observation window times fill observation window. leaky bucket accumulator decrements each leak observation window that passes with signal abnormality. Both windows operate consecutive, non-overlapping manner. bucket accumulator alarm assert alarm de-assert thresholds that each programmed from
Fill Observation Window, 16ms
Frequency Detector
Pulse Monitor
Leaky Bucket Accumulator
Alarm Assert
Alarm De-Assert
Leak Observation Window, 1~16 Fill Observation Window
Figure Activity Monitor Applications write following registers configure activity monitor: Fill_Obs_Window (0x09), Leak_Obs_Window (0x0a), Bucket_Size (0x0b), Assert_Threshold (0x0c), De_Assert_Threshold (0x0d). User bucket size equal turn activity monitor. This de-asserts activity alarms references. Otherwise, non-zero bucket size must greater than equal alarm assert
Rev: Date: August 2007
Preliminary
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Synchronous Clock SETS Data Sheet
threshold value, alarm assert threshold value must greater than alarm de-assert value. STC5230 will ignore writing these three registers value violates rules. User shall carefully plan scenario activity monitor re-configuration. Alarms appear Refs_Activity register (0x18,0x19). indicates activity, indicates alarm, activity. Note that reference detected different frequency, leaky bucket accumulator bucket size value reference will become inactive immediately. Reference inputs also monitored qualified frequency offset. reference qualification range programmed 102.3 writing register Qualification_Range (0x12,0x13), disqualification range 102.3 ppm, writing register Disqualification_Range (0x10,0x11). qualification range must less than disqualification range. Additionally, qualification timer programmed from seconds writing register Qualification_Timer (0x14). pull-in range same disqualification range. frequency offset centered digitally calibrated freerun clock. Each value read selecting reference Ref_Selector register (0x15) then reading offset value from register Ref_Frq_Offset (0x16,0x17). Figure shows reference qualification scheme. reference qualified activity alarm Functional Specification within qualification range more than qualification time. activity alarm frequency offset beyond disqualification range will disqualify reference. then re-qualified activity alarm reference within qualification range more than qualification time. reference qualification status each reference then read from register Refs_Qual (0x1a/1b).
STC5230
Active Reference Selection
timing generators individually operated either manual automatic input reference selection mode. mode selected T(0/4)_Control_Mode registers (0x1c/0x39). Manual Reference Selection Mode manual reference selection mode, user select reference. This mode selected T(0/4)_Control_Mode (0x1c/0x39) registers. reference selected writing T(0/ 4)_Manual_Active_Ref (0x1f/0x3c) registers. Automatic Reference Selection Mode automatic reference selection mode, device will select pre-qualified reference active reference. This mode T(0/4)_Control_Mode (0x1c/0x39) registers. active reference picked according indicated priority reference priority table, registers T(0/4)_Priority_Table (0x31~0x36/0x4e~0x53). Each reference entry table, which value from masks-out reference, while priority, where highest, `15' lowest priority. highest priority pre-qualified reference then candidate active reference. multiple references share same priority, qualified with longer duration will tie-break. This active reference candidate will promoted active reference immediately active reference exists. operating mode will then enter synchronized mode. candidate reference different existing active reference, this candidate revert
Activity Good Activity Alarm Asserted Activity Alarm Asserted
Activity Alarm De-Asserted
Within Offset Qualification Range more than Qualification Time
Activity Good
Qualified
Disqualification Range
Figure Reference Qualification Scheme
Preliminary
Data Sheet TM102
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Synchronous Clock SETS Data Sheet
pre-empt existing active reference. This determined either enabling disabling "revertive" T(0/4)_Control_Mode (0x1c/0x39) revertive non-revertive operation. When reversion (pre-emption) enabled, candidate reference will selected immediately active reference. When reversion disabled, current active reference will pre-empted candidate until disqualified. automatically selected active reference each DPLL read from T(0/4)_Auto_Active_Ref (0x1e/0x3b) registers. pre-qualification scheme described Reference Inputs Monitoring Qualification section. CLK2: Programmable 19.44MHz, 38.88MHz, 51.84, 77.76 MHz, 25MHz, Functional Specification 50MHz, 125MHz, disabled, writing CLK2_Sel register (0x58). CLK3: 8kHz, duty cycle programmable pulse width, disabled writing CLK3_Sel register (0x59). CLK4: 2kHz, duty cycle programmable pulse width, disabled writing CLK4_Sel register (0x5a). CLK8: second pair 155.52/125 (LVPECL), selected disabled writing CLK8_Sel register (0x65).
STC5230
more synthesizers generate additional clocks from DPLL: CLK5: Either rate, "disabled", programmed writing CLK5_Sel register (0x5b). CLK6: Programmable nxDS1 nxE1 rate, where n=1,2,4,8,16, disabled, writing CLK6_Sel register (0x5c).
Output Clocks
clock output section includes timing generators, APLL, four dividers, generates eight synchronized clocks, shown figure
DPLL Synthesizer Clk0 APLL Divider 155.52/125MHz Clk1 19.44/38.88/77.76/ 51.84/25/50/125
synthesizer driven DPLL: CLK7: Either rate, "disabled", programmed writing CLK7_Sel register (0x5d), bits
Clk2 19.44/38.88/77.76/ 51.84/25/50/125 Clk3 Divider Divider Clk4 Divider Clk8 155.52/125MHz
When clock output disabled, tri-stated. addition, T0_XSYNC_OUT output provides phase information state data master/slave operation timing generators. T4_XSYNC_OUT output provides 8kHz signal master/slave operation timing generator. Note that CLK0,1, phase aligned with CLK3 (8kHz) shown Figure CLk3 phase aligned with CLK4 (2kHz).
2kHz
Synthesizer Synthesizer
Clk5 DS3, Clk6 nxDS1, nxE1 1,2,4,8,16
DPLL
Clk7 Synthesizer
Figure Output Clocks first synthesizer drives analog generates output clocks. driven from DPLL: CLK0: 155.52/125 (LVPECL), selected disabled writing CLK0_Sel register (0x56). CLK1: Programmable 19.44MHz, 38.88MHz, 51.84MHz, 77.76 MHz, 25MHz, 50MHz, 125MHz, disabled, writing CLK1_Sel register (0x57).
8kHz 38.88MHz 77.76MHz T1/E1 T3/E3
Figure clock output Phase Alignment
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Data Sheet TM102
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Synchronous Clock SETS Data Sheet
Master/Slave Configuration
Pairs STC5230 devices operated master/slave configuration added reliability, shown Figure Devices configured master/slave pair crossconnecting their respective T(0/4)_XSYNC_OUT and/ T(0/4)_XSYNC_IN pins. T(0/4)_MS pins determine master slave mode each timing generator: 1=Master, 0=Slave. Thus, master/slave state always manually controlled application. slave synchronizes phase-aligns 2kHz domain according data received over T0_XSYNC_OUT T0_XSYNC_IN data link from paired partner. slave synchronizes phase-aligns 8kHz received T4_XSYNC_OUT T4_XSYNC_IN connection from paired partner well. ogous synchronized/master mode. T(0/ 4)_XSYNC_OUT data link/8kHz signals provide Functional Specification phase information 2kHz (T0) 8kHz (T4) phase alignment between master slave. addition phase information, T0_XSYNC_OUT also provides reference selection state ensure that later master lock same reference reference selection "automatic" mode. Perfect phase alignment Clk(x) output clocks (between paired timing generators devices) would require delay cross-couple data link connection. accommodate delay path, STC5230 provides programmable phase compensation feature. figures slave's Clk(x) outputs phase shifted from +409.5ns, 100ps increments according contents T(0/4)_Slave_Phase_Adj (0x05/06, 0x07/08) registers compensate path delay T(0/4)_XSYNC_OUT T(0/4)_XSYNC_IN connections. This offset therefore programmed exactly compensate actual path delay associated with particular application's cross-couple traces. Thus, master/slave switches with STC5230 devices accomplished with near-zero phase hits downstream devices.
2kHz
STC5230
T0_MS
T0_XSYNC_OUT
T0_MS
T0_XSYNC_IN T4_XSYNC_OUT T4_MS
T4_XSYNC_IN
T4_MS
STC5230
STC5230
Master Clock Synthesizer
8kHz 38.88MHz 77.76MHz
Figure Master/Slave Pair operated completely independent each other either both cross-connected master/slave pairs across STC5230 devices, master/slave states same opposite within given device. When STC5230 wired master/slave pair configuration, paired timing generators running master/master, master/slave, slave/master modes. However, running slave/slave mode will disable clock resonance closed loop. Same applies paired timing generators. T0_T4_MS_Sts register reflect states T(0/4)_MS pins.
STC5230
T1/E1 T3/E3 Programmable compensation from 409.5 2kHz
Slave Clock Synthesizer
8kHz 38.88MHz 77.76MHz
STC5230
T1/E1 T3/E3
Figure CLK0-6,8 Phase Alignment Master/Slave skew Control STC5230 capable trace report round-trip phase delay T0's cross-couple links. While configured master mode redundant application, phase delay between T0_XSYNC_OUT
Rev: Date: August 2007
Master/Slave Operation
While slave configuration, operation anal-
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Data Sheet TM102
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Synchronous Clock SETS Data Sheet
T0_XSYNC_IN pins continously measured. User obtain phase delay reading T0_MS_PHE register (0x62-0x64). Advanced users this information their further fault detection. first time timing generator becomes slave, such immediately after power-up, output clock phase starts arbitrary, will quickly phase-align master unit. phase error will eliminated converged programmed phase offset). whole pull-in-and-lock process will complete about seconds. There frequency ramp protection slave mode. Activity signals T(0/4)_XSYNC_IN pins available Refs_Activity register (0x18/19). (The leaky bucket algorithms applied these signals.) Note phase alignment clock outputs from timing generator with 2kHz output. Once pair timing generators been operating aligned master/slave mode, master/slave switch occurs, timing generator that becomes master will maintain output clock phase frequency while phase rebuild performed selected reference input. Therefore, master mode operation commences, there will phase frequency hits clock output. Assuming phase offset programmed actual delay this cross-couple path, there will again phase hits output clock timing generator that transitioned from master slave.
Master Clock Synthesizer
STC5230
Functional Specification
Event Interrupts
STC5230 could provide notice interrupts host processor EVENT_INTR (pin 32). hand certain events programmed trig interrupts. User turn each event individually writing register Intr_Enable (0x60-0x61). associated events which trigged interrupts will latched. After detected assert interrupt pin, application read list latched events from register Intr_Event (0x5e-0x5f). User clear events writing position each related event. EVENT_INTR returns normal when more event latched. There different events programmed trig interrupts. list covers some status change each timing generator change qualification status input references. status change timing generator includes change active reference automatic reference selection mode, change DPLL status, change cross reference activity. Each event could enabled disabled individually.
Field Upgrade Feature
initialization registers DPLL detailed behavior defined hardware firmware configuration data. Following device reset, either power-up operation reset pin, device needs loaded with configuration data. This data loaded from internal (programmed with factory default data), optional external EEPROM, from interface. Externally supplied data provides option accept future field upgrades. external data loading, manufacturer provide configuration data specific customer agreement. Load mode configuration pins load mode configuration pins determine configuration data pump method, shown table
T1/E1
STC5230
Programmable compensation from 409.5
Slave Clock Synthesizer
T1/E1
STC5230 Figure CLK7 Master/Slave Skew Control
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Data Sheet TM102
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Synchronous Clock SETS Data Sheet
Note that Load Mode pins should both high, device damage occur. load mode, configuration data loaded from internal ROM, which loaded with nominal manufacturer's data. Data loading occurs automatically power after reset. power reset. EEPROM interface shown Figure Functional Specification Load Process Data loading mode accomplished using Bus_Loader_Status (0x70), Bus_Loader_Data (0x71), Bus_Loader_Counter (0x72) registers. User shall follow procedure below:
data array data[10496] contains hardware/firmware configuration data, starting from index Procedure Bus_Load begin Label_Repeat: busy wait until "bus ready" Bus_Loader_Status equal `1'; 10,495 step begin write data[i] register Bus_Loader_Data; busy wait until "bus ready" register Bus_Loader_Status equal `1'; "load complete" register Bus_Loader_Status equal begin loading failed reset this device asserting RESET; goto Label_Repeat; "checksum status" register Bus_Loader_Status equal begin loading failed reset this device asserting RESET; goto Label_Repeat; Loading Success procedure Load
STC5230
Table Load Mode Configuration Pins
LM1,LM0 Description load mode load mode EEPROM load mode Reserved
Table Compatible EEPROMs
Manufacturer ATMEL Part Number AT25128A
EEP_CS EEP_SCK EEP_SI EEP_SO
EEPROM
ATMEL AT25128A
STC5230
Both HOLD have tied high
Figure EEPROM Configuration load mode, configuration data loaded from interface application, using device load register interface. Data provided customer agreement with manufacturer. load procedure described following section. EEPROM load mode, EEPROM loader will load configuration data from optional external EEPROM. Data will provided manufacturer agreement with customer. configuration data read from write external EEPROM interface. When EEPROM load mode selected, data loading occurs automatically immediately following
device will assert "load complete" register Bus_Loader_Status after application writes 10,496 bytes into register Bus_Loader_Data. After "load complete" asserted, application shall read check "checksum status" register Bus_Load_Status. indicates checksum passed; indicates failure loading. CRC-16
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Data Sheet TM102
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Synchronous Clock SETS Data Sheet
checksum encryption used configuration data assure detection transmission error. Should load fail, application must reset device repeat load process. Before "bus ready" asserted after "load complete" register Bus_Loader_Status asserted, writes Bus_Loader_Data register will ignored. time process, application read number bytes that have been written from Bus_Loader_Counter register. EEPROM Load Process When configured EEP_LOAD_MODE, configuration data will loaded from optional external EEPROM device's build-in EEPROM loader automatically. Application shall read check register EEP_CHECKSUM which indicates CRC-16 checksum status loading process. download failed, application must reset device repeat check this status again. EEPROM: Read Write Application pump configuration data into external EEPROM before normal operation expecting configure load data from EEPROM. When configured EEP_LOAD_MODE, application read write configuration data from/to external EEPROM device's EEPROM controller using register EEP_Controller_Mode, EEP_Controller_Cmd, EEP_Controller_Page, EEP_Controller_Data (0x71 0x74). After pump (writing) whole configuration data into external EEPROM, application read back comparison ensure transmission error happened. writing reading procedures follows:
Procedure EEP_Write begin data array data[10496] contains hardware/ firmware configuration data, starting from index busy wait until "ready" register EEP_Controller_Mode equal `1'; write 0x01 register EEP_Controller_Mode; turn write feature write 0x00 register EEP_Controller_Cmd; reset page FIFO buffer step begin write register EEP_Controller_Page; page index step begin write data[64*i+j] register EEP_Controller_Data; write 0x01 register EEP_Controller_Cmd; issue write command busy wait until "ready" register EEP_Controller_Mode equal `1'; write 0x00 register EEP_Controller_Mode; turn write feature procedure EEP_Write
STC5230
Functional Specification
Procedure EEP_Read begin busy wait until "ready" register EEP_Controller_Mode equal `1'; step begin write register EEP_Controller_Page; page index write 0x02 register EEP_Controller_Cmd; issue read command busy wait until "ready" register EEP_Controller_Mode equal `1'; step begin read copy value register EEP_Controller_Data into data[64*i+j]; data array data[10496] then carrying hardware/firmware configuration data, starting from index procedure EEP_Read
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Data Sheet TM102
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Synchronous Clock SETS Data Sheet
Processor Interface Descriptions
STC5230 supports serial interface. description bus's interface timing following: interface mode uses BUS_CS, BUS_ALE, BUS_RDB, BUS_RDY pins, corresponding SCLK, SDI, respectively, with timing shown figures Serial Timing
tCSHLD tCSMIN tCSTRI
STC5230
SCLK
tDHLD
tDRDY
Figure Serial Timing, Read access
tCSHLD tCSMIN
SCLK
Figure Serial Timing, Write access
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Table Serial Timing
Symbol tDRDY tDHLD tCSHLD tCSTRI tCSMIN Description SCLK high SCLK high time SCLK time Data setup time Data hold time Data ready Data hold Chip select hold Chip select data tri-state Minimum delay between successive accesses Unit
STC5230
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Data Sheet TM102
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Synchronous Clock SETS Data Sheet Register Descriptions Operation
General Register Operation
STC5230 device byte registers. One-byte registers read written directly. Multiple -byte registers must read written specific manner order, follows: Multibyte register reads multibyte register read must commence with read least significant byte first. This triggers transfer remaining byte(s) holding register, ensuring that remaining data will change with continuing operation device. remaining byte(s) must read consecutively with intervening read/writes from/to other registers. Multibyte register writes multibyte register write must commence with write least significant byte first. Subsequent writes remaining byte(s) must performed ascending byte order, consecutively, with intervening read/ writes from/to other registers, with timing restrictions. Multibyte register writes temporarily stored holding register, transferred target register when most significant byte written. Clearing bits Interrupt Status Register Interrupt event register (Intr_Event, 0x5e~0x5f) bits cleared writing position cleared. Interrupt positions left written with "0".
STC5230
Chip_ID, 0x00
Address 0x00 0x01 Bit7 Bit6 Bit5 Bit4 0x30 0x52 Bit3 Bit2 Bit1 Bit0
Chip_Rev, 0x02
Address 0x02 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Revision Number
Chip_Sub_Rev, 0x03
Address 0x03 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Sub-Revision Number
T0_T4_MS_Sts, 0x04 (R/W)
Address 0x04 Bit7 Bit6 Bit5 used Bit4 Bit3 Bit2 Bit1 Bit0
Reflects states T0/T4_MASTER_SLAVE select pins. Master, slave
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Synchronous Clock SETS Data Sheet
T0_Slave_Phase_Adj, 0x05 (R/W)
Address 0x05 0x06 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
STC5230
Adjust slave phase from 409.5 steps, lower bits used Adjust slave phase from 409.5 steps, upper bits
slave phase adjusted 409.5 relative cross couple input with resolution. This register, split across address 0x05 0x06. Default value:
T4_Slave_Phase_Adj, 0x07 (R/W)
Address 0x07 0x08 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Adjust slave phase from 409.5 steps, lower bits used Adjust slave phase from 409.5 steps, upper bits
slave phase adjusted 409.5 relative cross couple input with resolution. This register, split across address 0x07 0x08. Default value:
Fill_Obs_Window, 0x09 (R/W)
Address 0x09 Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Leaky bucket fill observation window,
Sets fill observation window size reference activity monitor (m+1) window size from 16ms. Default value: (1ms)
Leak_Obs_Window, 0x0a (R/W)
Address 0x0a Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Leaky bucket fill observation window,
Sets leak observation window size reference activity monitor times fill observation window size. Default value: times)
Bucket_Size, 0x0b (R/W)
Address 0x0b Bit7 used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Leaky bucket size,
Sets leaky bucket size reference activity monitor. Bucket size equal will leaky bucket active monitor off, which will assert activity alarm. Otherwise, bucket size must greater than equal alarm assert value. Invalid values will written register.
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Synchronous Clock SETS Data Sheet
Default value:
STC5230
Assert_Threshold, 0x0c (R/W)
Address 0x0c Bit7 used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Leaky bucket alarm assert threshold,
Sets leaky bucket alarm assert threshold reference activity monitor. alarm assert threshold value must greater than de-assert threshold value less than equal bucket size value. Invalid values will written register. Default value:
De_Assert_Threshold, 0x0d (R/W)
Address 0x0d Bit7 used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Leaky bucket alarm de-assert threshold,
Sets leaky bucket alarm de-assert threshold reference activity monitor. de-assert threshold value must less than assert threshold value. Invalid values will written register. Default value:
Freerun_Cal, 0x0e (R/W)
Address 0x0e 0x0f used Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Lower bits Upper bits
Freerun calibration, from -102.4 +102.3 ppm, 0.1ppm steps, two's complement. Default value:
Disqualification_Range, 0x10 (R/W)
Address 0x10 0x11 used Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Lower bits Upper bits
Reference disqualification range, from +102.3 ppm, steps. This also sets pull-in range. (See Reference Input Monitoring Qualification section) Default value: (range 11.0 ppm).
Qualification_Range, 0x12 (R/W)
Address 0x12 0x13 used Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Lower bits Upper bits
Reference qualification range, from +102.3 ppm, steps. Default value: (range 10.0 ppm).
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Synchronous Clock SETS Data Sheet
Qualification_Timer, 0x14 (R/W)
Address 0x14 Bit7 used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
STC5230
Reference qualification timer, from Default value:
Ref_Selector, 0x15 (R/W)
Address 0x15 Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(0x1 0xc)
Determines which reference data displayed register 0x16 0x17. Valid values from Invalid values will written register. Default value:
Ref_Frq_Offset, 0x16
Address 0x16 0x17 Reference frequency Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Lower bits frequency offset Upper bits frequency offset
Displays frequency offset reference frequency reference selected Ref_Selector (0x15) register. Frequency offset from -204.7 +204.7 relative calibrated freerun, steps, two's complement. value -2048 indicates reference range. reference frequency determined follows ("Unknown" indicates signal present, frequency undetermined):
0x17, bits Frequency signal 1.544 2.048 19.44 38.88 77.76 6.48MHz 8.192MHz 16.384MHz Unknown Reserved
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Refs_Activity, 0x18
Address 0x18 0x19 Bit7 used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
STC5230
T4_XSYNC_INT0_XSYNC_IN
Reference activity indicator, activity, activity.
Refs_Qual, 0x1a
Address 0x1a 0x1b Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reference qualification indicator, qualified, qualified.
T0_Control_Mode, 0x1c (R/W)
Address 0x1c Bit7 used Bit6 Bit5 OOP: Pull-in range: 0=Follow 1=Don't follow Bit4 Manual/ Auto 0=Manual 1=Auto Bit3 Revertive 0=Nonrevertive 1=Revertive Bit2
HO_Usage 0=DHH 1=User
Bit1 used
Bit0 Phase Align Mode 0=Arbitrary 1=Align
Mode control bits Phase Align Mode HO_Usage Arbitrary (use initial phase), Phase align Device Holdover History (DHH) used; User supplied history used. manual mode, when selected active reference pull-in range, specified register Disqualification_Range (0x10). will determine reference followed, Follow, Don't follow.
Default value:
T0_Bandwidth, 0x1d (R/W)
Address 0x1d Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Bandwidth select Bit1 Bit0
Sets loop bandwidth:
0x1d, bits Bandwidth,
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Synchronous Clock SETS Data Sheet
0x1d, bits Bandwidth, 0.37 0.18 0.09 Reserved
STC5230
Default value:
T0_Auto_Active_Ref, 0x1e
Address 0x1e Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Selection Bit1 Bit0
Indicates automatically selected active reference when this "master". When this "slave", master's active reference indicated. (Data valid automatic mode only)
Freerun Sync with Holdover Reserved Selection
T0_Manual_Active_Ref, 0x1f (R/W)
Address 0x1f Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Selection Bit1 Bit0
Selects active reference manual reference select mode.
Freerun Sync with Holdover Reserved Selection
Default value:
T0_Device_Holdover_History, 0x20
Address 0x20 0x21 0x22 0x23 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits Device Holdover History Bits Device Holdover History Bits Device Holdover History Bits Device Holdover History
Device holdover history relative MCLK. complement. Resolution 0.745x10-3ppb. Default value:
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Synchronous Clock SETS Data Sheet
T0_Long_Term_Accu_History, 0x24
Address 0x24 0x25 0x26 0x27 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
STC5230
Bits Long Term History Bits Long Term History Bits Long Term History Bits Long Term History
Long term accumulated history relative MCLK. complement. Resolution 0.745x10- ppb.
T0_Short_Term_Accu_History, 0x28
Address 0x28 0x29 0x2a 0x2b Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits Short Term History Bits Short Term History Bits Short Term History Bits Short Term History
Short term accumulated history relative MCLK. complement. Resolution 0.745x10-3 ppb.
T0_User_Accu_History, 0x2c (R/W)
Address 0x2c 0x2d 0x2e 0x2f Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits User Holdover History Bits User Holdover History Bits User Holdover History Bits User Holdover History
User accumulated history relative MCLK. complement. Resolution 0.745x10-3 ppb. Default value:
T0_History_Ramp, 0x30 (R/W)
Address 0x30 Bit7 used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Long Term History Bandwidth
Short Term History Bandwidth
Ramp control
Holdover bandwidth ramp controls
Long Term History -3dB Bandwidth 0.61 0.30
0x30, bits
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Synchronous Clock SETS Data Sheet
Short Term History -3dB Bandwidth 1.24 0.62 0.31
STC5230
0x30, bits
0x30, bits
Ramp control Control ppm/s ppm/s ppm/s
Default value: 0x27 (2.4mHz; 1.24Hz; 2ppm/s)
T0_Priority_Table, 0x31 (R/W)
Address 0x31 0x32 0x33 0x34 0x35 0x36 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Priority Priority Priority Priority Priority Priority
Priority Priority Priority Priority Priority Priority
Reference priority automatic reference selection mode. Lower values have higher priority:
0x31 0x36, bits 0000 0001 1111 Reference Priority Disable reference
Default value:
T0_PLL_Status, 0x37
Address 0x37 Bit7 1=Available 0=Not available Bit6 1=Ready 0=Not ready Bit5 Reserved Bit4 1=Stop pull-in range 0=Following Bit3 1=Out pull-in range 0=In range Bit2 0=No 1=LOL Bit1 0=No 1=LOS Bit0 SYNC: 0=No Sync 1=Sync
SYNC
Indicates synchronization been achieved Loss signal active reference Loss lock (Failure achieve maintain lock) pull-in range
Data Sheet TM102 Page Rev: Date: August 2007
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Synchronous Clock SETS Data Sheet
Active Holdover History Ready Holdover History Available Indicates output clocks stop following selected reference, caused pull-in range
Holdover Status Holdover History available: Device Holdover History tracking current active reference Holdover History available: Device Holdover History based last available history Holdover History available applicable
STC5230
T0_Accu_Flush, 0x38
Address 0x38 Bit7 Bit6 Bit5 Bit4 used Bit3 Bit2 Bit1 Bit0 flush
Writing this register will perform flush accumulated history. value zero determines which histories flushed. Flush reset long term history only; flush/reset both long term history device holdover history.
T4_Control_Mode, 0x39 (R/W)
Address 0x39 Bit7 used Bit6 Bit5 OOP: Pull-in range: 0=Follow 1=Don't follow Bit4 Manual/ Auto 0=Manual 1=Auto Bit3 Revertive 0=Nonrevertive 1=Revertive Bit2
HO_Usage 0=DHH 1=User
Bit1 used
Bit0 Phase Align Mode 0=Arbitrary 1=Align
Mode control bits Phase Align Mode HO_Usage Arbitrary (use initial phase), Phase align Device Holdover History (DHH) used; User supplied history used. manual mode, when selected active reference pull-in range, specified register Disqualification_Range (0x10). will determine reference followed, Follow, Don't follow.
Default value:
T4_Bandwidth, 0x3a (R/W)
Address 0x3a Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Bandwidth select Bit1 Bit0
Sets loop bandwidth:
0x3a, bits Bandwidth, Page Rev: Date: August 2007
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0x3a, bits Bandwidth, 0.37 0.18 0.09 Reserved
STC5230
Default value:
T4_Auto_Active_Ref, 0x3b
Address 0x3b Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Selection Bit1 Bit0
Indicates automatically selected active reference (Data valid automatic mode only)
Freerun Sync with Holdover Reserved Selection
T4_Manual_Active_Ref, 0x3c (R/W)
Address 0x3c Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Selection Bit1 Bit0
Selects active reference manual reference select mode. Default value:
Freerun Sync with Holdover Reserved Lock output Selection
T4_Device_Holdover_History, 0x3d
Address 0x3d 0x3e 0x3f 0x40 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits Device Holdover History Bits Device Holdover History Bits Device Holdover History Bits Device Holdover History Data Sheet TM102 Page Rev: Date: August 2007
Preliminary
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
Device holdover history relative MCLK. complement. Resolution 0.745x10-3ppb. Default value:
STC5230
T4_Long_Term_Accu_History, 0x41
Address 0x41 0x42 0x43 0x44 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits Long Term History Bits Long Term History Bits Long Term History Bits Long Term History
Long term accumulated history relative MCLK. complement. Resolution 0.745x10-3 ppb.
T4_Short_Term_Accu_History, 0x45
Address 0x45 0x46 0x47 0x48 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits Short Term History Bits Short Term History Bits Short Term History Bits Short Term History
Short term accumulated history relative MCLK. complement. Resolution 0.745x10-3 ppb.
T4_User_Accu_History, 0x49 (R/W)
Address 0x49 0x4a 0x4b 0x4c Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits User Holdover History Bits User Holdover History Bits User Holdover History Bits User Holdover History
User accumulated history relative MCLK. complement. Resolution 0.745x10-3 ppb. Default value:
T4_History_Ramp, 0x4d (R/W)
Address 0x4d Bit7 used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Long Term History bandwidth
Short Term History bandwidth
Ramp control
Holdover bandwidth ramp controls
Long Term History -3dB Bandwidth Page Rev: Date: August 2007
0x4d, bits
Preliminary
Data Sheet TM102
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Synchronous Clock SETS Data Sheet
0x4d, bits Long Term History -3dB Bandwidth 0.61 0.30 Short Term History -3dB Bandwidth 1.24 0.62 0.31 Ramp control Control ppm/s ppm/s ppm/s
STC5230
0x4d, bits 0x4d, bits
Default value: 0x27 (2.4mHz; 1.24Hz; 2ppm/s)
T4_Priority_Table, 0x4e (R/W)
Address 0x4e 0x4f 0x50 0x51 0x52 0x53 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Priority Priority Priority Priority Priority Priority
Priority Priority Priority Priority Priority Priority
Reference priority automatic reference selection mode. Lower values have higher priority:
0x4e 0x53, bits 0000 0001 1111 Reference Priority Disable reference
Default value:
T4_PLL_Status, 0x54
Address 0x54 Bit7 1=Available 0=Not available Bit6 1=Ready 0=Not ready Bit5 Reserved Bit4 1=Stop pull-in range 0=Following Page Bit3 1=Out pull-in range 0=In range Bit2 0=No 1=LOL Bit1 0=No 1=LOS Bit0 SYNC: 0=No Sync 1=Sync
Preliminary
Data Sheet TM102
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
SYNC Indicates synchronization been achieved Loss signal active reference Loss lock (Failure achieve maintain lock) pull-in range Active Holdover History Ready Holdover History Available Indicates output clocks stop following selected reference, caused pull-in range
Holdover Status Holdover History available: Device Holdover History tracking current active reference Holdover History available: Device Holdover History based last available history Holdover History available applicable
STC5230
T4_Accu_Flush, 0x55
Address 0x55 Bit7 Bit6 Bit5 Bit4 used Bit3 Bit2 Bit1 Bit0 flush
Writing this register will perform flush accumulated history. value zero determines which histories flushed. Flush reset long term history only; flush/reset both long term history device holdover history.
CLK0_Sel, 0x56 (R/W)
Address 0x56 Bit7 Bit6 Bit5 used Bit4 Bit3 Bit2 Bit1 Bit0
CLK0 Select
Selects disables CLK0 output. Default value:
0x56, bits CLK0 output Disabled 155.52MHz 125MHz Reserved
CLK1_Sel, 0x57 (R/W)
Address 0x57 Bit7 Bit6 Bit5 used Bit4 Bit3 Bit2 Bit1 CLK1 Select Bit0
Selects disables CLK1 output.
0x57, bits CLK1 output Disabled 19.44MHz
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
0x57, bits CLK1 output 38.88MHz 77.76MHz 51.84MHz 25MHz 50MHz 125MHz
STC5230
Default value:
CLK2_Sel, 0x58 (R/W)
Address 0x58 Bit7 Bit6 Bit5 used Bit4 Bit3 Bit2 Bit1 CLK2 Select Bit0
Selects disables CLK2 output.
0x58, bits CLK2 output Disabled 19.44MHz 38.88MHz 77.76MHz 51.84MHz 25MHz 50MHz 125MHz
Default value:
CLK3_Sel, 0x59 (R/W)
Address 0x59 Bit7 used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLK3 Select
Selects disables CLK3 output, sets pulse width. variable pulse width, width selected from times period 155.52MHz output (~6.43ns 399ns).
0x59, bits CLK3 8kHz output Disabled Pulse width cycles 155.52MHz duty cycle
Default value:
CLK4_Sel, 0x5a (R/W)
Address 0x5a Bit7 used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLK4 Select
Selects disables CLK4 output, sets pulse width. variable pulse width, width selected from times period 155.52MHz output (~6.43ns 399ns).
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
0x5a, bits CLK4 2kHz output Disabled Pulse width cycles 155.52MHz duty cycle
STC5230
Default value:
CLK5_Sel, 0x5b (R/W)
Address 0x5b Bit7 Bit6 Bit5 used Bit4 Bit3 Bit2 Bit1 Bit0
CLK5 Select
Selects disables CLK5 output.
0x5b, bits CLK5 output Disabled 44.736MHz (DS3) 34.368MHz (E3) Reserved
Default value:
CLK6_Sel, 0x5c (R/W)
Address 0x5c Bit7 Bit6 used Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLK6 Select
Selects disables CLK6 output.
0x5c, bits CLK6 output Disabled 2.048MHz 4.096MHz 8.192MHz 16.384MHz 32.768MHz Reserved 1.544MHz 3.088MHz 6.176MHz 12.352MHz 24.704MHz Reserved
Default value:
CLK7_Sel, 0x5d (R/W)
Address 0x5d Bit7 Bit6 Bit5 used Data Sheet TM102 Page Rev: Bit4 Bit3 Bit2 Bit1 Bit0
CLK7 Select Date: August 2007
Preliminary
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
Selects disables CLK7 output.
0x5d, bits CLK7 output Disabled 1.544MHz (T1) 2.048MHz (E1) Reserved
STC5230
Default value:
Intr_Event, 0x5e (R/W)
Address 0x5e Bit7 Event cross reference changed from nonactive active Bit6 Event cross reference changed from active nonactive Bit5 Event DPLL status changed Bit4 Event active reference changed auto selection mode Bit3 Event cross reference changed from nonactive active Bit2 Event cross reference changed from active nonactive Bit1 Event DPLL status changed Bit0 Event active reference changed auto selection mode Event reference changed from qualified disqualified
0x5f
Event reference changed from disqualified qualified
Interrupt event, event, event occurred. Interrupt apply reference inputs only. Interrupts cleared writing "1's" positions cleared (See General Register Operation, Clearing bits Interrupt Status Register section).
Intr_Enable, 0x60 (R/W)
Address 0x60 0x61 Bit7 Intr Enable Bit6 Intr Enable Bit5 Intr Enable Bit4 Intr Enable Bit3 Intr Enable Bit2 Intr Enable Bit1 Intr Enable Intr Enable Bit0 Intr Enable Intr Enable
Interrupt disable/enable, disable, enable. Default value:
T0_MS_PHE, 0x62
Address 0x62 0x63 0x64 used Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits Phase Delay Bits Phase Delay Bits Phase Delay
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
T0's phase delay round-trip cross-couple links from master slave then back master. complement. Resolution (12.5ns/64 0.2ns). Range from (-125us/2) (+125us/2). This value valid only when configured master mode.
STC5230
CLK8_Sel, 0x65 (R/W)
Address 0x65 Bit7 Bit6 Bit5 used Bit4 Bit3 Bit2 Bit1 Bit0
CLK8 Select
Selects disables CLK8 output. Default value:
0x65, bits CLK8 output Disabled 155.52MHz 125MHz Reserved
Bus_Loader_Status, 0x70
Address 0x70 Bit7 Bit6 Bit5 used Bit4 Bit3 Bit2 load complete Bit1 ready Bit0 Checksum status
load data mode been selected with pins LM0,1, this register Indicates loader's status. load complete ready checksum status when loading process complete load mode. when device ready load data load mode. data load successful (CRC-16 checksum over 10,496 bytes configuration data passes) load data mode. "checksum status" valid only after "load complete" been set.
Bus_Loader_Data, 0x71
Address 0x71 Bit7 Bit6 Bit5 Bit4 Data Bit3 Bit2 Bit1 Bit0
load data mode been selected with pins LM0,1, hardware firmware configuration data written this register.
Bus_Loader_Counter, 0x72
Address 0x72 0x73 used Bit7 Bit6 Bit5 Bit4 Bits Bits Bit3 Bit2 Bit1 Bit0
load data mode been selected with pins LM0,1, this register indicates number bytes that have been written Bus_Loader_Data register.
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
EEP_Loader_Checksum, 0x70
Address 0x70 Bit7 Bit6 Bit5 Bit4 used Bit3 Bit2 Bit1 Bit0 Checksum status
STC5230
EEPROM load data mode been selected with pins LM0,1, this register indicates checksum status loading process from external EEPROM. checksum status data load successful (ensured CRC-16 checksum encryption over 10,496 bytes configuration data) EEPROM load data mode.
EEP_Controller_Mode, 0x71 (R/W)
Address 0x71 Bit7 ready Bit6 Bit5 Bit4 used Bit3 Bit2 Bit1 Bit0 writable
EEPROM load data mode been selected with pins LM0,1, this register indicates readiness EEPROM controller used turn writing feature external EEPROM. ready writable when controller's page FIFO buffer ready used further read write data from/to external EEPROM. This used enable/disable writing feature external EEPROM. Write this makes EEROM writable. Writing this makes EEPROM writable.
EEP_Controller_Cmd, 0x72
Address 0x72 Bit7 Bit6 Bit5 used Bit4 Bit3 Bit2 Bit1 command Bit0
EEPROM load data mode been selected with pins LM0,1, this register used issue reset, write, read command EEPROM controller. command=0 command=1 command=2 command=3 reset clean page FIFO buffer. trig EEPROM controller write contents 64-byte page FIFO buffer certain page external EEPROM. trig EEPROM controller read copy 64-byte content certain page external EEPROM into page FIFO buffer. reserved
EEP_Controller_Page, 0x73
Address 0x73 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Page number
EEPROM load data mode been selected with pins LM0,1, this register used specify index page EEPROM further read write command. valid value from 163.
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
EEP_Controller_Data, 0x74 (R/W)
Address 0x74 Bit7 Bit6 Bit5 Bit4 data Bit3 Bit2 Bit1 Bit0
STC5230
EEPROM load data mode been selected with pins LM0,1, data read written from/to page FIFO buffer this register.
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet Noise Transfer Functions
User write T(0/4)_Bandwidth registers loop bandwidth DPLL each timing generator. noise transfer function filtering DPLL decided loop bandwidth. figure shows noise transfer functions loop bandwidths varying from 90mHz 107Hz.
STC5230
90mHz
Attenuation
Jitter Frequency
Figure Noise Transfer Functions
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet Application Notes
This section describes typical application STC5230 device. General section applies application variations.
STC5230
General
Power Ground Well-planned noise-minimizing power ground essential achieving best performance device. device requires 1.8V digital power 1.8V analog power input. digital 3.3V, LVTTL compatible, except pairs LVPECL clock outputs. desirable provide individual 0.1uF bypass capacitors, located close chip, each power input leads, subject board space layout constraints. power-up, desirable have 3.3V either lead coincident with, application both 1.8V supplies. Digital ground should provided continuous ground plane possible. separated analog ground plane recommended. Note: Un-used reference inputs must grounded.
3.3V digital power inputs
Vdd33 (10) MCLK
20MHz OCXO/ TCXO
STC5230
1.8V digital power inputs
Vdd18 (10) Digital ground
1.8V analog power inputs
AVdd18 (16) AVss
Analog ground Number pins
Figure Powers Grounds
external 20MHz TCXO/OCXO master oscillator connected MCLK pin.
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
Mechanical Specifications
STC5230
Controlling dimensions millimeters
Ordering Information
Part Number STC5230 STC5230-I Description Commercial Temperature Range Model Industrial Temperature Range Model
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet Revision History
following table summarizes significant changes made each revision. Additions reference current pages. Revision Initial issue Change Description Pages
STC5230
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet
STC5230
Preliminary
Data Sheet TM102
Page
Rev:
Date: August 2007
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Synchronous Clock SETS Data Sheet Functional Specification
STC5230
Information furnished Connor-Winfield believed accurate reliable. However, responsibility assumed Connor-Winfield use, infringements patents other rights third parties that result from use. Specifications subject change without notice.
more information, contact:
2111 Comprehensive Aurora, 60505, 630-851-4722 630-851-5040 www.conwin.com
Page Rev: Date: August 2007
Preliminary
Data Sheet TM102
Copyright Connor-Winfield Corp. Rights Reserved Specifications subject change without notice

STC5230 single chip solution timing source SDH, SONET, Synchronous Eth

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