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Synchronous Clock for SETS Data Sheet Description

STC5230

Synchronous Clock for SETS Data Sheet Description
STC5230
Features
Functional Specification
- For SDH SETS, SONET Stratum 3, 4E, 4 and SMC, and Synchronous Ethernet - Two timing generators, T0 and T4, for SETS - Complies with ITU-T G.813, Telcordia GR1244 and GR253 - Supports Master / Slave redundant application with the SyncLink cross-couple data links - Accepts 12 individual clock reference inputs - Reference clock inputs are automatically frequency detected each is monitored for quality - Support manual and automatic reference selection - T0 and T4 have independent reference lists and priority tables for automatic reference selection - Output 9 synchronized clocks - Could compensate the phase delay of the crosscouple links, in 0.1ns steps up to 409.5ns - Capable to trace the round-trip phase delay of the master / slave cross-couple links. - Hit-less reference and master / slave switching - Phase rebuild on re-lock and reference switches - Programmable loop bandwidth of each DPLL of the T0 and T4 timing generator, from 90mHz to 107Hz - Supports SPI bus interface - Field upgrade capability - IEEE 1149.1 JTAG boundary scan - Available in TQFP100 package
8 kHz 64 kHz 1.544 MHz 2.048 MHz 19.44 MHz 38.88 MHz 77.76 MHz 6.48 MHz 8.192 MHz 16.384 MHz 25 MHz 50 MHz 125 MHz
T0 Clock Synthesizer
8 kHz 2 kHz 1.544 / 3.088 / 6.176 / 12.352 / 24.704 MHz 2.048 / 4.096 / 8.192 / 16.384 / 32.768 MHz 44.736 MHz / 34.368 MHz LVPECL 155.52 / 125 MHz (2nd)
Activity & Frequency Offset Monitor T4 Active Ref Selector
STC5230
Phase Detector
Digital Filter
T4 Clock Synthesizer
20MHz
Serial Bus Interface
Control & Status Registers
IEEE 1194.1 JTAG
Figure 1: Functional Block Diagram
Preliminary
Data Sheet #: TM102
Page 1 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet Table of Contents
STC5230
Preliminary
Data Sheet #: TM102
Page 2 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet Table of Figures
Figure 1: Functional Block Diagram ......................................................... 1 Figure 2: Operating mode transition in automatic reference selection (Master mode).................. 14 Figure 3: Activity Monitor ................................................................ 15 Figure 4: Reference Qualification Scheme................................................... 16 Figure 5: Output Clocks................................................................. 17 Figure 6: T0 clock output Phase Alignment.................................................. 17 Figure 7: Master / Slave Pair .............................................................. 18 Figure 8: T0 CLK0-6, 8 Phase Alignment and Master / Slave skew Control ........................... 18 Figure 9: T4 CLK7 Master / Slave Skew Control............................................... 19 Figure 10: EEPROM Configuration ........................................................ 20 Figure 11: Serial Bus Timing, Read access .................................................. 22 Figure 12: Serial Bus Timing, Write access.................................................. 22 Figure 13: Noise Transfer Functions ....................................................... 43 Figure 14: Powers and Grounds .......................................................... 44
STC5230
Preliminary
Data Sheet #: TM102
Page 3 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet STC5230 Pin Diagram (Top View)
STC5230
Vdd33 LM0 Vss TRST TCK Vdd18
AVss MCLK PNC
Connor-Winfield STC5230
Page 4 of 48 Rev: P01
Note: Pins labeled "Test Pin" must be grounded.
Preliminary
Data Sheet #: TM102
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet STC5230 Pin Description
All I / O is LVCMOS, except for CLK0 and CLK8, which are LVPECL.
STC5230
Table 1: Pin Description
Pin Name Vdd33 Pin # 6, 22, 31, 44, 59, 61, 69, 80, 87, 97 9, 18, 27, 38, 47, 53, 60, 65, 84, 92 3, 13, 15, 20, 29, 35, 41, 56, 64, 67, 71, 78, 82, 88, 95 1, 76 75, 100 94 93 91 90 89 30 99 45 46 50 51 37 36 34 33 32 2 4 5 8 10 12 I I I I O I I I I I O I / O I / O I / O I / O O I I I I I I I / O 3.3V power input Description
Vdd18
1.8V power input
Digital ground
1.8V analog power input Analog ground JTAG boundary scan reset, active low JTAG boundary scan clock JTAG boundary scan mode selection JTAG boundary scan data input JTAG boundary scan data output Active low to reset the chip Master clock input, 20 MHz SPI bus chip select (CS) SPI bus clock input (SCLK) SPI bus data input (SDI) SPI bus data output (SDO) Optional external EEPROM SO Optional external EEPROM SI Optional external EEPROM SCK Optional external EEPROM CS event interrupt Reference input 1 Reference input 2 Reference input 3 Reference input 4 Reference input 5 Reference input 6 Page 5 of 48 Rev: P01 Date: August 22, 2007
Preliminary
Data Sheet #: TM102
Synchronous Clock for SETS Data Sheet
Table 1: Pin Description
STC5230
No connection. Pins can be left open, floating, tied up, or grounded Test pins, must be grounded for normal operation
Note 1: CLK0 and CLK8, which are LVPECL
Preliminary
Data Sheet #: TM102
Page 6 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet Absolute Maximum Ratings
Table 2: Absolute Maximum Ratings
Symbol Vdd33 Vdd18 AVdd18 VIN TSTG Parameter Logic power supply voltage, 3.3V Logic power supply voltage, 1.8V Analog power supply voltage, 1.8V Logic input voltage Storage Temperature Min. -0.5 -0.5 -0.5 -0.5 -65 Max 4.5 2.5 2.5 5.5 150 Units volts volts volts volts C Notes 2 2 2 2 2
STC5230
Note 2: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.
Operating Conditions and Electrical Characteristics
Table 3: Recommended Operating Conditions and Electrical Characteristics
Preliminary
Data Sheet #: TM102
Page 7 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Table 3: Recommended Operating Conditions and Electrical Characteristics
Symbol Voh Vol Vod LVPECL Parameter Output voltage high Output voltage low Output differential voltage Min. Vdd33 1.11 Vdd33 2.0 0.8 Nominal Max. Vdd33 0.67 Vdd33 1.4 2.66 Units Volts Volts Volts 4 Notes
STC5230
Preliminary
Data Sheet #: TM102
Page 8 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet Register Map
Table 4: Register Map
STC5230
0x31 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d
Preliminary
Data Sheet #: TM102
Page 9 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Table 4: Register Map
STC5230
0x4e 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x60 0x62 0x65
Preliminary
Data Sheet #: TM102
Page 10 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet General Description
STC5230
Preliminary
Data Sheet #: TM102
Page 11 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet Detailed Description
Chip Master Clock Input
STC5230
Operating Mode Details
Functional smooth clock outSTC5230 is designed to provide Specification puts to the downstream devices, even under the change of operating mode or reference switch. Both the phase and frequency transition will be continuous. The transfer into the self-timing mode (freerun and holdover) is designed to be free of frequency bump. A frequency ramp control limits the rate of frequency change when transferring in and out of self-timing mode.
Rev: P01 Date: August 22, 2007
Operating Mode General Description
Preliminary
Data Sheet #: TM102
Page 12 of 48
Synchronous Clock for SETS Data Sheet
STC5230
Operating Mode Transition Details
Rev: P01 Date: August 22, 2007
Preliminary
Data Sheet #: TM102
Page 13 of 48
Synchronous Clock for SETS Data Sheet
STC5230
Freerun
No Reference Available and HO not Available
Any Reference Available
Locking
Switch to a new active reference
Frequency Locked Locked Synchronized No Reference Available and HO Available Any Reference Available
Holdover
Figure 2: Operating mode transition in automatic reference selection (Master mode)
History Accumulation Details
Phase-Locked Loop Status Details
Rev: P01 Date: August 22, 2007
Preliminary
Data Sheet #: TM102
Page 14 of 48
Synchronous Clock for SETS Data Sheet
Data Sheet #: TM102
STC5230
Reference Input Monitoring and QualifiFunctional Specification cation
Fill Observation Window, 1ms ~ 16ms
Frequency Detector
Pulse Monitor
Leaky Bucket Accumulator
Alarm Assert
Alarm De-Assert
Leak Observation Window, 1~16 x Fill Observation Window
Rev: P01 Date: August 22, 2007
Preliminary
Page 15 of 48
Synchronous Clock for SETS Data Sheet
STC5230
Active Reference Selection
Activity Not Good Activity Alarm Asserted Activity Alarm Asserted
Activity Alarm De-Asserted
Within Offset Qualification Range for more than Qualification Time
Activity Good
Qualified
Out of Disqualification Range
Figure 4: Reference Qualification Scheme
Preliminary
Data Sheet #: TM102
Page 16 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
STC5230
Output Clocks
The clock output section includes 4 timing generators, an APLL, and four dividers, and generates eight synchronized clocks, as shown in figure 5.
T0 DPLL Clk Synthesizer Clk0 APLL Divider 155.52 / 125MHz Clk1 19.44 / 38.88 / 77.76 / 51.84 / 25 / 50 / 125 MHz
Clk2 19.44 / 38.88 / 77.76 / 51.84 / 25 / 50 / 125 MHz Clk3 8 kHz Divider Divider Clk4 Divider Clk8 2 kHz 155.52 / 125MHz
Clk Synthesizer Clk Synthesizer
T4 DPLL
Clk7 Clk Synthesizer
T1, E1
8kHz 38.88MHz 77.76MHz T1 / E1 T3 / E3
Figure 6: T0 clock output Phase Alignment
Preliminary
Data Sheet #: TM102
Page 17 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Master / Slave Configuration
STC5230
T0 PLL
T4 PLL
STC5230
Master T0 Clock Synthesizer
8kHz 38.88MHz 77.76MHz
STC5230
T1 / E1 T3 / E3 Programmable compensation from 0 to 409.5 ns 2kHz
Slave T0 Clock Synthesizer
8kHz 38.88MHz 77.76MHz
STC5230
Rev: P01 Date: August 22, 2007
Master / Slave Operation
While in the slave configuration, the operation is anal-
Preliminary
Data Sheet #: TM102
Page 18 of 48
Synchronous Clock for SETS Data Sheet
Master T4 Clock Synthesizer
STC5230
Functional Specification
Event Interrupts
Field Upgrade Feature
The initialization of registers and DPLL detailed behavior is defined by the hardware and firmware configuration data. Following any device reset, either via power-up or operation of the reset pin, the device needs to be loaded with the configuration data. This data may be loaded from the internal ROM (programmed with factory default data), an optional external EEPROM, or from the bus interface. Externally supplied data provides the option to accept future field upgrades. For external data loading, the manufacturer may provide the configuration data per a specific customer agreement. Load mode configuration pins The load mode configuration pins LM0 and LM1 determine the configuration data pump method, as shown in table 5:
STC5230
Programmable compensation from 0 to 409.5 ns
Slave T4 Clock Synthesizer
STC5230 Figure 9: T4 CLK7 Master / Slave Skew Control
Preliminary
Data Sheet #: TM102
Page 19 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
STC5230
Table 5: Load Mode Configuration Pins
LM1, LM0 0, 0 0, 1 1, 0 1, 1 Description ROM load mode Bus load mode EEPROM load mode Reserved - do not use
Table 6: Compatible EEPROMs
Manufacturer ATMEL Part Number AT25128A
EEPROM
ATMEL AT25128A
SCK SI SO
STC5230
Both WP and HOLD have to be tied high
Figure 10: EEPROM Configuration In the bus load mode, the configuration data is loaded from the SPI bus interface by the application, using the device bus load register interface. Data is provided to the customer per an agreement with the manufacturer. The load procedure is described in the following section. In the EEPROM load mode, an EEPROM loader will load the configuration data from an optional external EEPROM. Data will be provided by the manufacturer per an agreement with the customer. The configuration data may be read from or write to the external EEPROM via the SPI bus interface. When the EEPROM load mode is selected, data loading occurs automatically immediately following a
Preliminary
Data Sheet #: TM102
Page 20 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
STC5230
Functional Specification
Preliminary
Data Sheet #: TM102
Page 21 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Processor Interface Descriptions
tCS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tCSHLD 15 16 tCSMIN tCSTRI
STC5230
tDs tDh A6
tCH A4 A3
tCL A2 A1 A0
1 tDHLD D7
tDRDY
Figure 11: Serial Bus Timing, Read access
tDs tDh A6
tCH A4 A3
tCL A2 A1 A0
Figure 12: Serial Bus Timing, Write access
Preliminary
Data Sheet #: TM102
Page 22 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Table 7: Serial Bus Timing
Symbol tCS tCH tCL tDs tDh tDRDY tDHLD tCSHLD tCSTRI tCSMIN Description CS low to SCLK high SCLK high time SCLK low time Data setup time Data hold time Data ready Data hold Chip select hold Chip select to data tri-state Minimum delay between successive accesses 50 3 30 5 Min 10 25 25 10 10 7 Max Unit ns ns ns ns ns ns ns ns ns ns
STC5230
Preliminary
Data Sheet #: TM102
Page 23 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet Register Descriptions and Operation
General Register Operation
STC5230
Address 0x00 0x01 Bit7 Bit6 Bit5 Bit4 0x30 0x52 Bit3 Bit2 Bit1 Bit0
Address 0x02 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Revision Number
Address 0x03 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Sub-Revision Number
Address 0x04 Bit7 Bit6 Bit5 Not used Bit4 Bit3 Bit2 Bit1 T4 M / S Bit0 T0 M / S
Preliminary
Data Sheet #: TM102
Page 24 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Address 0x05 0x06 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
STC5230
Adjust T0 slave phase from 0 ~ 409.5 ns in 0.1 ns steps, lower 8 bits Not used Adjust T0 slave phase from 0 ~ 409.5 ns in 0.1 ns steps, upper 4 bits
The T0 slave phase may be adjusted 0 to 409.5 ns relative to the cross couple input with 0.1 ns resolution. This is a 12 bit register, split across address 0x05 and 0x06. Default value: 0
Address 0x07 0x08 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Adjust T4 slave phase from 0 ~ 409.5 ns in 0.1 ns steps, lower 8 bits Not used Adjust T4 slave phase from 0 ~ 409.5 ns in 0.1 ns steps, upper 4 bits
The T4 slave phase may be adjusted 0 to 409.5 ns relative to the cross couple input with 0.1 ns resolution. This is a 12 bit register, split across address 0x07 and 0x08. Default value: 0
Address 0x09 Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Address 0x0a Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Address 0x0b Bit7 Not used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Leaky bucket size, 0 ~ 63
Sets the leaky bucket size for the reference activity monitor. Bucket size equal to 0 will set the leaky bucket active monitor off, which will not assert activity alarm. Otherwise, the bucket size must be greater than or equal to the alarm assert value. Invalid values will not be written to the register.
Preliminary
Data Sheet #: TM102
Page 25 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Default value: 20
STC5230
Address 0x0c Bit7 Not used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Leaky bucket alarm assert threshold, 1 ~ 63
Sets the leaky bucket alarm assert threshold for the reference activity monitor. The alarm assert threshold value must be greater than the de-assert threshold value and less than or equal to the bucket size value. Invalid values will not be written to the register. Default value: 15
Address 0x0d Bit7 Not used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Leaky bucket alarm de-assert threshold, 0 ~ 62
Sets the leaky bucket alarm de-assert threshold for the reference activity monitor. The de-assert threshold value must be less than the assert threshold value. Invalid values will not be written to the register. Default value: 10
Address 0x0e 0x0f Not used Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Lower 8 bits Upper 3 bits
Address 0x10 0x11 Not used Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Lower 8 bits Upper 2 bits
Address 0x12 0x13 Not used Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Lower 8 bits Upper 2 bits
Preliminary
Data Sheet #: TM102
Page 26 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Address 0x14 Bit7 Not used Bit6 Bit5 Bit4 Bit3 0 ~ 63 s Bit2 Bit1 Bit0
STC5230
Reference qualification timer, from 0 to 63 s. Default value: 10
Address 0x15 Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1 ~ 12 (0x1 ~ 0xc)
Determines which reference data is displayed in register 0x16 and 0x17. Valid values from 1 to 12. Invalid values will not be written to the register. Default value: 1
Address 0x16 0x17 Reference frequency Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Lower 8 bits of frequency offset Upper 4 bits of frequency offset
0x17, bits 7 ~ 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Frequency No signal 8 kHz 64 kHz 1.544 MHz 2.048 MHz 19.44 MHz 38.88 MHz 77.76 MHz 6.48MHz 8.192MHz 16.384MHz 25 MHz 50 MHz 125 MHz Unknown Reserved
Preliminary
Data Sheet #: TM102
Page 27 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Address 0x18 0x19 Bit7 Ref 8 Not used Bit6 Ref 7 Bit5 Ref 6 Bit4 Ref 5 Bit3 Ref 4 Ref 12 Bit2 Ref 3 Ref 11 Bit1 Ref 2 Ref 10 Bit0 Ref 1 Ref 9
STC5230
Address 0x1a 0x1b Bit7 Ref 8 Bit6 Ref 7 Not used Bit5 Ref 6 Bit4 Ref 5 Bit3 Ref 4 Ref 12 Bit2 Ref 3 Ref 11 Bit1 Ref 2 Ref 10 Bit0 Ref 1 Ref 9
Bit1 Not used
Default value: 0
Address 0x1d Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 Bandwidth select Bit1 Bit0
Sets the T0 loop bandwidth:
0x1d, bits 4 ~ 0 0 1 2 3 4 5 Bandwidth, Hz 107 50 24 12 5.9 2.9
Preliminary
Data Sheet #: TM102
Page 28 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
0x1d, bits 4 ~ 0 6 7 8 9 10 31 ~ 11 Bandwidth, Hz 1.5 .73 0.37 0.18 0.09 Reserved
STC5230
Default value: 6
Address 0x1e Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 Selection Bit1 Bit0
Bit 3 ~ Bit 0 0 1 ~ 12 13 14, 15 Freerun Sync with Ref 1 ~ Ref 12 Holdover Reserved Selection
Address 0x1f Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 Selection Bit1 Bit0
Selects the active reference for T0 in manual reference select mode.
Bit 3 ~ Bit 0 0 1 ~ 12 13 14, 15 Freerun Sync with Ref 1 ~ Ref 12 Holdover Reserved Selection
Default value: 0
Address 0x20 0x21 0x22 0x23 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits 0 - 7 of 32 bit Device Holdover History Bits 8 - 15 of 32 bit Device Holdover History Bits 16 - 23 of 32 bit Device Holdover History Bits 24 - 31 of 32 bit Device Holdover History
Preliminary
Data Sheet #: TM102
Page 29 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Address 0x24 0x25 0x26 0x27 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
STC5230
Bits 0 - 7 of 32 bit Long Term History Bits 8 - 15 of 32 bit Long Term History Bits 16 - 23 of 32 bit Long Term History Bits 24 - 31 of 32 bit Long Term History
Address 0x28 0x29 0x2a 0x2b Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits 0 - 7 of 32 bit Short Term History Bits 8 - 15 of 32 bit Short Term History Bits 16 - 23 of 32 bit Short Term History Bits 24 - 31 of 32 bit Short Term History
Address 0x2c 0x2d 0x2e 0x2f Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits 0 - 7 of 32 bit User Holdover History Bits 8 - 15 of 32 bit User Holdover History Bits 16 - 23 of 32 bit User Holdover History Bits 24 - 31 of 32 bit User Holdover History
Address 0x30 Bit7 Not used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Long Term History Bandwidth
Short Term History Bandwidth
Ramp control
Holdover bandwidth and ramp controls for T0:
Long Term History -3dB Bandwidth 9.7 mHz 4.9 mHz 2.4 mHz 1.2 mHz 0.61 mHz 0.30 mHz
0x30, bits 6 ~ 4 000 001 010 011 100 101
Preliminary
Data Sheet #: TM102
Page 30 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Short Term History -3dB Bandwidth 2.5 Hz 1.24 Hz 0.62 Hz 0.31 Hz
STC5230
0x30, bits 3 ~ 2 00 01 10 11
0x30, bits 1 ~ 0 00 01 10 11
Ramp control No Control 1 ppm / s 1.5 ppm / s 2 ppm / s
Default value: 0x27 (2.4mHz 1.24Hz 2ppm / s)
Address 0x31 0x32 0x33 0x34 0x35 0x36 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Ref 2 Priority Ref 4 Priority Ref 6 Priority Ref 8 Priority Ref 10 Priority Ref 12 Priority
Ref 1 Priority Ref 3 Priority Ref 5 Priority Ref 7 Priority Ref 9 Priority Ref 11 Priority
Reference priority for automatic reference selection mode. Lower values have higher priority:
0x31 - 0x36, 4 bits 0000 0001 ~ 1111 Reference Priority Disable reference 1 ~ 15
Default value: 0
SYNC LOS LOL OOP
Indicates synchronization has been achieved Loss of signal of the active reference Loss of lock (Failure to achieve or maintain lock) Out of pull-in range
Data Sheet #: TM102 Page 31 of 48 Rev: P01 Date: August 22, 2007
Preliminary
Synchronous Clock for SETS Data Sheet
AHR HHA SAP Active Holdover History Ready Holdover History Available Indicates the output clocks stop following the selected reference, caused by out of pull-in range
HHA 1 1 0 0 AHR 1 0 0 1 Holdover Status Holdover History available: Device Holdover History tracking on the current active reference Holdover History available: Device Holdover History based on last available history Holdover History not available Not applicable
STC5230
Address 0x38 Bit7 Bit6 Bit5 Bit4 Not used Bit3 Bit2 Bit1 Bit0 HO flush
Bit1 Not used
Default value: 0
Address 0x3a Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 Bandwidth select Bit1 Bit0
Sets the T4 loop bandwidth:
0x3a, bits 4 ~ 0 0 1 Bandwidth, Hz 107 50 Page 32 of 48 Rev: P01 Date: August 22, 2007
Preliminary
Data Sheet #: TM102
Synchronous Clock for SETS Data Sheet
0x3a, bits 4 ~ 0 2 3 4 5 6 7 8 9 10 31 ~ 11 Bandwidth, Hz 24 12 5.9 2.9 1.5 .73 0.37 0.18 0.09 Reserved
STC5230
Default value: 0
Address 0x3b Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 Selection Bit1 Bit0
Indicates the automatically selected active reference for T4. (Data valid in automatic mode only)
Bit 3 ~ Bit 0 0 1 ~ 12 13 14, 15 Freerun Sync with Ref 1 ~ Ref 12 Holdover Reserved Selection
Address 0x3c Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 Selection Bit1 Bit0
Selects the active reference for T4 in manual reference select mode. Default value: 0
Bit 3 ~ Bit 0 0 1 ~ 12 13 14 15 Freerun Sync with Ref 1 ~ Ref 12 Holdover Reserved Lock on T0 output Selection
Address 0x3d 0x3e 0x3f 0x40 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits 0 - 7 of 32 bit Device Holdover History Bits 8 - 15 of 32 bit Device Holdover History Bits 16 - 23 of 32 bit Device Holdover History Bits 24 - 31 of 32 bit Device Holdover History Data Sheet #: TM102 Page 33 of 48 Rev: P01 Date: August 22, 2007
Preliminary
Synchronous Clock for SETS Data Sheet
STC5230
Address 0x41 0x42 0x43 0x44 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits 0 - 7 of 32 bit Long Term History Bits 8 - 15 of 32 bit Long Term History Bits 16 - 23 of 32 bit Long Term History Bits 24 - 31 of 32 bit Long Term History
Address 0x45 0x46 0x47 0x48 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits 0 - 7 of 32 bit Short Term History Bits 8 - 15 of 32 bit Short Term History Bits 16 - 23 of 32 bit Short Term History Bits 24 - 31 of 32 bit Short Term History
Address 0x49 0x4a 0x4b 0x4c Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits 0 - 7 of 32 bit User Holdover History Bits 8 - 15 of 32 bit User Holdover History Bits 16 - 23 of 32 bit User Holdover History Bits 24 - 31 of 32 bit User Holdover History
Address 0x4d Bit7 Not used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Long Term History bandwidth
Short Term History bandwidth
Ramp control
Holdover bandwidth and ramp controls for T4:
Long Term History -3dB Bandwidth 9.7 mHz 4.9 mHz 2.4 mHz Page 34 of 48 Rev: P01 Date: August 22, 2007
0x4d, bits 6 ~ 4 000 001 010
Preliminary
Data Sheet #: TM102
Synchronous Clock for SETS Data Sheet
0x4d, bits 6 ~ 4 011 100 101 Long Term History -3dB Bandwidth 1.2 mHz 0.61 mHz 0.30 mHz Short Term History -3dB Bandwidth 2.5 Hz 1.24 Hz 0.62 Hz 0.31 Hz Ramp control No Control 1 ppm / s 1.5 ppm / s 2 ppm / s
STC5230
0x4d, bits 3 ~ 2 00 01 10 11 0x4d, bits 1 ~ 0 00 01 10 11
Default value: 0x27 (2.4mHz 1.24Hz 2ppm / s)
Address 0x4e 0x4f 0x50 0x51 0x52 0x53 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Ref 2 Priority Ref 4 Priority Ref 6 Priority Ref 8 Priority Ref 10 Priority Ref 12 Priority
Ref 1 Priority Ref 3 Priority Ref 5 Priority Ref 7 Priority Ref 9 Priority Ref 11 Priority
Reference priority for automatic reference selection mode. Lower values have higher priority:
0x4e - 0x53, 4 bits 0000 0001 ~ 1111 Reference Priority Disable reference 1 ~ 15
Default value: 0
Preliminary
Data Sheet #: TM102
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
SYNC LOS LOL OOP AHR HHA SAP Indicates synchronization has been achieved Loss of signal of the active reference Loss of lock (Failure to achieve or maintain lock) Out of pull-in range Active Holdover History Ready Holdover History Available Indicates the output clocks stop following the selected reference, caused by out of pull-in range
HHA 1 1 0 0 AHR 1 0 0 1 Holdover Status Holdover History available: Device Holdover History tracking on the current active reference Holdover History available: Device Holdover History based on last available history Holdover History not available Not applicable
STC5230
Address 0x55 Bit7 Bit6 Bit5 Bit4 Not used Bit3 Bit2 Bit1 Bit0 HO flush
Address 0x56 Bit7 Bit6 Bit5 Not used Bit4 Bit3 Bit2 Bit1 Bit0
CLK0 Select
Selects or disables the CLK0 output. Default value: 0
0x56, bits 1 ~ 0 0 1 2 3 CLK0 output Disabled 155.52MHz 125MHz Reserved
Address 0x57 Bit7 Bit6 Bit5 Not used Bit4 Bit3 Bit2 Bit1 CLK1 Select Bit0
Selects or disables the CLK1 output.
0x57, bits 2 ~ 0 0 1 CLK1 output Disabled 19.44MHz
Preliminary
Data Sheet #: TM102
Page 36 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
0x57, bits 2 ~ 0 2 3 4 5 6 7 CLK1 output 38.88MHz 77.76MHz 51.84MHz 25MHz 50MHz 125MHz
STC5230
Default value: 1
Address 0x58 Bit7 Bit6 Bit5 Not used Bit4 Bit3 Bit2 Bit1 CLK2 Select Bit0
Selects or disables the CLK2 output.
0x58, bits 1 ~ 0 0 1 2 3 4 5 6 7 CLK2 output Disabled 19.44MHz 38.88MHz 77.76MHz 51.84MHz 25MHz 50MHz 125MHz
Default value: 2
Address 0x59 Bit7 Not used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLK3 Select
Selects or disables the CLK3 output, and sets the pulse width. In variable pulse width, the width may be selected from 1 to 62 times the period of the 155.52MHz output (~6.43ns to 399ns).
Default value: 63
Address 0x5a Bit7 Not used Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLK4 Select
Selects or disables the CLK4 output, and sets the pulse width. In variable pulse width, the width may be selected from 1 to 62 times the period of the 155.52MHz output (~6.43ns to 399ns).
Preliminary
Data Sheet #: TM102
Page 37 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
STC5230
Default value: 63
Address 0x5b Bit7 Bit6 Bit5 Not used Bit4 Bit3 Bit2 Bit1 Bit0
CLK5 Select
Selects or disables the CLK5 output.
0x5b, bits 1 ~ 0 0 1 2 3 CLK5 output Disabled 44.736MHz (DS3) 34.368MHz (E3) Reserved
Default value: 2
Address 0x5c Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLK6 Select
Selects or disables the CLK6 output.
0x5c, bits 3 ~ 0 0 1 2 3 4 5 6, 7, 8 9 10 11 12 13 14, 15 CLK6 output Disabled 2.048MHz 4.096MHz 8.192MHz 16.384MHz 32.768MHz Reserved 1.544MHz 3.088MHz 6.176MHz 12.352MHz 24.704MHz Reserved
Default value: 1
Address 0x5d Bit7 Bit6 Bit5 Not used Data Sheet #: TM102 Page 38 of 48 Rev: P01 Bit4 Bit3 Bit2 Bit1 Bit0
CLK7 Select Date: August 22, 2007
Preliminary
Synchronous Clock for SETS Data Sheet
Selects or disables the CLK7 output.
0x5d, bits 1 ~ 0 0 1 2 3 CLK7 output Disabled 1.544MHz (T1) 2.048MHz (E1) Reserved
STC5230
Default value: 2
Address 0x5e Bit7 Event 7: T4 cross reference changed from nonactive to active Bit6 Event 6: T4 cross reference changed from active to nonactive Bit5 Event 5: T4 DPLL status changed Bit4 Event 4: T4 active reference changed in auto selection mode Bit3 Event 3: T0 cross reference changed from nonactive to active Bit2 Event 2: T0 cross reference changed from active to nonactive Bit1 Event 1: T0 DPLL status changed Bit0 Event 0: T0 active reference changed in auto selection mode Event 8: Any reference changed from qualified to disqualified
Event 9: Any reference changed from disqualified to qualified
Address 0x60 0x61 Bit7 Intr 7 Enable Bit6 Intr 6 Enable Bit5 Intr 5 Enable Bit4 Intr 4 Enable Bit3 Intr 3 Enable Bit2 Intr 2 Enable Bit1 Intr 1 Enable Intr 9 Enable Bit0 Intr 0 Enable Intr 8 Enable
Address 0x62 0x63 0x64 Not used Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bits 0 - 7 of 20 bit Phase Delay Bits 8 - 15 of 20 bit Phase Delay Bits 16 - 19 of 20 bit Phase Delay
Preliminary
Data Sheet #: TM102
Page 39 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
STC5230
Address 0x65 Bit7 Bit6 Bit5 Not used Bit4 Bit3 Bit2 Bit1 Bit0
CLK8 Select
Selects or disables the CLK8 output. Default value: 0
0x65, bits 1 ~ 0 0 1 2 3 CLK8 output Disabled 155.52MHz 125MHz Reserved
Address 0x70 Bit7 Bit6 Bit5 Not used Bit4 Bit3 Bit2 load complete Bit1 bus ready Bit0 Checksum status
Address 0x71 Bit7 Bit6 Bit5 Bit4 Data Bit3 Bit2 Bit1 Bit0
If bus load data mode has been selected with pins LM0, 1, the hardware and firmware configuration data is written to this register.
Address 0x72 0x73 Not used Bit7 Bit6 Bit5 Bit4 Bits 0 -7 Bits 8 - 13 Bit3 Bit2 Bit1 Bit0
Preliminary
Data Sheet #: TM102
Page 40 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Address 0x70 Bit7 Bit6 Bit5 Bit4 Not used Bit3 Bit2 Bit1 Bit0 Checksum status
STC5230
If EEPROM load data mode has been selected with pins LM0, 1, this register indicates the checksum status of the loading process from the external EEPROM. checksum status Set to 1 if the data load is successful (ensured by the CRC-16 checksum encryption over the 10, 496 bytes of configuration data) in the EEPROM load data mode.
Address 0x71 Bit7 ready Bit6 Bit5 Bit4 no used Bit3 Bit2 Bit1 Bit0 writable
Address 0x72 Bit7 Bit6 Bit5 no used Bit4 Bit3 Bit2 Bit1 command Bit0
Address 0x73 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Page number
If EEPROM load data mode has been selected with pins LM0, 1, this register is used to specify the index of the page of the EEPROM for the further read and write command. The valid value is from 0 to 163.
Preliminary
Data Sheet #: TM102
Page 41 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Address 0x74 Bit7 Bit6 Bit5 Bit4 data Bit3 Bit2 Bit1 Bit0
STC5230
If EEPROM load data mode has been selected with pins LM0, 1, the data is read and written from / to the page FIFO buffer via this register.
Preliminary
Data Sheet #: TM102
Page 42 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet Noise Transfer Functions
STC5230
-3 dB 90mHz
-10 dB
180 mHz 370 mHz
Attenuation
-20 dB
730 mHz 1.5 Hz 2.9 Hz
-30 dB
5.9 Hz 12 Hz 24 Hz
-40 dB
50 Hz 107 Hz
-50 dB 10 mHz 100 mHz 1 Hz Jitter Frequency 10 Hz 100 Hz 1 kHz
Figure 13: Noise Transfer Functions
Preliminary
Data Sheet #: TM102
Page 43 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet Application Notes
This section describes typical application use of the STC5230 device. The General section applies to all application variations.
STC5230
General
Power and Ground Well-planned noise-minimizing power and ground are essential to achieving the best performance of the device. The device requires 3.3 and 1.8V digital power and 1.8V analog power input. All digital I / O is at 3.3V, LVTTL compatible, except of the two pairs of LVPECL clock outputs. It is desirable to provide individual 0.1uF bypass capacitors, located close to the chip, for each of the power input leads, subject to board space and layout constraints. On power-up, it is desirable to have the 3.3V either lead or be coincident with, but not lag the application of both 1.8V supplies. Digital ground should be provided by as continuous a ground plane as possible. A separated analog ground plane is recommended. Note: Un-used reference inputs must be grounded.
3.3V digital power inputs
Vdd33 (10) MCLK
20MHz OCXO / TCXO
STC5230
1.8V digital power inputs
Vdd18 (10) Digital ground
1.8V analog power inputs
AVdd18 (2) Vss (16) AVss (2)
Analog ground (x) Number of pins
Figure 14: Powers and Grounds
The external 20MHz TCXO / OCXO master oscillator is connected to the MCLK pin.
Preliminary
Data Sheet #: TM102
Page 44 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
Mechanical Specifications
STC5230
Controlling dimensions are in millimeters
Ordering Information
Part Number STC5230 STC5230-I Description Commercial Temperature Range Model Industrial Temperature Range Model
Preliminary
Data Sheet #: TM102
Page 45 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet Revision History
The following table summarizes significant changes made in each revision. Additions reference current pages. Revision P01 Initial issue Change Description Pages
STC5230
Preliminary
Data Sheet #: TM102
Page 46 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet
STC5230
Preliminary
Data Sheet #: TM102
Page 47 of 48
Rev: P01
Date: August 22, 2007
Synchronous Clock for SETS Data Sheet Functional Specification
STC5230
Information furnished by Connor-Winfield is believed to be accurate and reliable. However, no responsibility is assumed by Connor-Winfield for its use, nor for any infringements of patents or other rights of third parties that my result from its use. Specifications subject to change without notice.
For more information, contact:
2111 Comprehensive DR Aurora, IL. 60505, USA 630-851-4722 630-851-5040 FAX www.conwin.com
Page 48 of 48 Rev: P01 Date: August 22, 2007
Preliminary
Data Sheet #: TM102