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STC3500 INTEGRATED - STRATUM 3 TIMING SOURCE

OCXO / TCXO 12.8 MHz

STC3500 INTEGRATED - STRATUM 3 TIMING SOURCE
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Description
Features
· Complies with Telcordia GR-1244-CORE, GR-253-CORE, and ITU-T G.812 / G.813 · Supports Master / Slave operation · Supports Free Run, Locked, and Hold Over modes · Accepts 8 reference inputs from 8 kHz to 77.76 MHz and one 8 kHz cross reference · Continuous input reference quality monitoring · Input reference frequencies are automatically detected · Automatic or manual selection for active reference · Supports hardwire pins to select active reference · Four output signals: one selectable up to 155.52 MHz, one fixed at 8 kHz, one multiframe sync fixed at 2 kHz, and 1.544 MHz or 2.048 MHz BITS output · Output phase is adjustable in slave mode · Frequency ramp control during reference switching · Hit-less reference switching · Configurable bandwidth filter · Supports SPI and 8-bit parallel bus interface · IEEE 1149.1 JTAG boundary scan · Available in FBGA144 package
Functional Block Diagram
OCXO / TCXO 12.8 MHz
EEPROM 3
Reference Input Monitor
Control Mode
Reference Selection
Bulletin Page Revision Date
TM060 1 of 48 P06 22 NOV 04
Reference Priority, Revertivity and Mask Table
Bus Interface
STC3500
Table of Contents
How to read this document In the following sections, the intent is as follows: Detailed Description and Register Descriptions - "How the device works" Performance - This section provides terminology definitions and detailed data on how the chip performs Application Notes - "How to use the device" from an application perspective
Preliminary Data Sheet: TM060
Page 2 of 48
Rev: P06
Date: 11 / 22 / 04
STC3500 Ball Grid Diagram (Top View) Figure 1
Reset
R / W or SDI ALE or SCLK
Vdd2.5
RDY or SDO
Bmode
DACclk
Dmode
Vdd2.5
DACdin
E2scl
E2sda
DACld
Vdd2.5
Vdd3.3
AVdd2.5
Vdd3.3
Vdd2.5
AVdd2.5
Vdd2.5
Vdd3.3
Vdd2.5
Vdd3.3
Vdd2.5
Vdd3.3
Note: Pins indicated as "MNC" are mandatory no-connects. Pins indicated as "NC" may be left unconnected or may be grounded.
Preliminary Data Sheet: TM060
Page 3 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Pin Description
Table 1 Pin Name
Vdd2.5
A8, C4, E1, E10, H1, H5, H12 J7 E4, E6, E7, E9, H10, J3, L5, M10 A6, B2, B11, F5, F6, F7, F10, G2, G5, G6, G7, K7, K10, L1 E8, G3 E12, F2 L9 J8 M9 J10 L12 B10 B9 C3 A1 A2 B3 A3 B1 C1 A4 B4 A5 B5 B6 A7 B7 B8 J1
Description
2.5V Digital Power Supply
Vdd3.3
3.3V Digital Power Supply
Digital Ground
Preliminary Data Sheet: TM060
Page 4 of 48
Rev: P06
Date: 11 / 22 / 04
Pin Description
Table 1 continued Pin Name
Description
A10 A11 A12 C11 H2 J2 K2 K1 M1 M2 M3 M4 M5 M6 M7 M8 G12 J12 L11 K12 F1 F12 F11 E11 D11 B12 C12 D12 D1 D2 E2 G1, G4, L10, M11, M12
Preliminary Data Sheet: TM060
Page 5 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Absolute Maximum Ratings
Table 2 Symbol
Vdd2.5 Vdd3.3 AVdd2.5 VIN TSTG
Parameter
Logic power supply voltage, 2.5V Logic power supply voltage 3.3V Analog power supply voltage, 2.5V Logic input voltage, rel. to GND Storage Temperature
Minimum
Nominal
Maximum
3.0 4.0 4.0 Vdd3.3 + 0.5 110
Units
Volts Volts Volts Volts °C
Notes
Note 1: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.
Recommended Operating Conditions & Electrical Characteristics
Table 3 Symbol
Vdd2.5 Vdd3.3 AVdd2.5 VIH (3.3V) VIL (3.3V) VOH (3.3V) VOL (3.3V) VIL (PECL) VID (PECL) CIN THL TLH TRIP TRIN TA Icc (Vdd2.5) Icc (Vdd3.3) Pd
Parameter
Minimum
2.3 3.0 2.3 2.0 0.3 0.9Vdd3.3 0.86 1.49 0.3 10 10 0 -
Nominal
Maximum
2.7 3.6 2.7 Vdd3.3 + 0.3 0.8 0.4 2.125 2.72 Vdd3.3 10 5 5 70 500 200 50 2.0
Units
Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts pF nS nS nS nS °C mA mA mA W
Notes
VOH (PECL) High level input voltage (PECL inputs)
Icc (Avdd2.5) 2.5V analog supply current
Note 2: LVTTL compatible
Register Map
Table 4 Address
0x00 0x01 0x02 0x03 0x04 0x05
Reg Name
Description
Preliminary Data Sheet: TM060
Page 6 of 48
Rev: P06
Date: 11 / 22 / 04
Register Map continued
Table 4 Address
0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x30 0x31 0x32 0x33 0x36 0x37 0x38 0x39
Reg Name
Description
Maximum pull-in range in 0.1 ppm units Cross Reference activity and frequency Activities of 8 reference inputs In or out of pull-in range of 8 reference inputs Qualification of 8 reference inputs Availability mask for 8 reference inputs Availability of 8 reference inputs Reference reversion delay time, 0 - 255 minutes Local oscillator digital calibration in 0.05 ppm resolution Frame and multi-frame sync pulse width Digital Phase Locked Loop status Interrupt events Enable individual interrupt events Ref1 frequency offset in 0.2 ppm resolution Ref2 frequency offset in 0.2 ppm resolution Ref3 frequency offset in 0.2 ppm resolution Ref4 frequency offset in 0.2 ppm resolution Ref5 frequency offset in 0.2 ppm resolution Ref6 frequency offset in 0.2 ppm resolution Ref7 frequency offset in 0.2 ppm resolution Ref8 frequency offset in 0.2 ppm resolution Ref1 frequency and priority Ref2 frequency and priority Ref3 frequency and priority Ref4 frequency and priority Ref5 frequency and priority Ref6 frequency and priority Ref7 frequency and priority Ref8 frequency and priority Control and priority for designation of Free Run as a reference Sets policy for Hold Over history accumulation Save, restore, and flush commands for Hold Over History Indicates the time since entering the Hold Over state Configuration data write register Configuration data write counter, low byte Configuration data write counter, high byte Configuration data checksum pass / fail indicator Disables / Enables writing to the external EEPROM Page number for external EEPROM access Read / Write data for external EEPROM access
Read / Write command and ready indication register for external EEPROM Access R / W
Preliminary Data Sheet: TM060
Page 7 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Detailed Description
Preliminary Data Sheet: TM060
Page 8 of 48
Rev: P06
Date: 11 / 22 / 04
Detailed Description continued
Operating Modes: The STC3500 operates in either Free Run, locked, or Hold Over mode:
Preliminary Data Sheet: TM060
Page 9 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Detailed Description continued
Master / Slave Operation
Pairs of STC3500 devices may be operated in a master / slave configuration for added reliability. A typical configuration is shown below:
Master / Slave Configuration Figure 2
Ref In Xref
STC3500 1
Ref In
STC3500 2
Preliminary Data Sheet: TM060
Page 10 of 48
Rev: P06
Date: 11 / 22 / 04
Detailed Description continued
Control Modes
Hardware Reference Selection and Mode Control Table 5 Pin Sel3
Function Sel1
Free Run Locked Locked Locked Locked Locked Locked Locked Locked Hold Over Hold Over Hold Over Hold Over Hold Over Hold Over Hold Over
Reference
Preliminary Data Sheet: TM060
Page 11 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Detailed Description continued
Parallel Bus Timing, Read Access Figure 3
tCA tALE tAR
tRWs tRWh
tRDY tRC tCR
tCR tAs
Address
Read Data
Parallel Bus Timing, Write Access Figure 4
tCA tALE tAR
tRWs tRWh
tRDY tRC tCR
tCR tAs
Address
WriteData
Parallel Bus Timing Table 6 Symbol
Parameter
CS low to ALE low ALE low time ALE high to RDY low R / W setup time R / W hold time RDY low time RDY high to CS high CS to RDY active / tristate time Address setup time Address hold time Read data setup time Read data hold time Write data setup time Write data hold time
Minimum
Nominal
Maximum
Units
Notes
CA ALE AR RWs RWh RDY RC As Ah RDs RDh WDs WDh
Preliminary Data Sheet: TM060
Page 12 of 48
Rev: P06
Date: 11 / 22 / 04
Detailed Description continued
Serial Bus Timing, Read Access Figure 5
tRWs tRWh A0
tCH A2 A3
tDRDY
tDHLD D0
Serial Bus Timing, Write Access Figure 6
tRWs tRWh A0
tCH A2 A3
Serial Bus Timing Table 7 Symbol
Parameter
CS low to SCLK low SCLK high time SCLK low time Read / Write setup time Read / Write hold time Data ready Data hold Chip select to data tri-state Minimum delay between successive accesses
Minimum
Nominal
Maximum
Units
Notes
CS CH CL RWs RWh DRDY
DHLD CSTRI CSMIN
Preliminary Data Sheet: TM060
Page 13 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Detailed Description continued
Reference Input Quality Monitoring
Reference Input Selection, Frequencies, and Mode Selection
Preliminary Data Sheet: TM060
Page 14 of 48
Rev: P06
Date: 11 / 22 / 04
Detailed Description continued
The automatic reference selection is shown in the following state diagram:
Automatic Reference Selection Figure 7
Ref n returns, Ref m marked revertive
Ref n returns, Ref m marked non-revertive
Locked on Ref n
Loss of Ref n
Select & Lock on Ref m
The operational mode is according to the following state diagram:
Automatic Operational Mode Selection Figure 8
Reference Available (Select highest priority) Higher priority Ref return with prior reference marked revertive Locked Ref loss w / no good holdover history and no other available reference Ref Return Freerun Ref Return Holdover Ref Loss w / good holdover history and no alternate reference available Ref Loss w / alternate reference available
No available reference and no holdover history
Preliminary Data Sheet: TM060
Page 15 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Detailed Description continued
Output Signals and Frequency
Hold Over History Accumulation and Maintenance
To be provided.
Preliminary Data Sheet: TM060
Page 16 of 48
Rev: P06
Date: 11 / 22 / 04
Detailed Description continued
Interrupts
OCXO / TCXO Calibration
The OCXO / TCXO may be calibrated by writing a frequency offset v.s. nominal frequency into the Calibration register. This calibration is used by the synchronization software to create a frequency corrected from the actual OCXO / TCXO output by the value written to the Calibration register. See Register Descriptions and Operation section.
Preliminary Data Sheet: TM060
Page 17 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Register Descriptions and Operation
Low byte of chip ID: 0x12
High byte of chip ID: 0x30
Chip revision number: Chip revision number is subject to change.
Bandwidth, 0x03 (R / W) Bit 7 ~ Bit 4
Reserved
Bandwidth Selection in Hz: 0000 - 0101: 0.025 0110: 0.049 0111: 0.098 (Reset Default) 1000: 0.20 1001: 0.39 1010: 0.78 1011 - 1111: 1.6
Bits 3 - 0 select the phase lock loop bandwidth in Hertz. The reset default is .098 Hz.
Reserved
BITS Clock Output Frequency: 1: 1.544 MHz 0: 2.048 MHz (read only)
HM Ref: 1: Sel0-3 pin control of op mode / ref 0: Register control of op model / ref (read only)
Active Reference Selection: 1: Manual 0: Automatic Default: 1
Input Reference Frequency Selection: 1: Manual 0: Automatic Default: 0
Preliminary Data Sheet: TM060
Page 18 of 48
Rev: P06
Date: 11 / 22 / 04
Register Descriptions and Operation continued
Reserved
Master or Slave Mode 1: Master 0: Slave (read-only)
Free Run, Locked, or Hold Over: 0000: Free Run mode 0001: Locked on Ref1 0010: Locked on Ref2 0011: Locked on Ref3 0100: Locked on Ref4 0101: Locked on Ref5 0110: Locked on Ref6 0111: Locked on Ref7 1000: Locked on Ref8 1001 - 1111: Hold Over
Reserved
Xref signal / frequency 0000: No Signal 0001: 8 kHz 0100: 12.96 MHz 0101: 19.44 MHz 0110: 25.92 MHz 0111: 38.88 MHz 1000: 51.84 MHz 1001: 77.76 MHz 1010-111: Reserved
Indicates signal presence and auto-detected frequency for the Xref input.
ref8 activity 1: on 0: off
ref7 activity 1: on 0: off
ref6 activity 1: on 0: off
ref5 activity 1: on 0: off
ref4 activity 1: on 0: off
ref3 activity 1: on 0: off
ref2 activity 1: on 0: off
ref1 activity 1: on 0: off
Each bit indicates the presence of a signal for that reference.
Preliminary Data Sheet: TM060
Page 19 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Register Descriptions and Operation continued
ref8 sts 1: in range 0: out range
ref7 sts 1: in range 0: out range
ref6 sts 1: in range 0: out range
ref5 sts 1: in range 0: out range
ref4 sts 1: in range 0: out range
ref3 sts 1: in range 0: out range
ref2 sts 1: in range 0: out range
ref1 sts 1: in range 0: out range
ref8 qual: 1: avail. 0: not avail.
ref7 qual: 1: avail. 0: not avail.
ref6 qual: 1: avail. 0: not avail.
ref5 qual: 1: avail. 0: not avail.
ref4 qual: 1: avail. 0: not avail.
ref3 qual: 1: avail. 0: not avail.
ref2 qual: 1: avail. 0: not avail.
ref1 qual: 1: avail. 0: not avail.
ref8 mask: 1: avail. 0: not avail. Default: 0
ref7 mask: 1: avail. 0: not avail. Default: 0
ref6 mask: 1: avail. 0: not avail. Default: 0
ref5 mask: 1: avail. 0: not avail. Default: 0
ref4 mask: 1: avail. 0: not avail. Default: 0
ref3 mask: 1: avail. 0: not avail. Default: 0
ref2 mask: 1: avail. 0: not avail. Default: 0
ref1 mask: 1: avail. 0: not avail. Default: 0
ref8 avail: 1: avail. 0: not avail.
ref7 avail: 1: avail. 0: not avail.
ref6 avail: 1: avail. 0: not avail.
ref5 avail: 1: avail. 0: not avail.
ref4 avail: 1: avail. 0: not avail.
ref3 avail: 1: avail. 0: not avail.
ref2 avail: 1: avail. 0: not avail.
ref1 avail: 1: avail. 0: not
Preliminary Data Sheet: TM060
Page 20 of 48
Rev: P06
Date: 11 / 22 / 04
Register Descriptions and Operation continued
Calibration, 0x0f (R / W) Bit 7 ~ Bit 0
Reserved
Hold Over Build Complete 1: Hold Over history build complete 0: Hold Over history build not complete
Hold Over Available 1: Avail. 0: Not avail.
Locked 1: Locked 0: Not locked
Loss of Lock 1: Loss of Lock 0: No loss of lock
Loss of Signal 1: No activity on active reference 0: Active reference signal present
Preliminary Data Sheet: TM060
Page 21 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Register Descriptions and Operation continued
Loss of Lock
Loss of Signal
Active reference change
DPLL Mode status change
Xref Change from no activity to activity
Xref Change from activity to no activity
Any reference change from not available to available
Any reference change from available able to not available
Enable Interrupt event 7 1: Enable 0: Disable Default: 0
Enable Interrupt event 6 1: Enable 0: Disable Default: 0
Enable Interrupt event 5: 1: Enable 0: Disable Default: 0
Enable Interrupt event 4: 1: Enable 0: Disable Default: 0
Enable Interrupt event 3: 1: Enable 0: Disable Default: 0
Enable Interrupt event 2: 1: Enable 0: Disable Default: 0
Enable Interrupt event 1: 1: Enable 0: Disable Default: 0
Enable Interrupt event 0: 1: Enable 0: Disable Default: 0
Preliminary Data Sheet: TM060
Page 22 of 48
Rev: P06
Date: 11 / 22 / 04
Register Descriptions and Operation continued
Frequency 0000: None 0001: 8 kHz 0010: 1.544 MHz 0011: 2.048 MHz 0100: 12.96 MHz 0101: 19.44 MHz 0110: 25.92 MHz 0111: 38.88 MHz 1000: 51.84 MHz 1001: 77.76 MHz 1010-1111: Reserved
Revertivity 1: revertive 0: non-revertive Default: 0, non revertive
Priority 0: highest 7: lowest Default: 0
Enable / disable 1: enabled 2: disabled 0: Default, disabled
revertivity 1: revertive 0: non-revertive 0: Default, non-revertive
priority 0: highest 7: lowest 0: Default
Free Run may be treated like a reference. When it is enabled, Free Run will be entered when all references of higher priority are lost or masked. If / when a higher priority reference returns, it is switched if Free Run is set as "revertive". When disabled, Free Run will be entered only if manually selected, or all references fail and no Hold Over history is available. For equal priority value, Free Run will be treated as lower priority.
Reserved
Reference switch Hold Over History Policy 0: rebuild 1: continue
Bit 0 determines if Hold Over history is retained or rebuilt when a reference switch occurs. See Application Notes, Hold Over History Accumulation and Management section.
Preliminary Data Sheet: TM060
Page 23 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Register Descriptions and Operation continued
Reserved
Hold Over history commands 01: Save active history to backup history 10: Restore active history from backup 11: Flush the active history and accumulated register 00: No command
Bits 0-1 are written to save a Hold Over history to the backup history, restore the active Hold Over history from the backup, or flush the active history. The default value of the register is 00. The last command is latched and may be ready by the application. A flush does not affect the back up history. See Application Notes, Hold Over History Accumulation and Management section.
Indicates the time since entering the Hold Over state. From 0 to 255, one bit per hour. Zero in non-Hold Over state, stops at 255.
Cfgdata, 0x30 (R / W) Bit 7 ~ Bit 0
Configuration data write register Configuration data is written to this register. See Application Notes, Configuration Data section.
Configuration data write counter low byte Low order byte of configuration data write counter. See Application Notes, Configuration Data section. Initialized to zero on power-up / reset.
Configuration data write counter high byte High order byte of configuration data write counter. See Application Notes, Configuration Data section. Initialized to zero on power-up / reset.
Preliminary Data Sheet: TM060
Page 24 of 48
Rev: P06
Date: 11 / 22 / 04
Register Descriptions and Operation continued
Chksum, 0x33 (R) Bit 7 ~ Bit 1
Reserved
EEPROM write enable register. See Application Notes, General, Reading and Writing EEPROM Data section.
Reserved
EEPROM read / write command register. See Application Notes, General, Reading and Writing EEPROM Data section.
EEPROM read / write page number, 0x00 to 0x9f (0 - 159) EEPROM read / write page number register. EEPROM consists of 160 pages. See Application Notes, General, Reading and Writing EEPROM Data section.
EEPROM read / write FIFO data EEPROM read / write FIFO port register. EEPROM data is written to / read from here. See Application Notes, General, Reading and Writing EEPROM Data section.
Preliminary Data Sheet: TM060
Page 25 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Performance Specifications
Performance Definitions
STC3500 performance
Input Jitter Tolerance - Input jitter tolerance is the amount of jitter at its input a clock can tolerate before generating an indication of improper operation. GR-1244 and ITU-813 requirements specify jitter amplitude v.s. jitter frequency for jitter tolerance. The STC3500 device provides jitter tolerance that meets the specified requirements. Input Wander Tolerance - Input wander tolerance is the amount of wander at its input a clock can tolerate before generating an indication of improper operation. GR-1244 and ITU-813 requirements specify input wander TDEV v.s. integration time as shown below.
Integration Time, (seconds)
TDEV (nS)
100 31.6 x
The STC3500 device provides wander tolerance that meets these requirements.
Preliminary Data Sheet: TM060
Page 26 of 48
Rev: P06
Date: 11 / 22 / 04
Performance Specifications continued
Phase Transient Tolerance - GR-1244 specifies maximum reference input phase transients that a clock system must tolerate without generating an indication of improper operation. The phase transient tolerance is specified in MTIE(nS) v.s. observation time from .001 to 100 seconds, as shown below.
Observation time S (Seconds)
MTIE (nanoseconds)
61, 000 x S 925 + 4600 x S (only for Stratum 3) 10, 000 (only for Stratum 3)
Wander Generation Characteristics - MTIE
Wander Generation Characteristics - TDEV
GR-1244-CORE, R5-5
GR-1244-CORE, R5-
TDEV (ns)
MTIE (ns)
Observation Time (sec)
Integration Time (sec)
Preliminary Data Sheet: TM060
Page 27 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Performance Specifications continued
Wander Transfer - Wander transfer is the degree to which input wander is attenuated (or amplified) from input to output of a clock.
Integration time, (seconds)
Stratum 3 TDEV (nanoseconds)
N / A 1020 x 102 102 32.2 x
0.5 32.2 x 0.5
The STC3500, when configured for the appropriate stratum 3 bandwidth frequency, meets the stratum 3 requirements, Jitter Generation - Jitter generation is the process whereby jitter appears at the output of a clock in the absence of input jitter. The device jitter generation performance is as shown below:
Jitter
Broadband 500 Hz - 1.3 MHz 65 kHz - 1.3 MHz
STC3500 Performance
Requirement, p-p
T1 / E1:32 nS T1 / E1: 32 nS, STM-1: 3.21nS T1 / E1: 32 nS, STM-1: 643 pS
Jitter Transfer - Jitter transfer is the degree to which input jitter is attenuated (or amplified) from input to output of a clock. It is a function of the selected bandwidth. The STC3500 jitter transfer characteristics are shown below:
Jitter Transfer Characteristics
Jitter Attenuation (dB)
0.011 Hz 0.005, 3 Hz 0.002, 7 Hz 0.001, 3 Hz 0.000, 66 Hz
Jitter Modulation Frequency (Hz)
Preliminary Data Sheet: TM060
Page 28 of 48
Rev: P06
Date: 11 / 22 / 04
Performance Specifications continued
Phase Transients - MITE
Phase Transients - TDEV
GR-1244-CORE, R5-14
MTIE (ns)
TDEV (ns)
GR-1244-CORE
Observation Time (sec)
Integration Time (sec)
Capture Range and Lock Range - Capture range and lock range are the maximum frequency errors on the reference input within which the phase locked loop is able to achieve lock and hold lock, respectively. The STC3500 stratum 3 performance is shown below:
Characteristic
Capture range Lock in range
STC3500
Requirement
Master / Slave Skew, Reference switch settling time, and Phase Build-Out resolution - Master / Slave Skew, Reference switch settling time, and Phase Build-Out resolution performance are shown below:
Characteristic
Master / Slave phase skew Reference switch settling time Phase Build-Out resolution
STC3500
Requirement
Preliminary Data Sheet: TM060
Page 29 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Application Notes
This section describes typical application use of the STC3500 device. The General section applies to all application variations, while the remaining sections detail use depending on the level of control and automatic operation the application desires.
General
Preliminary Data Sheet: TM060
Page 30 of 48
Rev: P06
Date: 11 / 22 / 04
Application Notes continued
Power Input, Filtering and Peripheral Connections Figure 9
ferrite bead
TDK ACZ1005Y-301
.01uF ceramic 3.3V 3.3V digital power inputs Vdd3.3 (8)
STC3500
Clock Out
.1uF ceramic VCXO
Jumper with ferrite bead
+2.2uF +
3.9K ohm 10uF
.22uF
330 ohm
EEPROM
(optional)
Dmode
GND (14)
E2wp AGND (2)
Preliminary Data Sheet: TM060
Page 31 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Application Notes continued
Component Selections
Table 8 Component
OCXO (CT only) OCXO (IT only) TCXO (CT range only) VCXO (CT range) VCXO (IT range) DAC EEPROM (Optional)
Vendor
Connor-Winfield Connor-Winfield Connor-Winfield Connor-Winfield Connor-Winfield Linear Technology Atmel
Part Number / Description
Device Pins
OCXO OCXO TCXO VCXO VCXO DACclk, DACdin, DACld E2scl, E2sda, E2wp
Preliminary Data Sheet: TM060
Page 32 of 48
Rev: P06
Date: 11 / 22 / 04
Application Notes continued
Master / Slave Configuration Figure 10
Reference 1 In
STC3500 1
Reference n In
Refn STC3500
Xref (8 kHz)
8 kHz Synchronized clock output BITS clock output 2 kHz multi-frame sync
STC3500 2
Preliminary Data Sheet: TM060
Page 33 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Application Notes continued
Configuration Data Registers Table 9:
EEPROM Access Registers Table 10:
Preliminary Data Sheet: TM060
Page 34 of 48
Rev: P06
Date: 11 / 22 / 04
Application Notes continued
Figure 11 shows the basic EEPROM access architecture:
EEPROM Access Architecture Figure 11
EEPROM
Address / Control Data 32 Bytes 32 Bytes Page 0 Page 1
32 Byte FIFO
32 Bytes
Page 231
STC3500
Preliminary Data Sheet: TM060
Page 35 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Application Notes continued
Holdover History accumulation register
Active Holdover History
Backup Holdover History
Once lock has been achieved, Hold Over history is compiled in the accumulation register. It is transferred to the Active Hold Over history when it is ready (typically in about 15 minutes). The "Holdover Available" bit and output pin are set to "1". From then on, the Active Hold Over history is continually updated and kept in sync with the Hold Over history accumulation register. (See Figure 12).
Hold Over History Access and Control Registers Table 11
Preliminary Data Sheet: TM060
Page 36 of 48
Rev: P06
Date: 11 / 22 / 04
Application Notes continued
Hold Over History and Status States Figure 12
Reference Switch
Flush
Reference Switch
History restored from backup, re-start the building procedure
Preliminary Data Sheet: TM060
Page 37 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Application Notes continued
Preliminary Data Sheet: TM060
Page 38 of 48
Rev: P06
Date: 11 / 22 / 04
Application Notes continued
Control Modes
The STC3500 device may be controlled and interfaced in a pure hardware mode with pin signals, or via SPI or parallel bus / register access. With register access, the device can in turn be operated in a manual control mode, or automatic control and reference selection mode. Hardware mode is most suitable for simple environments where minimal external intelligence is desired. Register access provides more detailed visibility and control for references and general synchronization operation. These three main operating environments are detailed as follows:
Hardware Control Interfaces Figure 12
Reset
BITS output frequency select
Preliminary Data Sheet: TM060
Page 39 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Application Notes continued
Sel0-3 - Write to the appropriate values for the desired reference selection and operating mode, as shown below:
Hardware Reference Selection and Mode Control Table 12 Pin Reference / Mode
Free Run Lock to Ref1 Lock to Ref2 Lock to Ref3 Lock to Ref4 Lock to Ref5 Lock to Ref6 Lock to Ref7 Lock to Ref8 Hold Over
Preliminary Data Sheet: TM060
Page 40 of 48
Rev: P06
Date: 11 / 22 / 04
Application Notes continued
Register Access Manual Control
In Register Control Mode, far more internal device information is available. However, Operational mode and Reference Selection may still be performed manually. The control configuration for this mode of operation is shown in Figure 13:
Register Access Manual Control Interfaces Figure 13
Reset
STC3500
LOS LOL
Bmode
(Optional Use)
Outputs
CS ALE or SCLK Bus Interface R / W or SDI RDY or SDO 8 Interrupt AD0-7 INTR
Preliminary Data Sheet: TM060
Page 41 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Application Notes continued
Pulse Width Control
Reg. 0x03 BITS 5-4
Free Run Lock on Ref1 Lock on Ref2 Lock on Ref3 Lock on Ref4 Lock on Ref5 Lock on Ref6 Lock on Ref7 Lock on Ref8 Hold Over
Reg. 0x03
Preliminary Data Sheet: TM060
Page 42 of 48
Rev: P06
Date: 11 / 22 / 04
Application Notes continued
Preliminary Data Sheet: TM060
Page 43 of 48
Rev: P06
Date: 11 / 22 / 04
All Rights Reserved Specifications subject to change without notice
Application Notes continued
Register Access Automatic Control
Pulse Width Control
Reg. 0x03 BITS 5-4
Preliminary Data Sheet: TM060
Page 44 of 48
Rev: P06
Date: 11 / 22 / 04
Application Notes continued