STC3500 integrated single chip solution Synchronous Timing Source SONE
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STC3500 INTEGRATED STRATUM TIMING SOURCE
STC3500 integrated single chip solution Synchronous Timing Source SONET/SDH network elements. device generates four synchronous clocks, including BITS, fully compliant with Telcordia GR-1244-CORE, GR-253-CORE ITU-T G.812/G.813. STC3500 operate Free Run, locked Hold Over mode. Free mode, locks OCXO TCXO. locked mode, locks input reference clocks. frequency each input reference clock user selected automatically detected device. active reference automatically selected device based priority table manually controlled user. reference switches hit-less. Hold Over mode, device generates outputs based frequency history last locked reference. STC3500 supports Master Slave mode operation redundant designs. master mode, device operates Free Run, locked Hold Over. slave mode, output clocks locked master's primary Sync_Clk synchronous clock output phase offset adjustable. Parallel serial interfaces provided access STC3500 internal control status registers. Major operations performed from either interface external hardwire pins.
Features
Complies with Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812/G.813 Supports Master/Slave operation Supports Free Run, Locked, Hold Over modes Accepts reference inputs from 77.76 cross reference Continuous input reference quality monitoring Input reference frequencies automatically detected Automatic manual selection active reference Supports hardwire pins select active reference Four output signals: selectable 155.52 MHz, fixed kHz, multiframe sync fixed kHz, 1.544 2.048 BITS output Output phase adjustable slave mode Frequency ramp control during reference switching Hit-less reference switching Configurable bandwidth filter Supports 8-bit parallel interface IEEE 1149.1 JTAG boundary scan Available FBGA144 package
Functional Block Diagram
OCXO/TCXO 12.8
Xref Ref1-8 Reset HM_Ref Sel0-3 BITS_Sel VC_Sel Bmode Dmode ALE/SCLK RW/SDI RDY/SDO AD0-7 INTR
EEPROM
VCXO
Reference Input Monitor
Sync_Clk Sync_8K Sync_2K DPLL APLL BITS_Clk
Control Mode
Reference Selection
Bulletin Page Revision Date
TM060
Reference Priority, Revertivity Mask Table
Hold_Avail
Interface
STC3500
Table Contents
Diagram (Top View) Description Absolute Maximum Ratings Operating Conditions Electrical Characteristics Register Detailed Description 8-17 Operating Modes Free Locked Hold Over Master/Slave Operation Control Modes 11-15 Hardware Control Register Control Reference Input Quality Monitoring Reference Input Selection, Frequencies, Mode Selection 15-16 Output Signals Frequency Interrupts OCXO/TCXO Calibration Register Descriptions Operation 18-25 Performance Specifications 26-29 Performance Definitions Jitter Wander Fractional Frequency Offset Drift Time Interval Error (TIE) Maximum Time Interval Error (MTIE) Time Deviation (TDEV) STC3500 performance 26-29 Input Jitter Tolerance Input Wander Tolerance Phase Transient Tolerance Free Frequency Accuracy Hold Over Frequency Stability Wander Generation Wander Transfer Jitter Generation Jitter Transfer Phase Transients Capture Range Lock Range Master/Slave Skew, Reference Switch Settling Time, Phase Build-Out Resolution Application Notes 30-45 General 30-35 Power Ground Peripherals Environment External Component Selection Reference Inputs Master/Slave Operation Reset Configuration Data Reading Writing EEPROM Data Hold Over History Accummulation Maintenance Boundary Scan Control Modes 36-45 Hardware Control Register Access Manual Control Register Access Automatic Control Mechanical Specifications Package Dimensions
read this document following sections, intent follows: Detailed Description Register Descriptions "How device works" Performance This section provides terminology definitions detailed data chip performs Application Notes "How device" from application perspective
Preliminary Data Sheet: TM060
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Date: 11/22/04
Copyright 2001 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
STC3500 Ball Grid Diagram (Top View) Figure
Reset
SCLK
Vdd2.5
Sel0
Sel1
Sel2
Sel3
Bmode
HM_Ref
DACclk
INTR
Dmode
Vdd2.5
BITS_Sel
DACdin
E2scl
E2sda
VCXO_Sel
DACld
Vdd2.5
E2wp
Vdd3.3
Vdd3.3
Vdd3.3
AVdd2.5
Vdd3.3
Vdd2.5
V_NPECL
AGND
M_Clk
AGND
V_PPECL
V_TTL
AVdd2.5
Sync_Clk
Vdd2.5
Vdd2.5
Vdd3.3
Vdd2.5
Vdd3.3
Vdd2.5
Sync_8k
Xref
Hold_Rdy
Sync_2k
Vdd3.3
BITS_Clk
TRST
Ref1
Ref2
Ref3
Ref4
Ref5
Ref6
Ref7
Ref8
Vdd3.3
Note: Pins indicated "MNC" mandatory no-connects. Pins indicated "NC" left unconnected grounded.
Preliminary Data Sheet: TM060
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Table Name
Vdd2.5
E10, H10, B11, F10, K10, E12,
2.5V Digital Power Supply
Vdd3.3
3.3V Digital Power Supply
Digital Ground
AVdd2.5 AGND TRST HM_Ref Bmode Dmode Reset SCLK INTR
2.5V Analog Power Supply Analog Ground Controls Boundary Scan Clock input Boundary Scan Serial input Boundary Scan Serial output Boundary Scan Active input resetting boundary-scan circuitry Hardware Mode reference selection: Enable, Disable interface selection, Parallel, Selects configuration data source, interface, EEPROM Active reset logic, minimum time: Chip Select: Asserted enable interface Address Latch Enable parallel interface mode, SCLK mode Read/Write Parallel Interface Mode, Mode Ready Parallel Mode, Mode Active notify Micro-controller events, cleared reading register Int_Event AD0: Address/Data (multiplexed) Parallel Mode AD1: Address/Data (multiplexed) Parallel Mode AD2: Address/Data (multiplexed) Parallel Mode AD3: Address/Data (multiplexed) Parallel Mode AD4: Address/Data (multiplexed) Parallel Mode AD5: Address/Data (multiplexed) Parallel Mode AD6: Address/Data (multiplexed) Parallel Mode AD7: Address/Data (multiplexed) Parallel Mode Master Slave Selection, Master, Slave
Preliminary Data Sheet: TM060
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Table continued Name
Sel0
Hardware Mode (HM_Ref Sel0 Sel3 will determine Free Run, Locked, Hold Over, Active Reference Locked Mode. Table Hardware Control Modes section Table Hardware Control Modes section Table Hardware Control Modes section Table Hardware Control Modes section 1.544 2.048 BITS clock selection, 1.544 MHz, 2.048 Loss signal indicator selected reference, Loss Signal Loss phase lock, Loss Lock Hold Over history built usable Cross Reference Input Reference Input Reference Input Reference Input Reference Input Reference Input Reference Input Reference Input Reference Input Synchronous Clock: Output frequency dependent VCXO frequency Synchronous Clock: BITS clock output Multi-frame sync: OCXO TCXO local crystal oscillator input VCXO input VCXO PPECL input VCXO NPECL input Selects VCXO output signal electrical format, PECL, Serial Interface: Serial Interface: Serial Interface: CS/LD EEPROM interface: EEPROM interface: EEPROM interface: Mandatory no-connect must left floating
Sel1 Sel2 Sel3 BITS_Sel Hold_Rdy Xref Ref1 Ref2 Ref3 Ref4 Ref5 Ref6 Ref7 Ref8 Sync_Clk Sync_8K BITS_Clk Sync_2K M_Clk VC_TTL VC_PPECL VC_NPECL VC_Sel DACclk DACdin DACld E2sda E2wp
L10, M11,
Preliminary Data Sheet: TM060
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Absolute Maximum Ratings
Table Symbol
Vdd2.5 Vdd3.3 AVdd2.5 TSTG
Parameter
Logic power supply voltage, 2.5V Logic power supply voltage 3.3V Analog power supply voltage, 2.5V Logic input voltage, rel. Storage Temperature
Minimum
-0.3 -0.3 -0.3 -0.3
Nominal
Maximum
Vdd3.3
Units
Volts Volts Volts Volts
Notes
Note Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions.
Recommended Operating Conditions Electrical Characteristics
Table Symbol
Vdd2.5 Vdd3.3 AVdd2.5 (3.3V) (3.3V) (3.3V) (3.3V) (PECL) (PECL) TRIP TRIN (Vdd2.5) (Vdd3.3)
Parameter
2.5V digital power supply voltage 3.3V digital power supply voltage 2.5V analog power supply voltage High level input voltage level input voltage High level output voltage (IOH -7mA) level output voltage (IOL =10mA) level input voltage (PECL inputs) PECL differential input voltage Input capacitance Clock fall time (TCXO, OCXO, VCXO) Clock rise time (TCXO, OCXO, VCXO) Input reference signal positive pulse width Input reference signal negative pulse width Operating Ambient Temperature Range 2.5V digital supply current 3.3V digital supply current Device power dissipation
Minimum
0.9*Vdd3.3 0.86 1.49
Nominal
Maximum
Vdd3.3 2.125 2.72 Vdd3.3
Units
Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts
Notes
(PECL) High level input voltage (PECL inputs)
(Avdd2.5) 2.5V analog supply current
Note LVTTL compatible
Register
Table Address
0x00 0x01 0x02 0x03 0x04 0x05
Name
Chip_ID_Low Chip_ID_High Chip_Revision Bandwidth_PBO Ctl_Mode Op_Mode
byte chip High byte chip Chip revision number Bandwidth Phase Build-Out option Manual automatic selection Op_Mode, BITS clock output frequency indication, frame/multi-frame sync pulse width mode control Master Free Run, Locked, Hold Over mode, Slave mode
Type
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Register continued
Table Address
0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x30 0x31 0x32 0x33 0x36 0x37 0x38 0x39
Name
Max_Pullin_Range Xref_Activity Ref_Activity Ref_Pullin_Sts Ref_Qualified Ref_Mask Ref_Available Ref_Rev_Delay MS_Phase_Offset Calibration Fr_Pulse_Width DPLL_Status Intr_Event Intr_Enable Ref1_Frq_Offset1 Ref2_Frq_Offset2 Ref3_Frq_Offset3 Ref4_Frq_Offset4 Ref5_Frq_Offset5 Ref6_Frq_Offset6 Ref7_Frq_Offset7 Ref8_Frq_Offset8 Ref1_Frq_Priority1 Ref2_Frq_Priority2 Ref3_Frq_Priority3 Ref4_Frq_Priority4 Ref5_Frq_Priority5 Ref6_Frq_Priority6 Ref7_Frq_Priority7 Ref8_Frq_Priority8 Free Run_Priority History_Policy History_Cmd Hold Over_Time Cfgdata Cfgctr_Lo Cfgctr_Hi Chksum EE_Wrt_Mode EE_Cmd EE_Page_Num EE_FIFO_Port
Maximum pull-in range units Cross Reference activity frequency Activities reference inputs pull-in range reference inputs Qualification reference inputs Availability mask reference inputs Availability reference inputs Reference reversion delay time, minutes Local oscillator digital calibration 0.05 resolution Frame multi-frame sync pulse width Digital Phase Locked Loop status Interrupt events Enable individual interrupt events Ref1 frequency offset resolution Ref2 frequency offset resolution Ref3 frequency offset resolution Ref4 frequency offset resolution Ref5 frequency offset resolution Ref6 frequency offset resolution Ref7 frequency offset resolution Ref8 frequency offset resolution Ref1 frequency priority Ref2 frequency priority Ref3 frequency priority Ref4 frequency priority Ref5 frequency priority Ref6 frequency priority Ref7 frequency priority Ref8 frequency priority Control priority designation Free reference Sets policy Hold Over history accumulation Save, restore, flush commands Hold Over History Indicates time since entering Hold Over state Configuration data write register Configuration data write counter, byte Configuration data write counter, high byte Configuration data checksum pass/fail indicator Disables/Enables writing external EEPROM Page number external EEPROM access Read/Write data external EEPROM access
Type
Phase offset between Xref Sync_8K (for slave operation), resolution
Read/Write command ready indication register external EEPROM Access
Preliminary Data Sheet: TM060
Copyright 2001 Connor-Winfield Corp.
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Detailed STC3500 single chip synchronization timing solution Stratum network elements. highly integrated design includes hardware software implement necessary reference selection, monitoring, digital filtering, synthesis, control functions. external OCXO/TCXO, DAC, VCXO (and optional EEPROM) complete system level solution (see Functional Block Diagram). external references, each from 77.76 MHz, equipped monitored signal presence frequency offset. Additionally, cross-couple reference input, accepting from 77.76 MHz, provided master/slave operation. Reference selection manual automatic, according pre-programmed priorities. reference switches performed hitless manner, frequency ramp controls ensure smooth output signal transitions. When references switched, device provides controllable phase build-out minimize phase transitions output clocks. Three phase aligned output signals provided, first 155.52 (determined VCXO selection), second fixed frame signal. Both these also used cross-couple reference master/slave operation. slave mode, output phase adjusted from +31.75nS relative master, accommodate downstream system needs, such different clock distribution path lengths. third phase aligned output multi-frame sync output. fourth output BITS clock, selectable either 1.544 2.048 Device operation Free Run, synchronized, Hold Over modes. Free Run, clock outputs simply determined accuracy digitally calibrated OCXO/TCXO. synchronized mode, chip phase locks selected input reference. While synchronized, frequency history accumulated. Hold Over mode, chip outputs generated according this history. Digital Phase Locked Loop which provides critical filtering frequency/phase control functions implemented with well-proven algorithms control that meet exceed requirements lead industry critical jitter accuracy performance parameters. Filter bandwidth configured. Control functions provided either direct hardware signals standard 8-bit parallel register interfaces. Direct hardware control provides very simple system interface, while bus/register access provides greater visibility into variety registered information well providing more extensive programmable control capability.
Preliminary Data Sheet: TM060
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Detailed Description continued
Operating Modes: STC3500 operates either Free Run, locked, Hold Over mode:
Free Free mode, Sync_Clk, Sync_8K, BITS_Clk, Sync_2K, output clocks, determined directly from have accuracy calibrated free running OCXO/TCXO. Reference inputs continue monitored signal presence frequency offset, used synchronize outputs. Locked Sync_Clk, Sync_8K, BITS_Clk, Sync_2K outputs phase locked track selected input reference. Upon entering Locked mode, device begins acquisition process that includes reference qualification frequency slew rate limiting, needed. Once satisfactory lock achieved, "Locked" DPLL_Status register, frequency history selected reference will begin compiled. When usable Hold Over history been established, Hold_Avail set, "Hold Over Available" DPLL_Status register. Phase comparison phase lock loop filtering operations STC3500 completely digital. result, device loop behavior entirely predictable, repeatable, extremely accurate. Carefully designed proven algorithms techniques ensure completely hit-less reference switches, operational mode changes, master/slave switches. Basic loop bandwidth programmable from milliHertz Hertz, giving user wide range control over system response. When reference acquired, maximum frequency slew limits ensure smooth frequency changes. Once lock achieved, (<100 seconds stratum) "Locked" set. STC3500 unable maintain lock, Loss Lock (LOL) asserted. transitions between locked, Hold Over Free modes performed with phase smooth frequency phase transitions. Reference phase hits phase differences encountered when switching references when entering locked mode) nulled with automatic phase build-out function, with residual phase error less than optional Phase build-out feature disabled phase hits selected reference, required Stratum Hold Over Upon entering Hold Over mode, Sync_Clk, Sync_8K, BITS_Clk, Sync_2K outputs determined from Hold Over history established last selected reference. Output frequency determined weighted average Hold Over history, accuracy determined OCXO/TCXO. Hold Over mode entered manually automatically. Automatic entry into Hold Over mode occurs when operating automatic mode, reference lost, other valid reference exists. transfer into Hold Over mode designed smooth free hits. frequency slew also limited maximum ppm/sec. history accumulation algorithm uses first order frequency difference filtering algorithm. Typical Hold Over accumulation takes about minutes. When usable Hold Over history been established, Hold_Avail set, "Hold Over Available" DPLL_Status register. Hold Over history continues updated after "Hold Over Available" declared. Hold Over history accumulates only when locked either external reference Master operation Xref clock Slave operation, starting minutes after power Tracking will suspended automatically when switching reference, while Hold Over mode, Free mode. registers allows application control Hold Over history maintenance policy, enabling either rebuild continuance history when reference switch occurs. Furthermore, under register access control, backup Hold Over history register provided. loaded from active Hold Over history restored active Hold Over history. active Hold Over history also flushed. Hold Over History Accumulation Maintenance section. Hold Over mode entered time. there Hold Over history available, prior output frequency will maintained. When Hold Over, application read (via register access) time since Hold Over entered.
Preliminary Data Sheet: TM060
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Detailed Description continued
Master/Slave Operation
Pairs STC3500 devices operated master/slave configuration added reliability. typical configuration shown below:
Master Slave Configuration Figure
Xref
STC3500
Sync_8K Sync_Clk
Xref
STC3500
Sync_8K Sync_Clk
Sync_8K Sync_Clk output each device cross-connected other device's Xref input. device autodetects frequency Xref input. Master slave state device determined pin. Thus, master/ slave state always manually controlled application. master synchronizes selected input reference, while slave synchronizes Xref input. (Note that frame phase alignment maintained across master/ slave pair devices only Sync_8K used cross couple signal.) unit operating slave mode locks phase-aligns cross-reference clock (Sync_8K Sync_Clk) from unit master mode. phase skew between input cross-reference output clock slave unit typically less than ±1ns (under ±3ns dynamic situations, including reference jitter wander). Perfect phase alignment Sync_Clk output clocks would require delay cross-reference clock connection. accommodate path length delays, STC3500 provides programmable phase skew feature. slave's Sync_Clk/8k output phase shifted -32nS +31.75nS relative Xref according contents Phase_Offset register compensate path length Sync_8K Sync_Clk Xref connection. This offset therefore programmed exactly compensate actual path length delay associated with particular application's cross-reference traces. offset further adjusted accommodate output clock distribution path delay differences. Thus, master/slave switches with STC3500 devices accomplished with near-zero phase hits. first time unit becomes slave, such immediately after power-up, output clock phase starts arbitrary, will quickly phase-align cross-reference from master unit. phase skew will eliminated converged programmed phase offset) step step. whole pull-in-and-lock process will complete about seconds. There frequency slew protection slave mode. slave mode, unit's mission lock follow master. Once pair units been operating aligned master/slave mode, master/slave switch occurs, unit that becomes master will maintain output clock phase frequency while phase build-out current output clock phase) performed selected reference input. Therefore, master mode operation commences, there will phase frequency hits clock output. Likewise, unit that becomes slave will maintain output clock frequency phase msec before starting follow cross-reference, protecting downstream clock users during switch. Assuming phase offset programmed actual propagation delay this cross-reference path, there will again phase hits output clock unit that transitioned from master slave.
Preliminary Data Sheet: TM060
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Detailed Description continued
Control Modes
Parallel serial interfaces provided access STC3500 internal control status registers. selected reference, operational modes, master/slave mode, enabling phase build-out loop bandwidth controls accessed from either interface external device pins. Hardware Control device configured direct control over functions simple hardwired configurations. HM_Ref enables hardware control reference selection operational mode. When "1", mode control reference input selection provided direct hardware inputs Sel0-3 (see Table corresponding register access becomes read-only. When HM_Ref disabled (=0), reference selection operational mode control register access. determines master slave mode. 1=Master, 0=Slave. master mode with HM_Ref hardware control operational mode reference selection shown table below:
Hardware Reference Selection Mode Control Table Sel3
Function Sel1
Sel2
Sel0
Mode
Free Locked Locked Locked Locked Locked Locked Locked Locked Hold Over Hold Over Hold Over Hold Over Hold Over Hold Over Hold Over
Reference
slave mode, operational mode "locked" reference Xref input. Register Descriptions Operation Application section: Control Modes more details. VC_Sel determines VCXO input chip PECL, TTL, PECL. Application Notes, Peripherals section. Following device reset, either power-up operation Reset pin, device needs loaded with DPLL configuration data. This data come from either external EEPROM, interface. Dmode selects source configuration data, from interface, from EEPROM. source EEPROM, devices pre-loaded with configuration data available from Connor-Winfield (See Application Notes, External Component Selection section). Data also loaded into read from EEPROM interface (See Application Notes, Reading Writing EEPROM Data section). data application provided reset through interface (i.e. optional EEPROM equipped), data available from Connor-Winfield file loaded procedure described Application Note, Configuration Data section.
Preliminary Data Sheet: TM060
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Detailed Description continued
Register Control Bus/Register access available 8-bit parallel form, selected Bmode pin. Bmode=1 selects parallel access, Bmode=0 selects SPI. Parallel data operations shown follows.
Parallel Timing, Read Access Figure
tALE
tRWs tRWh
tRDY
Address
tRDs
tRDh
Read Data
Parallel Timing, Write Access Figure
tALE
tRWs tRWh
tRDY
Address
tWDs
tWDh
WriteData
Parallel Timing Table Symbol
Parameter
time high setup time hold time time high high active/tristate time Address setup time Address hold time Read data setup time Read data hold time Write data setup time Write data hold time
Minimum
Nominal
Maximum
Units
Notes
Preliminary Data Sheet: TM060
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Detailed Description continued
Serial Timing, Read Access Figure
tCSMIN tCSTRI
SCLK
tRWs tRWh
tDRDY
tDHLD
Serial Timing, Write Access Figure
tCSMIN
SCLK
tRWs tRWh
Serial Timing Table Symbol
Parameter
SCLK SCLK high time SCLK time Read/Write setup time Read/Write hold time Data ready Data hold Chip select data tri-state Minimum delay between successive accesses
Minimum
Nominal
Maximum
Units
Notes
DRDY
DHLD CSTRI CSMIN
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Detailed Description continued
Reference Input Quality Monitoring
Each reference input monitored signal presence frequency offset. Signal presence Ref1-8 inputs indicated Ref_Activity register signal presence frequency Xref input indicated bits Xref_Activity register. frequency offset between Ref1-8 inputs calibrated local oscillator available Ref_Frq_Offset registers (8). Register Ref_Pullin_Sts indicates, each Ref1-8 inputs, reference within maximum pull-in range. maximum pull-in range indicated register Max_Pullin_Range, .1ppm increments. Typically, would according values specified standards (GR-1244) appropriate particular stratum operation. Ref_Qualified register contains "anded" condition Ref_Activity Ref_Pullin_Sts registers each Ref1-8 inputs, qualified seconds. When reference signal been present seconds within pull-in range, it's set. Ref_Available register contains "anded" condition Ref_Qualified register Ref_Mask register, therefore represents availability reference selection when automatic reference operational mode selection enabled. When active reference selection manual (see Reference Input Selection below), selected reference signal lost, Loss Signal (LOS) asserted, active "high" (pin output DPLL_Status register).
Reference Input Selection, Frequencies, Mode Selection
eight reference input signals (Ref1-8) selected synchronization Master mode described below Op_Mode register description). Ref1-8 each kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 Reference frequencies auto-detected (frequency determined chip) detected frequency read from Ref_Frq_Priority registers (See Register Descriptions Operation section). Xref input slave operation frequency auto-detected kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. Signal presence frequency Xref input indicated bits Xref_Activity register. Register Mode reference operational mode selection (HM_Ref active reference operational mode selection manual automatic, determined Ctl_Mode register. manual mode, register writes Op_Mode select reference mode. reset default manual mode. automatic mode, reference selected according priorities written eight Ref_Frq_Priority registers. Individual references masked use/non-use according Ref_Mask register. reference only selected "available" that qualified, indicated Ref_Qualified register, masked (See Reference Input Quality Monitoring Register Descriptions Operation sections). Furthermore, each Ref_Frq_Priority register will determine that reference revertive non-revertive. When reference fails, next highest priority "available" (signal present, non-masked, acceptable frequency offset) reference will selected. When reference returns, will switched only higher priority current active reference marked "Revertive". Additionally, reversion delayed according value written Ref_Rev_Delay register (From minutes).
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Detailed Description continued
automatic reference selection shown following state diagram:
Automatic Reference Selection Figure
Stay Locked time Ref_Rev_Delay
Ref_Rev_Delay time expired
returns, marked revertive
returns, marked non-revertive
Locked
Loss
Select reference: Next highest priority, Qualified (within max. pull-in range, signal present sec.), Non-masked
Select Lock
operational mode according following state diagram:
Automatic Operational Mode Selection Figure
Reference Available (Select highest priority) Higher priority return with prior reference marked revertive Locked loss w/no good holdover history other available reference Return Freerun Return Holdover Loss w/good holdover history alternate reference available Loss w/alternate reference available
available reference holdover history
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Detailed Description continued
Output Signals Frequency
Sync_Clk primary chip output, locked mode synchronized selected reference. Sync_Clk following frequencies: 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 frequency determined choice VCXO. External Component Selection section. Operation 155.52 also permitted with 155.52 VCXO, requires PECL buffer provide main clock output. (See Application Notes/Peripherals section). Device PECL VCXO clock input also needs selected (via VC_Sel pin). When PECL outputs selected, Sync_Clk output disabled. Sync_8K output available frame reference used synchronization signal crosscoupled pairs STC3500 devices operated master/slave mode. Sync_8K duty cycle signal, variable high-going pulse width, determined Ctl_Mode Fr_Pulse_Width registers. variable pulse width mode, width from multiples Sync_Clk cycle time. Register Descriptions Operation section. Sync_2K multi-frame sync output. duty cycle signal, variable high-going pulse width, determined Ctl_Mode Fr_Pulse_Width registers. variable pulse width mode, width from multiples Sync_Clk cycle time. Register Descriptions Operation section. These three output signals phase aligned, locked mode synchronized selected reference. slave mode, they phase with Xref input, offset value written Phase_Offset register (+31.75 -32nS, with .25nS resolution). BITS_Clk BITS clock output either 1.544 2.048 selected BITS_Sel input state read Ctl_Mode register. When BITS_Sel BITS frequency 1.544 when BITS_Sel BITS frequency 2.048 MHz. This output clock digitally synthesized from SYNC_CLK directly will synchronized SYNC_8k SYNC_2k.
Hold Over History Accumulation Maintenance
provided.
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Detailed Description continued
Interrupts
Eight interrupts provided appear INTR_EVENT (0x12) register. Each interrupt individually enabled disabled INTR_ENABLE (0x13) register. Each enables disables corresponding interrupt from asserting SPI_INT pin. Interrupt events still appear INTR_EVENT (0x12) register independent their enable state. interrupts cleared once INTR_EVENT (0x12) register read. interrupts provided are: reference changing from available available reference changing from available available Xref changing from activity activity Xref changing from activity activity DPLL Mode status change Reference switch automatic reference selection mode Loss Signal Loss Lock Interrupts Reference change Autonomous mode Interrupts used determine cause reference change autonomous mode. assume that module currently locked REF1. module switches REF2 SPI_INT asserted. user reads INTR_EVENT (0x12) register. module operating autonomous non-revertive mode, cause determined from bits4, Bit5 indicate Active reference change. Bit6 then cause reference change Loss Active Reference. Bit7 then cause reference change Loss Lock alarm active reference. module operating autonomous revertive mode, cause determined from bits1, 4,5, Bit5 indicate Active reference change. Bit6 then cause reference change Loss Active Reference. Bit7 then cause reference change Loss Lock alarm active reference. Bit1 then cause reference change availability higher priority reference. Note: DPLL Mode Status Change (Bit4) also indicate change DPLL_STATUS (0x11) register, during interrupt caused reference change. data DPLL_STATUS (0x11) register however useful determining cause reference change. This because bits0-2 this register always reflects status current active reference hence cannot used determine status last active reference. Interrupts Manual Mode manual operating mode, when active reference fails Loss Signal Loss Lock alarm, interrupt generated. example, case Loss Signal, bits4 INTR_EVENT (0x12) register would indicate Loss Signal DPLL Mode Status Change. user choose read DPLL_STATUS (0x11) register, though manual mode bit6 INTR_EVENT (0x12) register mirror bit0 DPLL_STATUS (0x11) register. This holds true Loss Lock alarm, where bit7 INTR_EVENT (0x12) register mirror bit1 DPLL_STATUS (0x11) register.
OCXO/TCXO Calibration
OCXO/TCXO calibrated writing frequency offset v.s. nominal frequency into Calibration register. This calibration used synchronization software create frequency corrected from actual OCXO/TCXO output value written Calibration register. Register Descriptions Operation section.
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Register Descriptions Operation
Chip_ID_low, 0x00
byte chip 0x12
Chip_ID_High, 0x01
High byte chip 0x30
Chip_Revision, 0x02
Chip revision number: Chip revision number subject change.
Bandwidth, 0x03 (R/W)
Reserved
Bandwidth Selection 0000 0101: 0.025 0110: 0.049 0111: 0.098 (Reset Default) 1000: 0.20 1001: 0.39 1010: 0.78 1011 1111:
Bits select phase lock loop bandwidth Hertz. reset default .098
Ctl_Mode, 0x04 (R/W)
Reserved
Synk Pulse width control: Controlled FR_Pulse_Width register Default:
Sync Pulse width control: Controlled FR_Pulse_Width register Default:
BITS Clock Output Frequency: 1.544 2.048 (read only)
Ref: Sel0-3 control mode/ref Register control model/ref (read only)
Active Reference Selection: Manual Automatic Default:
Input Reference Frequency Selection: Manual Automatic Default:
When reset (automatic frequency selection), bits Ref_Frq_Priority registers become read-only. When reset (automatic reference mode selection), bits Op_Mode register become read-only. power-up default control mode Bits manual reference automatic reference frequency selection, duty cycle Sync_8K Sync_2K. When HM_Ref enabling hardware control reference selection, this register read-only Bits always read-only.
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Register Descriptions Operation continued
Op_Mode, 0x05 (R/W)
Reserved
Master Slave Mode Master Slave (read-only)
Free Run, Locked, Hold Over: 0000: Free mode 0001: Locked Ref1 0010: Locked Ref2 0011: Locked Ref3 0100: Locked Ref4 0101: Locked Ref5 0110: Locked Ref6 0111: Locked Ref7 1000: Locked Ref8 1001 1111: Hold Over
When HM_Ref enabling hardware control reference selection operational mode control, bits this register read-only reflect state device Sel3-0 inputs. this register read-only follows state pin. When device slave mode, will lock Xref input, independent values written bits Op_mode register. operational mode reference selection written bits while slave mode will, however, take effect when device made master. When Ctl_Mode register reset (automatic reference mode selection) device master mode, bits Op_Mode register become read-only.
Max_Pullin_Range, 0x06 (R/W)
Maximum pull-in range unit This register should according values specified standards (GR-1244) appropriate particular stratum operation. power-up default value 4.6ppm aging 4.6ppm pullin margin).
Xref_Activity, 0x07
Reserved
Xref signal/frequency 0000: Signal 0001: 0100: 12.96 0101: 19.44 0110: 25.92 0111: 38.88 1000: 51.84 1001: 77.76 1010-111: Reserved
Indicates signal presence auto-detected frequency Xref input.
Ref_Activity, 0x08
ref8 activity
ref7 activity
ref6 activity
ref5 activity
ref4 activity
ref3 activity
ref2 activity
ref1 activity
Each indicates presence signal that reference.
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Register Descriptions Operation continued
Ref_Pullin_Sts, 0x09
ref8 range range
ref7 range range
ref6 range range
ref5 range range
ref4 range range
ref3 range range
ref2 range range
ref1 range range
Each indicates reference within frequency range specified value Max_Pullin_Range register.
Ref_Qualified, 0x0a
ref8 qual: avail. avail.
ref7 qual: avail. avail.
ref6 qual: avail. avail.
ref5 qual: avail. avail.
ref4 qual: avail. avail.
ref3 qual: avail. avail.
ref2 qual: avail. avail.
ref1 qual: avail. avail.
This register contains "anded" condition Ref_Activity Ref_Pullin_Sts registers each Ref1-8 inputs, qualified seconds. When reference signal been present seconds within pull-in range, it's set.
Ref_Mask, 0x0b (R/W)
ref8 mask: avail. avail. Default:
ref7 mask: avail. avail. Default:
ref6 mask: avail. avail. Default:
ref5 mask: avail. avail. Default:
ref4 mask: avail. avail. Default:
ref3 mask: avail. avail. Default:
ref2 mask: avail. avail. Default:
ref1 mask: avail. avail. Default:
Individual references marked "use" use" selection automatic reference selection mode (bit Ctl_Mode register). reset default value use". manual reference selection, either hardware register controlled, reference masks have effect, remain valid applied upon transition automatic mode.
Ref_Available, 0x0c
ref8 avail: avail. avail.
ref7 avail: avail. avail.
ref6 avail: avail. avail.
ref5 avail: avail. avail.
ref4 avail: avail. avail.
ref3 avail: avail. avail.
ref2 avail: avail. avail.
ref1 avail: avail.
This register contains "anded" condition Ref_Qualified Ref_Mask registers.
Ref_Rev_Delay, 0x0d (R/W)
Reference reversion delay time, minutes. default 0000 0101, minutes automatic reference selection mode, when reference fails later returns, must available time specified Ref_Rev_Delay register before switched back active reference reference marked "revertive"). Figure
Preliminary Data Sheet: TM060
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Register Descriptions Operation continued
Phase_Offset, 0x0e (R/W)
complement value phase offset between Sync_8K Xref, ranges from +31.75 Positive Value: Sync_8K rising edge leads Xref Negative Value: Sync_8K rising edge lags Xref slave mode, slave's outputs phase shifted -32nS +31.75nS .25nS increments, relative Xref according contents Phase_Offset register, compensate path length Sync_8K Sync_Clk Xref connection. phase offset used, then STC3500 devices would typically written appropriate phase offset values respective path lengths each Sync_8K Sync_Clk Xref connection, ensure that same relative output signal phases will persist through master/slave switches.
Calibration, 0x0f (R/W)
complement value local oscillator digital calibration 0.05 resolution digitally calibrate free running clock synthesized from OCXO/TCXO, this register written with value corresponding known frequency offset oscillator from nominal center frequency.
Fr_Pulse_Width, 0x10 (R/W) Bit4
Reserved
Pulse width Sync_8K Sync_2K clock outputs, 1-15 multiples Sync_Clk clock period.
Bits Ctl_Mode register determine Sync_8K and/or Sync_2K outputs duty cycle pulsed (high going) outputs. When they pulsed, Fr_Pulse_Width register determines width. Width register value multiple Sync_Clk clock period. Valid values same pulse width applied both Sync_8K Sync_2K. Reset default 0001. Writing 0000 maps 0001.
DPLL_Status, 0x11
Reserved
Hold Over Build Complete Hold Over history build complete Hold Over history build complete
Hold Over Available Avail. avail.
Locked Locked locked
Loss Lock Loss Lock loss lock
Loss Signal activity active reference Active reference signal present
indicates presence signal selected reference. indicates loss lock (LOL). Loss lock will asserted lock achieved within specified time stratum operation, lock lost after previously having been established. will asserted automatic reference switches. indicates successful phase lock. will typically <100 seconds, with good reference. will indicate "not locked" lock lost. indicates Hold Over history available. indicates when Hold Over history been successfully built transferred active Hold Over history.
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Register Descriptions Operation continued
Intr_Event, 0x12
Loss Lock
Loss Signal
Active reference change
DPLL Mode status change
Xref Change from activity activity
Xref Change from activity activity
reference change from available available
reference change from available able available
Interrupt state When enabled interrupt occurs, INTR asserted, active low. interrupts cleared INTR pulled high when register read. Reset default
Intr_Enable, 0x13 (R/W)
Enable Interrupt event Enable Disable Default:
Enable Interrupt event Enable Disable Default:
Enable Interrupt event Enable Disable Default:
Enable Interrupt event Enable Disable Default:
Enable Interrupt event Enable Disable Default:
Enable Interrupt event Enable Disable Default:
Enable Interrupt event Enable Disable Default:
Enable Interrupt event Enable Disable Default:
Enables disables corresponding interrupts from asserting INTR pin. Interrupt events still appear Intr_Event register independent their "enable" state. Reset default interrupts disabled.
Ref(1-8)_Frq_Offset, 0x14 0x1b
complement value frequency offset between reference calibrated local oscillator, resolution These registers indicate frequency offset, resolution, between each reference local calibrated oscillator. 0x14 0x1b correspond Ref1 Ref8.
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Register Descriptions Operation continued
Ref(1-8)_Frq_Priority, 0x1c 0x23 (R/W)
Frequency 0000: None 0001: 0010: 1.544 0011: 2.048 0100: 12.96 0101: 19.44 0110: 25.92 0111: 38.88 1000: 51.84 1001: 77.76 1010-1111: Reserved
Revertivity revertive non-revertive Default: revertive
Priority highest lowest Default:
Bits indicate priority each reference automatic reference selection mode (bit Ctl_Mode register =0). manual reference selection mode (bit Ctl_Mode register HM_Ref these bits read-only will contain either reset default values written when last automatic reference selection mode. equal priority values, lower reference numbers have higher priority. specifies reference revertive non-revertive automatic reference selection mode. When reference fails, next highest priority "available" (signal present, non-masked, acceptable frequency offset) reference will selected. When reference returns, will switched only higher priority current active reference marked "Revertive". Bits indicate auto-detected frequency each reference. Invalid frequencies result erroneous device operation. there activity reference, bits will 0000. Bits read only. Registers 0x1c 0x23 correspond Ref1 Ref8.
Free Run_Priority, 0x24 (R/W)
Enable/disable enabled disabled Default, disabled
revertivity revertive non-revertive Default, non-revertive
priority highest lowest Default
Free treated like reference. When enabled, Free will entered when references higher priority lost masked. If/when higher priority reference returns, switched Free "revertive". When disabled, Free will entered only manually selected, references fail Hold Over history available. equal priority value, Free will treated lower priority.
History_Policy, 0x25 (R/W)
Reserved
Reference switch Hold Over History Policy rebuild continue
determines Hold Over history retained rebuilt when reference switch occurs. Application Notes, Hold Over History Accumulation Management section.
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Register Descriptions Operation continued
History_Cmd, 0x26 (R/W)
Reserved
Hold Over history commands Save active history backup history Restore active history from backup Flush active history accumulated register command
Bits written save Hold Over history backup history, restore active Hold Over history from backup, flush active history. default value register last command latched ready application. flush does affect back history. Application Notes, Hold Over History Accumulation Management section.
Hold Over_Time, 0x27
Indicates time since entering Hold Over state. From 255, hour. Zero non-Hold Over state, stops 255.
Cfgdata, 0x30 (R/W)
Configuration data write register Configuration data written this register. Application Notes, Configuration Data section.
Cfgctr_Lo, 0x31
Configuration data write counter byte order byte configuration data write counter. Application Notes, Configuration Data section. Initialized zero power-up/reset.
Cfgctr_Hi, 0x32
Configuration data write counter high byte High order byte configuration data write counter. Application Notes, Configuration Data section. Initialized zero power-up/reset.
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Register Descriptions Operation continued
Chksum, 0x33
Reserved
Configuration Data checksum pass/fail indicator: fail, pass
Checksum verification register configuration data. Application Notes, Configuration Data section. Initialized zero power-up/reset, indicates fail pass upon configuration data pump completion.
EE_Mode, 0x36 (R/W)
Reserved
EEPROM write enable: disabled, enabled
EEPROM write enable register. Application Notes, General, Reading Writing EEPROM Data section.
EE_Cmd, 0x37
EEPROM read/write ready bit: ready ready
Reserved
EEPROM read/write command bits: Reset FIFO Write command Read command
EEPROM read/write command register. Application Notes, General, Reading Writing EEPROM Data section.
EE_Page_Num, 0x38
EEPROM read/write page number, 0x00 0x9f 159) EEPROM read/write page number register. EEPROM consists pages. Application Notes, General, Reading Writing EEPROM Data section.
EE_FIFO_Port, 0x39
EEPROM read/write FIFO data EEPROM read/write FIFO port register. EEPROM data written to/read from here. Application Notes, General, Reading Writing EEPROM Data section.
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Performance Specifications
Performance Definitions
Jitter Wander Jitter wander defined respectively "the short-term long-term variations significant instants digital signal from their ideal positions time". They therefore phase position time modulations digital signal's transitions's transitions relative their ideal positions. These phase modulations turn characterized terms their amplitude frequency. Jitter defined those phase variations rates above wander those variations rates below Fractional frequency offset drift fractional frequency offset clock ratio frequency error (from nominal desired frequency) desired frequency. typically expressed parts 10x), 10-x). Drift measure clock's frequency offset over time. expressed same offset. Time Interval Error (TIE) measure wander defined variation time delay given signal relative ideal signal over particular time period. typically measured zero start measurement, thus represents phase change since beginning measurement. Maximum Time Interval Error (MTIE) MTIE measurement wander that finds peak-to-peak variations time delay signal given window time, called observation interval Therefore largest peak-topeak observation interval length within entire measurement window data. MTIE therefore useful measure phase transients, maximum wander frequency offsets. MTIE increases monotonically with increasing observation interval. Time Deviation (TDEV) TDEV measurement wander that characterizes spectral content phase noise. TDEV() filtered TIE, where bandpass filter centered frequency 0.42/.
STC3500 performance
Input Jitter Tolerance Input jitter tolerance amount jitter input clock tolerate before generating indication improper operation. GR-1244 ITU-813 requirements specify jitter amplitude v.s. jitter frequency jitter tolerance. STC3500 device provides jitter tolerance that meets specified requirements. Input Wander Tolerance Input wander tolerance amount wander input clock tolerate before generating indication improper operation. GR-1244 ITU-813 requirements specify input wander TDEV v.s. integration time shown below.
Integration Time, (seconds)
0.05 1000
TDEV (nS)
31.6
1000
STC3500 device provides wander tolerance that meets these requirements.
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Performance Specifications continued
Phase Transient Tolerance GR-1244 specifies maximum reference input phase transients that clock system must tolerate without generating indication improper operation. phase transient tolerance specified MTIE(nS) v.s. observation time from .001 seconds, shown below.
Observation time (Seconds)
0.001326 0.0164 0.0164 1.97 1.97
MTIE (nanoseconds)
61,000 4600 (only Stratum 10,000 (only Stratum
STC3500 will tolerate reference input transients within GR-1244 specification. Free Frequency Accuracy Free frequency accuracy maximum fractional frequency offset while Free mode. determined accuracy TCXO/OCXO. TCXO/OCXO devices recommended with STC3500 application section will meet GR-1244 G.813 requirements. Hold Over Frequency Stability Hold Over frequency stability maximum fractional frequency offset while Hold Over mode. determined stability TCXO/OCXO. TCXO/OCXO devices recommended with STC3500 application section will meet GR-1244 G.813 requirements. Wander Generation Wander generation process whereby wander appears output clock absence input wander. STC3500 wander generation characteristics, MTIE TDEV, shown below, along with requirements masks (bandwidth 0.34 Hz):
Wander Generation Characteristics MTIE
1000
Wander Generation Characteristics TDEV
GR-1244-CORE, R5-5
GR-1244-CORE,
TDEV (ns)
1000 10000 100000
MTIE (ns)
0.01 0.01
1000
10000
100000
Observation Time (sec)
Integration Time (sec)
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Performance Specifications continued
Wander Transfer Wander transfer degree which input wander attenuated amplified) from input output clock.
Integration time, (seconds)
Stratum TDEV (nanoseconds)
1020 32.2
0.05 0.05 1.44 1.44 1000 1000
32.2
STC3500, when configured appropriate stratum bandwidth frequency, meets stratum requirements, Jitter Generation Jitter generation process whereby jitter appears output clock absence input jitter. device jitter generation performance shown below:
Jitter
Broadband
STC3500 Performance
RMS,
Requirement,
T1/E1:32 T1/E1: STM-1: 3.21nS T1/E1: STM-1:
Jitter Transfer Jitter transfer degree which input jitter attenuated amplified) from input output clock. function selected bandwidth. STC3500 jitter transfer characteristics shown below:
Jitter Transfer Characteristics
fc=1.36Hz Bandwidth (fc) 1.56 0.58 fc=0.66mHz 0.34 0.17 0.085 0.043
Jitter Attenuation (dB)
0.011 0.005,3 0.002,7 0.001,3 0.000,66
0.0001
0.001
0.01
1000
Jitter Modulation Frequency (Hz)
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Performance Specifications continued
Phase Transients phase transient unusual step change phase-time signal over relatively short time period. This switching between equipment, reference switching, diagnostics, entry exit to/from Hold Over, input reference transients. STC3500 performance reference switches shown below (loop bandwidth 0.098 Hz):
Phase Transients MITE
10000
Phase Transients TDEV
1000
GR-1244-CORE, R5-14
MTIE (ns)
TDEV (ns)
GR-1244-CORE
0.001
0.01 1000
0.01
1000
10000
Observation Time (sec)
Integration Time (sec)
Capture Range Lock Range Capture range lock range maximum frequency errors reference input within which phase locked loop able achieve lock hold lock, respectively. STC3500 stratum performance shown below:
Characteristic
Capture range Lock range
STC3500
Requirement
This minimum chip capability, guarantees ability capture lock with reference that offset maximum allowed direction presence OCXO/TCXO that offset maximum opposite direction (4.6 ppm).
Master/Slave Skew, Reference switch settling time, Phase Build-Out resolution Master/Slave Skew, Reference switch settling time, Phase Build-Out resolution performance shown below:
Characteristic
Master/Slave phase skew Reference switch settling time Phase Build-Out resolution
STC3500
Stratum sec. frequency offset
Requirement
Stratum sec. frequency offset
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Application Notes
This section describes typical application STC3500 device. General section applies application variations, while remaining sections detail depending level control automatic operation application desires.
General
Power Ground Well-planned noise-minimizing power ground essential achieving best performance device. device requires 2.5V 3.3V digital power 2.5V analog power input. digital 3.3V, LVTTL compatible. 2.5V originate from common source should individually filtered isolated, shown Figure Alternatively, separate 2.5V regulator used analog volts. filter components should chosen minimum inductance kept close chip possible. Note ferrite bead power filter bypass capacitors associated with oscillator power. Mount bypass capacitors close oscillators possible. Oscillator EEPROM ground digital ground. desirable provide individual bypass capacitors, located close chip, each digital power input leads, subject board space layout constraints. power-up, desirable have 3.3V either lead coincident with, application 2.5V. Digital ground should provided continuous ground plane possible. While analog digital grounds tied together inside chip, recommended that they tied together externally single point close chip well. Peripherals Peripheral connections also shown Figure OCXO/TCXO output connected M_Clk pin. VCXOs 77.76 connect VC_TTL pin, device configured input tying VC_Sel high. VCXO 155.52 MHz, output will typically PECL compatible should connected VC_PPECL VC_NPECL pins. VC_Sel PECL input. 155.52 operation, PECL buffer will also need provided 155.52 clock output. Digital analog converter clock, data, chip select connect pins DACclk, DACdin, DACld, respectively. output connected VCXO input through simple filter shown Figure below. capacitors preferably tantalum. optional EEPROM included, serial clock, serial data, connect pins E2scl, E2sda, E2wp, respectively. Dmode selects source configuration data, from interface, from EEPROM.
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Application Notes continued
Power Input, Filtering Peripheral Connections Figure
ferrite bead
ACZ1005Y-301
.01uF ceramic 3.3V 3.3V digital power inputs Vdd3.3
.1uF ceramic M_Clk OCXO/ TCXO
22uF
STC3500
PECL Buffer .01uF ceramic 2.5V Reg. 2.5V digital power inputs Vdd2.5 VC_TTL VC_PPECL VC_NPECL
Clock
.1uF ceramic VCXO
22uF
Jumper with ferrite bead
+2.2uF
3.9K 10uF
.22uF
ohm,1/4W Digital ground Analog ground Number pins 2.5V analog power inputs PECL VC_Sel AVdd2.5 DACclk DACdin DACld E2scl E2sda
EEPROM
(optional)
Config. Data from: EEPROM
Dmode
(14)
E2wp AGND
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Application Notes continued
Environment maximum device power dissipation Board layout device location need account adequate cooling. device input output signal levels 3.3V LVTTL (Except VC_PPECL VC_NPECL, which LVPECL). External Component Selection Following recommended external components used with STC3500. device pins which they connect also shown. main oscillator OCXO TCXO:
Component Selections
Table Component
OCXO only) OCXO only) TCXO range only) VCXO range) VCXO range) EEPROM (Optional)
Vendor
Connor-Winfield Connor-Winfield Connor-Winfield Connor-Winfield Connor-Winfield Linear Technology Atmel
Part Number/ASOF3S3 12.8 AGOF3S3 12.8 DSOF3S3 12.8 BGOF3S3 12.8 T-501 VKB52B2 Sync_Clk frequency) VKB62B2 Sync_Clk frequency) LTC1655LCS8 AT24C64N-10SI-2.7
Device Pins
OCXO OCXO TCXO VCXO VCXO DACclk, DACdin, DACld E2scl, E2sda, E2wp
VCXO determines Sync_Clk output frequency. Acceptable output frequencies are: 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 51.84 MHz, 77.76 MHz, 155.52 MHz. device will operationally autodetect output frequency. EEPROM optional, required hold device configuration data application intends operate hardware control mode only interface). interface used, application provide configuration data pump, EEPROM required. Application Notes, Configuration Data section. Reference Inputs application supply reference inputs, applied input pins Ref1 They each kHz, 1.544 MHz, 2.048 MHz, 19.44 MHz, 38.88 MHz, 77.76 MHz. device auto-detects frequency hardware control modes, auto-detect have frequency written registers register control mode, described control mode sections that follow. References would typically (but need connected decreasing order usage priority. example redundant BITS clocks available, they would typically assigned Ref1 Ref2, with other transmission derived signals following thereafter. Master/slave operation some applications, reliability requirements demand that clock system duplicated. STC3500 device will support master/slave duplicated configuration such applications. facilitate it's use, device includes necessary signal cross coupling control functions. Redundancy reliability implies major considerations: Maintaining separate failure groups such that failure group does affect it's mate, Physical logical partitioning repair, such that failed component replaced while mate remains service, desired. System design needs account these appropriately system level goals met. Master/Slave Configuration pair devices interconnected cross-coupling their respective Sync_8K Sync_Clk outputs other device's Xref input (See Figure 10). Note that frame phase alignment maintained across master/slave pair devices only Sync_8K used cross couple signal. Additionally, reference inputs each device would typically correspondingly same, that when Master/ Slave switch occurs, synchronization would continue with same reference. references driven same signal directly separate drivers, redundancy that part system requires. Distribution path lengths critical here, phase build-out will occur when device switches from slave master.
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Application Notes continued
path lengths Sync_8K Sync_Clk Xref signals interest, however. They need same. However, accommodate path length delays, STC3500 provides programmable phase skew feature, which allows application offset output clocks from cross-reference signal 0.25nS increments. This offset therefore programmed exactly compensate actual path length delay associated with particular application's cross-reference traces. offset further adjusted accommodate output clock distribution path delay differences. Phase offset programmed writing Phase_Offset register, typically one-time device initialization function. (See register description Register Access Control sections). Thus, master/slave switches with STC3500 devices accomplished with near-zero phase hits. applications that Hardware Control only (i.e. phase offset programming available), desirable keep cross couple path lengths minimum relatively equal length, path length will appear phase slave clock output when master/slave switch occurs Hardware Control configuration.
Master Slave Configuration Figure
Reference
Ref1
STC3500
Sync_2K BITS_Clk Sync_Clk Sync_8K multi-frame sync BITS clock output Synchronized clock output
Reference
Refn STC3500
Xref kHz)
Xref kHz)
Ref1
Sync_8K Sync_Clk BITS_Clk Sync_2K
Synchronized clock output BITS clock output multi-frame sync
Refn
STC3500
Master/Slave Operation Control Master/Slave state always manually controlled application. Master slave state device determined pin. Choosing master/slave states function application, based configuration rest system potential detected fault conditions. When operating Hardware Control Register Access Manual Control mode, important slave reference selection same master ensure same reference when/if slave becomes master. Register Access Manual Control mode, Ref_Mask register should also written same value both devices. Master/slave switches should performed with minimal delay between switching states each devices. This easily accomplished, example, controlling master/slave state with single signal, coupled devices through inverter. case Register Access Automatic Control mode, where reference selection automatic, necessary read operational mode (bits 3-0) from master's Op_Mode register write slave's Op_Mode register. master's reference selection will then used slave when becomes master. addition having references populated same, same order both devices, desireable write reference frequency priority registers Ref(1-8)_Frq_Priority Ref_Mask registers same values both devices ensure seamless master/ slave switches. Reset Device reset initialization time function, which resets internal logic register values. reset performed automatically when device powered Registers return their default values, noted register descriptions. Device mode functionality following reset determined state various hardware control pins.
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Application Notes continued
Configuration Data Following device reset, either power-up operation Reset pin, device needs loaded with DPLL configuration data. This data come from either external EEPROM, interface. Dmode selects source configuration data, from interface, from EEPROM. source EEPROM, devices pre-loaded with data availbale from Connor-Winfield (See External Component Selection section). Following reset, device automatically pumps data from EEPROM. data application provided through interface, data available from Connor-Winfield file loaded following procedure Table
Configuration Data Registers Table
0x30 0x31 0x32 0x33 Cfgdata Cfgctr_Lo Cfgctr_Hi Chksum
Table shows registers associated with configuration data pumping process. configuration file size 7424 bytes. Following reset, pumping process consists simply writing 7424 bytes Cfgdata register. Each write increments Cfgctr_Lo/Hi counter registers, which initialized 0x00 after reset. Completion pump coincides with counter registers reaching value Cfgctr_Lo/Hi 0x1d/ 0x00, corresponding 7424. last bytes configuration data contain checksum (CRC-16), which compared computed checksum device. Chksum register indicates correct incorrect checksum position. after reset, valid after 7424th write Cfgdata register, checksum correct, incorrect. Further writes beyond 7424 will affect device. typical pump sequence after reset, example, would consist checking Cfgctr_Lo/Hi Chksum registers value 0x00, followed 7424 consecutive writes Cfgdata register. Then, successful completion pump checked verifying values Cfgctr_Lo/Hi registers 0x1d/0x00, Chksum 0x01. Incrementing Cfgctr_Lo/Hi values optionally checked while writing. Dmode configuration data pumped automatically from EEPROM, operation configuration data registers still valid. Pump completion checksum correctness verified reading Cfgctr_Lo/Hi Chksum registers. Writes Cfgdata register will have effect device when Dmode case, writes Cfgdata register will have effect device after configuration data pump complete. Reading Writing EEPROM Data optional external EEPROM provided, read written interface. Access provided following registers Table (Also Register Descriptions Operation section):
EEPROM Access Registers Table
0x36 0x37 0x38 0x39 EE_Wrt_Mode EE_Cmd EE_Page_Num EE_FIFO_Port
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Application Notes continued
Figure shows basic EEPROM access architecture:
EEPROM Access Architecture Figure
EE_Page_Num Register Control EE_Wrt_Mode EE_Cmd Registers Read/Write Control
EEPROM
Address/Control Data Bytes Bytes Page Page
Byte FIFO
Data
EE_FIFO_Port Register
Bytes
Page
STC3500
Data EEPROM organized pages bytes each. byte FIFO provides data read/write buffering path EEPROM accesses, page numbers provided EE_Page_Num register. writes, application loads page number bytes data into FIFO. write command then initiates write sequence, which completed automatically device. read, application writes page number, followed read command. device reads data into FIFO, application retrieves data with successive reads EE_FIFO_Port register. Specifically, sequence operations perform write follows: Enable writing setting write enable (write 0x01 EE_Wrt_Mode register) Poll Ready (bit EE_Cmd register, ready until ready Write page number 231, 0x00 0xe7) EE_Page_Num register Reset FIFO clearing bits EE_Cmd register (write 0x00 EE_Cmd register) Perform successive writes EE_FIFO_Port register with desired data that page number Issue write command setting write (write 0x01 EE_Cmd register) Poll Ready (bit EE_Cmd register, ready until ready Disable writing clearing write enable (write 0x00 EE_Wrt_Mode register) After power-up reset, EEPROM loaded correctly, Chksum register should read This sequence repeated each page data desired written. Writing particular byte data requires writing full page. multiple page writes, write enable/disable operation encapsulate entire write sequence, i.e. does need repeated page. Read operations performed follows: Poll Ready (bit EE_Cmd register, ready until ready Write page number 231, 0x00 0xe7) EE_Page_Num register read (write 0x02 EE_Cmd register) Poll Ready (bit EE_Cmd register, ready until ready successive reads EE_FIFO_Port register retrieve data This sequence repeated each page data desired read. Reading particular byte data requires reading full page. Aborted read write sequences which complete full read write cycles given page automatically cleared device beginning next read write operation.
Preliminary Data Sheet: TM060
Copyright 2001 Connor-Winfield Corp.
Page
Rev:
Date: 11/22/04
Rights Reserved Specifications subject change without notice
Application Notes continued
Hold Over History Accumulation Maintenance Hold Over history accumulation maintenance controlled greater detail register access device provided. Hold Over history accumulation control encompasses three device internal registers, three access registers control access, status bits DPLL_Status register.
Holdover History accumulation register
Active Holdover History
Backup Holdover History
Once lock been achieved, Hold Over history compiled accumulation register. transferred Active Hold Over history when ready (typically about minutes). "Holdover Available" output "1". From then Active Hold Over history continually updated kept sync with Hold Over history accumulation register. (See Figure 12).
Hold Over History Access Control Registers Table
0x25 0x26 0x27 0x11 History_Policy History_Cmd Hold Over_Time DPLL_Status Sets policy Hold Over history accumulation: "Rebuild" "Continue" Save, restore, flush commands Hold over history Indicates time since entering Hold Over state Bits3 "Hold Over Available" "Hold Over Build Complete"
Preliminary Data Sheet: TM060
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Rev:
Date: 11/22/04
Copyright 2001 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Application Notes continued
Hold Over History Status States Figure
Reset Reference Switch Flush Acquire Reference Hold Complete Hold Avail Reference lock Build History Hold Complete Hold Avail History bulid complete Locked, history complete Hold Complete Hold Avail Reference Lock (with "Continue" set) Reference switch Acquire Reference Hold Complete Hold Avail Reference Lock (with "Rebuild" set) Build History Hold Complete Hold Avail History Build Complete, replace active holdover history Flush
Reference Switch
Flush
Reference Switch
Reference Switch
History restored from backup, re-start building procedure
Preliminary Data Sheet: TM060
Copyright 2001 Connor-Winfield Corp.
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Date: 11/22/04
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Application Notes continued
Hold Over History Accumulation Maintenance continued Whenever Hold Over entered, Active Holdover History that used determine Hold Over frequency. History_Cmd register allows application issue three Hold Over history control commands: Save Active Holdover History Backup History. Restore Backup History Active. Flush active History well accumulation register. Backup history remains intact. Both Active Backup Hold Over histories loaded with calibrated Free synthesizer control data reset/power-up. application might "save backup" situation where, example, primary reference known higher quality than secondary references, which case desirable save then restore Hold Over history accumulated primary reference primary reference lost Hold Over entered upon loss secondary reference. Users restore history from backup time, even while operating Holdover mode. frequency transient will smooth continuous. responsibility application software keep track viability Hold Over backup history. Given time temperature effects oscillator aging, application wish periodically perform "Save" Active history keep backup current. When switching reference, active Hold Over history will remain intact marked "Holdover Available" available before reference switch) until history accumulated reference (Typically minutes after lock been achieved). During history accumulation, "Holdover Build Complete" reset. Once history accumulation complete, transferred Active History "Holdover Build Complete" set. active history will then continue updated track reference. History_Policy register allows application control history built. When "Rebuild": History accumulation begins when lock achieved reference. Hold Over history rebuilt (taking about minutes). Active History remains untouched until replaced when build complete. When policy "Continue": there "Available" Active History, build occurs, under "Rebuild" policy. there "Available" Active History, will continue, accumulation register will loaded from Active History, "Build" process essentially completed immediately following lock reference. "Continue" policy used application example, known that reference switched traced same source therefore likely frequency offset from prior reference. that case, "Continue" policy avoids delay rebuilding Hold Over history. switch likely between references with known unknown frequency offset, then preferable "Rebuild" policy. time since Hold Over state entered read from Hold Over_Time register. Values from hours, limited 255, reset when Hold Over state. Boundary Scan STC3800 provides standard IEEE 1149.1 JTAG boundary scan interface TMS, TCK, TDI, TDO, TRST pins. Boundary scan used verify proper device connectivity functionality.
Preliminary Data Sheet: TM060
Page
Rev:
Date: 11/22/04
Copyright 2001 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Application Notes continued
Control Modes
STC3500 device controlled interfaced pure hardware mode with signals, parallel bus/register access. With register access, device turn operated manual control mode, automatic control reference selection mode. Hardware mode most suitable simple environments where minimal external intelligence desired. Register access provides more detailed visibility control references general synchronization operation. These three main operating environments detailed follows:
Hardware Control Interfaces Figure
STC3500 Reset BITS_Sel
Reset
BITS output frequency select
Master/Slave Inputs Vdd3.3 Reference/ Operational Mode Select HM_Ref Sel0 Sel1 Sel2 Sel3 Hold_Avail Outputs
Hardware Control device interfaces hardware control shown Figure Reset pulled minimum 100nS during chip start-up other desired time) initialize full device state. However, power-up will also perform reset, minimal configuration, Reset tied input high. BITS clock output frequency selected BITS_Sel pin. When BITS_Sel BITS frequency 1.544 MHz, when BITS_Sel BITS frequency 2.048 MHz. Determines master slave mode. master, slave. Master/slave switches should performed with minimal delay between switching states each devices. This easily accomplished, example, controlling master/slave state with single signal, coupled devices through inverter. simplex operation, device should Master mode "1". HM_Ref hardware control reference selection operational mode.
Preliminary Data Sheet: TM060
Copyright 2001 Connor-Winfield Corp.
Page
Rev:
Date: 11/22/04
Rights Reserved Specifications subject change without notice
Application Notes continued
Sel0-3 Write appropriate values desired reference selection operating mode, shown below:
Hardware Reference Selection Mode Control Table Reference Mode
Free Lock Ref1 Lock Ref2 Lock Ref3 Lock Ref4 Lock Ref5 Lock Ref6 Lock Ref7 Lock Ref8 Hold Over
Sel3
Sel2
Sel1
Sel0
LOS, LOL, Hold_Avail status indication outputs. Their discretion application. Operating Modes, Reference Input Quality Mode, Description sections details their operation. Hardware Control mode, Sync_8K Sync_2K signals default duty cycle, DPLL bandwidth/ phase buildout default stratum
Preliminary Data Sheet: TM060
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Date: 11/22/04
Copyright 2001 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Application Notes continued
Register Access Manual Control
Register Control Mode, more internal device information available. However, Operational mode Reference Selection still performed manually. control configuration this mode operation shown Figure
Register Access Manual Control Interfaces Figure
Reset
Reset BITS_Sel
STC3500
BITS output frequency select 2.048 1.544
HM_Ref
Mode: Parallel
Bmode
Hold_Avail INTR
(Optional Use)
Outputs
SCLK Interface Interrupt AD0-7 INTR
Register Access Manual Control Operation, hardware control pin, HM_Ref, tied low. Reset pulled minimum 100nS during chip start-up other desired time) initialize full device state. Following reset, device configuration data must pumped, either automatically from external EEPROM, application through interface (see Application Notes, General, Configuration Data section). Dmode "High" EEPROM pump, "Low" register pump. optional EEPROM equipped, EEPROM data read written interface. Application Notes, General, Reading Writing EEPROM section. BITS clock output frequency selected BITS_Sel pin. When BITS_Sel BITS frequency 1.544 when BITS_Sel BITS frequency 2.048 access either parallel mode. Bmode connected "high" parallel "low" operation. Parallel operation uses ALE, R/W, RDY, AD0-7, described Register Control section, Figures Table uses SCLK, SDI, SDO, described Register Control section, Figures Table
Preliminary Data Sheet: TM060
Copyright 2001 Connor-Winfield Corp.
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Date: 11/22/04
Rights Reserved Specifications subject change without notice
Application Notes continued
device bandwidth enable/disable phase build-out writing appropriate values Bandwidth_PBO register, 0x03. (See Register Descriptions Operation). recommended value .098 Stratum
Select duty cycle variable pulse width Sync_8K Sync_2K output writing appropriate values bits Ctl_Mode register (0x04), shown below:
Pulse Width Control
Sync_2K Sync_8K duty cycle Sync_2K duty cycle, Sync_8K variable pulse width Sync_2K variable pulse width, Sync_8K duty cycle Sync_2K Sync_8K variable pulse width
Reg. 0x03 BITS
variable pulse width mode, desired pulse width written register FR_Pulse_Width (0x10). pulse width register value (valid range multiple Sync_Clk clock period. same pulse width applied both Sync_8K Sync_2K. example, Sync_Clk 19.44 desired pulse width 206nS, write FR_Pulse_Width 0000 0100 51.5nS). auto-detected input reference frequencies read from bits Ref(1-8)_Frq_Priority registers. desired, write Freerun_Priority register (0x24) enable Free treated like reference (See Register Descriptions Operation section). enabled, desired priority revertivity.
Select desired operational mode reference writing appropriate value register Op_Mode (0x05).
Mode
Free Lock Ref1 Lock Ref2 Lock Ref3 Lock Ref4 Lock Ref5 Lock Ref6 Lock Ref7 Lock Ref8 Hold Over
Reg. 0x03
0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110 0001 0111 0001 1000 0001 1001
Preliminary Data Sheet: TM060
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Rev:
Date: 11/22/04
Copyright 2001 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Application Notes continued
When device slave mode, will lock Xref input, independent values written bits Op_mode register. operational mode reference selection written bits while slave mode will, however, take effect when device made master. simplex operation, device should Master mode. Select desired Hold Over history policy, "Continue" "Rebuild", writing History_Policy register, (0x25). application further save, restore, flush Hold Over history using History_Cmd register (2x26), described Hold Over History Accumulation Maintenance section. remainder registers provide access device internals, such synchronization state, reference activity quality, operational customizations. Their discretion application. Some typical uses described below (see also Register Descriptions Operation section): Max_Pullin_Range (0x06) maximum allowed frequency offset reference. Ref_Qualified (0x0a) read determine reference active within pull-in range before selecting active reference. Phase_Offset (0x0e) used compensate master/slave Sync_8K Sync_Clk Xref pathlength clock distribution paths, desired. Requires analytic/experimental technique determine appropriate values. also Master/Slave Operation sections. Calibration (0x0f) This register used compensate known OCXO/TCXO frequency offset. Write value representing difference between oscillator's measured frequency nominal frequency. DPLL_Status (0x11) This register provides active reference, lock, Hold Over history status support mode control decisions application. Interrupts Five interrupts provided application monitoring control synchronization. They individually maskeable Intr_Enable register (0x13), readable Intr_Event (0x12) register. INTR pulled when non-masked interrupt occurs. Ctl_Mode (0x04) state BITS_Sel HM_Ref pins read from bits Holdover_Time (2x27) time, from hours, since Hold Over state entered, read. While same information available register access, LOS, LOL, Hold_Avail status indication outputs also functional used discretion application.
Preliminary Data Sheet: TM060
Copyright 2001 Connor-Winfield Corp.
Page
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Date: 11/22/04
Rights Reserved Specifications subject change without notice
Application Notes continued
Register Access Automatic Control
Register Access Automatic Control, interfaces, reset, operations same shown Figure described Register Access Manual Control section. Bandwidth_PBO register write operation also same. BITS clock output frequency selected BITS_Sel pin. When BITS_Sel BITS frequency 1.544 when BITS_Sel BITS frequency 2.048 Reset pulled minimum 100nS during chip start-up other desired time) initialize full device state. Following reset, device configuration data must pumped, either automatically from external EEPROM, application through interface (see Application Notes, General, Configuration Data section). Dmode "High" EEPROM pump, "Low" register pump. optional EEPROM equipped, EEPROM data read written interface. Application Notes, General, Reading Writing EEPROM section. Select automatic active reference selection writing register Ctl_Mode (0x04) auto-detected input reference frequencies read from bits Ref(1-8)_Frq_Priority registers. With automatic reference selection, device master mode) also performs operational mode selection (Locked, Hold Over, Free Run) automatically, shown Figure Individual references enabled disable writing appropriate values Ref_Mask (0x0b) register. Select duty cycle variable pulse width Sync_8K Sync_2K output writing appropriate values bits Ctl_Mode register (0x04), shown below:
Pulse Width Control
Sync_2K Sync_8K duty cycle Sync_2K duty cycle, Sync_8K variable pulse width Sync_2K variable pulse width, Sync_8K duty cycle Sync_2K Sync_8K variable pulse width
Reg. 0x03 BITS
variable pulse width mode, desired pulse width written register FR_Pulse_Width (0x10). pulse width register value multiple (valid range Sync_Clk clock period. same pulse width applied both Sync_8K Sync_2K. example, Sync_Clk 19.44 desired pulse width 206nS, write FR_Pulse_Width 0000 0100 51.5nS).
Preliminary Data Sheet: TM060
Page
Rev:
Date: 11/22/04
Copyright 2001 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Application Notes continued
Max_Pullin_Range register (0x06) maximum allowed frequency offset reference. Automatic reference selection accompanied per-reference selectable priorities. These written bits Ref(1-8)_Frq_Priority registers. highest priority lowest equal priorities, lower reference numbers have higher priority. Active reference selection then made according priority conditioned reference availability (registered Ref_Available). figure Each reference also marked "revertive" "non-revertive", writing Ref(1-8)_Frq_Priority registers revertive non-revertive. When reference becomes unavailable, device automatically picks available reference next lower priority. When reference returns, will switched only higher priority current active reference marked "Revertive". Return previously failed reference delayed value Ref_Rev_Delay register. Write value from minutes Ref_Rev_Delay register desired delay. (See figure Reference Input Selection, Frequencies, Mode Selection section). operating master/slave configuration, sure write Ref_Mask Ref(1-8)_Frq_Priority registers same values both devices. Read operational mode (lower bits) from master's Op_Mode register, write them lower bits slave's Op_Mode (0x05) register. This needs repeated whenever there reference switch master. facilitate this, interrupt (bit Intr_Event register) provided indicate reference change. (Alternatively, application choose poll master's Op_Mode register detect reference switches.) Select desired Hold Over history policy, "Continue" "Rebuild", writing History_Policy register, (0x25). application further save, restore, flush Hold Over history using History_Cmd register (2x26), described Hold Over History Accumulation Maintenance section. remainder registers provide access device internals, such synchronization state, reference activity quality, operational customizations. Their discretion application. Some typical uses described below (see also Register Descriptions Operation section): Phase_Offset (0x0e) used compensate master/slave Sync_8K Sync_Clk Xref path-length clock distribution paths, desired. Requires analytic/experimental technique determine appropriate values. also Master/Slave Operation sections. Calibration (0x0f) This register used compensate known OCXO/TCXO frequency offset. Write value representing difference between oscillator's measured frequency nominal frequency. DPLL_Status (0x11) This register provides active reference, lock, Hold Over history status. Interrupts Five interrupts provided application monitoring control synchronization. They individually maskeable Intr_Enable register (0x13), readable Intr_Event (0x12) register. INTR pulled when non-masked interrupt occurs. Ref_Qualified (0x0a) read determine reference active within pull-in range. Ref_Available (0x0c) read determine reference qualified masked. Ref(1-8)_Frq_Offset (0x13 -0x1a) read determine frequency offset, resolution, between each reference local calibrated oscillator. Ctl_Mode (0x04) state BITS_Sel HM_Ref pins read from bits While same information available register access, LOS, LOL, Hold_Avail status indication outputs also functional used discretion application. Ref(1-8)_Frq_Offset (0x13 -0x1a) read determine frequency offset, resolution, between each reference local calibrated oscillator. Ctl_Mode (0x04) state BITS_Sel HM_Ref pins read from bits Holdover_Time (2x27) time, from hours, since Hold Over state entered, read.
Preliminary Data Sheet: TM060
Copyright 2001 Connor-Winfield Corp.
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Rev:
Date: 11/22/04
Rights Reserved Specifications subject change without notice
Mechanical Specifications
Package Dimensions Figure
VIEW
BOTTOM VIEW
Ball Corner
Ball Corner
1.00 [0.04"]
13.00 [0.51"]
11.00 [0.43"]
13.00 [0.51"]
1.00 [0.04"] 11.00 [0.43"]
0.70 [0.03"]
0.35 [0.01"]
0.25 [0.01"]
11.00 [0.43"]
1.50 [0.06"]
dimensions ±10% unless otherwise indicated
Preliminary Data Sheet: TM060
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Rev:
Date: 11/22/04
Copyright 2001 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Mechanical Specifications continued
Additional External Components
Place series resistors ohms) reference inputs. Place series resistors ohms) SPI_IN SPI_CLK inputs. Place .01uF input power pins. 4.7uF (25V) capacitor required pin. 4.7uF (25V) capacitor required pin.
Layout Recommendations
Place caps close pins. Place de-coupling and/or filter components close module pins possible. Ensure that only clean well-regulated power supplied module. Isolate power ground inputs module from noisy sources. Must provide separate power ground trace oscillator that provides sufficient power oscillator. Keep module signals away from sensitive noisy analog digital circuitry. Avoid split ground planes high-frequency return currents affected. Allow extra spacing between traces high-frequency inputs outputs. Keep traces short possible avoid meandering trace paths. recommended that connections JTAG, pins routed pads, preferably pattern shown Figure below. recommended 0.1" center center spacing.
JTAG/ISP Header Connections
Figure
Preliminary Data Sheet: TM060
Copyright 2001 Connor-Winfield Corp.
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Rev:
Date: 11/22/04
Rights Reserved Specifications subject change without notice
Revision
Revision Date 07/01/03 01/21/04 02/05/04 02/19/04 11/15/04 11/22/04
Note Advance Release Miscellaneous Spec Revisions Features GR-253-CORE, 10-6 ppb, External Components, Layout Rec, JTAG/ISP EEPROM Access Architecture Chip Revision Update
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