SM3E Timing Module complete system clock module Stratum timing applica

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SM3E Timing Module complete system clock module Stratum timing applica

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SM3E ULTRA MINIATURE STRATUM MODULE
SM3E Timing Module complete system clock module Stratum timing applications conforms GR-1244-CORE (Issue GR-253-CORE (Issue ITU-T G.812 (Option Applications include shared port adapters, data digital cross connects, ADM's, DSLAM's, multiservice platforms, switches routers TDM, SONET environments. SM3E Timing Module guarantees full Stratum compliance with minimum effort cost smallest complete package available.
Features
Small Package Size, 2.05 1.25 0.75 inches Eight Auto Select Input References, 77.76 Phase Buildout Hitless Reference Switching Better than 1ppb initial Hold Over offset Frequency Qualification Loss Reference detection each input Master/Slave Operation with Phase Adjustment Manual/Autonomous Operation Bi-Directional Port Control Status Reporting Three CMOS Frequency Outputs Output1 from 1.544 77.76MHz, S_Out@8KHz, BITS @2.048 1.544 3.3V operation
Bulletin Page Revision Date Issued
TM054
General Description
SM3E timing module provides clock output that meets exceeds Stratum specifications given GR-1244-CORE (Issue GR-253-CORE (Issue ITU-T G.812 (option SM3E features eight reference inputs. Each input will autodetect following reference frequencies: kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 77.76 MHz. SM3E timing module configured during production produce output 77.76MHz. This output derived from onboard VCXO must specified when ordering. second output BITS output selectable either 1.544 2.048 MHz. master/slave output 8KHz. user communicates with SM3E module through port. user controls SM3E operation writing appropriate registers. user also enable disable operation through SPI_Enable pin. SM3E offers wide range options system designer. bandwidth Port-selectable from 0.00084 0.0016 recommended operational bandwidth Stratum applications. output adjustable pulse width. pull-in range also adjustable establish desired reference frequency rejection limits. Free frequency calibration value written module provide high degree accuracy free mode. reference frequency given reference input automatically detected. wealth status information available through Port registers. user also choice between autonomous full manual control operation. manual mode, user controls module operating modes Free Run, Hold Over locked specific reference. chosen reference unavailable disqualified module automatically enters Hold Over. autonomous control mode, operational mode selection occurs automatically based reference priority qualification status. When active reference becomes disqualified, module will switch another qualified reference. none available, will switch Hold Over. revertive mode module will seek acquire highest priority qualified reference. nonrevertive mode module will return previous reference even after re-qualified unless there other qualified references. Switching between references hitless. Likewise, output frequency slew rate minimized during change operating mode, including entry into return from Free Hold Over protect traffic from transient-induced errors. Reference Status information operating mode information accessed through status registers. module will Interrupt (SPI_INT) indicate status change. Free operation guarantees output within 4.6ppm nominal frequency Hold Over operation guarantees output frequency will change more than 0.012ppm during first hours. Frequency accuracy based precision oven provide stabilty required Stratum compliance. SM3E programmed startup mode bandwidth. module even programmed operate fully autonomous mode with further configuration required. module operates 3.3V with typical power drain less than turn dropping approximately room temperature after warming module operates over commercial temperature range. Phase buildout enabled disabled means port.
Functional Block Diagram
Figure
TRST Input Reset T1/E1 SPI_ENBL SPI_Clk SPI_In SPI_Out SPI_INT Interface Reference Priority, Revertivity Mask Table Control Mode Reference Selection Reference Input Monitor OCXO EEPROM VCXO Output Output BITS_Clk
DPLL
APLL Hold_Good
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Specifications Ultra Miniature Stratum
Table Parameter
Voltage Power Reference Frequency CMOS Output Frequency M/S_Out BITS_Clk Master/Slave Input Reference Pulse Width Free Accuracy Hold Over Accuracy Hold Over Stability Dimensions
Specification
3.3V Maximum during start 1.5W Typical room temperature 77.76 (Determined customer's application) 77.76 1.544/2.048 (Selectable) kHz, 0.001 0.012 first hours 2.05 1.25 0.75 inches (52.07 31.75 19.05
Description
Table
Name REF1 REF2 REF3 REF4 TRST BITS_CLK M/S_OUT OUTPUT1 REF5 REF6 REF8 REF7 T1/E1 HOLD_GOOD SPI_CLK SPI_IN SPI_ENBL RESET SPI_OUT SPI_INT MASTER SELECT Description Alarm output Loss Active Reference Signal Alarm Output Loss Lock Master/Slave reference input Reference Input 77.76 auto detected Reference Input 77.76 auto detected Reference Input 77.76 auto detected Reference Input 77.76 auto detected JTAG JTAG JTAG TRST 1.544 2.048 output selected Master/Slave output Synchronous Primary Output Positive Programming Supply Pin. During normal operation, recommended float this pin. Reference Input 77.76 auto detected Reference Input 77.76 auto detected Reference Input 77.76 auto detected Reference Input 77.76 auto detected Negative Programming Supply Pin. During normal operation, recommended float this pin. BITS_CLK select input 1=1.544 MHz, 0=2.048 Holdover Good Output Flag 1=Holdover Available JTAG JTAG Module Ground Port Clock input Port Data input Supply Input Port Enable input Active Module Reset Active Port Data Output Port Interrupt Output Master/Slave select input 1=Master, 0=Slave
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Diagram
Figure
SM3E
REF1 REF2 REF3 REF4 TRST BITS_CLK M/S_OUT OUTPUT1 REF5 REF6
MASTER SELECT SPI_INT SPI_OUT RESET SPI_ENBL SPI_IN SPI_CLK HOLD_GOOD T1/E1 REF7 REF8
(TOP VIEW)
Register
Table Address
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b
Name
Chip_ID_Low Chip_ID_High Chip_Revision Bandwidth_PBO Ctl_Mode Op_Mode Max_Pullin_Range Input_Activity Ref_Activity Ref_Pullin_Sts Ref_Qualified Ref_Mask
Description
byte chip High byte chip Chip revision number Bandwidth Phase Build-Out option Manual automatic selection Op_Mode,BITS clock output frequency indication, frame/multi-frame sync pulse width mode control Master Free Run, Locked, Hold Over mode, Slave mode Maximum pull-in range units Cross Reference activity Activities reference inputs pull-in range reference inputs Qualification reference inputs Availability mask reference inputs
Type
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Register Continued
Table
0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x30 0x31 0x32 0x33 0x35 0x37 0x38 0x39 Ref_Available Ref_Rev_Delay Phase_Offset Calibration Fr_Pulse_Width DPLL_Status Intr_Event Intr_Enable Ref1_Frq_Offset Ref2_Frq_Offset Ref3_Frq_Offset Ref4_Frq_Offset Ref5_Frq_Offset Ref6_Frq_Offset Ref7_Frq_Offset Ref8_Frq_Offset Ref1_Frq_Priority Ref2_Frq_Priority Ref3_Frq_Priority Ref4_Frq_Priority Ref5_Frq_Priority Ref6_Frq_Priority Ref7_Frq_Priority Ref8_Frq_Priority FreeRun Priority History_Policy History_CMD HoldOver_Time Cfgdata Cfgctr_Lo Cfgctr_Hi Chksum EE_Wrt_Mode EE_Cmd EE_Page_Num EE_FIFO_Port Availability reference inputs Reference reversion delay time, minutes Phase offset between Output (for Slave operation) 250ps resolution Local oscillator digital calibration 0.05 resolution Frame sync pulse width Digital Phase Locked Loop status Interrupt events Enable individual interrupt events Ref1 frequency offset resolution Ref2 frequency offset resolution Ref3 frequency offset resolution Ref4 frequency offset resolution Ref5 frequency offset resolution Ref6 frequency offset resolution Ref7 frequency offset resolution Ref8 frequency offset resolution Ref1 frequency priority Ref2 frequency priority Ref3 frequency priority Ref4 frequency priority Ref5 frequency priority Ref6 frequency priority Ref7 frequency priority Ref8 frequency priority Control Priority designation Free reference Sets policy Hold Over history accumulation Save, restore flush comands Hold Over history Indicates time since entering Hold Over state Configuration data write register Configuration data write counter, byte Configuration data write counter, high byte Configuration data checksum pass/fail indicator Disables/Enables writing external EEPROM Read/Write command ready indication register ext. EEPROM access Page number external EEPROM access Read/Write data external EEPROM access
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Detailed Description
SM3E utilizes external references, each from 77.76 MHz, equipped monitored signal presence frequency offset. Additionally, cross-couple reference input provided master/slave operation. Reference selection manual automatic, according pre-programmed priorities. reference switches performed hitless manner, frequency ramp controls ensure smooth output signal transitions. When references switched, device provides controllable phase build-out minimize phase transitions output clocks. Three output signals provided, first 77.76 second fixed frame sync signal well cross-couple reference master/slave operation. slave mode, output phase adjusted from +31.75nS relative master, accommodate downstream system needs, such different clock distribution path lengths. third output BITS clock, selectable either 1.544 2.048 MHz. Device operation Free Run, locked, Hold Over modes. Free Run, clock outputs simply determined Free frequency accuracy calibrated internal clock. locked mode, chip phase locks selected input reference. While locked, frequency history accumulated. Hold Over mode, chip outputs generated according this history. Digital Phase Locked Loop provides critical filtering frequency/phase control functions that meet exceed requirements critical jitter accuracy performance parameters. Filter bandwidth configured suit applications requirements. Control functions provided standard register interface. Register access provides visibility into variety registered information well providing extensive programmable control capability. Operating Modes: SM3E Operates Either Free Run, Locked, Hold Over Mode: Free Free mode, Output M/S_Out, BITS_Clk, output clocks, determined directly from have accuracy calibrated free running internal clock. Reference inputs continue monitored signal presence frequency offset, used synchronize outputs. Locked Output M/S_Out, BITS_Clk, outputs phase locked track selected input reference. Upon entering Locked mode, device begins acquisition process that includes reference qualification frequency slew rate limiting, needed. Once satisfactory lock achieved, "Locked" DPLL_Status register, compilation frequency history selected reference started. When usable Hold Over history been established, Hold_Good set, "Hold Over Available" DPLL_Status register. Phase comparison phase lock loop filtering operations SM3E completely digital. result, device loop behavior entirely predictable, repeatable, extremely accurate. Carefully designed proven algorithms techniques ensure completely hitless reference switches, operational mode changes, master/slave switches. Basic loop bandwidth programmable from 0.84 Hertz, giving user wide range control over system response. When reference acquired, maximum frequency slew limits ensure smooth frequency changes. Once lock achieved, (<700 seconds Stratum 3E), "Locked" set. SM3E unable maintain lock, Loss Lock (LOL) asserted. transitions between locked, Hold Over Free modes performed with minimal phase events smooth frequency phase transitions. Reference phase hits phase differences encountered when switching references when entering locked mode) nulled with automatic phase build-out function. Phase build-out performed with residual phase error less than optionally disabled hits selected reference, required Stratum Hold Over Upon entering Hold Over mode, Output M/S_Out, BITS_Clk, outputs determined from Hold Over history established last selected reference. Output frequency determined weighted average Hold Over history, accuracy determined internal clock. Hold Over mode entered manually automatically. Automatic entry into Hold Over mode occurs when operating automatic mode, reference lost, other valid reference exists. transfer into Hold Over mode designed smooth free transients. frequency slew also limited maximum ppm/sec. history accumulation algorithm uses first order frequency difference filtering algorithm. Typical holdover accumulation takes about minutes. When usable holdover history been established, Hold_Good set, "Holdover Available" DPLL_Status register. holdover history continues updated after "Holdover Avaialble" declared. algorithm accumulates holdover history only when locked either external reference Master operation clock Slave operation, starting minutes after power Tracking will suspended automatically when switching reference Free Hold Over mode. registers allows application control holdover history maintenance policy, enabling either re-build continuance history when reference switch occurs.
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Detailed Description continued
Furthermore, under register access control, backup holdover history register provided. loaded from active holdover history restored active holdover history. active holdover history also flushed. Holdover mode entered time. there holdover history available, prior output frequency will maintained. When holdover, application read (via register access) time since holdover enterred. Master/Slave Operation Pairs SM3E devices operated master/slave configuration redundant timing source applications. typical configuration shown below.:
Master Slave Configuration
Figure
REFS1-8
SM3E STC3500
M/S_OUT OUTPUT1 BITS
REFS1-8
SM3E
M/S_OUT OUTPUT1 BITS
Output Output each device cross-connected other device's input. device auto-detects frequency input. Master slave state device determined pin. Thus, master/slave state always manually controlled application. master synchronizes selected input reference, while slave synchronizes input. (Note that 8kHz frame phase alignment maintained across master/slave pair devices only Output used cross couple signal.) unit operating slave mode locks phase-aligns cross-reference clock (M/S Output Output from unit master mode. phase skew between input cross-reference output clock slave unit typically less than ±1ns (under ±3ns dynamic situations, including reference jitter wander). Perfect phase alignment Output output clocks would require delay cross-reference clock connection. accommodate path length delays, SM3E provides programmable phase skew feature. slave's Output Output phase shifted -32nS +31.75nS relative Input according contents MS_Phase_Offset register compensate path length Output Output Input connection. This offset therefore programmed exactly compensate actual path length delay associated with particular application's cross-reference traces. offset further adjusted accommodate output clock distribution path delay differences. Thus, master/slave switches with devices accomplished with near-zero phase hits. first time unit becomes slave, such immediately after power-up, output clock phase starts arbitrary, will quickly phase-align cross-reference from master unit. phase skew will eliminated converged programmed phase offset) step step. whole pull-in-and-lock process will complete about seconds. There frequency slew protection slave mode. slave mode, unit's mission lock follow master. Once pair units been operating aligned master/slave mode, master/slave switch occurs, unit that becomes master will maintain output clock phase frequency while phase build-out current output clock phase) performed selected reference input. Therefore, master mode operation commences, there will phase frequency hits clock output. Likewise, unit that becomes slave will maintain output clock frequency phase msec before starting follow cross-reference, protecting downstream clock users during switch. Assuming phase offset programmed actual propagation delay this cross-reference path, there will again phase hits output clock unit that transitioned from master slave.
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Detailed Description continued
Serial Communication user control operation SM3E module through port. Timing diagrams shown below. When SPI_ENABLE high, SPI_OUT Tri-state mode.
Serial Interface Timing, Read Access
Figure
SPI_Enable
SPI_Clk
tRWs tRWh
SPI_In SPI_Out
tDRDY
Serial Interface Timing, Write Access
Figure
SPI_Enable
SPI_Clk
tRWs
tRWh
SPI_In
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Detailed Description continued Serial Interface Timing
Table Symbol
tRWs tRWh tDRDY tHLD tCSTRI tCSMIN
Parameter
SPI_Enable SPI_CLK SPI_CLK high time SPI_CLK time Read/Write setup time Read/Write hold time Data ready Data Hold Chip Select data tri-state
Minimum
Nominal
Maximum
Units
Notes
Minimum delay between successive accesses300
Note: port should accessed until 1200ms after reset transitioned from high state.
Reference Input Quality Monitoring Each reference input monitored signal presence frequency offset. Signal presence Ref1-8 inputs indicated Ref_Activity register signal presence indicated REF_Activity register. frequency offset between Ref1-8 inputs calibrated local oscillator available Ref_Frq_Offset registers (8). Register Ref_Pullin_Sts indicates, each Ref1-8 inputs, reference within maximum pull-in range. maximum pull-in range indicated register Max_Pullin_Range, 0.1ppm increments. Typically, would according values specified standards (GR-1244) appropriate particular stratum operation. Ref_Qualified register contains "anded" condition Ref_Activity Ref_Pullin_Sts registers each Ref1-8 inputs, qualified seconds. When reference signal been present seconds within pull-in range, it's set. Ref_Available register contains "anded" condition Ref_Qualified register Ref_Mask register, therefore represents availability reference selection when automatic reference operational mode selection enabled. Reference Input Selection, Frequencies, Mode Selection eight reference input signals (Ref 1-8) selected synchronization Master mode below Op_Mode register description. 0x05). each kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 77.76 MHz. Reference frequencies auto-detected detected frequency read from Ref_Frq_Priority registers (See Register Descriptions Operation section). Active reference operational mode selection manual automatic, determined Ctl_Mode register. manual mode, register writes Op_Mode select reference mode. reset default manual mode. input slave operation frequency auto-detected 8kHz, 1.544MHz, 2.048MHz, 12.96MHz, 19.44MHz, 25.92MHz, 38.88MHz, 51.84MHz 77.76MHz. Signal presence frequency input indicated bits REF_Activity register. automatic mode, reference selected according priorities written eight Ref_Frq_Priority registers. Individual references masked use/non-use according Ref_Mask register. reference only selected "available" that qualified, indicated Ref_Qualified register, masked (See Reference Input Quality Monitoring Register Descriptions Operation sections). Furthermore, each Ref_Frq_Priority register will determine that reference revertive non-revertive. When reference fails, next highest priority "available" (signal present, non-masked, acceptable frequency offset) reference will selected. When reference returns, will switched only higher priority current active reference marked "Revertive". Additionally, reversion delayed according value written Ref_Rev_Delay register (From minutes).
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Detailed Description continued
automatic reference selection shown following state diagram:
Automatic Reference Selection
Figure
Stay Locked time Ref_Rev_Delay
Ref_Rev_Delay time expired
returns, marked "revertive"
returns, marked "non-revertive"
Locked
Loss
Select reference: Next highest priority, Qualified (within max. pull-in range, signal present sec.), Non-masked
Select Lock
operational mode according following state diagram: available reference Hold Over history loss w/no good Hold Over history other available reference
Automatic Operational Mode Selection
Figure
Reference Available (Select highest priority) Higher priority return with prior reference marked "revertive" Locked loss w/no good hold over history other available reference Return Free Return Hold Over Loss w/good hold over history alternate reference available Loss w/alternate reference available
available reference hold over history
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Detailed Description continued
Output Signals Frequency Output primary chip output, locked mode synchronized selected reference. Output following frequencies: 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 77.76 MHz. M/S_Out output available frame reference synchronization signal cross-coupled pairs SM3E devices operated master/slave mode. master mode, M/S_Out synchronized selected reference. slave mode, M/S_Out phase with offset value written Phase_offset register (+31.75 -32nS, with .25nS resolution). M/S_Out duty cycle signal, variable high-going pulse width, determined Ctl_Mode Fr_Pulse_Width registers. variable pulse width mode, width from multiples Output cycle time. Register Descriptions Operation section. BITS_Clk BITS clock output either 1.544 2.048 MHz. selected T1/E1 input state read Ctl_Mode register. When T1/E1 BITS frequency 1.544 MHz, when T1/E1 BITS frequency 2.048 MHz. Interrupts SM3E module supports eight different interrupts appears INTR_EVENT (0x12) register. Each interrupt individually enabled disabled INTR_ENABLE (0x13) register. Each enables disables corresponding interrupt from asserting SPI_INT pin. Interrupt events still appear INTR_EVENT (0x12) register independent their enable state. interrupts cleared once INTR_EVENT (0x12) register read. interrupts are: reference changing from available available reference changing from available available changing from activity activity changing from activity activity DPLL Mode status change Reference switch automatic reference selection mode Loss Signal Loss Lock Interrupts Reference Change Autonomous Mode Interrupts used determine cause reference change autonomous mode. assume that module currently locked REF1. module switches REF2 SPI_INT asserted. user reads INTR_EVENT (0x12) register. module operating autonomous non-revertive mode, cause determined from bits indicate Active reference change. then cause reference change Loss Active Reference. then cause reference change Loss Lock alarm active reference. module operating autonomous revertive mode, cause determined from bits 4,5, indicate Active reference change. then cause reference change Loss Active Reference. then cause reference change Loss Lock alarm active reference. then cause reference change availability higher priority reference. Note: DPLL Mode Status Change (Bit also indicate change DPLL_STATUS (0x11) register, during interrupt caused reference change. data DPLL_STATUS (0x11) register however useful determining cause reference change. This because bits this register always reflects status current active reference hence cannot used determine status last active reference. Interrupts Manual Mode manual operating mode, when active reference fails Loss Signal Loss Lock alarm, interrupt generated. example, case Loss Signal, bits4 INTR_EVENT (0x12) register would indicate Loss Signal DPLL Mode Status Change. user choose read DPLL_STATUS (0x11) register, though manual mode bit6 INTR_EVENT (0x12) register mirror bit0 DPLL_STATUS (0x11) register. This holds true Loss Lock alarm, where bit7 INTR_EVENT (0x12) register mirror bit1 DPLL_STATUS (0x11) register. Internal Clock Calibration internal clock calibrated writing frequency offset v.s. nominal frequency into Calibration register. This calibration used synchronization software create frequency corrected from actual internal clock output value written Calibration register. register descriptions.
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Register Descriptions Operation
Chip_ID_low, 0x00
byte chip 0x11
Chip_ID_High, 0x01
High byte chip 0x30
Chip_Revision, 0x02
Chip revision number: 0x02
Bandwidth_PBO, 0x03 (R/W)
Reserved
Phase Build-out Option: Enable Disable Default:
Bandwidth Selection 0000: 0.00084 0001: 0.0016 0010: 0.0032 0011: 0.0063 0100: 0.012 0101: 0.025 0110: 0.049 0111: 0.098 (Reset Default) 1000: 0.20 1001: 0.39 1010: 0.78 1011 1111: BITS select phase lock loop bandwidth Hertz. reset default 0.098 enables disables phase build-out active reference phase hits. Phase build-out operation requires register access operation device.
Ctl_Mode, 0x04 (R/W)
Reserved
Default:
Output Pulse width control: Controlled FR_Pulse_Width register Default:
BITS Clock Output Frequency: 1.544 2.048 (read only)
Ref: Register control mode/ref (Will always
Active Reference Selection: Manual Automatic Default:
Reserved
When reset (automatic reference mode selection), Bits Op_Mode register become read-only. power-up default manual reference selection default duty cycle Output. When device slave mode, will lock REF, independent values written BITS Op_mode register. operational mode reference selection written Bits while slave mode will, however, take effect when device made master. When Ctl_Mode register reset (automatic reference mode selection) device master mode, BITS Op_Mode register become read-only.
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Register Descriptions Operation continued
Op_Mode, 0x05 (R/W)
Reserved
Master Slave Mode Master Slave (Read Only)
Free Run, Locked, Hold Over: 0000: Free mode 0001: Locked Ref1 0010: Locked Ref2 0011: Locked Ref3 0100: Locked Ref4 0101: Locked Ref5 0110: Locked Ref6 0111: Locked Ref7 1000: Locked Ref8 1001 1111: Hold Over
Max_Pullin_Range, 0x06 (R/W)
Maximum pull-in range unit This register should according values specified standards (GR-1244) appropriate particular stratum operation. power-up default value ppm. 4.6ppm aging pullin margin).
REF_Activity, 0x07
Reserved
Cross reference activity 0000: signal 0001: 8kHz 0100: 12.96MHz 0101: 19.44MHz 0110: 25.92MHz 0111: 38.88MHz 1000: 51.84MHz 1001: 77.76MHz 1010-1111: Reserved
Indicates signal presence auto-detected frequency input.
Ref_Activity, 0x08
ref4 activity
ref3 activity
ref2 activity
ref1 activity
ref8 activity ref7 activity ref6 activity ref5 activity Each indicates presence signal that reference.
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Register Descriptions Operation continued
Ref_Pullin_Sts, 0x09
ref1 range range
ref8 ref7 ref6 ref5 ref4 ref3 ref2 range range range range range range range range range range range range range range Each indicates reference within frequency range specified value Max_Pullin register.
Ref_Qualified, 0x0a
ref8 qual: ref7 qual: ref6 qual: ref5 qual: ref4 qual: ref3 qual: ref2 qual: ref1 qual: avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. This register contains "anded" condition Ref_Activity Ref_Pullin_Sts registers each Ref1-8 inputs, qualified seconds. When reference signal been present seconds within pull-in range, set.
Ref_Mask, 0x0b (R/W)
ref8 mask: ref7 mask: ref6 mask: ref5 mask: ref4 mask: ref3 mask: ref2 mask: ref1 mask: avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. Default: Default: Default: Default: Default: Default: Default: Default: Individual references marked "available" "not available" selection automatic reference selection mode (bit Ctl_Mode register). reset default value "not available". manual reference selection, either hardware register controlled, reference masks have effect, remain valid applied upon transition automatic mode.
Ref_Available, 0x0c
ref2 avail: avail. avail.
ref1 avail: avail.
ref8 avail: ref7 avail: ref6 avail: ref5 avail: ref4 avail: ref3 avail: avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. avail. This register contains "anded" condition Ref_Qualified Ref_Mask registers.
Ref_Rev_Delay, 0x0d (R/W)
Reference reversion delay time, minutes. default 0000 0101, minutes automatic reference selection mode, when reference fails later returns, must available time specified Ref_Rev_Delay register before switched back active reference reference marked "revertive").
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Register Descriptions Operation continued
Phase_Offset, 0x0e (R/W)
complement value phase offset between Master Output module Slave Output module, ranges from +31.75 Positive Value: Master Output rising edge leads Slave Output Negative Value: Master Output rising edge lags Slave Output slave mode, slave's outputs phase shifted -32nS +31.75nS .25nS increments, relative according contents Phase_Offset register, compensate path length connection. phase offset used, then SM3E devices would typically written appropriate phase offset values respective path lengths each Master Slave connection, ensure that same relative output signal phases will persist through master/slave switches.
Calibration, 0x0f (R/W)
complement value local oscillator digital calibration 0.05 resolution digitally calibrate free running clock synthesized from internal clock, this register written with value corresponding known frequency offset oscillator from nominal center frequency.
Fr_Pulse_Width, 0x10 (R/W)
Bit4
Reserved
Pulse width clock output, 1-15 multiples Sync_Clk clock period. BITS Ctl_Mode register determine output duty cycle pulsed (high going) outputs. When they pulsed, Fr_Pulse_Width register determines width. Width register value multiple Sync_Clk clock period. Valid values Reset default 0001. Writing 0000 maps 0001.
DPLL_Status, 0x11
~Bit
Reserved
Hold Over Build Complete Complete Incomplete
Hold Over Available Avail. avail.
Locked Locked locked
Loss Lock Loss Lock loss lock
Loss Signal activity active reference Active reference signal present
indicates presence signal selected reference. indicates loss lock (LOL). Loss lock will asserted lock achieved within specified time stratum level operation, lock lost after being established previously. will asserted automatic reference switches. indicates successful phase lock. will typically <700 seconds Stratum with good reference. will indicate "not locked" lock lost. indicates Hold Over history available. indicates when Hold Over history been sucessfully built transferred active Hold Over history. Detailed Description section under Interrupts Reference Change Autonomous Mode Interrupts Manual Mode
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Register Descriptions Operation continued
Intr_Event, 0x12
Loss Lock
Loss Signal
Active reference change
DPLL Mode status change
Change from activity activity
Change from activity activity
referAny refererence change erence change from from available available able available available Interrupt state When enabled interrupt occurs, SPI_INT asserted, active low. interrupts cleared SPI_INT pulled high when register read. Reset default Detailed Description section under Interrupts Reference Change Autonomous Mode Interrupts Manual Mode
Intr_Enable, 0x13 (R/W)
Enable Inter- Enable Inter- Enable InterEnable Inter- Enable Inter- Enable InterEnable InterEnable Interrupt event rupt event rupt event rupt event rupt event rupt event rupt event rupt event Enable Enable Enable Enable Enable Enable Enable Enable Disable Disable Disable Disable Disable Disable Disable Disable Default: Default: Default: Default: Default: Default: Default: Default: Enables disables corresponding interrupts from asserting SPI_INT pin. Interrupt events still appear Intr_Event register independent their "enable" state. Reset default interrupts disabled.
Ref(1-8)_Frq_Offset, 0x14 0x1b
complement value frequency offset between reference calibrated local oscillator, 0.2ppm resolution These registers indicate frequency offset, 0.2ppm resolution, between each reference local calibrated oscillator. 0x14 0x1b correspond Ref1 Ref8.
Ref(1-8)_Frq_Priority, 0x1c 0x23 (R/W)
Frequency Revertivity Priority 0000: None revertive highest 0001: non-revertive lowest 0010: 1.544 Default: Default: 0011: 2.048 revertive 0100: 12.96 0101: 19.44 0110: 25.92 0111: 38.88 1000: 51.84 1001: 77.76 1010-1111: Reserved BITS indicate priority each reference automatic reference selection mode (bit Ctl_Mode register =0). manual reference selection mode (bit Ctl_Mode register these BITS read-only will contain either reset default values written when last automatic reference selection mode. equal priority values, lower reference numbers have higher priority. specifies reference revertive non-revertive automatic reference selection mode. When reference fails, next highest priority "available" (signal present, non-masked, acceptable frequency offset) reference will selected. When reference returns, will switched only higher priority current active reference marked "Revertive". BITS indicate auto-detected frequency each reference. Invalid frequencies result erroneous device operation. there activity reference, bits 7-4will 0000. Bits read only. 0x1c 0x23 correspond Ref1 Ref8.
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Register Descriptions Operation continued
FreeRun_Priority, 0x24 (R/W)
Enable/ Revertivity Priority Disable Enable Highest Reserved Enable Disable Lowest Disable Default: Default: Default: non-revertive Free treated like reference. When enabled, Free will entered when references higher priority lost masked. when higher priority reference returns, switched Free "revertive". When disabled, Free will entered only manually selected references fail without available Hold Over history. equal priority value, Free will treated lower priority. History_Policy, 0x25 (R/W)
Reference Switch Hold Over Hisory Policy Reserved Rebuild Continue determines Hold Over retained rebuilt when reference switch occurs. Application Notes, Holdover History Accumulation Management section.
History_Cmd, 0x26 (R/W)
Hold Over Histroy Commands Save active history backup history Reserved Restore active history from backup Flush active history accumulation register command Bits written save holdover history backup history, restore active holdover history from backup, flush active history. default value register last command latched read application. flush does affect backup history. Application Notes, Holdover History Accumulation Management section.
HoldOver_Time, 0x27
Indicates time since entering Hold Over state. from 0-255, hour. Zero non-Hold Over state stops 255.
Cfgdata, 0x30 (R/W)
Configuration data write register. Configuration data written this register. Internal only.
Cfgctr_Lo, 0x31
Configuration data write counter byte. order byte configuration data write counter. Internal only.
Data Sheet TM054
Page Rev: Date: 11/07/08
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Register Descriptions Operation continued
Cfgctr_Hi, 0x32
Configuration data write counter high byte. High order byte configuration data write counter. Internal only.
Chksum, 0x33 (R/W)
Configuration Data Checksum pass/fail indicator Fail Pass
Reserved Checksum verification register configuration data. Internal only.
EE_Mode, 0x36 (R/W)
Reserved EEPROM write enable register.
EEPROM Write Enable Disable Enable
EE_Cmd, 0x37 (R/W)
EEPROM read/write ready bit: Ready Ready EEPROM read/write command register.
EEPROM read/write command bits: Reset FIFO Write Command Read Command
Reserved
EE_Page_Num, 0x38 (R/W)
EEPROM read/write page number, 0x00 0x9f 159) EEPROM read/write page number register. EEPROM consist pages.
EE_FIFO_Port, 0x39 (R/W)
EEPROM read/write FIFO data. EEPROM read/write FIFO port register. EEPROM data written to/read from this location.
Data Sheet TM054
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Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Performance Specifications
Performance Definitions
Jitter Wander Jitter wander defined respectively "the short-term long-term variations significant instants digital signal from their ideal positions time". They therefore phase position time modulations digital signal relative their ideal positions. These phase modulations turn characterized terms their amplitude frequency. Jitter defined those phase variations rates above 10Hz, wander those variations rates below 10Hz. Fractional frequency offset drift fractional frequency offset clock ratio frequency error (from nominal desired frequency) desired frequency. typically expressed parts 10X), 10-X). Drift measure clock's frequency offset over time. expressed same offset. Time Interval Error (TIE) measure wander defined variation time delay given signal relative ideal signal over particular time period. typically measured zero start measurement, thus represents phase change since beginning measurement. Maximum Time Interval Error (MTIE) MTIE measurement wander that finds peak-to-peak variations time delay signal given window time, called observation interval (t). Therefore largest peak-to-peak observation interval length within entire measurement window data. MTIE therefore useful measure phase transients, maximum wander frequency offsets. MTIE increases monotonically with increasing observation interval. Time Deviation (TDEV) TDEV measurement wander that characterizes spectral content phase noise. TDEV(t filtered TIE, where bandpass filter centered frequency 0.42/t.
SM3E Performance
Input Jitter Tolerance Input jitter tolerance amount jitter input clock tolerate before generating indication improper operation. GR-1244 ITU-813 requirements specify jitter amplitude v.s. jitter frequency jitter tolerance. SM3E device provides jitter tolerance that meets specified requirements. Input Wander Tolerance Input wander tolerance amount wander input clock tolerate before generating indication improper operation. GR-1244 ITU-813 requirements specify input wander TDEV v.s. integration time shown below.
Integration Time, (seconds)
0.05 1000 1000
TDEV (ns)
31.6
SM3E device provides wander tolerance that meets these requirements. Phase Transient Tolerance GR-1244 specifies maximum reference input phase transients that clock system must tolerate without generating indication improper operation. phase transient tolerance specified MTIE(nS) v.s. observation time from .001 seconds, shown below.
Observation time (Seconds)
0.001326 0.0164 0.0164 1.97 1.97
MTIE (ns)
61,000 4600 10,000
SM3E will tolerate reference input transients within GR-1244 specification. Free-run Frequency Accuracy ability clock produce frequency close possible nominal frequency absence reference. Hold Over Frequency Stability measure clock's performance while Hold Over mode over hours, subjected specified temperature variations.
Data Sheet TM054
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Performance Specifications continued
Wander Generation Wander generation process whereby wander appears output clock absence input wander. SM3EG wander generation characteristics, MTIE TDEV, shown below, along with requirements masks (bandwidth 0.0016 Hz): Wander Generation Characteristics MTIE
1000
GR-253-CORE, 5-17
MTIE (ns)
1000 10000 100000
Observation Time (sec)
Wander Generation Characteristics TDEV
GR-1244-CORE, R5-4 GR-253-CORE, 5-18
TDEV (ns)
0.01 0.01 1000 10000 100000
Integration Time (sec)
Data Sheet TM054
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Performance Specifications continued
Wander Transfer Wander transfer degree which input wander attenuated amplified) from input output clock. GR-1244 requirements wander transfer limits shown below.
Integration time, (seconds)
Stratum TDEV (nanoseconds)
3.16
0.05 0.05 1.44 1.44 1000 1000
10000
-0.5
1.86 1.86 32.2
GR-1244-CORE, Fig5-6, Wander Transfer Wander Transfer TDEV
1000
TDEV (ns)
0.01
Integration Time (sec)
1000
10000
SM3E, when configured appropriate Stratum bandwidth frequency, meets Stratum requirements, Jitter Generation Jitter generation process whereby jitter appears output clock absence input jitter. device jitter generation performance shown below:
Jitter
Broadband MHz) SONET Band
19.44
Typical
77.76
Typical
-2MHz) -20MHz) Typical Typical Jitter Transfer Jitter transfer degree which input jitter attenuated amplified) from input output clock. function selected bandwidth. SM3E jitter transfer characteristics shown below: Jitter Attenuation Input Frequency
Jitter attenuation (dB)
-10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 0.001
0.01
INPUT Jitter frequency (Hz)
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Phase Transients phase transient unusual step change phase-time signal over relatively short time period. This switching between equipment, reference switching, diagnostics, entry exit to/from Hold Over, input reference transients. SM3EG performance reference switches shown below: Phase Transients MTIE
10000
GR-253-CORE, 5-19
1000
Requirement
MTIE (ns)
Objective
0.01
1000
Observation Time (sec)
Phase Transients MTIE
10000
GR-253-CORE, 5-19
1000
MTIE (ns)
0.01
Observation Time (sec)
1000
Data Sheet TM054
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Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Performance Specifications continued
Capture range Lock range Capture range lock range maximum frequency errors reference input within which phase locked loop able achieve lock hold lock, respectively. SM3E Stratum performance shown below:
Characteristic
Capture range Lock range
SM3E
Requirement
This minimum capability, guarantees ability capture lock with reference that offset maximum allowed direction presence OCXO that offset maximum opposite direction (4.6 ppm). Master/Slave Skew, Reference switch settling time, Phase Build-Out resolution Master/Slave Skew, Reference switch settling time, Phase Build-Out resolution performance shown below:
Characteristic
Master/Slave phase skew Reference switch settling time Phase Build-Out resolution
SM3E
Stratum sec. frequency offset
Requirement
Stratum sec. frequency offset
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
SM3E Initialization:
Power-up: possible, always start master mode. After module powered hold reset 10ms. Wait 1200ms read contents register 0x33. reads1 then module came properly. reads then reset module reread register 0x33 after 1200ms. contents 0x33 must read before continuing. Remain default free-run mode seconds then read value register 0x11 alarm output. alarm set, reset must pulled above. free-run mode alarm should never set. This indicates module invalid state. there alarm free-run module ready. Operation: power after reset registers loaded with their default values. default values some important registers given below assuming SM34 module operates Master Address(Hex) Register Name Value(Binary first) Notes 0x03 Bandwidth_PBO 00000111 Bandwidth 0.098Hz 0x04 Ctl_Mode 0000r010 Read Only 0x05 Op_Mode 00010000 Indicates Free mode 0x06 Max_Pullin_Range 01100100 0x0b Ref_Mask 00000000 0x0d Ref_Rev_Delay 00000101 0x0e Phase_Offset 00000000 0x0f Calibration 00000000 0x11 DPLL_Status 00000000 Indicates Active Reference 0x13 Intr_Enable 00000000 Indicates Interrupts disabled 0x1c-0x23 Ref(1-8)_Frq_Priority xxxx0000 Frequencies auto detected 0x33 Chksum xxxxxxx1 Bit0 should high indicate that data been loaded correctly from EEPROM. unit starts Free operates Manual mode. Here steps that need taken lock unit reference Manual mode. Apply signal reference inputs. appropriate pull range writing address 0x06. value 0001xxxx, depending which (Ref 1-8) reference lock should written address 0x05. Enable Reference mask appropriate references writing reference address 0x0b. Enable Interrupts writing 11111111 address 0x13. lock unit reference autonomous (automatic) mode after power reset, following steps should taken. also switch from Manual Autonomous mode directly. When doing please ensure that appropriate references available checking REF_AVAILABLE register (address: 0x0c). III. Clear bit1 CTL_MODE register (address: 0x04). This puts module autonomous mode. Apply signal reference inputs appropriate pull range writing address 0x06 default bandwidth 0.098 appropriate Stratum operation. Enable Reference mask appropriate references writing reference address 0x0b. priority revertivity input references writing appropriate Ref_Frq_Priority registers (bits 3-0). Enable Interrupts writing 11111111 address 0x13. unit operate autonomous mode clearing bit1 address 0x04
Slave Mode Operation: Slave, module operates Autonomous mode. Bandwidth set, default, 1.6Hz (Bandwidth_PBO register (Address 0x03): 00001011). Note that OP_MODE register (Address 0x05) cleared. values Bits this register have effect operation Slave module. Slave module track Master accurately, appropriate Phase Offset value should written PHASE_OFFSET register (Address 0x0e), compensate path delay. module will lock Cross Reference Input (XREF) from master.
RESET Parameters: reset should held minimum milliseconds ensure complete reset occurs. interface should accessed minimum 1200ms after reset de-asserted.
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Application Notes
Available Output1 frequencies are: 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 77.76MHz. After module powered pull reset 10ms. Wait 1200ms read contents register 0x33. reads then module came properly. reads then reset module re-read register0c33 after 1200ms. contents 0x33 must read before using module. Reference Inputs application supply reference inputs, applied input pins Ref1 They each kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 77.76 MHz. device auto-detects reference frequencies, they read from Ref(1-8)_Frq_Priority registers register control mode, described control mode sections that follow. Reference switches performed hitless manner. However, application externally changes frequency particular reference, device requires 20ms auto-detect frequency. Manual switches frequency changed reference should made during this interval. Automatic reference selection mode accounts auto-detection reference qualification. References would typically (but need connected decreasing order usage priority. example redundant BITS clocks available, they would typically assigned Ref1 Ref2, with other transmission derived signals following thereafter. Master/Slave operation some applications, reliability requirements demand that clock system duplicated. SM3E device will support master/slave duplicated configuration such applications. facilitate it's use, device includes necessary signal cross coupling control functions. Redundancy reliability implies major considerations: Maintaining separate failure groups such that failure group does affect it's mate, Physical logical partitioning repair, such that failed component replaced while mate remains service, desired. System design needs account meet system level goals.
Master Slave Configuration
Figure
Reference
Ref1
SM3E
BITS_Clk Output BITS lock output Synchronized clock output
Reference
Ref8 STC3500
Output (8KHz)
(8KHz)
Sync_8K Output BITS_Clk
Synchronized clock output BITS clock output
Ref1
Ref8
SM3E
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Application Notes continued
Master/Slave Configuration pair devices interconnected cross-coupling their respective Outputs Output1 other device's input (See Figure Additionally, reference inputs each device would typically correspondingly same, that when Master/Slave switch occurs, synchronization would continue with same reference. references driven same signal directly separate drivers, redundancy that part system requires. Distribution path lengths critical here, phase build-out will occur when device switches from slave master. path lengths Output signals interest, however. They need same. However, accommodate path length delays, SM3E provides programmable phase skew feature, which allows application offset output clock from cross-reference signal -32ns +31.75ns. This offset therefore programmed exactly compensate actual path length delay associated with particular application's cross-reference traces. offset further adjusted accommodate output clock distribution path delay differences. Phase offset programmed writing Phase_Offset register, typically one-time device initialization function. (See register description Register Access Control sections). Thus, master/ slave switches with SM3E devices accomplished with near-zero phase hits. applications that Hardware Control only (i.e. phase offset programming available), desirable keep cross couple path lengths minimum relatively equal length, path length will appear phase slave clock output when master/slave switch occurs Hardware Control configuration. Master/Slave Operation Control Master/Slave state always manually controlled application. Master slave state device determined MASTER SELECT pin. Choosing master/slave states function application, based configuration rest system potential detected fault conditions. Master/slave switches should performed with minimal delay between switching states each devices. This easily accomplished, example, controlling master/slave state with single signal, coupled devices through inverter. While performing Master/Slave switches, make sure that both modules slave mode. This creates "Timing Loop" that cause undesirable effects. case Register Access Automatic Control mode, where reference selection automatic, necessary read operational mode BITS 3-0) from master's Op_Mode register write slave's Op_Mode register. master's reference selection will then used slave when becomes master. addition having references populated same, same order both devices, desireable write reference frequency priority registers Ref(1-8)_Frq_Priority Ref_Mask registers same values both devices ensure seamless master/slave switches. Reset Device reset initialization time function, which resets internal logic register values. reset performed automatically when device powered Registers return their default values, noted register descriptions. Device mode functionality following reset determined state various hardware control pins. Holdover History Accumulation Maintenance Holdover history accumulation maintenance controlled greater detail register access device provided. Holdover history accumulation control encompasses three device internal registers, three access registers control access, status bits DPLL_Status register.
Hold Over History Accumulation Register
Active Hold Over History
Backup Hold Over History
Once lock been achieved, holdover history compiled accumulation register. transferred Active holdover history when ready (typically about minutes). "Holdover Available" output "1". From then Active holdover history continually updated kept sync with holdover history accumulation register. (See Figure 11).
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Application Notes continued Hold Over History access Control Registers
Table Register
0x25 0x26 0x27 0x11
Register Name
History_Policy History_Cmd Holdover_Time DPLL_Status
Description
Sets policy Hold Over history accumulation: "Rebuild" "Continue" Save, restore, flush commands Hold Over history Indicates time since entering Hold Over state Bits Hold Over Available" "Hold Over Build Complete"
Hold Over History Status States
Figure
Reference Switch Acquire Reference Hold Control Hold Available Reference Lock Reference Switch
Flush
Flush
Build History Hold Control Hold Available Flush
History Build Complete
Locked, History Complete Hold Control Hold Available Reference Lock (with "Continue" set)
Reference Switch History Build Complete, Replace Active Hold Over History
Reference Switch
Acquire Reference Hold Control Hold Available Reference Lock (with "Rebuild" set)
Reference Switch Build History Hold Control Hold Available
History Restored from backup, re-start building procedure.
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Application Notes continued
Holdover History Accumulation Maintenance continued Whenever holdover entered, Active Holdover History that used determine holdover frequency. History_Cmd register allows application issue three holdover history control commands: Save Active Holdover History Backup History. Restore Backup History Active. Flush active History well accumulation register. Backup history remains intact. Both Active Backup holdover histories loaded with calibrated freerun synthesizer control data reset/power-up. application might "save backup" situation where, example, primary reference known higher quality than secondary references, which case desirable save then restore holdover history accumulated primary reference primary reference lost holdover entered upon loss secondary reference. Users restore history from backup time, even while operating Holdover mode. frequency transient will smooth continuous. responsibility application software keep track viability holdover backup history. Given time temperature effects oscillator aging, application wish periodically perform "Save" Active history keep backup current. When switching reference, active holdover history will remain intact marked "Holdover Available" available before reference switch) until history accumulated reference (Typically minutes after lock been achieved). During history accumulation, "Holdover Build Complete" reset. Once history accumulation complete, transferred Active History "Holdover Build Complete" set. active history will then continue updated track reference. History_Policy register allows application control history built. When "Rebuild": History accumulation begins when lock achieved reference. holdover history rebuilt (taking about minutes). Active History remains untouched until replaced when build complete. When policy "Continue": there "Available" Active History, build occurs, under "Rebuild" policy. there "Available" Active History, will continue, accumulation register will loaded from Active History, "Build" process essentially completed immediately following lock reference. "Continue" policy used application example, known that reference switched traced same source therefore likely frequency offset from prior reference. that case, "Continue" policy avoids delay rebuilding holdover history. switch likely between references with known unknown frequency offset, then preferable "Rebuild" policy. time since holdover state entered read from Holdover_Time register. Values from hours, limited 255, reset when holdover state. Boundary Scan IEEE1149.1-2001 (Limited Testability Support) This module exposes boundary scan chain which contains more boundary scan testable IEEE1149.1-2001 complaint devices. exposed boundary scan chain IEEE1149.1-2001 compliant, supports documented testing modes devices contained within chain. Integration this module into existing boundary scan chain will require following. Substitution modules footprint with provided testability model schematic. Modified list will need loaded into boundary scan test vector generation software. Testability Model Schematic BSDL file(s) obtained directly from factory. Control Modes device must operated manual control mode, automatic control reference selection mode. Reset pulled minimum 10mS during chip start-up other desired time) initialize full device state. BITS clock output frequency selected T1/E1 pin. When T1/E1 BITS frequency 1.544 MHz, when T1/E1 BITS frequency 2.048 MHz. MASTER SELECT- Determines master slave mode. master, slave. Master/slave switches should performed with minimal delay between switching states each devices. This easily accomplished, example, controlling master/slave state with single signal, coupled devices through inverter. simplex operation, device should Master mode MASTER SELECT "1".
Data Sheet TM054
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Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Application Notes continued Phase Build-out Operation
General: module, when locked reference maintains fixed phase relationship between input output signals. phase detector used determines this relationship. Typically, would recognize phase change input reference adjust oscillator control maintain same input output relationship. programmed ignore input phase change thereby create phase relationship between input output signals. This particularly useful some applications where desirable pass phase hits inputs through outputs. This process limiting absorbing phase known "Phase Build Out". Requirements: module that supports phase build-out should meet following requirements specified GR-1244, section 5-7. R5-15 Input phase-time changes 3.5us greater over interval less than 0.1seconds less shall built-out stratum clocks reduce resulting clock phase-time change less than 50ns. Phase-time changes 1.0us less over interval 0.1seconds shall built-out." R5-16 Stratum clocks shall perform phase build-out." "Based above requirement, phase-time changes more than 1.0us less than 3.5us that occur over interval less than 0.1seconds built-out". module should show alarms during phase build-out operation. Also module should capable tolerating jitter rate (3.2 perform phase build-out. Module Setup: module, default, does have phase build-out enabled. enabled setting "PHASE BUILD-OUT OPTION" bit, which bit4 BANDWIDTH_PBO register (0x03).
Note: Phase build-out same "Hitless Reference Switching" even though they similar implementation. While phase build-out implemented stratum timing modules higher, hitless reference switching implemented stratum level timing module that accepts more reference inputs. Also, phase build-out used only build-out phase hits that exceed hitless reference switching such limits.
Data Sheet TM054
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Application Notes continued SM3E Application Note Interrupts
SM3/3E module supports eight different interrupts appears INTR_EVENT (0x12) register. Each interrupt individually enabled disabled INTR_ENABLE (0x13) register. Each enables disables corresponding interrupt from asserting SPI_INT pin. Interrupt events still appear INTR_EVENT (0x12) register independent their enable state. interrupts cleared once INTR_EVENT (0x12) register read. interrupts reference changing from available available reference changing from available available M/SREF changing from activity activity M/SREF changing from activity activity DPLL Mode status change Active reference change Loss Signal Loss Lock
Interrupts Reference change Autonomous mode: Interrupts used determine cause reference change autonomous mode. assume that module currently locked REF1. module switches REF2 SPI_INT asserted. user reads INTR_EVENT (0x12) register. module operating autonomous non-revertive mode, cause determined from bits4, indicate Active reference change. then cause reference change Loss Active Reference. then cause reference change Loss Lock alarm active reference. module operating autonomous revertive mode, cause determined from bits indicate Active reference change. Bit6 then cause reference change Loss Active Reference. then cause reference change Loss Lock alarm active reference. then cause reference change availability higher priority reference. Note: DPLL Mode Status Change (Bit also indicate change DPLL_STATUS (0x11) register, during interrupt caused reference change. data DPLL_STATUS (0x11) register however useful determining cause reference change. This because bits0-2 this register always reflects status current active reference hence cannot used determine status last active reference. Interrupts Manual Mode: manual operating mode, when active reference fails Loss Signal Loss Lock alarm, interrupt generated. example, case Loss Signal, bits INTR_EVENT (0x12) register would indicate Loss Signal DPLL Mode Status Change. user choose read DPLL_STATUS (0x11) register, though manual mode bit6 INTR_EVENT (0x12) register mirror DPLL_STATUS (0x11) register. This holds true Loss Lock alarm, where INTR_EVENT (0x12) register mirror DPLL_STATUS (0x11) register.
Data Sheet TM054
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Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Mechanical Specifications Mechanical Dimensions
Figure
2.050 [52.07mm] MAX. .075 [1.91mm]
1.250 [31.75mm] MAX.
1.100 [27.93mm]
.125 [3.17mm] .750 [19.05mm] MAX.
.070 [1.78mm]
.018 [.46mm]
.100 [2.54mm]
Footprint Dimensions
Figure
VIEW
1.300 1.200
CUSTOMER COMPONENT KEEP AREA
HOLE/PAD SIZE PLACES): 0.034" DIA. PLATED HOLE WITH 0.070" DIA. PAD.
0.100 0.000
1.000
1.100
1.200
1.300
1.400
1.500
1.600
1.700
1.800
0.000
0.300
0.400
0.500
0.600
0.700
0.800
0.900
Data Sheet TM054
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2.100
Mechanical Specifications continued Required External Components
Place series resistors ohms) reference inputs (Pins 15-18). Place series resistors ohms) SPI_IN SPI_CLK inputs (Pins 26). Place .01uF 47-100uF capacitor input power (Pin 27). 4.7uF (25V) capacitor required (Pin 14). 4.7uF (25V) capacitor required (Pin 19).
Layout Recommendations
Orient module airflow parallel along header strips (pins). Place de-coupling and/or filter components close module pins possible. place components directly beneath module topside host PCB. Ensure that only clean well-regulated power supplied module. Isolate power ground inputs module from noisy sources. Provide power ground connections through 0.050" wide trace (minimum) using 1-oz. equivalent copper feature (i.e. internal plane, copper area fill, etc.). Keep module signals away from sensitive noisy analog digital circuitry. Avoid split ground planes high-frequency return currents affected. Allow extra spacing between traces high-frequency inputs outputs. 10.Keep traces short possible avoid meandering trace paths. 11.Avoid routing signals directly beneath module topside host PCB. 12.If possible, provide copper area directly beneath module topside host PCB. Connect this copper area ground. 13.It recommended that connections JTAG, pins routed pads, preferably pattern shown Figure below. recommended 0.1" center center spacing.
Figure
Optional Socket Mounting Recommendations
Mating sockets used permanent installation module desired. possible sources these sockets include: Samtec, "Low Profile Socket Strips", Series, SL-116-G-19. (http://www.samtec.com/) Mill-Max, "Single-In-Line Sockets", Series, 315-xx-116-41-001. (http://www.mill-max.com/) SM3E requires 16-pin sockets. optional dual footprint configuration shown Figure requires 14-pin 16-pin sockets.
Data Sheet TM054
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Page Rev: Date: 11/07/08
Mechanical Specifications continued Optional SM3/SM3E Dual Footprint
dual footprint configuration used when designing host circuit board containing Connor Winfield SM3E modules. smaller contains subset signal pins found larger SM3E locations which allow simple dual footprint arrangement like shown Figure
SM3E
REF1 REF2 REF3 REF4 TRST BITS_CLK M/S_OUT OUTPUT1 REF5 REF6
MASTER SELECT SPI_INT SPI_OUT RESET SPI_ENBL SPI_IN
(TOP VIEW)
SPI_CLK HOLD_GOOD T1/E1 REF7 REF8
0.850" 1.100"
Figure
modules shown Figure arranged left-justified fashion. Notice that right justified center justified (with additional column pins) arrangements also possible, depending designer's preference. Placement external components Place series resistors ohms) source reference input (SM3 Pins SM3E Pins 15-18). Place series resistors ohms) source SPI_IN SPI_CLK inputs (SM3 Pins 21,22, SM3E Pins 26). Place .01uF 47-100uF capacitor input power (SM3 SM3E 27). 4.7uF (25V) capacitor required (SM3 SM3E 14). 4.7uF (25V) capacitor required (SM3 SM3E 19). sure consult Connor Winfield's respective datasheets additional mechanical, electrical, footprint keep-out information.
Data Sheet TM054
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Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
SM3E Reference Design
Figure
INPUT TRST BITS_CLK M/S_OUT OUTPUT1 XREF REF1 REF2 REF3 REF4 TRST BITS_CLK M/S_OUT OUTPUT1 REF5 REF6 SM3E_MODULE BRDVCC_3.3 THFB1608K-301T10 SPI_INT SPI_OUT RESET SPI_ENBL 3.3V SPI_IN SPI_CLK HOLD_RDY BITS_SEL REF7 REF8 HOLD_GOOD T1/E1 SPI_INT SPI_OUT RESET SPI_ENBL SPI_IN SPI_CLK
10uF
0.01uF
NOTES: recommended that incoming References terminated source 33ohm resistors.
Data Sheet TM054
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Optional Programing Header Reference Design
Figure
VDDP VDDP TRST
4.7uF TRST
4.7uF
4.7uF (low ESR, <1W, Tantalum, greater rating) *Not required header installed.
FTSH-113-01-L-D-K
SAMTEC
programming header optional. provides means re-programming chip board necessary. SAMTEC header notch should laid such that notch pin1 side. header specified here thru-hole part surface mount versions available. Please refer www.samtec.com more information header.
Ordering Information
SM3E-XXX.XXM Replace XXX.XX with following available frequencies, 012.96MHz, 019.44MHz, 025.92MHz, 038.88MHz, 051.84MHz 077.76MHz. Please contact Connor-Winfield other frequencies that available. Similar Products from Connor-Winfield SM3-XXX.XXM Stratum module with input references. SM3-8R-XXX.XXM Stratum module with input references. SM3-IT-XXX.XXM Industrial temperature rated Stratum module with input references.
Data Sheet TM054
Page Rev: Date: 11/07/08
Copyright 2008 Connor-Winfield Corp. Rights Reserved Specifications subject change without notice
Revision
Revision Date
03/31/05 08/11/05 11/07/08
Note
Final Release Data Sheet Corrected Typographical Errors Added Input Pulse Width Spec Table

SM3E Timing Module complete system clock module Stratum timing applica

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