High-performance 32-bit Instruction Thumb® High-code-density 16-bit In

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High-performance 32-bit Instruction Thumb® High-code-density 16-bit In

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Based ARM® SC100SecureCore32-bit RISC Processor Instruction Sets
High-performance 32-bit Instruction Thumb® High-code-density 16-bit Instruction Neumann Load/Store Architecture Single 32-bit Data Instructions Data 3-stage Pipeline Architecture Fetch, Decode, Execute Stages 8-bit, 16-bit, 32-bit Data Types On-chip Programmable System Clock 38MHz Very Power Consumption Industry Leader MIPS/Watt power Idle Power down Modes Bond Locations Confirming ISO7816-2 Protection ±6000V Operating range: 1.62V 5.5V Compliant with GSM, Industry Compatible,
32-bit Secure Microcontrollers AT91SC464384RCU Summary
Memory
464K Bytes Program Memory 384K Bytes EEPROM, Including Bytes
Typically More than 500,000 Write/Erase Cycles Temperature 25°C Years Data Retention EEPROM Erase Only Mode Write EEPROM With Without Autoerase Bytes Bytes shared with AdvXcrypto processor) Bytes dedicated Atmel's crypto Library
Peripherals
7816 Controller
Kbps Single Wire Interface (Digital Interface front chip) 16-bit Timers Random Number Generator (RNG) 2-level, 15-vector Interrupt Controller Hardware Triple (DPA Resistant) Checksum Accelerator CRC16 Engine 32-bit Cryptographic Accelerator Public Operations RSA, DSA, ECC, Diffie-Hellman High performance Hardware Java Card Accelerator
6546A-SPD-29Mar07
Note: This summary document. complete document will available under NDA. more information, please contact your local Atmel sales office.
Security
Dedicated Hardware Protection Against SPA/DPA Attacks Protection Against Physical Attack Environmental Protection Systems Voltage, Frequency, Light, Temperature Protection Systems Secure Memory Management/Access Protection
Development Tools
Hardware Development Support ATV4-91SC Voyager Emulation Platform Software Libraries Application Notes
Description
AT91SC464384RCU power, high performance, 32-bit RISC microcontroller with program memory, EEPROM data memory, cryptographic accelerator, based SC100 advanced secure processor. This general purpose 32-bit processor offers high performance, very power consumption, additional features help combat fraud. AT91SC464384RCU features 384K bytes high performance EEPROM (fast erase/write time, high endurance). SC100s MPU, real hardware firewall used increase overall security level application without intense software development. cryptographic accelerator featured AT91SC series AdvX., N-bit multiplier-accumulator dedicated performing fast encryption authentication functions. AdvX based custom 32-bit co-processor, thus enabling fast computation power operation. AdvX conjuction with controlling firmware running within SC100 core, supports standard finite arithmetic functions (including RSA, DSA, ECC) GF(2N). Unique hardware features significantly accelerate execution Java Card Byte Code removing common software bottlenecks encountered during implementation Java Virtual Machine. Additional security features include power frequency protection logic, logical scrambling program data addresses, power analysis countermeasures, memory access controlled supervisor mode.
AT91SC464384RCU
6546A-SPD-29Mar07
AT91SC464384RCU
Configuration
AT91SC512384RCT pinout configuration confirms ISO7816-2 interface. Note: convention, corresponds signal ISO7816-3 Protocol, both active low.)
I/O0 Ground (reference voltage) Power Supply Input Input Output serial data (ISO7816 Clock signal input external clock operating circuit Reset signal input, state stops core dedicated
Architectural Overview
SC100 stage pipeline, 32-bit RISC processor. uses Neumann Load/store architecture, this architecture characterized single data address instruction data. SC100 processor employs unique architectural strategy known Thumb®, super reduced instruction that ideally suited high volume applications with memory restrictions, applications where code density important factor. Essentially, SC100 processor instruction sets: standard instruction using 32-bit instructions offering maximum performance Thumb instruction using 16-bit instructions offering maximum code density Both instruction sets operate 8-bit, 16-bit 32-bit data types. Thumb's 16-bit instruction length allows achieve almost twice density standard code, whilst retaining most performance advantage over traditional 16-bit processor using 16-bit registers. This possible because 16-bit Thumb instructions operate same 32-bit register 32-bit instruction set. Thumb code smaller than equivalent code, whilst providing 160% performance equivalent processor connected 16-bit memory system. Figure shows block diagram AT91SC464384RCU device.
6546A-SPD-29Mar07
Figure AT91SC464384RCU block diagram
8/16/32 EEPROM Memory Program Memory 8/16/32 Acce lerator
AdvX ptoAcce lerator
Control
Circuit
DES/3DES
CRC16&32 Engine
On-chip security (SPA, DPA, I/O0 Firewall
Timer
SC100TMore
7816 Controller 7816 I/O0
Thumb Instruction decompressor Pipeline
AT91SC464384RCU
6546A-SPD-29Mar07
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6546A-SPD-29Mar07

High-performance 32-bit Instruction Thumb® High-code-density 16-bit In

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