Core mAgicV VLIW Magic DSPfamily, optimized Audio, Communication Beam-

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DIOPSIS® Dual Core System Integrating ARM926EJ-SARM® Thumb® Processor
Core mAgicV VLIW Magic DSPfamily, optimized Audio, Communication Beam-forming Applications High Performance MagicV VLIW GFLOPS Gops Master Port, integrated Engine Slave Port Arithmetic Operations Cycle Multiply, Add/subtract, Add, Subtract 40-bit Floating Point 32-bit Integer) Allowing Single Cycle Butterfly Native Support Complex Arithmetic Vectorial SIMD Operations: Complex Multiply with Dual Add/sub Clock Cycle Real Multiply Add/sub Simple Scalar Operations 32-bit Integer IEEE® 40-bit Extended Precision Floating Point Numeric Format 16-port Data Register File: Registers Organized 128-register Banks 5-issue predicated VLIW Architecture with Orthogonal ISA, Code Compression Hardware Support Code Efficient Software Pipeline Loops Accesses Cycle Data Memory System Accesses Cycle VLIW Operations Accesses Cycle Transfers) supported Flexible Addressing Capability Independent Address Generation Units Operating Registers Address Register File Supporting Complex Micro-Vectorial Accesses, features: Programmable Stride Circular Buffers Mbits On-chip SRAM: 40-bit Data Memory Locations Memory Accesses Cycle) 128-bit Dual Port Program Memory Location, Equivalent ~50K Assembler Instructions (typical) thanks Code Compression Pipelining Access External Program Data Memory Three Main Operating Modes: Run, Debug Sleep Modes User Mode Privileged Interrupt Service Mode Efficient Optimizing Assembler C-Oriented Architecture: Allows Easy Exploitation Available Hardware Parallelism ARM926EJ-S Thumb Processor instruction extensions Jazelle® Technology Java® Acceleration 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer 220MIPS 200MHz Memory Management Unit EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support Efficient Interface through master slave ports, Memory Mapped Registers Ports, Interrupt Lines Semaphores Additional Embedded Memories 32-KByte internal ROM, two-cycle access maximum speed 48-KByte internal SRAM, single-cycle access maximum processor speed External Interface (EBI) Supports SDRAM, Static Memory, SmartMedia® NAND Flash, CompactFlash® Full Speed Mbits second) Host Double Port
DIOPSIS 940HF
ARM926EJ-S PLUS GFLOPS
AT572D940HF Preliminary Summary
NOTE: This summary document. complete document available under NDA. more information, please contact your local Atmel sales office.
7010AS-DSP-07/07
Dual On-chip Transceivers Integrated FIFOs Dedicated Channels Full Speed Mbits second) Device Port On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs dedicated channels Ethernet 10/100 Reduced Media Independent Interface (RMII) Physical Layer Integrated channel Matrix Seven Masters Five Slaves Handled Boot Mode Select Option Remap Command System Controller (SYSC) Reset Controller Periodic Interval Timer, Watchdog Real-Time Timer Power Management Controller (PMC) Very Slow Clock (32768Hz) Operating Mode Software Programmable Power Optimization Capabilities On-chip Oscillator PLLs Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Three External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected Three 32-bit Parallel Input/Output Controllers (PIO) Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up resistor Synchronous Output Twenty-three Peripheral Data Controller (PDC) Channels Debug Unit (DBGU) 2-wire USART support Debug Communication Channel, Programmable Access Prevention dedicated channels Four Synchronous Serial Controllers (SSC) Independent Clock Frame Sync Pair Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer dedicated channels each Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation Support ISO7816 T0/T1 Smart Card, Hardware Software Handshaking, RS485 Support dedicated channels each USART Master/Slave Serial Peripheral Interface (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects dedicated channels each Three-channel 16-bit Timer/Counters (TC) Three External Clock Inputs, multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Two-Wire Interfaces (TWI) Master Mode Support, Two-wire Atmel EEPROM's Supported Interfaces Fully compliant with Part Part
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Multimedia Card Interface (MCI)
Automatic Protocol Control Fast Automatic Data Transfers with PDMA, SDCard Compliant
IEEE 1149.1 JTAG Boundary Scan Digital Pins Required Power Supplies:
1.1V 1.2V VDDCORE VDDOSC 3.3V VDDPLLA 3.3V VDDIOP (Peripheral I/Os) VDDIOM (Memory I/Os) Available 324-ball CABGA Package
7010AS-DSP-07/07
Description
DIOPSIS 940HF Dual Processor integrating mAgicV VLIW ARM926EJS RISC MCU, plus total Kbytes SRAM. system combines flexibility ARM926RISC controller with very high performance DSP. mAgicV high performance VLIW Magic family, delivering Giga floatingpoint operations second (GFLOPS) Gops clock rate MHz. equipped with master port slave port system-on-chip integration. data registers, address registers, independent arithmetic operating units, independent address generation units engine. sustain internal parallelism, data bandwidth among Register File, Operators Data Memory System, bytes/cycle. Data Memory System designed transfer bytes/cycle. instance, mAgicV produce complete butterfly cycle activating computing units. mAgicV operates IEEE 40-bit extended precision floating-point 32-bit integer numeric format numerical computations, while internal memory accesses supported powerful 16-bit MAGU (Multiple Address Generation Unit). also on-chip 40-bit 6-access/cycle data memory system 128-bit dual port program memory locations. Efficient usage internal program memory achieved through general purpose code compression mechanism software pipelining support systematic loops. C-oriented architecture optimizing assembler ease user from burden dealing with parallelism processor resources significantly simplifies code development. rich library C-callable routines available. ARM926 embedded micro controller core member Advanced RISC Machines (ARM) family general purpose 32-bit microprocessors, which offer high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than micro programmed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response. ARM926 supports 16-bit Thumb subset most commonly used 32-bit instructions. These expanded time with degradation system performance. This gives 16-bit code density (saving memory area cost) coupled with 32-bit processor performance. rich peripherals Kbytes internal memory provide highly flexible integrated system solution. ARM926EJ-S supports Jazelle technology Java acceleration.
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Ball Configuration
Table 2-1.
Name A0/NBS0 A1/NBS2/NWR2 A16/SD_BA0 A17/SD_BA1 A_JCFG A_RTCK A_TCK A_TDI A_TDO A_TMS A_NTRST
AT572D940HF Ball Assignment (I/O: balls)
Name M_NTRST M_TCK M_TDI M_TDO M_TMS NCS0 NCS1/SD_CS Name NCS2 NCS3/SM_NCS NRD/NOE/CF_NOE NRST NWR0/NWE/CF_NWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW PIOA0 PIOA1 PIOA2 PIOA3 PIOA4 PIOA5 PIOA6 PIOA7 PIOA8 PIOA9 PIOA10 PIOA11 PIOA12 PIOA13 PIOA14 PIOA15 PIOA16 PIOA17 PIOA18 PIOA19 PIOA20 PIOA21 PIOA22 PIOA23 PIOA24 PIOA25 PIOA26 Name PIOA27 PIOA28 PIOA29 PIOA30 PIOA31 PIOB0 PIOB1 PIOB2 PIOB3 PIOB4 PIOB5 PIOB6 PIOB7 PIOB8 PIOB9 PIOB10 PIOB11 PIOB12 PIOB13 PIOB14 PIOB15 PIOB16 PIOB17 PIOB18 PIOB19 PIOB20 PIOB21 PIOB22 PIOB23 PIOB24 PIOB25 PIOB26 PIOB27 PIOB28
7010AS-DSP-07/07
Table 2-1.
Name PIOB29 PIOB30 PIOB31 PIOC0 PIOC1 PIOC2 PIOC3 PIOC4 PIOC5 PIOC6 PIOC7 PIOC8 PIOC9 PIOC10
AT572D940HF Ball Assignment (I/O: balls) (Continued)
Name PIOC11 PIOC12 PIOC13 PIOC14 PIOC15 PIOC16 PIOC17 PIOC18 PIOC19 PIOC20 PIOC21 PIOC22 PIOC23 PIOC24 Name PIOC25 PIOC26 PIOC27 PIOC28 PIOC29 PIOC30 PIOC31 PLL_RCA PLL_RCB SD_A10 SD_CK SD_CKE SD_NCAS SD_NRAS Name SD_NWE TEST USBD_DM USBD_DP USBHA_DM USBHA_DP USBHB_DM USBHB_DP XOUT X32EN X32IN X32OUT
Table 2-2.
Name VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDIOM VDDIOM
AT572D940HF Ball Assignment (Power Ground: balls)
Name VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOMP VDDIOMP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Name VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDOSC32 VDDOSCM Name VDDPLLA
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 2-2.
Name
AT572D940HF Ball Assignment (Power Ground: balls) (Continued)
Name Name Name GNDOSC32 GNDOSCM GNDPLLA
pins comprised Table Table "not connected".
Name Conventions
names built using following structure: (functional block name) (activity level) (line name) (bus index) where: functional block name name related functional block (when global function) activity level active lines; blank high active lines line name name function line index number corresponding index when line element
7010AS-DSP-07/07
Description
Table 3-1.
Module JTAG JTAG JTAG JTAG JTAG JTAG Logic Logic Logic Logic Logic Logic Logic DBGU DBGU
AT572D940HF Description
Name EXT_IRQ0 EXT_IRQ2 M_MODE M_SIRQ0 M_SIRQ3 A_JCFG A_RTCK A_TCK A_TDI A_TDO A_TMS CAN0_RX CAN0_TX CAN1_RX CAN1_TX CF_NCE1CF_NCE2 CF_NOE CF_NWE CF_NIOR CF_NIOW CF_RNW CF_NCS0 CF_NCS1 DBG_RXD DBG_TXD NWAIT E_RXER Function External Interrupt Request Interrupt Request from mAgicV Generic Interrupt Request from mAgicV JTAG Chip Boundary Scan select JTAG Returned Test Clock JTAG Test Clock JTAG Test Data Input JTAG Test Data Output JTAG Test Mode Select Data Data Data Data CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash Read CompactFlash Write CompactFlash Read Write CompactFlash Chip Select Debug Serial Line Data Debug Serial Line Data Address Address Data External Wait Signal Boot Memory Select Ethernet RMII Receive Error bi-03 Type bi-03 bi-03 bi-03 out-03 out-03 bi-03 bi-03 bi-03 bi-03 bi-03 out-03 out-03 out-03 out-03 bi-03 bi-03 bi-03 bi-03 out-03 bi-03 bi-03 output through line output through line input through line output through line reset output through line reset Pulled-up input reset input through line input through line external boot selected internal boot selected input through line pull-up resistor input through line output through line input through line output through line output through line pull-up resistor pull-up resistor Active Level Notes input through line output through line output through line internal pull-down resistor (ARM JTAG selected)
bi-03
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 3-1.
Module JTAG JTAG JTAG JTAG JTAG
AT572D940HF Description (Continued)
Name E_TXD0 E_TXD1 E_TXEN E_REFCK E_CRSDV E_RXD0 E_RXD1 E_FCE100 E_MDIO E_MDCK MCCK MCCDA MCDA0MCDA3 M_NTRST M_TCK M_TDI M_TDO M_TMS XOUT X32IN X32OUT X32EN PIOA0 PIOA31 PIOB0 PIOB31 PIOC0 PIOC31 PLL_RCA PLL_RCB A_CK Function Ethernet RMII Transmit Data Ethernet RMII Transmit Enable Ethernet RMII Reference Clock Ethernet RMII Carrier Sense/Data Valid Ethernet RMII Receive Data Ethernet RMII Force Mb/s operation Ethernet RMII Management Data Ethernet RMII Management Clock Multimedia Card Clock Multimedia Card Command Multimedia Card Data mAgicV JTAG Test Reset mAgicV JTAG Test Clock mAgicV JTAG Test Data Input mAgicV JTAG Test Data Output mAgicV JTAG Test Mode Select Main Oscillator Quartz Main Oscillator Quartz Slow Clock Oscillator Quartz Slow Clock Oscillator Quartz Slow Clock Oscillator Enable Parallel Input/Output Parallel Input/Output Parallel Input/Output Filter Filter Clock Type bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 out-03 bi-03 bi-03 bi-03 bi-03 left floating (test input) output through line test purpose high internal pull-up resistor (internal oscillator enabled) general purpose programmable I/Os peripheral I/Os; Pulled-up input reset general purpose programmable I/Os peripheral I/Os; Pulled-up input reset general purpose programmable I/Os peripheral I/Os; Pulled-up input reset pull-up resistor pull-up resistor pull-up resistor high Active Level Notes output through line output through line input through line input through line input through line output through line through line output through line through line through line through line
7010AS-DSP-07/07
Table 3-1.
Module SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC Logic Logic
AT572D940HF Description (Continued)
Name M_CK P_CK0-P_CK3 SDCK SD_CKE SD_NCS SD_BA0 SD_BA1 SD_NWE SD_NRAS SD_NCAS SD_A10 NCS0 NCS3 NCS4 NCS7 NWR0 NWR3 NBS0 NBS3 SM_NOE SM_NWE SPI0_MOSI Function mAgicV Clock Programmable Clock SDRAM Clock Output SDRAM Clock Enable SDRAM Chip Select SDRAM Bank Select SDRAM Write Enable Column Address Strobe SDRAM Address Chip Select Signal Chip Select Signal Write Signal Output Enable Read Signal Write Enable Byte Select SmartMedia Output Enable SmartMedia Write Enable Master Out/Slave data Type bi-03 bi-03 out-03 out-04 out-03 out-03 out-04 out-04 out-04 out-03 bi-03 out-03 out-03 out-03 out-03 out-03 bi-03 bi-03 bi-03 reset; reset output through line reset reset reset reset reset output through line output through line through line data input data output through line data output data input through line Input Output output through line n.a. Outputs through line clock input clock output high Active Level Notes output through line test purpose output through line
SPI0_MISO
Master In/Slave data
bi-03
SPI0_NCS0
Input/Output Chip select
out-03
SPI0_NCS1 SPI0_NCS3
Output Chip Selects
bi-03
SPI0_CK
Serial clock
bi-03
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 3-1.
Module
AT572D940HF Description (Continued)
Name SPI1_MOSI Function Master Out/Slave data Type bi-03 Active Level Notes through line data input data output through line data output data input through line Input Output output through line n.a. Outputs through line clock input clock output output through line input through line through line through line through line through line output through line input through line through line through line through line through line output through line through line
SPI1_MISO
Master In/Slave data
bi-03
SPI1_NCS0
Input/Output Chip select
out-03
SPI1_NCS1 SPI1_NCS3
Output Chip Selects
bi-03
SPI1_CK
Serial clock Synchronous Serial Controller Data Synchronous Serial Controller Data Synchronous Serial Controller Transmit Frame Clock Synchronous Serial Controller Receive Frame Clock Synchronous Serial Controller Transmit Clock Synchronous Serial Controller Receive Clock Synchronous Serial Controller Data Synchronous Serial Controller Data Synchronous Serial Controller Transmit Frame Clock Synchronous Serial Controller Receive Frame Clock Synchronous Serial Controller Transmit Clock Synchronous Serial Controller Receive Clock Synchronous Serial Controller Data Synchronous Serial Controller Transmit Frame Clock
bi-03
SSC0_TXD SSC0_RXD SSC0_TF SSC0_RF SSC0_TK SSC0_RK SSC1_TXD SSC1_RXD SSC1_TF SSC1_RF SSC1_TK SSC1_RK SSC2_TXD SSC2_TF
bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03
7010AS-DSP-07/07
Table 3-1.
Module SYSC USBD USBD USBH
AT572D940HF Description (Continued)
Name SSC2_RF SSC2_TK SSC2_RK SSC2_RXD SSC3_TXD SSC3_RXD SSC3_TF SSC3_RF SSC3_TK SSC3_RK NRST TC_OUT_A0 TC_OUT_A1 TC_OUT_A2 TC_OUT_B0 TC_OUT_B1 TC_OUT_B2 TC_IN_0 TC_IN_1 TC_IN_2 TEST TW0_D TW0_CK TW1_D TW1_CK USBD_DM USBD_DP USBHA_DM Function Synchronous Serial Controller Receive Frame Clock Synchronous Serial Controller Transmit Clock Synchronous Serial Controller Receive Clock Synchronous Serial Controller Data Synchronous Serial Controller Data Synchronous Serial Controller Data Synchronous Serial Controller Transmit Frame Clock Synchronous Serial Controller Receive Frame Clock Synchronous Serial Controller Transmit Clock Synchronous Serial Controller Receive Clock Chip Reset Timer Counter Timer Counter Timer Counter Timer Counter Timer Counter Timer Counter Timer Counter Timer Counter Timer Counter Test Mode Select Wire Data Wire Clock Wire Data Wire Clock Device Port Data Device Port Data Host Port Data Type bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 usb-bi usb-bi usb-bi high Active Level Notes through line through line through line input through line output through line input through line through line through line through line through line open drain through line bidirectional through line bidirectional through line bidirectional through line bidirectional through line bidirectional through line input through line input through line input through line pull-down resistor (Functional Mode selected) bidirectional through line bidirectional through line bidirectional through line bidirectional through line
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Table 3-1.
Module USBH USBH USBH USART USART USART USART USART USART USART USART USART USART USART USART USART USART USART Power Power Power Power Power Power Ground Ground Ground Ground
AT572D940HF Description (Continued)
Name USBHA_DP USBHB_DM USBHB_DP USART0_RXD USART0_TXD USART0_SCK USART0_CTS USART0_RTS USART1_RXD USART1_TXD USART1_SCK USART1_CTS USART1_RTS USART2_RXD USART2_TXD USART2_SCK USART2_CTS USART2_RTS VDDCORE VDDIOP VDDIOM VDDOSC32 VDDOSCM VDDPLLA GNDOSC32 GNDOSCM GNDPLLA Function Host Port Data Host Port Data Host Port Data USART Data USART Data USART Serial clock USART Clear send USART Request send USART Data USART Data USART Serial clock USART Clear send USART Request send USART Data USART Data USART Serial clock USART Clear send USART Request send Core power supply Peripherals Lines Power Supply Lines Power Supply 32KHz Oscillator Power Supply Main Oscillator PLLB Power Supply PLLA power supply Core Ground 32KHz Oscillator Ground Main Oscillator PLLB Ground PLLA Ground Type usb-bi usb-bi usb-bi bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 Power Power Power Power Power Power Ground Ground Ground Ground input through line bidirectional through line bidirectional through line synchronous mode only input through line output through line input through line bidirectional through line bidirectional through line synchronous mode only input through line output through line input through line bidirectional through line bidirectional through line synchronous mode only input through line output through line 1.1V 1.2V 3.3V 3.3V 1.1V 1.2V 1.1V 1.2V 3.3V Active Level Notes
7010AS-DSP-07/07
Block Diagram
Figure 4-1. AT572D940HF Architecture
ARM926EJ-S
JTAG
Instruction Cache bytes Data Cache bytes
D0-D31 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A21 A16/SD_BA0 A17/SD_BA1 NCS0 NCS1/SD_NCS NCS2 NCS3/SM_NCS NRD/NOE/CF_NOE NWR0/NWE/CF_NWE NWR1/NBS1/CF_NIOR NWR3/NBS3/CF_NIOW SD_CK SD_CKE SD_NRAS-SD_NCAS SD_NWE SD_A10 A22-A25/CF_RNW NCS4/CF_NCS0 NCS5/CF_NCS1 CF_NCE1 CF_NCE2 NCS6/SM_NOE NCS7/SM_NWE NWAIT
A_JCFG A_TDI A_TMS A_RTCK A_TCK A_TDO
CompactFlash SmartMedia NAND Flash
NRST TEST VDDCORE
SYSC
CNTL
ITCM DTCM
X32IN X32OUT X32EN XOUT PLL_RCA PLL_RCB A_CK M_CK PCK0-PCK3
Fast SRAM Kbytes
SDRAM CNTL
MAIN
Fast Kbytes
Static Memory CNTL
Peripheral Bridge
EXT_IRQ0-EXT_IRQ2
MATRIX
FIFO
TRANSCEIVER
USBHA_M USBHA_P USBHB_M USBHB_P
HOST
DBG_TXD DBG_RXD
DBGU
USARTx_TXD USARTx_RXD USARTx_SCK USARTx_CTS USARTx_RTS
USART 0-1-2
mAgic JTAG
M_TDI M_TMS M_NTRST M_TCK M_TDO
SPIx_MOSI SPIx_MISO SPIx_NCS0 SPIx_NCS1-SPIx_NCS3 SPIx_CK
mAgic
memories
M_MODE M_SIRQ0-M_SIRQ3
PIOx
A-B-C Controllers
FIFO RMII
TWx_CK TWx_D
SSCx_RXD SSCx_TXD SSCx_TF SSCx_TK SSCx_RF SSCx_RK
E_MDIO E_MDC E_FCE100 E_RXER E_TX0-E_TX1 E_TXEN E_REFCK E_CRSDV E_RX0-E_RX1
PIOx
0-1-2-3
Timer Counter
MCCK MCCDA MCDA0-MCDA3
TC_OUT_A_0 TC_OUT_A_1 TC_OUT_A_2 TC_OUT_B_0 TC_OUT_B_1 TC_OUT_B_2 TC_IN_0 TC_IN_1 TC_IN_2
CANx_RX CANx_TX
FIFO DEVICE
TRANSCEIVER
USBD_M USBD_P
AT572D940HF Preliminary
7010AS-DSP-07/07
AT572D940HF Preliminary
Architectural Overview
DIOPSIS (also named D940HF) high performance dual-core processing platform audio, communication beam-forming applications, integrating floating-point (mAgicV VLIW DSP) ARM926EJ-S Reduced Instruction Computer (RISC). D940HF optimally suited floating point applications with significant need complex domain computations like frequency domain phase-shift algorithms, requiring high dynamic range maximum numerical precision. D940HF combines flexibility ARM926 RISC controller with very high performance oriented VLIW architecture mAgicV.
System management
availability standard RISC on-chip lowers software development effort critical control segments application. ARM926 features virtual memory sophisticated memory protection, making ideal platform operating systems such WinCE Linux. This leaves mAgicV fully available numerically intensive part application. synchronization between processors either based interrupts software polling semaphores. ARM926 D940HF master processor. bootstrap sequence D940HF starts from bootstrap ARM926 from internal external non-volatile memory. then boots mAgicV from non-volatile memory. After bootstrap D940HF start normal operations. side many applications implemented D940HF using only internal memory. fact, program memory size 128-bit coupled with availability general purpose code compression software pipelining systematic loops, gives equivalent on-chip program memory size about cycles, corresponding ~50K assembler instructions (typical).
AMBA Architecture
architecture based AMBAbus: multilayer matrix APB. matrix consists seven masters: ARM926 Instruction ARM926-Data Peripheral Data Controller (PDC) mAgicV Host Ethernet 10/100 mAgicV JTAG five slaves: ARM926 SRAM ARM926 mAgicV Registers Memories Host Registers External Interface AHB-APB bridge
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mAgicV VLIW Processor
mAgicV VLIW numeric processor D940HF. operates IEEE 40-bit extended precision floating-point 32-bit integer numeric format. main components subsystem core processor, on-chip memories, engine master slave interfaces. operators block, register file, multiple address generation unit program decoding sequencing unit computing part core processor. short description each block given following paragraphs. Figure 5-1. mAgicV Block Diagram
layer-y layer-x
Multi Layer System
2-port, 8Kx128-bit, VLIW Program Memory VLIW Decompressor Flow Controller, VLIW Decoder Program Condition Status Instruction Counter Generation Register Decoder
Master Engine
Slave, e.g. Target
16-port 256x40-bit Data Register File System
4-address/cycle Multiple Address Generation Unit multi-field Address Register File
6-access/cycle Data Memory System 16Kx40-bit
Operators: 10-float ops/cycle
5.3.1
RISC-like VLIW mAgicV Very Long Instruction Word engine, from user point view, works like RISC machine implementing triadic computing operations data coming from register file, data move operations between local memories register file. operators pipelined maximum performance. pipeline depth depends operator used. scheduling parallelism operations automatically defined managed compile time assembler-optimizer, allowing efficient code execution. architecture designed efficient C-language support. 16-port, 256x40-bit Data Register File System order provide optimal data bandwidth give best support RISC-like programming model, mAgicV arithmetic computations supported 16-ported, 256x40-bit entries, Data Register File System. Data Register File also viewed complex 128-entry register file. used complex register file (real imaginary part), dual register file vectorial operations. When performing scalar instructions real domain, register file used ordinary register file. Both even sides register file 9-ported (4-read ports 4-write ports computing/move operations port independent debug access), making total ports available data
5.3.2
AT572D940HF Preliminary
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AT572D940HF Preliminary
move from operators block memory, plus ports debug accesses. total data bandwidth between register file, operators block data memory bytes clock cycle, thus avoiding bottlenecks data flow inside VLIW core. Operators block, Data Register File, Multiple Address Generation Unit FlowController computing part core processor. core integrated with 6access/cycle, 16Kx40-bit on-chip Data Memory System 2-port, 8Kx128-bit on-chip VLIW Program Memory. mAgicV VLIW equipped with integrated master Engine plus Slave interface. 5.3.3 Operators Block Operators Block contains hardware that performs arithmetical operations. works 32-bit signed integers IEEE extended precision 40-bit floating-point data. Operators Block composed four integer/floating point multipliers, adder, subtractor add-subtract integer/floating point units; moreover, shift/logic units, Min/Max operator seed generators efficient division inverse square root computation. operators block arranged order natively support complex arithmetic (single cycle complex multiply multiply add), fast (single cycle butterfly computation) vectorial computations (e.g. Audio Stereo Channel support). peak performance mAgicV achieved during single cycle butterfly execution, when mAgicV delivers floating-point operations clock cycle. 6-port On-Chip Data Memory System Data Memory System mAgicV contains 16K*40-bit on-chip memory locations supporting accesses/cycle. 4-accesses/cycle reserved activities driven Multiple Address Generation unit mAgicV: these accesses reserved computing part core. access/cycle assigned serve activity launched core itself, through mAgicV master port. additional access/cycle simultaneously requested external devices through mAgicV slave port (e.g data exchange with interfaces converters). Data Memory System physically organized using banks (assigned even addresses) quadruple-port memories. total bandwidth available bytes/cycle; computing part core bytes clock cycle, allowing full speed implementation numerically intensive algorithms (e.g. complex FIR), plus bytes/cycle assigned master slave interfaces. Multiple Address Generation Unit (MAGU) core access vectorial single data stored Data Memory. Accessing complex data equivalent accessing vectorial data pair consecutive even addresses pointing pair banks). vectorial mode, Multiple Address Generation Unit (MAGU) able generate addresses/cycle: pairs vectorial addresses, access Data Memory System reading consecutive pair memory locations address writing consecutive pair memory locations. MAGU also generate combination scalar accesses Data Memory System (Read-Read, Read-Write, Write-Write pair single location accesses), combination vectorial access scalar access. MAGU supports linear addressing oriented features like stride access circular buffers. address generation unit supported multi field addressing registers each composed 16-bit individually addressable registers, total signed 16-bit integer registers. Registers named A0-A15 used storage pointers, while registers M0-M15 16-bit integer modifiers. circular buffers, S0-S15 store Start Addresses buffers, L0-L15 initialized with circular buffer lengths. MAGU
5.3.4
5.3.5
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also used perform 16-bit signed integer arithmetic operations parallel with activities operators block (40-bit floating point signed integer operations). MAGU also performs loop control computations needed verify loop reached. 5.3.6 Flow Controller Flow Controller dedicated program address generation, conditioning, predication software pipelining systematic loops. Program Address Generation Unit devoted control correct Program Counter generation according program flow. generates addresses linear code execution well non-sequential program flow. Condition Generation Unit combines flags generated operators MAGU produce complex conditions flags used control program execution. Program Address Generation Unit also allows perform conditioned unconditioned branch instructions, loops, call subroutines return from subroutines. Dual-Port On-Chip Program Memory Program Memory stores VLIW program executed mAgicV. words 128-bit dual port memory. port driven Flow Controller fetch compressed VLIW word. other port accessed engine, supported master interface, external devices through mAgicV slave port. predicated VLIW Issues every cycle, typical mAgicV VLIW instruction activates issues named AGU0, AGU1, ADD, MULT FLOW. first issues associated pair independent Address Generation Units MAGU. third issue drives Arithmetic Add/Subtract section Operators Block, fourth drives Multiplier section, last issue drives Flow Controller. Each issue predicated specific predication field, conditional execution without pipeline breaking penalties. Using different instruction formats, VLIW word also contain initialization requests engine, single cycle loading multiple immediate values other service instructions. Software pipelining Software pipelining systematic loops optimally supported dedicated engine which activates VLIW issues only during appropriate loop iterations. This mechanism designed reach optimal program memory usage library completes general purpose Code Compression scheme. Program Compression mAgicV VLIW architecture natively designed optimal program density. Moreover, program compression scheme allows average additional program compression between Therefore, more than issues stored each program memory locations. high Program Memory density achieved thanks combined effect Program Compression Software Pipelining. side many applications implemented D940HF using only internal memory. fact, 128-bit program memory size provides, with code compression, ~50K assembler instructions stored on-chip (typical). libraries, density even greater where software pipelining activated. on-chip program memory large enough contain full application, must launched refill dual-port Program Memory. Thanks program compression, program memory refill does stall activities core.
5.3.7
5.3.8
5.3.9
5.3.10
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5.3.11 mAgicV master interface mAgicV VLIW equipped with master which supports mAgicV engine. Data Memory System every cycle, port on-chip Data Memory System reserved fetch/store activity driven Engine. external memories other devices mapped System supported mAgicV master interface. engine generate stride access external memory. transfers from on-chip Memory executed parallel with full speed core instructions execution with zero-overhead without intervention core processor, except initiating Program Memory on-chip Program Memory mAgicV dual port. port reserved instruction fetch other engine. parallel with activities core, activated between external memories other devices mapped System Bus. mAgicV slave interface External masters, like JTAG access memories registers mAgicV through mAgicV slave interface. Debug mode (see Section 5.3.15.3 below) internal resources memory mapped, while mode sleep mode access restrictions apply (see Section 5.3.15.1 Section 5.3.15.2 below). every cycle, port Data Memory System reserved read/store accesses performed through slave interface. Example usage: data sampled Converters written inside mAgicV Data Memory parallel (through master port) VLIW operations. Operating Modes mAgicV mAgicV VLIW operate three operating modes: mode, Sleep mode Debug mode. access allowed different resources through slave port depends status mode: Mode Mode, mAgicV VLIW program under execution. mAgicV access external resources through master interface. Control status registers visible. port Data Memory System accessible through Slave port. 5.3.15.2 Sleep Mode Sleep Mode, Master Slave port engine still active. However, only "non-destructive access paths" guaranteed through slave interface. Control Status registers active. Data Address Registers frozen (readable writable). 5.3.15.3 Debug Mode Debug Mode, mAgicV suspends execution any) debug paths allowed. Data Program memories readable. Data Address registers readable. Pipeline registers frozen. external master, like JTAG access internal resources mAgicV debug purpose. ability access internal mAgicV resources Debug Mode used initialization also debugging purposes. accessing Command Register, change operating status (Run/System Mode),
5.3.12
5.3.13
5.3.14
5.3.15
5.3.15.1
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initiate transactions, force single multiple step execution, simply read operating status. 5.3.16 User/ Privileged Interrupt Mode During mode, mAgicV execute either User mode Privileged Interrupt Mode. ARM<->mAgicV Interrupts order allow tight coupling between operations mAgicV time, they exchange synchronization signals, based interrupts.
5.3.17
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ARM926 Processor
ARM926 member ARM9family general purpose microprocessors. ARM926 targeted multi-tasking applications where full memory management, high performance power important. ARM926 supports 32-bit 16-bit THUMB instruction sets, enabling user trade between high performance high code density. ARM926 includes features efficient execution Java byte codes. ARM926 supports debug architecture includes logic assist both hardware software debug. ARM926 provides integer core that supports instruction extension. ARM926 supports virtual memory addressing through standard memory management unit (MMU). ARM926 provides independent master interfaces data instruction. ARM926 provides independent Tightly Coupled Memory (TCM) interfaces. ARM926 implements architecture version 5TEJ with stage pipeline. ARM926 embeds 16-Kbyte Data Cache 16-Kbyte Instruction Cache. 5.4.1 Memories ARM926 memories consist 32Kbyte selectable boot memory 48Kbyte Fast SRAM Single Cycle Access full speed Supports ARM926EJ-S interface full processor speed D-TCM I-TCM programmable size 5.4.2 Boot system always boots address 0x0. memory layout configured with parameters ensure maximum number possibilities booting. REMAP allows user first internal SRAM bank ease development. This done software once system booted each Master Matrix. When REMAP ignored. Refer Matrix Section more details. When REMAP allows user, ones convenience, external memory 0x0. This done hardware reset. Note that Memory blocks affected these parameters always seen their specified base addresses. complete memory presented Table Table 5-4. Matrix manages boot memory that depends level reset. internal memory area mapped between address 0x000F FFFF reserved this purpose. detected boot memory embedded ROM. detected boot memory memory connected Chip Select External Interface.
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5.4.2.1
Boot Embedded system boots using Boot Program from embedded following steps listed below: Checks presence card with boot.bin file main dir: file found: Downloads code internal SRAM 0x300000 Executes Remap command Runs Boot code file found, downloads code from DataFlash®: Downloads code internal SRAM 0x300000 Checks presence valid code first word Executes Remap command Runs DataFlash Boot code case valid program detected external DataFlash: Activates Boot uploader enabling small monitor functionalities (read/write/run) interface with SAM-BAapplication Performs automatic detection communication link: Serial communication DBGU (XModem protocol) Device Port (CDC Protocol)
5.4.2.2
Boot External Memory Boot slow clock (32,768 Boot with default configuration Static Memory Controller, byte select mode, 32-bit data bus, Read/Write controlled Chip Select, allows boot 32-bit non-volatile memory. customer-programmed software must perform complete configuration. speed boot sequence when booting (BMS=0), user must take following steps: Program (main oscillator enable bypass mode). Program start PLL. Reprogram setup, cycle, hold, mode timings registers adapt them clock Peripheral Data Controller (PDC). Switch main clock value.
Peripheral Data Controller (PDC)
acting master controls data transfer between chip peripherals: USARTs, SPIs, SSCs, MCI, DBGU, TWIs off-chip memories. This leaves both processors free overhead related this function.
Host
host acting master controls data exchange between host channels (port port Internal external memories. Host Port features:
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Compliance with Open specification Compliance with V2.0 Full-speed Low-speed Specification Supports both Low-speed Mbps Full-speed Mbps devices Root integrated with downstream ports embedded transceivers
Ethernet 10/100
Ethernet acting master controls data exchange between ethernet channel Internal external memories. Ethernet hardware implementation sub-layer reference model between physical layer (PHY) logical link layer (LLC). controls data exchange between host layer according Ethernet IEEE 802.3u data frame format. Ethernet contains required logic transmits receives FIFOs management. addition, interfaced through MDIO/MDC pins layer management. Ethernet transfer data through Reduced Media Independent Interface (RMII). interface reduction lower count switch product that connected multiple interfaces. characteristics specific RMII mode are: Single clock frequency Reduction required control pins Reduction data paths di-bit (2-bit wide) doubling clock frequency Mbits/sec. Mbits/sec. data capability
mAgicV JTAG
mAgicV-JTAG provides JTAG interface mAgicV core. converts JTAG commands coming from JTAG probe into cycles. Acting master access mAgicV memories registers, thus allowing mAgicV debug software control core resources: upload/download data programs configure functional debug registers.
External Interface (EBI)
Each enabled master access external memory resources through EBI. External incorporates Static Memory Controller (SMC) Synchronous Dynamic controller (SDRAMC). features: Eight Chip Select Lines (four lines) 26-bit Address (four lines) 32-bit Data Multiple Access Modes supported Byte Write Lines Programmable Wait State Generation Programmable Data Float Time Slow clock mode supported
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5.9.1
Static Memory Controller (SMC) gives enabled Hosts capability access following type external memories: SRAM, Nor-Flash, EPROM, EEPROM. additional NAND LOGIC also provides with capability interface SmartMedia removable non-volatile memory cards Nand FLASH memory chips. additional Compact Flash logic provides with capability interface Compact Flash removable non-volatile memory cards.
5.9.2
Synchronous Dynamic Controller (SDRAMC) SDRAMC provides interface external 16-bit 32-bit SDRAM device. page size supports ranges from 2048 8192 number columns from 2048. supports byte (8-bit), half-word (16-bit) word (32-bit) accesses. SDRAMC supports read write burst length location. does support byte read/write bursts half-word write bursts. keeps track active each bank (avoiding precharge active when, changing bank, accessed), thus maximizing SDRAM performance, e.g., application placed bank data other banks. advisable avoid accessing different rows same bank order optimize performance. maximum number SDRAM locations that randomly accessed without penalty cycles (precharge, active) corresponds device size number banks. SDRAMC support size 2048 locations banks: hence maximum locations accessed without penalties. Anyway, typical SDRAM size 512/256 locations maximum 2K/1K locations accessed without penalties.
5.10
Memory Mapping
present section describes memory mapping ARM9System. Table shows D940HF global memory map:
Table 5-1.
D940HF Global Memory
masters
Start Address 0x0000 0000 0x1000 0000 0x9000 0000 0xF000 0000
Size (MB)
ARM9-I
ARM9-D
magicV
m-JTAG
Internal Memories (See Table 5-3) External Memories (See Table 5-2) Undefined (Abort) Internal Peripherals (See Table 5-4)
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Table shows external memory mapping: Table 5-2. External Memory
masters Start Address 0x1000 0000 0x2000 0000 0x3000 0000 0x4000 0000 0x5000 0000 0x6000 0000 0x7000 0000 0x8000 0000 Size (MB) ARM9-I ARM-D magicV CS0: CS1: SDRAMC CS2: CS3: (SmartMedia NAND-Flash) CS4: (Compact Flash slot CS5: (Compact Flash slot CS6: CS7: m-JTAG
Table shows internal memory map: Table 5-3. Internal Memory
masters
ARM9-I Size (MB) IntROM magicV magic magic REMAP=0 BMS=1 IntROM BMS=0 NCS0 IntRAM REMAP=1 ARM9-D REMAP=0 BMS=1 IntROM BMS=0 NCS0 IntRAM I-TCM D-TCM REMAP=1 magic mst# mJTAG
Start Address 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000 0x0040 0000 0x0050 0000 0x0060 0000
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Table 5-4.
Internal Peripherals
masters
Start Address 0xF000 0000 0xFFFA 0000 0xFFFA 4000 0xFFFA 8000 0xFFFA C000 0xFFFB 0000 0xFFFB 4000 0xFFFB 8000 0xFFFB C000 0xFFFC 0000 0xFFFC 4000 0xFFFC 8000 0xFFFC C000 0xFFFD 0000 0xFFFD 4000 0xFFFD 8000 0xFFFD C000 0xFFFE 0000 0xFFFE 4000 0xFFFF 0000 0xFFFF EA00 0xFFFF EC00 0xFFFF EE00 0xFFFF F000 0xFFFF F200 0xFFFF F400 0xFFFF F600 0xFFFF F800 0xFFFF FA00 0xFFFF FC00 0xFFFF FD00 0xFFFF FE00
Size (byte)
ARM9-I
ARM9-D
reserved TWI-0 USART-0 USART-1 USART-2 SSC-0 SSC-1 SSC-2 SPI-0 SPI-1 SSC-3 TWI-1 CAN-0 CAN-1 reserved reserved SDRAMC HMATRIX DBGU reserved SYSC reserved
magicV
m-JTAG
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5.11 peripherals
D940HF provides rich peripherals connected bus. enabled masters access these peripherals through AHB-APB bridge. 5.11.1 Peripheral Table defines Peripheral Identifiers D940HF. peripheral identifier required control peripheral interrupt with Advanced Interrupt Controller control peripheral clock with Power Management Controller. Table 5-5. Peripheral
Peripheral Clock Assignment Host Clock Assignment
Peripheral
USART-0 USART-1 USART-2 Device TWI-0 SPI-0 SPI-1 SSC-0 SSC-1 SSC-2 TIMER-0 TIMER-1 TIMER-2 HOST SSC-3 CAN-0 CAN-1
MAGIC Core
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Table 5-5.
Peripheral (Continued)
Peripheral Clock Assignment Host Clock Assignment
Peripheral
5.11.2
Peripheral Multiplexing D940HF features three controllers, PIOA, PIOB PIOC, that multiplex lines peripheral set. Each controller manages thirty-two lines. Each line assigned peripheral functions, Table Table define lines peripherals multiplexed Controllers. Note that some output only peripheral functions might duplicated within tables indicated with suffix III. Line Resource Mapping
Periph INPUT Periph OUTPUT Periph INPUT Periph OUTPUT mAgicV output: M_SIRQ0 EBI: output: CFCE1 (III) EBI: output: CFCE2 (III) dout (III) mAgicV output: M_SIRQ2 TIMER bidir: TIMER_OUT TIMER bidir: TIMER_OUT DBGU output: DTXD(III) output: CKOUT output: (III) USART output: USART bidir: input: EXT_IRQ1 (also mAgicV) bidir MDIO output output: FCE100 input: EREFCK input: ECRSDV input: ERX0 input: ERX1 input: ERXER output: ETX0 output: ETX1 input: EXT_IRQ2 (also mAgicV) TIMER input: TIMER_IN output: CKOUT EBI: output: NCS4/CFCS0 (III) EBI: output: NCS5/CFCS1 (III) EBI: output: NCS6 (III) EBI: output: NCS7 (III) TEST output: m_ck TEST output: a_ck TIMER input: TIMER_IN output: (III) USART output: (III) mAgicV output: M_SIRQ1
Table 5-6.
[10] [11] [12] [13] [14] [15] [016 [17] [18] [19] [20] [21] [22]
bidir: MISO bidir: MOSI bidir: bidir: output: output: output: USART input: USART bidir: USART input:
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Table 5-6.
[23] [24] [25] [26] [27] [28] [29] [30] [31] input: input: NWAIT output: NCS4/CFCS0 output: NCS5/CFCS1 output: NCS6 output: NCS7 output: CFCE1 output: CFCE2
Line Resource Mapping (Continued)
Periph INPUT Periph OUTPUT output: ETXEN Periph INPUT Periph OUTPUT mAgicV output: M_SIRQ0 (III) mAgicV output: M_SIRQ1 (III) USART output: (III) TIMER bidir: TIMER_OUT output: CKOUT output: SMOE output: SMWE output: CKOUT mAgicV output: M_SIRQ3
Table 5-7.
[10] [11] [12] [13] [14] [15] [016 [17] [18] [19] [20] [21]
Line Resource Mapping
Periph INPUT SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: Periph OUTPUT Periph INPUT Periph OUTPUT output: (III) TIMER bidir: TIMER_OUT CKOUT (II) dout (II) USART (II) mAgicV output: M_SIRQ1 (II) dout (III) TIMER bidir: TIMER_OUT CKOUT (II) output: (III) USART (III) EBI: A[22] (III) EBI: A[23] (III) mAgicV output: M_SIRQ2 (II) EBI: A[24] (III) output: (II) output: (II) output: FCE100 (II) EBI: A[25]-CFRNW (III) mAgicV output: M_SIRQ0 (II) output: (III) output: FCE100 (III)
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Table 5-7.
[22] [23] [24] [25] [26] [27] [28] [29] [30] [31]
Line Resource Mapping (Continued)
Periph INPUT Periph OUTPUT SSC: SSC: TIMER input: TIMER_IN input: EXT_IRQ0 (also mAgicV) dout EBI: A[22] EBI: A[23] EBI: A[24] EBI: A[25]-CFRNW Periph INPUT Periph OUTPUT USART (II) DBGU output: DTXD (II) mAgicV output: M_MODE USART (II) output: (III) mAgicV output: M_SIRQ3 (II) output: (II) output: (II) CKOUT (II) CKOUT 3(II)
Table 5-8.
[10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
Line Resource mapping
Periph INPUT Periph OUTPUT Periph INPUT Periph OUTPUT SSC: (II) SSC: (II) SSC: (II) output: ETX0 (II) output: ETX1 (II) mAgicV output: M_SIRQ3 (III) EBI: output: SMOE (III) SSC: (III) SSC: (III) SSC: (III) output: ETX0 (III) output: ETX1 (III) USART USART USART USART USART USART USART TIMER bidir: TIMER_OUT output: (II) SSC: (II) EBI: A[22] (II) EBI: A[23] (II) EBI: A[24] (II) EBI: A[25]-CFRNW (II) output: (II) output: (II)
bi-directional: MISO bi-directional: MOSI bi-directional: bi-directional: output: output: output: bi-directional: bi-directional: TWCK USART USART USART
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Table 5-8.
[20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] DBGU input: DRXD DBGU output: DTXD
Line Resource mapping (Continued)
Periph INPUT Periph OUTPUT Periph INPUT Periph OUTPUT SSC: (III) output: (III) dout (II) mAgicV output: M_SIRQ2 (III) EBI: SMOE (II) EBI: SMWE (II) EBI: NCS4/CFCS0 (II) EBI: NCS5/CFCS1 (II) EBI: NCS6 (II) dout EBI: NCS7 (II) EBI: CFCE1 (II) EBI: CFCE2 (II)
bi-directional: bi-directional: TWCK bidir: MCCK bidir: MCCDA bidir: MCDA0 bidir: MCDA1 bidir: MCDA2 bidir: MCDA3
5.11.3
System Controller (SYSC) SYSC includes Reset Controller (RSTC) System Timers (SYST). RSTC manages system resets: external devices reset, processors reset peripheral reset. sources reset Power-On, Watch Dog, reset, External reset. SYST features: 16-bit Period Interval Timer 12-bit key-protected Watchdog Timer 20-bit Free-running Real-time Timer
5.11.4
Power Management Controller (PMC) features clock sources: Slow Clock Oscillator (32.768 Main Oscillator MHz). dividers, Phase Lock Loops, allow wide range frequencies generated from either slow clock and/or main clock. provides dedicated clocks toward: ARM926, Matrix, mAgicV, mAgicV Memories, USB, Ethernet Peripherals.
5.11.5
Advanced Interrupt Controller (AIC) features: Controls interrupt lines (nIRQ nFIQ) ARM926 Thirty-two individually maskable vectored interrupt sources Programmable Edge-triggered Level-sensitive Internal Sources Programmable Positive/Negative Edge-triggered High/Low Level sensitive
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8-level Priority Controller Fast Forcing: allows redirection normal interrupt source nFIQ 5.11.6 Parallel Input/Output (PIO) three PIOs provide globally programmable Lines. These lines fully programmable through Set/Clear Registers linked peripheral functions. Each Line (assigned peripheral used general purpose I/O) provides: Input change interrupt Glitch filter Multi-drive option enables driving open drain Programmable pull each line data status register, supplies visibility level time 5.11.7 Universal Synchronous Device (USBD) Device provides communication services between external host D940HF. device connected through FIFO. Device features: V2.0 full-speed compliant, Mbits second Embedded V2.0 full-speed transceiver Embedded dual-port endpoints Suspend/Resume logic Embedded Transceivers 5.11.8 Timer Counter (TC) consists three 16-bit Timer Counter Channels providing wide range functions including: Frequency Measurement Event Counting Interval Measurement Pulse Generation Delay Timing Pulse Width Modulation Up/down Capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs multi-purpose input/output signals 5.11.9 Wire Interface (TWI) D940HF provides independent TWIs.
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Each interconnects components unique two-wire bus, made clock line data line which speeds Kbits second, based byte oriented transfer format. Each programmable master with sequential single-byte access. configurable baud rate generator allows output data rate adapted wide range core clock frequencies. 5.11.10 Universal Synchronous Asynchronous (USART) D940HF provides three independent USARTs. Each USART features: Synchronous Asynchronous mode Programmable Baud Rate Generator 115.2 Kbps Asynchronous Mode system clock frequency Synchronous Mode) RS485 with driver control signal ISO7816, Protocols interfacing with smart cards IrDA modulation demodulation connection 5.11.11 Serial Synchronous Controller (SSC) D940HF provides four independent SSCs. Each provides programmable serial synchronous communication link used audio telecom applications (CODECs Master Slave Modes, I2S, Buses, Magnetic Card Reader, SPI, connection allows direct data transfer between CODECs mAgicV data memory, internal memory external memories. 5.11.12 Serial Peripheral Interface (SPI) D940HF provides independent SPIs. Each supports communication with serial external devices such DataFlash, ADCs, DACs, Controllers, Controllers Sensors. Four chip selects with external decoder support allow communication with peripherals. connection allows direct data transfer between these serial devices mAgicV data memory, internal memory external memories. 5.11.13 Debug Unit (DBGU) DBGU 2-wire UART dedicated Debug Communication. DBGU channels associated with channels. Debug Unit also generates Debug Communication Channel (DCC) signals provided In-circuit Emulator processor visible software. These signals indicate status read write registers generate interrupt processor, allowing handling under interrupt control.
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5.11.14
Controller Area Network (CAN) D940HF provides independent CANs. Each fully compliant with Part Part supports bit/rate Mbps.
5.11.15
Multimedia Card Interface (MCI) D940HF provides MCI. slots, each supporting: slot MultiMedia Card cards) Memory Card connection allows direct data transfer between these serial devices mAgicV data memory, internal memory external memories.
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AT572D940HF Preliminary
Mechanical Drawing
Figure 6-1. 324-ball CABGA Package Drawing (dimensions
7010AS-DSP-07/07
Power Dissipation
D940HF kinds power supply pins: VDDCORE pins, which power chip core (1.1V 1.2V) VDDOSC32 pins, which power 32KHz oscillator cell (1.1V 1.2V) VDDOSCM pins, which power main oscillator cell (1.1V 1.2V) VDDIOM pins, which power lines (3.3V) VDDIOP pins, which power Peripheral lines (3.3V) VDDPLLA pins, which power PLLA cell (3.3V)
Power Consumption
D940HF consumes about typical conditions static current VDDCORE. dynamic power consumption D940HF consumes about 300mA typical conditions maximum working frequencies with toggling rate.
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Ordering Guide
Table 8-1. Ordering Information
Temp. Range 70°C Speed Grade (Max) Operating Voltage 3.3V (I/O) 1.1V (core) 1.8V-2.5V-3.3V (I/O) 1.2V (core) 1.8V-2.5V-3.3V (I/O) 1.2V (core) Package CA324BGA (RoHS) CA324BGA (RoHS) CA324BGA (RoHS) Notes Full Peripheral Reduced Periperal Full Peripheral Status Sampling Contact: diopsis@atmel.com Contact: diopsis@atmel.com
Part Number AT572D940HF
AT572D940HF-CL
70°C
AT572D940HF-CJ
-40°C 85°C
Some peripherals accessible user this low-cost version. Reduced Peripheral Full Peripheral CANs SSCs USARTs. Consequently related lines used only controlled lines (not linked peripherals).
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Revision History
Doc. Rev. 7010AS Date 07/07 Comments
Initial document release
AT572D940HF Preliminary
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