Core MagicV VLIW Magic DSPis optimized Audio, Communication Beam-formi
|
|
|
Top Searches for this datasheet
DIOPSIS® Dual Core System Integrating ARM926EJ-SARM® Thumb® Processor
Core MagicV VLIW Magic DSPis optimized Audio, Communication Beam-forming Applications High Performance MagicV VLIW GFLOPS Gops Master Port, integrated Engine Slave Port Arithmetic Operations Cycle Multiply, Add/Subtract, Add, Subtract 40-bit Floating Point 32-bit Integer) allowing Single Cycle Butterfly Native Support Complex Arithmetic Vectorial SIMD Operations: Complex Multiply with Dual Add/Sub Clock Cycle Multiply Add/sub Simple Scalar Operations 32-bit Integer IEEE® 40-bit Extended Precision Floating Point Numeric Format 16-port Data Register File: Registers organized 128-register Banks 5-issue predicated VLIW Architecture with Orthogonal ISA, Code Compression Hardware Support Code Efficient Software Pipeline Loops Accesses Cycle Data Memory System Accesses Cycle VLIW Operations Accesses Cycle Transfers) supported Flexible Addressing Capability Independent Address Generation Units Operating 64-register Address Register File Supporting Complex Micro-Vectorial Accesses features: Programmable Stride Circular Buffers Mbits On-chip SRAM: 40-bit Data Memory Locations Memory Accesses Cycle) 128-bit Dual Port Program Memory Location, Equivalent ~50K Assembler Instructions (typical) thanks Code Compression Pipelining Access External Program Data Memory Three Main Operating Modes: Run, Debug Sleep User Mode Privileged Interrupt Service Mode Efficient Optimizing Assembler C-Oriented Architecture: allows Easy Exploitation available Hardware Parallelism ARM926EJ-S Thumb Processor Instruction Extensions Jazelle® Technology Java® Acceleration 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer 220MIPS 200MHz Memory Management Unit EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support Additional Embedded Memories 32-KByte internal ROM, two-cycle access maximum speed 48-KByte internal SRAM, single-cycle access maximum processor speed External Interface (EBI) Supports SDRAM, Static Memory, SmartMediaand NAND Flash, CompactFlashUSB Full Speed Mbits second) Host Double Port Dual On-chip Transceivers Integrated FIFOs Dedicated Channels
DIOPSIS 940HF
ARM926EJ-S PLUS GFLOPS
AT572D940HF Preliminary
7010A-DSP-07/08
Full Speed Mbits second) Device Port On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs dedicated channels Ethernet 10/100 Reduced Media Independent Interface (RMII) Physical Layer Integrated channel Matrix Seven Masters Five Slaves Handled Boot Mode Select Option Remap Command System Controller (SYSC) Reset Controller Periodic Interval Timer, Watchdog Real-Time Timer Power Management Controller (PMC) Very Slow Clock (32768Hz) Operating Mode Software Programmable Power Optimization Capabilities On-chip Oscillator PLLs Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Three External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected Three 32-bit Parallel Input/Output Controllers (PIO) Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up resistor Synchronous Output Twenty-three Peripheral Data Controller (PDC) Channels Debug Unit (DBGU) 2-wire USART support Debug Communication Channel, Programmable Access Prevention dedicated channels Four Synchronous Serial Controllers (SSC) Independent Clock Frame Sync Pair Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer dedicated channels each Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation Support ISO7816 T0/T1 Smart Card, Hardware Software Handshaking, RS485 Support dedicated channels each USART Master/Slave Serial Peripheral Interface (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects dedicated Channels each Three-channel 16-bit Timer/Counters (TC) Three External Clock Inputs, multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Two-wire Interfaces (TWI) Master Mode Support, Atmel Two-wire EEPROMs Supported Interfaces Fully compliant with Part Part Multimedia Card Interface (MCI) Automatic Protocol Control Fast Automatic Data Transfers with PDMA, SDCard Compliant
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
IEEE 1149.1 JTAG Boundary Scan Digital Pins Required Power Supplies:
1.1V 1.2V VDDCORE VDDOSC 3.3V VDDPLLA 3.3V VDDIOP (Peripheral I/Os) VDDIOM (Memory I/Os) Available 324-ball CABGA Package Efficient Interface through master slave ports, Memory Mapped Registers Ports, Interrupt Lines Semaphores
7010A-DSP-07/08
Description
DIOPSIS 940HF Dual Processor integrating MagicV VLIW ARM926EJS RISC MCU, plus Kbyte SRAM. system combines flexibility ARM926RISC controller with very high performance DSP. MagicV high performance VLIW delivering Giga floating-point operations second (GFLOPS) Gops clock rate. equipped with master port slave port system-on-chip integration. data registers, address registers, independent arithmetic operating units, independent address generation units engine. sustain internal parallelism, data bandwidth among Register File, Operators Data Memory System, bytes/cycle. Data Memory System designed transfer bytes/cycle. instance, MagicV produce complete butterfly cycle activating computing units; operates IEEE 40-bit extended precision floating-point 32-bit integer numeric format numerical computations, while internal memory accesses supported powerful 16-bit MAGU (Multiple Address Generation Unit). also on-chip 40-bit 6-access/cycle data memory system 128-bit dual port program memory locations. Efficient usage internal program memory achieved through general purpose code compression mechanism software pipelining support systematic loops. C-oriented Architecture optimizing assembler facilitate user dealing with parallelism processor resources drastically simplify code development. rich library C-callable routines available. ARM926 embedded micro controller core member Advanced RISC Machines (ARM) family general purpose 32-bit microprocessors, which offer high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles; instruction related decode mechanism much simpler than micro programmed Complex Instruction Computers. result this simplicity high instruction throughput impressive real-time interrupt response. ARM926 supports 16-bit Thumb subset most commonly used 32-bit instructions. These expanded time with degradation system performance. This gives 16-bit code density (saving memory area cost) coupled with 32-bit processor performance. rich peripherals Kbyte internal memory provide highly flexible integrated system solution. ARM926EJ-S supports Jazelle Technology Java acceleration.
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Ball Configuration
Table 2-1.
Name A0/NBS0 A1/NBS2/NWR2 A16/SD_BA0 A17/SD_BA1 A_JCFG A_RTCK A_TCK A_TDI A_TDO A_TMS A_NTRST
AT572D940HF Ball Assignment (I/O: balls)
Name M_NTRST M_TCK M_TDI M_TDO M_TMS NCS0 NCS1/SD_CS Name NCS2 NCS3/SM_NCS NRD/NOE/CF_NOE NRST NWR0/NWE/CF_NWE
NWR1/NBS1/CF_NIOR NWR3/NBS3/CF_NIOW
Name PIOA27 PIOA28 PIOA29 PIOA30 PIOA31 PIOB0 PIOB1 PIOB2 PIOB3 PIOB4 PIOB5 PIOB6 PIOB7 PIOB8 PIOB9 PIOB10 PIOB11 PIOB12 PIOB13 PIOB14 PIOB15 PIOB16 PIOB17 PIOB18 PIOB19 PIOB20 PIOB21 PIOB22 PIOB23 PIOB24 PIOB25 PIOB26 PIOB27 PIOB28
PIOA0 PIOA1 PIOA2 PIOA3 PIOA4 PIOA5 PIOA6 PIOA7 PIOA8 PIOA9 PIOA10 PIOA11 PIOA12 PIOA13 PIOA14 PIOA15 PIOA16 PIOA17 PIOA18 PIOA19 PIOA20 PIOA21 PIOA22 PIOA23 PIOA24 PIOA25 PIOA26
7010A-DSP-07/08
Table 2-1.
Name PIOB29 PIOB30 PIOB31 PIOC0 PIOC1 PIOC2 PIOC3 PIOC4 PIOC5 PIOC6 PIOC7 PIOC8 PIOC9 PIOC10
AT572D940HF Ball Assignment (I/O: balls) (Continued)
Name PIOC11 PIOC12 PIOC13 PIOC14 PIOC15 PIOC16 PIOC17 PIOC18 PIOC19 PIOC20 PIOC21 PIOC22 PIOC23 PIOC24 Name PIOC25 PIOC26 PIOC27 PIOC28 PIOC29 PIOC30 PIOC31 PLL_RCA PLL_RCB SD_A10 SD_CK SD_CKE SD_NCAS SD_NRAS Name SD_NWE TEST USBD_M USBD_P USBHA_M USBHA_P USBHB_M USBHB_P XOUT X32EN X32IN X32OUT
Table 2-2.
Name VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDIOM VDDIOM
AT572D940HF Ball Assignment (Power Ground: balls)
Name VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOMP VDDIOMP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Name VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDOSC32 VDDOSCM Name VDDPLLA
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Table 2-2.
Name
AT572D940HF Ball Assignment (Power Ground: balls) (Continued)
Name Name Name GNDOSC32 GNDOSCM GNDPLLA
pins listed Table Table "not connected".
Name Conventions
names built using following structure: (functional block name) (activity level) (line name) (bus index) where: functional block name name related functional block (when global function) activity level active lines; blank high active lines line name name line function index number corresponding index when line element
7010A-DSP-07/08
Description
Table 3-1.
Module JTAG JTAG JTAG JTAG JTAG JTAG Logic Logic Logic Logic Logic Logic Logic DBGU DBGU
AT572D940HF Description
Name EXT_IRQ0 EXT_IRQ2 M_MODE M_SIRQ0 M_SIRQ3 A_JCFG A_RTCK A_TCK A_TDI A_TDO A_TMS CAN0_RX CAN0_TX CAN1_RX CAN1_TX CF_NCE1CF_NCE2 CF_NOE CF_NWE CF_NIOR CF_NIOW CF_RNW CF_NCS0 CF_NCS1 DBG_RXD DBG_TXD NWAIT E_RXER Function External Interrupt Request Interrupt Request from MagicV Generic Interrupt Request from MagicV JTAG Chip Boundary Scan select JTAG Returned Test Clock JTAG Test Clock JTAG Test Data Input JTAG Test Data Output JTAG Test Mode Select Data Data Data Data CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash Read CompactFlash Write CompactFlash Read Write CompactFlash Chip Select Debug Serial Line Data Debug Serial Line Data Address Address Data External Wait Signal Boot Memory Select Ethernet RMII Receive Error bi-03 Type bi-03 bi-03 bi-03 out-03 out-03 bi-03 bi-03 bi-03 bi-03 bi-03 out-03 out-03 out-03 out-03 bi-03 bi-03 bi-03 bi-03 out-03 bi-03 bi-03 output through line output through line input through line output through line reset output through line reset pulled-up input reset input through line input through line external boot selected internal boot selected input through line pull-up resistor input through line output through line input through line output through line output through line pull-up resistor pull-up resistor Active Level Notes input through line output through line output through line internal pull-down resistor (low JTAG selected)
bi-03
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Table 3-1.
Module JTAG JTAG JTAG JTAG JTAG
AT572D940HF Description (Continued)
Name E_TXD0 E_TXD1 E_TXEN E_REFCK E_CRSDV E_RXD0 E_RXD1 E_FCE100 E_MDIO E_MDCK MCCK MCCDA MCDA0MCDA3 M_NTRST M_TCK M_TDI M_TDO M_TMS XOUT X32IN X32OUT X32EN PIOA0 PIOA31 PIOB0 PIOB31 PIOC0 PIOC31 PLL_RCA PLL_RCB A_CK Function Ethernet RMII Transmit Data Ethernet RMII Transmit Enable Ethernet RMII Reference Clock Ethernet RMII Carrier Sense/Data Valid Ethernet RMII Receive Data Ethernet RMII Force Mb/s operation Ethernet RMII Management Data Ethernet RMII Management Clock Multimedia Card Clock Multimedia Card Command Multimedia Card Data MagicV JTAG Test Reset MagicV JTAG Test Clock MagicV JTAG Test Data Input MagicV JTAG Test Data Output MagicV JTAG Test Mode Select Main Oscillator Quartz Main Oscillator Quartz Slow Clock Oscillator Quartz Slow Clock Oscillator Quartz Slow Clock Oscillator Enable Parallel Input/Output Parallel Input/Output Parallel Input/Output Filter Filter Clock Type bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 out-03 bi-03 bi-03 bi-03 bi-03 left floating (test input) output through line test purpose high internal pull-up resistor (internal oscillator enabled) general purpose programmable I/Os peripheral I/Os; Pulled-up input reset general purpose programmable I/Os peripheral I/Os; Pulled-up input reset general purpose programmable I/Os peripheral I/Os; Pulled-up input reset pull-up resistor pull-up resistor pull-up resistor high Active Level Notes output through line output through line input through line input through line input through line output through line through line output through line through line through line through line
7010A-DSP-07/08
Table 3-1.
Module SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC Logic Logic
AT572D940HF Description (Continued)
Name M_CK P_CK0-P_CK3 SDCK SD_CKE SD_NCS SD_BA0 SD_BA1 SD_NWE SD_NRAS SD_NCAS SD_A10 NCS0 NCS3 NCS4 NCS7 NWR0 NWR3 NBS0 NBS3 SM_NOE SM_NWE SPI0_MOSI Function MagicV Clock Programmable Clock SDRAM Clock Output SDRAM Clock Enable SDRAM Chip Select SDRAM Bank Select SDRAM Write Enable Column Address Strobe SDRAM Address Chip Select Signal Chip Select Signal Write Signal Output Enable Read Signal Write Enable Byte Select SmartMedia Output Enable SmartMedia Write Enable Master Out/Slave data Type bi-03 bi-03 out-03 out-04 out-03 out-03 out-04 out-04 out-04 out-03 bi-03 out-03 out-03 out-03 out-03 out-03 bi-03 bi-03 bi-03 reset; reset output through line reset reset reset reset reset output through line output through line through line data input data output through line data output data input through line Input Output output through line n.a. Outputs through line clock input clock output high Active Level Notes output through line test purpose output through line
SPI0_MISO
Master In/Slave data
bi-03
SPI0_NCS0
Input/Output Chip select
out-03
SPI0_NCS1 SPI0_NCS3
Output Chip Selects
bi-03
SPI0_CK
Serial clock
bi-03
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Table 3-1.
Module
AT572D940HF Description (Continued)
Name SPI1_MOSI Function Master Out/Slave data Type bi-03 Active Level Notes through line data input data output through line data output data input through line Input Output output through line n.a. Outputs through line clock input clock output output through line input through line through line through line through line through line output through line input through line through line through line through line through line output through line through line
SPI1_MISO
Master In/Slave data
bi-03
SPI1_NCS0
Input/Output Chip select
out-03
SPI1_NCS1 SPI1_NCS3
Output Chip Selects
bi-03
SPI1_CK
Serial clock Synchronous Serial Controller Data Synchronous Serial Controller Data Synchronous Serial Controller Transmit Frame Clock Synchronous Serial Controller Receive Frame Clock Synchronous Serial Controller Transmit Clock Synchronous Serial Controller Receive Clock Synchronous Serial Controller Data Synchronous Serial Controller Data Synchronous Serial Controller Transmit Frame Clock Synchronous Serial Controller Receive Frame Clock Synchronous Serial Controller Transmit Clock Synchronous Serial Controller Receive Clock Synchronous Serial Controller Data Synchronous Serial Controller Transmit Frame Clock
bi-03
SSC0_TXD SSC0_RXD SSC0_TF SSC0_RF SSC0_TK SSC0_RK SSC1_TXD SSC1_RXD SSC1_TF SSC1_RF SSC1_TK SSC1_RK SSC2_TXD SSC2_TF
bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03
7010A-DSP-07/08
Table 3-1.
Module SYSC USBD USBD USBH
AT572D940HF Description (Continued)
Name SSC2_RF SSC2_TK SSC2_RK SSC2_RXD SSC3_TXD SSC3_RXD SSC3_TF SSC3_RF SSC3_TK SSC3_RK NRST TC_OUT_A0 TC_OUT_A1 TC_OUT_A2 TC_OUT_B0 TC_OUT_B1 TC_OUT_B2 TC_IN_0 TC_IN_1 TC_IN_2 TEST TW0_D TW0_CK TW1_D TW1_CK USBD_M USBD_P USBHA_M Function Synchronous Serial Controller Receive Frame Clock Synchronous Serial Controller Transmit Clock Synchronous Serial Controller Receive Clock Synchronous Serial Controller Data Synchronous Serial Controller Data Synchronous Serial Controller Data Synchronous Serial Controller Transmit Frame Clock Synchronous Serial Controller Receive Frame Clock Synchronous Serial Controller Transmit Clock Synchronous Serial Controller Receive Clock Chip Reset Timer Counter Timer Counter Timer Counter Timer Counter Timer Counter Timer Counter Timer Counter Timer Counter Timer Counter Test Mode Select Wire Data Wire Clock Wire Data Wire Clock Device Port Data Device Port Data Host Port Data Type bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 usb-bi usb-bi usb-bi external pull-down required high Active Level Notes through line through line through line input through line output through line input through line through line through line through line through line open drain through line bidirectional through line bidirectional through line bidirectional through line bidirectional through line bidirectional through line input through line input through line input through line pull-down resistor (Functional Mode selected) bidirectional through line bidirectional through line bidirectional through line bidirectional through line
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Table 3-1.
Module USBH USBH USBH USART USART USART USART USART USART USART USART USART USART USART USART USART USART USART Power Power Power Power Power Power Power Ground Ground Ground Ground
AT572D940HF Description (Continued)
Name USBHA_P USBHB_M USBHB_P USART0_RXD USART0_TXD USART0_SCK USART0_CTS USART0_RTS USART1_RXD USART1_TXD USART1_SCK USART1_CTS USART1_RTS USART2_RXD USART2_TXD USART2_SCK USART2_CTS USART2_RTS VDDCORE VDDIOP VDDIOM VDDIOMP VDDOSC32 VDDOSCM VDDPLLA GNDOSC32 GNDOSCM GNDPLLA Function Host Port Data Host Port Data Host Port Data USART Data USART Data USART Serial clock USART Clear send USART Request send USART Data USART Data USART Serial clock USART Clear send USART Request send USART Data USART Data USART Serial clock USART Clear send USART Request send Core power supply Peripherals Lines Power Supply Lines Power Supply EBI/Peripherals Lines Power Supply 32KHz Oscillator Power Supply Main Oscillator PLLB Power Supply PLLA power supply Core Ground 32KHz Oscillator Ground Main Oscillator PLLB Ground PLLA Ground Type usb-bi usb-bi usb-bi bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 bi-03 Power Power Power Power Power Power Power Ground Ground Ground Ground Active Level Notes external pull-down required external pull-down required external pull-down required input through line bidirectional through line bidirectional through line synchronous mode only input through line output through line input through line bidirectional through line bidirectional through line synchronous mode only input through line output through line input through line bidirectional through line bidirectional through line synchronous mode only input through line output through line 1.1V 1.2V (nominal) 3.3V (nominal) 3.3V (nominal) 3.3V (nominal) 1.1V 1.2V (nominal) 1.1V 1.2V (nominal) 3.3V (nominal)
7010A-DSP-07/08
Block Diagram
Figure 4-1. AT572D940HF Architecture
ARM926EJ-S
JTAG
Instruction Cache bytes Data Cache bytes
D0-D31 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A21 A16/SD_BA0 A17/SD_BA1 NCS0 NCS1/SD_NCS NCS2 NCS3/SM_NCS NRD/NOE/CF_NOE NWR0/NWE/CF_NWE NWR1/NBS1/CF_NIOR NWR3/NBS3/CF_NIOW SD_CK SD_CKE SD_NRAS-SD_NCAS SD_NWE SD_A10 A22-A25/CF_RNW NCS4/CF_NCS0 NCS5/CF_NCS1 CF_NCE1 CF_NCE2 NCS6/SM_NOE NCS7/SM_NWE NWAIT
A_JCFG A_TDI A_TMS A_RTCK A_TCK A_TDO
CompactFlash SmartMedia NAND Flash
NRST TEST VDDCORE
SYSC
CNTL
ITCM DTCM
X32IN X32OUT X32EN XOUT PLL_RCA PLL_RCB A_CK M_CK PCK0-PCK3
Fast SRAM Kbytes
SDRAM CNTL
MAIN
Fast Kbytes
Static Memory CNTL
Peripheral Bridge
EXT_IRQ0-EXT_IRQ2
MATRIX
FIFO
TRANSCEIVER
USBHA_M USBHA_P USBHB_M USBHB_P
HOST
DBG_TXD DBG_RXD
DBGU
USARTx_TXD USARTx_RXD USARTx_SCK USARTx_CTS USARTx_RTS
USART 0-1-2
mAgic JTAG
M_TDI M_TMS M_NTRST M_TCK M_TDO
SPIx_MOSI SPIx_MISO SPIx_NCS0 SPIx_NCS1-SPIx_NCS3 SPIx_CK
mAgic
memories
M_MODE M_SIRQ0-M_SIRQ3
PIOx
A-B-C Controllers
FIFO RMII
TWx_CK TWx_D
SSCx_RXD SSCx_TXD SSCx_TF SSCx_TK SSCx_RF SSCx_RK
E_MDIO E_MDC E_FCE100 E_RXER E_TX0-E_TX1 E_TXEN E_REFCK E_CRSDV E_RX0-E_RX1
PIOx
0-1-2-3
Timer Counter
MCCK MCCDA MCDA0-MCDA3
TC_OUT_A_0 TC_OUT_A_1 TC_OUT_A_2 TC_OUT_B_0 TC_OUT_B_1 TC_OUT_B_2 TC_IN_0 TC_IN_1 TC_IN_2
CANx_RX CANx_TX
FIFO DEVICE
TRANSCEIVER
USBD_M USBD_P
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Architectural Overview
DIOPSIS (also named D940HF) dual-core processing platform prosumer audio, speech processing, automotive sound robotics applications, integrating floating-point Magic DSPand ARM926EJ-S RISC microprocessor. system combines flexibility ARM926 RISC controller with processing power mAgic VLIW floating-point DSP. This combination makes DIOPSIS suited applications needing both control intensive numerical applications. 40-bit floating-point provides high dynamic range maximum numerical precision, reducing time market. DIOPSIS horse-power fully exploited complex domain applications, like frequency domain signal processing.
System management
availability standard RISC on-chip reduces software development effort critical control segments application. ARM926 features virtual memory sophisticated memory protection, making ideal platform operating systems such Windows Linux®. This leaves MagicV fully available numerically intensive part application. synchronization between processors either based interrupts software polling semaphores. ARM926 master processor D940HF. bootstrap sequence D940HF starts bootstrap ARM926 from internal external non-volatile memory. then boots MagicV from non-volatile memory. After bootstrap D940HF start normal operations. side many applications implemented D940HF using only internal memory. fact, 128-bit program memory coupled with availability general purpose code compression software pipelining systematic loops, gives equivalent on-chip program memory size about cycles, corresponding ~50K assembler instructions (typically).
AMBAArchitecture
architecture based AMBA bus: multilayer matrix APB. matrix consists seven masters: ARM926 Instruction ARM926-Data Peripheral Data Controller (PDC) MagicV Host Ethernet 10/100 MagicV JTAG five slaves: ARM926 SRAM ARM926 MagicV Registers Memories Host Registers External Interface AHB-APB bridge following table defines possible MST-SLV links:
7010A-DSP-07/08
Table 5-1.
Masters-Slaves possible links
MASTERS
SLAVES MagicVUSBH HEBI HBRIDGE
ARM-I (default MST) (default MST)
ARM-D (default MST)
HPDC
MagicV
HOST
M-JTAG
(default MST)
(default MST)
MagicV VLIW Processor
MagicV VLIW numeric processor D940HF. operates IEEE 40-bit extended precision floating-point 32-bit integer numeric format. main components subsystem core processor, on-chip memories, engine master slave interfaces. operators block, register file, multiple address generation unit program decoding sequencing unit computing part core processor. short description each block given following paragraphs. Figure 5-1. MagicV Block Diagram
layer-y layer-x
Multi Layer System
2-port, 8Kx128-bit, VLIW Program Memory VLIW Decompressor Flow Controller, VLIW Decoder Program Condition Status Instruction Counter Generation Register Decoder
Master Engine
Slave, e.g. Target
16-port 256x40-bit Data Register File System
4-address/cycle Multiple Address Generation Unit multi-field Address Register File
6-access/cycle Data Memory System 16Kx40-bit
Operators: 10-float ops/cycle
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
5.3.1 RISC-like VLIW MagicV Very Long Instruction Word engine, from user's point view, works like RISC machine implementing triadic computing operations data coming from register file data move operations between local memories register file. operators pipelined maximum performance. pipeline depth depends operator used. scheduling parallelism operations automatically defined managed compile time assembler-optimizer, allowing efficient code execution. architecture designed efficient C-language support. Memories Data Register File MagicV Data Memory System contains 16K*40-bit on-chip memory locations supporting accesses/cycle. 4-accesses/cycle reserved activities driven MagicV Multiple Address Generation unit: these accesses reserved computing part core. access/cycle assigned serve activity launched core itself through MagicV master port. additional access/cycle simultaneously requested external devices through MagicV slave port (e.g data exchange with interfaces converters). Program Memory stores VLIW program executed MagicV. 8K-word 128-bit dual port memory. port driven Flow Controller fetch compressed VLIW word. other port accessed engine, supported master interface, external devices through MagicV slave port. provide optimal data bandwidth give best support RISC-like programming model, MagicV arithmetic computations supported 16-ported, 256x40-bit entries, Data Register File System. 5.3.3 Operators Block Operators Block contains hardware that performs arithmetical operations. works 32-bit signed integers IEEE extended precision 40-bit floating-point data. Operators Block composed four integer/floating point multipliers, adder, subtractor add-subtract integer/floating point units; moreover, shift/logic units, Min/Max operator seed generators efficient division inverse square root computation. MagicV master interface MagicV VLIW equipped with master which supports MagicV engine. MagicV slave interface External masters, like JTAG access memories registers MagicV through MagicV slave interface. Debug mode internal resources memory mapped, while mode sleep mode access restrictions apply. every cycle, port Data Memory System reserved read/store accesses performed through slave interface. Example usage: data sampled Converters written inside MagicV Data Memory parallel (through master port) VLIW operations. ARM<->MagicV Interrupts MagicV exchange synchronization signals based interrupts allow tight coupling between their operations time.
5.3.2
5.3.4
5.3.5
5.3.6
7010A-DSP-07/08
ARM926 Processor
ARM926 member ARM9 family general purpose microprocessors. ARM926 targeted multi-tasking applications where full memory management, high performance power important. ARM926 supports 32-bit 16-bit THUMB instruction sets, enabling user trade between high performance high code density. ARM926 includes features efficient execution Java byte codes. ARM926 supports debug architecture includes logic assist both hardware software debug. ARM926 provides integer core that supports instruction extension. ARM926 supports virtual memory addressing through standard memory management unit (MMU). ARM926 provides independent master interfaces data instruction. ARM926 provides independent Tightly Coupled Memory (TCM) interfaces. ARM926 implements architecture version 5TEJ with stage pipeline. ARM926 embeds 16-Kbyte Data Cache 16-Kbyte Instruction Cache.
5.4.1
Memories ARM926 memories consist 32Kbyte selectable boot memory 48Kbyte Fast SRAM Single Cycle Access full speed Supports ARM926EJ-S interface full processor speed D-TCM I-TCM programmable size
5.4.2
Boot system always boots address 0x0. memory layout configured with parameters ensure maximum number possibilities booting. REMAP allows user first internal SRAM bank ease development. This done software once system booted each Master Matrix. When REMAP ignored. Refer Matrix Section more details. When REMAP allows user, ones convenience, external memory 0x0. This done hardware reset. Note that Memory blocks affected these parameters always seen their specified base addresses. complete memory presented Table Table 5-7. D940HF Matrix manages boot memory that depends level reset. internal memory area mapped between address 0x000F FFFF reserved this purpose. detected boot memory embedded ROM. detected boot memory memory connected Chip Select External Interface.
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
5.4.2.1 Boot Embedded system boots using Boot Program from embedded following steps listed below: Checks presence card with boot.bin file main dir: file found: Downloads code internal SRAM 0x300000 Executes Remap command Runs Boot code file found, downloads code from DataFlash®: Downloads code internal SRAM 0x300000 Checks presence valid code first words Executes Remap command Runs DataFlash Boot code case valid program detected external DataFlash: Activates Boot uploader enabling small monitor functionalities (read/write/run) interface with SAM-BA® application Performs automatic detection communication link: Serial communication DBGU (XModem protocol) Device Port (CDC Protocol) 5.4.2.2 Boot External Memory Boot slow clock (32,768 Boot with default configuration Static Memory Controller, byte select mode, 32-bit data bus, Read/Write controlled Chip Select, allows boot 32-bit non-volatile memory. custom-programmed software must perform complete configuration. speed boot sequence when booting NCS0 (BMS=0), user must take following steps: Program (main oscillator enable bypass mode). Program start PLL. Reprogram setup, cycle, hold, mode timings registers NCS0 adapt them clock Peripheral Data Controller (PDC). Switch main clock value.
Peripheral Data Controller (PDC)
acting master controls data transfer between chip peripherals: USARTs, SPIs, SSCs, MCI, DBGU, TWIs off-chip memories. This leaves both processors free from overhead related this function. following list defines channel mapping: CHANNEL22 PDC_RX_TX to/from TWI1 CHANNEL21 PDC_RX_TX to/from TWI0 CHANNEL20 PDC_TX DBGU
7010A-DSP-07/08
CHANNEL19 PDC_TX USART2 CHANNEL18 PDC_TX USART1 CHANNEL17 PDC_TX USART0 CHANNEL16 PDC_TX SPI1 CHANNEL15 PDC_TX SPI0 CHANNEL14 PDC_TX SSC3 CHANNEL13 PDC_TX SSC2 CHANNEL12 PDC_TX SSC1 CHANNEL11 PDC_TX SSC0 CHANNEL10 PDC_RX from DBGU CHANNEL9 PDC_RX from USART2 CHANNEL8 PDC_RX from USART1 CHANNEL7 PDC_RX from USART0 CHANNEL6 PDC_RX from SPI1 CHANNEL5 PDC_RX from SPI0 CHANNEL4 PDC_RX from SSC3 CHANNEL3 PDC_RX from SSC2 CHANNEL2 PDC_RX from SSC1 CHANNEL1 PDC_RX from SSC0 CHANNEL0 PDC_RX_TX to/from
Host
host acting master controls data exchange between host channels (port port Internal external memories. Host Port features: Compliance with Open specification Compliance with V2.0 Full-speed Low-speed Specification Supports both Low-speed Mbps Full-speed Mbps devices Root integrated with downstream ports embedded transceivers
Ethernet 10/100
Ethernet acting master controls data exchange between Ethernet channel Internal external memories. Ethernet hardware implementation sub-layer reference model between physical layer (PHY) logical link layer (LLC). controls data exchange between host layer according Ethernet IEEE 802.3u data frame format. Ethernet contains required logic transmits receives FIFOs
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
management. addition, interfaced through MDIO/MDC pins layer management. Ethernet transfer data through Reduced Media Independent Interface (RMII). interface reduction lower count switch product that connected multiple interfaces. RMII mode specific characteristics are: Single clock frequency Reduction required control pins Reduction data paths di-bit (2-bit wide) doubling clock frequency Mbits/sec. Mbits/sec. data capability reference clock obtained either from PCK0 output through PIOA16 which then goes toward both external D940HF EREFCLK from external dedicated oscillator.
MagicV JTAG
MagicV-JTAG provides JTAG interface MagicV core. converts JTAG commands coming from JTAG probe into cycles. Acting master access MagicV memories registers, thus allowing MagicV debug software control core resources: upload/download data programs configure functional debug registers.
System Internal
System internal consists Kbyte SRAM. internal SRAM accessed Double-Word bit), Word bit) Byte bit) format; neither BURST ACCESS PROTECTION supported. This internal SRAM split into decoded areas: Instruction TCM. user this SRAM block anywhere ARM926 instruction memory space using CP15 instructions. This SRAM block also accessible ARM926D Master enabled Masters through address 0x0010 0000. Data TCM. user this SRAM block anywhere ARM926 data memory space using CP15 instructions. This SRAM block also accessible ARM926-D Master enabled Masters through address 0x0020 0000. only accessible Masters. After reset until Remap Command performed, only (48Kbytes) accessible through address 0x00300000 enabled Masters. After Remap, becomes also accessible ARM926 Instruction ARM926 Data Masters through address Kbyte SRAM available, amount memory assigned each block then software programmable multiple This configuration defined through dedicated Matrix Special Function Register (see Section 14.5.6).
7010A-DSP-07/08
following table defines possible size configurations: ITCM possible sizes second row; DTCM possible sizes second column possible sizes remaining cells. Table 5-2. configuration
ITCM DTCM
Note that three 16kB blocks that constitute Internal SRAM, permanently assigned MEM. reset, whole memory (48kB) assigned MEM. memory blocks assigned ITCM, DTCM decoded areas contiguous when user changes dynamically Internal SRAM configuration through first Matrix Special Function Register (MATRIX SFR0), Kbyte block organization affect previous configuration from software point view. following table defines three Kbyte blocks (called SRAM mapped four possible configurations. Table 5-3. DTCM-ITCM configuration
ITCM=0kB DTCM=0kB AHB=48kB ITCM=16kB DTCM=0kB AHB=32kB SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM ITCM=0kB DTCM=16kB AHB=32kB ITCM=16kB DTCM=16kB AHB=16kB SRAM SRAM SRAM
Decoded Area ITCM DTCM
Address 0x0010_0000 0x0020_0000 0x0030_0000
0x0030_4000 0x0030_8000
performs access ITCM DTCM SRAM their buses single clock cycle MHz; ns); accesses ITCM SRAM DTCM SRAM D-AHB system clock cycles MHz; ns).
5.10
System Internal
internal internal stores boot-loader program. internal accessed only Double-Word format bit); neither BURST ACCESS PROTECTION supported.
5.11
External Interface (EBI)
Each enabled master access external memory resources through EBI. External incorporates Static Memory Controller (SMC) Synchronous Dynamic controller (SDRAMC).
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
features: Eight Chip Select Lines (four lines) 26-bit Address (four MSBs lines) 32-bit Data Multiple Access Modes supported Byte Write Lines Programmable Wait State Generation Programmable Data Float Time Slow clock mode supported
7010A-DSP-07/08
5.11.1
Static Memory Controller (SMC) gives enabled Hosts capability access following external memories: SRAM, Nor-Flash, EPROM, EEPROM. additional NAND LOGIC also provides with capability interface SmartMedia removable non-volatile memory cards Nand FLASH memory chips. additional Compact Flash logic provides with capability interface Compact Flash removable non-volatile memory cards.
5.11.2
Synchronous Dynamic Controller (SDRAMC) SDRAMC provides interface external 16-bit 32-bit SDRAM device. page size supports ranges from 2048 8192 columns from number 2048. supports byte (8-bit), half-word (16-bit) word (32-bit) accesses. SDRAMC supports read write burst length location. does support byte read/write bursts half-word write bursts. keeps track active each bank (avoiding precharge active when, changing bank, accessed), thus maximizing SDRAM performance, e.g., application placed bank data other banks. optimize performane advisable access different rows same bank. maximum number SDRAM locations that randomly accessed without penalty cycles (precharge, active) corresponds device size number banks. SDRAMC support size 2048 locations banks: hence maximum locations accessed without penalties. Anyway, typical SDRAM size 512/256 locations maximum 2K/1K locations accessed without penalties.
5.12
Memory Mapping
present section describes memory mapping ARM9System. Table shows D940HF global memory map:
Table 5-4.
D940HF Global Memory
masters
Start Address 0x0000 0000 0x1000 0000 0x9000 0000 0xF000 0000
Size (MB)
ARM9-I
ARM9-D
MagicV
m-JTAG
Internal Memories (See Table 5-6) External Memories (See Table 5-5) Undefined (Abort) Internal Peripherals (See Table 5-7)
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Table shows external memory mapping: Table 5-5. External Memory
masters Start Address 0x1000 0000 0x2000 0000 0x3000 0000 0x4000 0000 0x5000 0000 0x6000 0000 0x7000 0000 0x8000 0000 Size (MB) ARM9-I ARM-D MagicV m-JTAG
NCS0: (Generic Static Memory) NCS1: (Generic Static Memory) SDRAMC NCS2: (Generic Static Memory) NCS3: (Generic Static Memory SmartMedia/NAND-Flash) NCS4: (Generic Static Memory Compact Flash slot NCS5: (Generic Static Memory Compact Flash slot NCS6: (Generic Static Memory) NCS7: (Generic Static Memory)
1.Please refer Section 14.5.6.
Table shows internal memory mapping: Table 5-6. Internal Memory
masters
ARM9-I Size (MB) IntROM MagicV Magic Magic REMAP=0 BMS=1 IntROM BMS=0 NCS0 IntRAM REMAP=1 ARM9-D REMAP=0 BMS=1 IntROM BMS=0 NCS0 IntRAM I-TCM D-TCM REMAP=1 Magic mst# mJTAG
Start Address 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000 0x0040 0000 0x0050 0000 0x0060 0000
7010A-DSP-07/08
Table 5-7.
Internal Peripherals
masters
Start Address 0xF000 0000 0xFFFA 0000 0xFFFA 4000 0xFFFA 8000 0xFFFA C000 0xFFFB 0000 0xFFFB 4000 0xFFFB 8000 0xFFFB C000 0xFFFC 0000 0xFFFC 4000 0xFFFC 8000 0xFFFC C000 0xFFFD 0000 0xFFFD 4000 0xFFFD 8000 0xFFFD C000 0xFFFE 0000 0xFFFE 4000 0xFFFF 0000 0xFFFF EA00 0xFFFF EC00 0xFFFF EE00 0xFFFF F000 0xFFFF F200 0xFFFF F400 0xFFFF F600 0xFFFF F800 0xFFFF FA00 0xFFFF FC00 0xFFFF FD00 0xFFFF FE00
Size (byte)
ARM9-I
ARM9-D
reserved TWI-0 USART-0 USART-1 USART-2 SSC-0 SSC-1 SSC-2 SPI-0 SPI-1 SSC-3 TWI-1 CAN-0 CAN-1 reserved reserved SDRAMC HMATRIX DBGU reserved SYSC reserved
MagicV
m-JTAG
1.SYSC includes following peripherals: RSTC, RTT, PIT, WDG.
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
5.13 Peripherals
D940HF provides rich peripherals connected bus. enabled masters access these peripherals through AHB-APB bridge. 5.13.1 Peripheral Table defines Peripheral Identifiers D940HF. peripheral identifier required control peripheral interrupt with Advanced Interrupt Controller control peripheral clock with Power Management Controller. Table 5-8. Peripheral
Peripheral Clock Assignment Host Clock Assignment
Peripheral
USART-0 USART-1 USART-2 Device TWI-0 SPI-0 SPI-1 SSC-0 SSC-1 SSC-2 TIMER-0 TIMER-1 TIMER-2 HOST SSC-3 CAN-0 CAN-1
MAGIC Core
7010A-DSP-07/08
Table 5-8.
Peripheral (Continued)
Peripheral Clock Assignment Host Clock Assignment
Peripheral
5.13.2
Peripheral Multiplexing D940HF features three controllers, PIOA, PIOB PIOC, that multiplex lines peripheral set. Each controller manages thirty-two lines. Each line assigned peripheral functions, Table Table 5-11 define lines peripherals multiplexed Controllers. Note that some output only peripheral functions might duplicated within tables indicated with suffixes III. Line Resource Mapping
Periph INPUT Periph OUTPUT Periph INPUT Periph OUTPUT MagicV output: M_SIRQ0 EBI: output: CFCE1 (III) EBI: output: CFCE2 (III) dout (III) MagicV output: M_SIRQ2 TIMER bidir: TIMER_OUT TIMER bidir: TIMER_OUT DBGU output: DTXD(III) output: CKOUT output: (III) USART output: USART bidir: input: EXT_IRQ1 (also MagicV) bidir MDIO output output: FCE100 input: EREFCK input: ECRSDV input: ERX0 input: ERX1 input: ERXER output: ETX0 output: ETX1 input: EXT_IRQ2 (also MagicV) TIMER input: TIMER_IN output: CKOUT EBI: output: NCS4/CFCS0 (III) EBI: output: NCS5/CFCS1 (III) EBI: output: NCS6 (III) EBI: output: NCS7 (III) TEST output: m_ck TEST output: a_ck TIMER input: TIMER_IN output: (III) USART output: (III) MagicV output: M_SIRQ1
Table 5-9.
[10] [11] [12] [13] [14] [15] [016 [17] [18] [19] [20] [21] [22]
bidir: MISO bidir: MOSI bidir: bidir: output: output: output: USART input: USART bidir: USART input:
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Table 5-9.
[23] [24] [25] [26] [27] [28] [29] [30] [31] input: input: NWAIT output: NCS4/CFCS0 output: NCS5/CFCS1 output: NCS6 output: NCS7 output: CFCE1 output: CFCE2
Line Resource Mapping (Continued)
Periph INPUT Periph OUTPUT output: ETXEN Periph INPUT Periph OUTPUT MagicV output: M_SIRQ0 (III) MagicV output: M_SIRQ1 (III) USART output: (III) TIMER bidir: TIMER_OUT output: CKOUT output: SMOE output: SMWE output: CKOUT MagicV output: M_SIRQ3
Table 5-10.
[10] [11] [12] [13] [14] [15] [016 [17] [18] [19] [20] [21]
Line Resource Mapping
Periph INPUT SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: SSC: Periph OUTPUT Periph INPUT Periph OUTPUT output: (III) TIMER bidir: TIMER_OUT CKOUT (II) dout (II) USART (II) MagicV output: M_SIRQ1 (II) dout (III) TIMER bidir: TIMER_OUT CKOUT (II) output: (III) USART (III) EBI: A[22] (III) EBI: A[23] (III) MagicV output: M_SIRQ2 (II) EBI: A[24] (III) output: (II) output: (II) output: FCE100 (II) EBI: A[25]-CFRNW (III) MagicV output: M_SIRQ0 (II) output: (III) output: FCE100 (III)
7010A-DSP-07/08
Table 5-10.
[22] [23] [24] [25] [26] [27] [28] [29] [30] [31]
Line Resource Mapping (Continued)
Periph INPUT Periph OUTPUT SSC: SSC: TIMER input: TIMER_IN input: EXT_IRQ0 (also MagicV) dout EBI: A[22] EBI: A[23] EBI: A[24] EBI: A[25]-CFRNW Periph INPUT Periph OUTPUT USART (II) DBGU output: DTXD (II) MagicV output: M_MODE USART (II) output: (III) MagicV output: M_SIRQ3 (II) output: (II) output: (II) CKOUT (II) CKOUT 3(II)
Table 5-11.
[10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20]
Line Resource Mapping
Periph INPUT Periph OUTPUT Periph INPUT Periph OUTPUT SSC: (II) SSC: (II) SSC: (II) output: ETX0 (II) output: ETX1 (II) MagicV output: M_SIRQ3 (III) EBI: output: SMOE (III) SSC: (III) SSC: (III) SSC: (III) output: ETX0 (III) output: ETX1 (III) USART USART USART USART USART USART USART TIMER bidir: TIMER_OUT bi-directional: output: (II) SSC: (II) EBI: A[22] (II) EBI: A[23] (II) EBI: A[24] (II) EBI: A[25]-CFRNW (II) output: (II) output: (II) SSC: (III)
bi-directional: MISO bi-directional: MOSI bi-directional: bi-directional: output: output: output: bi-directional: bi-directional: TWCK USART USART USART
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Table 5-11.
[21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] DBGU input: DRXD DBGU output: DTXD
Line Resource Mapping (Continued)
Periph INPUT Periph OUTPUT Periph INPUT Periph OUTPUT output: (III) dout (II) MagicV output: M_SIRQ2 (III) EBI: SMOE (II) EBI: SMWE (II) EBI: NCS4/CFCS0 (II) EBI: NCS5/CFCS1 (II) EBI: NCS6 (II) dout EBI: NCS7 (II) EBI: CFCE1 (II) EBI: CFCE2 (II)
bi-directional: TWCK bidir: MCCK bidir: MCCDA bidir: MCDA0 bidir: MCDA1 bidir: MCDA2 bidir: MCDA3
After power PIO_A[21] PIO_A[22] started linked peripheral monitor clock MagicV clock right after power-up. After power-up PIO_A[23] gets started linked peripheral avoid that pull-up lets receive HIGH level ETXEN after power-up (ETXEN from after powerup). After power-up PIO_A[26] PIO_A[31] started linked peripheral Chip Select lines immediately after reset. After power-up PIO_B[28] PIO_B[31] started linked peripheral address bus. After power-up other lines start inputs controlled (not linked peripheral). PIO, apart from PIO_A[24], have embedded programmable pull-up (active after powerup). PIO_A[24] input internally connected (Boot Memory Select); needs external pull-up pull-down level (BMS sampled only reset rise). Pads from PIO_A[25] PIO_A[31] from PIO_B[28] PIO_B[31] powered VDDIOMP, rest pads powered VDDIOP.
5.13.3
System Controller (SYSC) SYSC includes Reset Controller (RSTC) System Timers. RSTC manages system resets: external devices reset, processors reset peripheral reset. sources reset Power-On, Watch Dog, reset, External reset. System Timers features: 16-bit Period Interval Timer (PIT)
7010A-DSP-07/08
12-bit key-protected Watchdog Timer (WDG) 20-bit Free-running Real-time Timer (RTT) 5.13.4 Power Management Controller (PMC) features clock sources: Slow Clock Oscillator (32.768 Main Oscillator MHz). dividers, Phase Lock Loops, allow generation wide range frequencies either from slow clock and/or from main clock. provides dedicated clocks toward: ARM926, Matrix, MagicV, MagicV Memories, USB, Ethernet Peripherals. 5.13.5 Advanced Interrupt Controller (AIC) features: Controls interrupt lines (nIRQ nFIQ) ARM926 Thirty-two individually maskable vectored interrupt sources Programmable Edge-triggered Level-sensitive Internal Sources Programmable Positive/Negative Edge-triggered High/Low Level sensitive 8-level Priority Controller Fast Forcing: allows redirection normal interrupt source nFIQ following table defines interrupt mapping:
Table 5-12.
source mapping
Type Edge/Level Negative/Positive Peripheral M_SIRQ0 from MagicV
Interrupt
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Table 5-12. source mapping
Type Peripheral SYSIRQ: SDRAMC, DBGU, SYSC, USART-0 USART-1 USART-2 Device TWI-0 Edge/Level Positive only SPI-0 SPI-1 SSC-0 SSC-1 SSC-2 TIMER-0 TIMER-1 TIMER-2 Host SSC-3 CAN-0 CAN-1 M_HALT from MagicV M_SIRQ0 from MagicV M_EXC from MagicV END_DMA from MagicV Edge/Level Negative/Positive EXT_IRQ0 from PIOB25 also MagicV SHARM_IRQ1[0] EXT_IRQ1 from PIOA12 also MagicV SHARM_IRQ1[1] EXT_IRQ2 from PIOA14 also MagicV SHARM_IRQ1[2]
Interrupt
5.13.6
Parallel Input/Output (PIO) three PIOs provide globally programmable Lines.
7010A-DSP-07/08
These lines fully programmable through Set/Clear registers linked peripheral functions. Each Line (assigned peripheral used general purpose I/O) provides: Input change interrupt Glitch filter Multi-drive option enables driving open drain Programmable pull each line data status register supplies visibility level time 5.13.7 Universal Synchronous Device (USBD) Device provides communication services between external host D940HF. device connected through FIFO. Device features: V2.0 full-speed compliant, Mbits second Embedded V2.0 full-speed transceiver Embedded dual-port endpoints Suspend/Resume logic Embedded Transceivers 5.13.8 Timer Counter (TC) consists three 16-bit Timer Counter Channels providing wide range functions including: Frequency Measurement Event Counting Interval Measurement Pulse Generation Delay Timing Pulse Width Modulation Up/down Capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs multi-purpose input/output signals 5.13.9 Wire Interface (TWI) D940HF provides independent TWIs. Each interconnects components unique two-wire bus, made clock line data line which speed Kbits second, based byte oriented transfer format. Each programmable master, multi-master slave mode with sequential singlebyte access. configurable baud rate generator allows output data rate adapted wide range core clock frequencies.
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
5.13.10 Universal Synchronous Asynchronous (USART) D940HF provides three independent USARTs. Each USART features: Synchronous Asynchronous mode Programmable Baud Rate Generator 115.2 Kbps Asynchronous Mode system clock frequency Synchronous Mode) RS485 with driver control signal ISO7816, Protocols interfacing with smart cards IrDA modulation demodulation connection 5.13.11 Serial Synchronous Controller (SSC) D940HF provides four independent SSCs. Each provides programmable serial synchronous communication link used audio telecom applications (CODECs Master Slave Modes, I2S, Buses, Magnetic Card Reader, SPI, etc.). connection allows direct data transfer between CODECs either MagicV data memory internal memory external memories. 5.13.12 Serial Peripheral Interface (SPI) D940HF provides independent SPIs. Each supports communication with serial external devices such DataFlash, ADCs, DACs, Controllers, Controllers Sensors. Four chip selects with external decoder supports allow communication with peripherals. connection allows direct data transfer between these serial devices either MagicV data memory internal memory external memories. 5.13.13 Debug Unit (DBGU) DBGU 2-wire UART dedicated Debug Communication. DBGU channels associated with channels. Debug Unit also generates Debug Communication Channel (DCC) signals provided In-circuit Emulator processor visible software. These signals indicate status read write registers generate interrupt processor, allowing handling under interrupt control.
7010A-DSP-07/08
5.13.14
Controller Area Network (CAN) D940HF provides independent CANs. Each fully compliant with Part Part supports bit/rate Mbps.
5.13.15
Multimedia Card Interface (MCI) D940HF provides MCI. slots, each supporting: slot MultiMediaCard cards) Memory Card connection allows direct data transfer between these serial devices MagicV data memory, internal memory external memories.
5.14
ARMSystem-MagicV interface
MagicV connected System through master slave Addition, System MagicV exchange discrete lines cores interconnection. following lines from System MagicV: three external interrupt input lines that from external (through PIO) also sharm_irq1[2:0] lines MagicV (that activates MagicV Int1 internal interrupt line). When line programmed controlled used activate interrupt toward MagicV. four internal interrupt lines that from SSC(0-3) also sharm_irq0[3:0] lines MagicV (that activates MagicV Int0 internal interrupt line). NINT line that goes from fast interrupt NFIQ NIRQ toward ARM) goes also sharm_irq1[3] line MagicV (that activates Int1 MagicV internal interrupt line). clock line that goes from TIMER (TCOA1) external (through PIO) also goes arm_irq[0] line MagicV. When line programmed controlled used activate interrupt toward MagicV Int2 internal interrupt line. interrupt line that goes from SPI0 goes also arm_irq[1] line MagicV Int3 internal interrupt line. clock lines from MagicV providing MagicV main clock (Peripheral Clock[26]) MagicV memories clock (PCLK[4] Peripheral Clock[26]). peripheral reset line that goes from CNTL peripherals goes also MagicV. Four generic interrupt lines M_SIRQ[3:0] from MagicV external (through PIO). these four interrupt lines (MSIRQ[1:0]) also direct input AIC. other lines (MSIRQ[2:3]) also used interrupt source programming related line event detection interrupt. This implies that MSIRQ[1:0] generates interrupts with high pulses, while MSIRQ[2:3] generates interrupts with toggling level signals. Three dedicated interrupt lines (M_EXC, M_HALT, END_DMA) from MagicV AIC. dedicated status line (M_MODE) goes from MagicV external (through PIO).
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
cross-triggering debug request line goes from MagicV Debug unit debug unit signal MagicV debug request event toward debugger. cross-triggering debug request line goes from debug unit MagicV debug unit signal debug request event toward MagicV debugger.
7010A-DSP-07/08
Magic VLIW Overview
Overview
mAgicV high performance Very Long Instruction Word (VLIW) delivering Giga floating-point operations second (GFLOPS) Gops clock rate MHz. equipped with master port slave port system-on-chip integration. 256x40-bit data registers, 16x64-bit multi-field address registers support oriented addressing modes like circular stride accesses, arithmetic operating units, independent AGUs (Address Generation Unit) engine. sustain internal parallelism, data bandwidth through Register File byte/cycle. architecture optimized work complex domain. When activating computing units, mAgicV produce complete butterfly cycle. also supports natively vectorial arithmetic operations. mAgicV operates IEEE 40-bit extended precision floating-point 32-bit integer numeric format numerical computations. Figure 6-1. mAgicV block diagram
External interrupts
2-port 8Kx128 Program Memory Interrupt controller Decompressor Flow Controller
Debug logic
Master
Engine
Slave
port3 (master) AGU0 add0 AGU1 add1
port2 (slave)
4-port 16Kx40(8Kx80) Data Memory
Data Memory Bank0 8Kx40 Data Memory Bank1 8Kx40
256x40 (128x80)
4R+4W 128x40 4R+4W 128x40
4x16x16-bit Address Register File
Operator block
10-float 40bit ops/cycle
(agu0) port0
(agu1) port1
Harvard memory architecture composed on-chip 2x8Kx40-bit data memory on-chip 8Kx128-bit program memory. Efficient usage program memory achieved through mechanism program compression, performed software tool chain supported hardware decompression engine. program memory management unit supports virtual program space 64Kx128-bit locations. Interrupts vectorized minimize interrupt service latency.
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
VLIW overview
VLIW processors execute operations parallel based fixed schedule determined when programs compiled. Since determining order operations execution (including which operations executed simultaneously) handled compiler, processor does need hardware support scheduling. result, VLIW CPUs offer significant computational power with less hardware complexity (but greater compiler complexity) compared with most superscalar CPUs. rows mAgicV program memory wide. When "default" decoding scheme applied program word, composed bits, drives five execution units through five operation VLIW fields named issues. Eight additional bits drive program decompression engine. mAgicV' issues named: FLOW, AGU0, MUL, AGU1, ADD. Figure 6-2.
FLOW
conceptual representation issues default VLIW decoding scheme
AGU0 AGU1
issues associated pair independent AGUs. issues drive respectively add/subtract multiplier Operator units. FLOW issue manages program flow unit. Each issue predicated predication register conditional execution without pipeline breaking penalties.
Program Memory
Program Memory system contains 8K*128-bit on-chip memory locations supporting accesses/cycle. 1-accesses/cycle reserved core fetch program, while other access used internal master (i.e: DMA) internal slave (e.g.: debug accesses executed external master) accesses. read latency during program fetch 1-cycle. While write read latencies through shown Table 6-1. efficient usage Program Memory achieved through program memory decompressor engine that able decompress, single clock cycle, words that stored using compression format. that total latency program fetch, including compression, cycles.
Register File
provide optimal data bandwidth give best support RISC-like programming model, mAgicV arithmetic computations supported 16-port 256x40-bit entries Register File (RF). registers numbered from RF255. registers accessed individually scalar operations pairs aligned even addresses operations complex vectorial domain.
Operator Block
Operator Block performs arithmetical operations. works 32-bit signed integers IEEE extended precision 40-bit floating-point data. 16-bit unsigned signed integers managed AGUs 16-bit. operators arranged order support: arithmetic complex domain (throughput complex multiply, multiply cycle); fast (throughput complete butterfly computation cycle);
7010A-DSP-07/08
vectorial arithmetic acting operands constituted pairs data.The operator block able launch vectorial multiply plus vectorial every cycle; scalar arithmetic acting data pairs.The operator block able launch every cycle pair scalar multiply scalar add; peak performance mAgicV achieved during single cycle butterfly execution, when mAgicV delivers floating-point 32-bit signed integer operations clock cycle. operands manipulated operator block specified addresses. addresses scalar domain operations even. Vectorial Complex operand pairs need even addresses.
On-Chip Data Memory
Data Memory System contains banks locations 40-bit words on-chip data memory. On-chip Data Memory System provides maximum throughput words/cycle. On-chip Data Memory simultaneously accessed three subjects: computational data path, master slave. Simultaneously, computational datapath fetch store maximum four 40-bit data cycle, master drive single access 32-bit word cycle slave support single accesses 32bits cycle. simultaneous activity master slave requires external multilayer matrix implementation. Each access through (and/or through P1B) either transfer single 40-bit data (scalar access) access pair consecutive memory locations aligned even addresses (for operation complex vectorial data types). Accesses through reserved computational data-path their addresses generated AGU0 AGU1. Figure Data Memory system. Figure 6-3. Quad port Data Memory
2x8K
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Address Generation Units
There identical Address Generation Units mAgicV named AGU0 AGU1. Each driven dedicated VLIW issue. generate complex/vectorial scalar accesses. complex/vectorial mode words accesses instead (scalar mode). supports linear addressing oriented features like circular buffers. address generation unit supported multi field Address Registers File (ARF) composed 4x16x16-bit registers, total 16-bit integer registers. Register named A0-A15 used manage integers/pointers, while M0-M15 registers 16-bit integer/pointer modifiers. When circular buffers used, S0S15 store start addresses buffers, while L0-L15 store their lengths (zero length means circular buffer). Each contains also private 16-bit register (TMP0 TMP1) which used arithmetic addressing operations. able perform 16-bit signed/unsigned integer arithmetic operations parallel activities 40-bit floating point 32-bit signed integer operator block. Figure 6-4.
64-bit register
every clock cycle each perform both addressing (addressing mode) arithmetic operations (arithmetic mode). output both arithmetic addressing operations written field register internal register named TMP. compiler, generating both addressing arithmetic operations, exploit different solutions terms issue generation. most compact orthogonal solution generate issues that select single 64-bit ARFx; sometimes convenient 16-bit field from different 64-bit ARF. When different used, some other issues inhibited because need additional coding bits, which creates overlapping other issues.
Slave Port
slave AMBA compliant, directly pluggable into AHB-lite system. give only "OK" "ERROR" responses AMBA transactions, never issues "RETRY" "SPLIT". Errors revealed following cases: wrong address space (address space existent) data size 32-bit (i.e. byte half-word accesses permitted) address 32-bit aligned (i.e. need "00")
case error pulse signal raised registered into MGCEXCEPTION register. Slave decoder receives clocks, side other related core side.
7010A-DSP-07/08
There must integer ratio between clock frequencies (i.e. 1:2, 3:1, etc. etc.); skew between rising edges clocks need carefully controlled relative phase must stable. mAgicV implementation manual details insert clock-tree inside SoC. Slave accesses pipelined; each access decoded issued slave decoder block running core frequency when completed access processed. During processing time slave emits "WAIT" answer. Slave decodes three addressing regions: program memory, data memory registers, with different access times. Table 6-1. Addressing Regions
Write Latency Read Latency
Resource DM_I DM_F DM_D REGS RESERVED
Start Address 0x00600000 0x00620000 0x00640000 0x00660000 0x00680000 0x00682000
Address 0x0061FFFF 0x0062FFFF 0x0064FFFF 0x0067FFFF 0x00681FFF 0x006FFFFF
Size 128KB 64KB 64KB 128KB 632KB
Access word32 word32 word32 word32 word32 word32
Master Port
master AMBA compliant, directly pluggable into system. does implement protection default value issued). supports only accesses. issues only incremental bursts unspecified length, even case single transfers. does emit wait states. Master grant always asserted arbitration present, it's under addressed slave's responsibility on-going transfer modulating HREADY signal) following picture indicates main parts master engine. When channel ready start transfer turns master data move to/from core memories. FIFOs controlled signals side decoder interface that transmits receives data from memories through master decoder block that responsible correctness check data dispatching.
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Figure 6-5. master engine
Write data fifo
interface
Read data fifo
Decoder interface
engine
slave interface
mAgicV Core interfaces
master activated engine companion. master first chooses next winning channel according fixed priority algorithm, then copies transfer parameters starts cycles soon possible. programmable length words burst then managed directly master: core engine asks delivers data internal memories side manages protocol. Between part core part there FIFOs, transmitting locations) other receiving data locations). sides clocked different clock frequencies, with fixed ratio with fixed relative phase (ratios like 2:1, 4:1, etc. etc. allowed). different clocked worlds separated FIFO. Whenever transfer write from internal memories running data transfer interrupted after completion current data transfer then continued after re-gaining grant, without need busy issuing that would occupy wast useful bandwidth. Whenever transfer read from memories filling FIFO, transfer interrupted after completion current data transfer; master will then transfer FIFO content internal memories only when FIFO will empty transfer will continue after re-gaining grant, without need busy issuing that would waste cycles.FLOW Control Block
6.10
FLOW Control Block
FLOW control block performs following tasks: Registers movement
7010A-DSP-07/08
Program flow control Condition management FLOW issue many formats FLOW code change default format other issues. basic default format FLOW shown Figure 6-6. Figure 6-6.
vliw[3:2] FLOW predication
default FLOW issue
vliw[118:113] vliw[51:50]
FLOW code
FLOW predication write
FLOW predication specifies four predication registers, condition pointed predication register "false" (logic `0') issue will executed. NOTE: FLOW codes predicated. FLOW code specifies FLOW operations performed. FLOW predication write specifies predication destination address.
6.11
Program Management Unit
mAgicV architecture specifies 16-bit virtual program memory space (64K 128-bit words). This virtual space mapped into physical 13-bit physical program memory space PMU. word (program word) composed bit, maps words external program memory words internal memory. external program memory space divided into pages words. Each word page divided itself into sixteen chunks, each composed words, described following Figure. Figure 6-7.
Virtual address
virtual page
chunk
offset
efficient page replacement alghorithm realized hardware avoid software overhead. possible instruct physical pages, excluding them from replacement algorithm. Each physical pages associated PMUMAPPEDVIRT register used specify virtual page (each page described PMUVIRT registers) chunks already loaded internal memory. every cycle types faults generated: Page fault Chunk fault page fault generated when virtual page isn't physically mapped into eight internal physical pages. this case finds physical page host virtual page.
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
physical pages allocated, will replace most recently used page with one, using hardware replacement algorithm which operates register
6.12
Data Formats
mAgicV supports data type shown Table 6-2. Table 6-2.
type half-word word 16-bits 32-bits
data types
Data width Description used signed/unsigned 16-bit integers used signed 32-bit integers used either external memory storage 32-bit standard precision floating-point data 32-bit data communication through AMBA interface used internal floating point computation (extended IEEE754 format) used either external memory storage extended precision floating-point data extended precision data communication through AMBA interface
32-bits
extended-word
40-bits
64-bits
6.13
Data Organization
memory data stored quantities (extended-word). Integers quantities have padded with zero. Vector accesses occupy consecutive addresses vector memory access with addresses generates exceptions). "right" part vector quantity contained lower addresses. following figures show representation Table data types. Figure 6-8.
half-word unsigned
000000000000000000000000
halfword
Figure 6-9.
half-word signed extended
00000000
1111111111111111
halfword
Figure 6-10. word
00000000
word
full 64-bit (SLAM) register packed memory using consecutive words. Figure 6-11. even word
00000000
field
field
7010A-DSP-07/08
Figure 6-12. word
00000000
field
field
6.14
States
mAgicV supports main modes: debug. When processor mode there three other possible states: step, sleep, interrupt. Mode changes either caused software control (i.e. FLOW opcodes accesses from external masters through slave interfaces, both writing MGCCTRL register), activated external interrupts exceptions processing. mode interrupted higher priority mode never lower priority mode. external master change mAgicV state. Nested interrupts aren't supported. Table 6-3.
Priority
States
State debug Description core pipelines frozen, it's safe access internal memories registers through slave interface. Pending completed. pipeline frozen state running waiting some events. This mode used mainly combination with write/read operations wait transfer (EOT). Causes cycle state followed debug state mAgicV executing ISR. pipelines running, interrupts arriving other lines stored will served after execution RETI instruction. Hardware support pipeline disabled. pipelines running. Interrupt will served branches execution.
sleep step interrupt
6.15
Multicore Synchronization Support
mAgicV provides mutexes safely manage resources shared between external master controller mAgicV core. There predefined meaning mutex registers. association among mutex shared resources driven software that must control code manage access shared resources. hardware guarantees atomic write test operation lock mutexes, fixed priority (external master first) contemporaneous write accesses.
6.16
Event Handling
When event occurs execution instruction stream passed event handler address specified MGCINTSVR registers. resumed previous sleep mode. halted then pass into debug mode.
6.16.1
Interrupt handling mAgicV allows very fast interrupt handling, treating interrupts routine processor instruction (branch, call, ret). Interrupts don't break pipelines save only return program counter into read only MGCINTRET register. mAgicV doesn't cross protection domains take interrupt.
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Since protection domain remains unchanged interrupt, Interrupt Service Routine called normal function call. There prioritized interrupt lines. Line0 line1 multiplex four lines each (named shared lines), that number interrupt lines Each interrupt line associated interrupt vector register (MGCINTSVR) that must valid program address, corresponding handler interrupt routine. interrupt, previously enabled masked interrupt line (via MGCINTCTRL register), registered into PEND field MGCINTSTAT interrupt status register. Interrupts masked using MGCINTMASK, masked interrupt always registered pending interrupt, won't served until it's masked. When program jumps Interrupt Service Routine ISVR MGCSTAT will set, indicating that more interrupts will served until return from interrupt instruction (RETI) executed. user code return address saved into MGCINTRET register it's automatically restored into MGCPC register when RETI issue executed. case more than pending interrupts, line having higher priority will served, case equal priority interrupt line with lower number will served. priority register MGCINTPRIO register that allows associate three priority bits each line. Pending interrupts cleared using MGCINTSETRESET; this feature used generate clear interrupts software over each line. Sleep wake-up. 6.16.2 Sleep Wakeup mAgicV sleep mode writing MGCCTRL register using explicit FLOW codes. processor will waken interrupts, four (End Transfer) events coming from DMA. events that wake mAgicV from sleep state selected using MGCWAKECTRL control register. Exceptions mAgicV exceptions divided into fatal fatal exceptions. masked fatal exceptions cause processor stop immediately enter into debug mode. Other exceptions handled mode exception interrupt routine number Exception register MGCEXCEPTION collects exceptions.
6.16.3
6.17
Profiling Registers
user able evaluate performance system through mAgicV counter registers. MGCSTEP register used collect information cycles spent mode. includes cycles pipeline stall program cache miss sleep mode. This counter accessed mAgicV external master controller. possible start stop MGCSTEP counter register accessing respectively TICKON TICKOFF MGCCTRL control bits interrupt handler installed line, signalling overflow this counter. overflow registered MGCSTAT register it's cleared write operations MGCSTEP register. PMUMISSCNT register used collect information about number programs misdone. This register accessed only external master controller.
7010A-DSP-07/08
These events monitored reading PMUSTAT.Debug
6.18
Debug
debug features accessed external master that read write mAgicV internal resources (memories registers). There limitation writing RF'registers.
6.18.1
Breakpoint Support mAgicV supports breakpoints toggling program VLIW corresponding breakpoint pma. setting PMCHKON BREAKON MGCCTRL control register, parity error detected interpreted breakpoint (MGCSTAT's PTY2BREAK flag). external debug engine should check triggered breakpoint break point real parity exception. Watch Point Support mAgicV supports watchpoints through watch point register MGCWATCH that must contain internal data address watched variable. watch-point logic detects write operations upon specified watch address. MGCCTRL's WATCHON must enable watchpoints. Cross Triggering Support main function Cross Triggering pass debug events from processor another. communicate debug state information from core (mAgicV) another, that, required, program execution both processors stopped same time. mode enabled mAgicV setting MGCCTRL's TRIGGON bit. this mode dedicated mAgicV input line (dbg_req_from_arm) used mAgicV immediately cycle latency) debug mode. Vice versa mAgicV dedicated output line communicate debug state another core(dbg_req_to_arm).
6.18.2
6.18.3
6.18.4
Step Mode Support this mode program executed step step; this possible examine internal registers each cycle. external master controller activate this mode setting MGCCTRL's STEPON bit. controller advance program execution cycle setting MGCCTRL's CONTINUE bit. NOTE: this mode cannot interrupted continues even core frozen), that temporizations altered compared normal mode. example, presence DMA, MGCSTEP counts less cycles than normal mode.
6.19
engine single channel with independent programmable registers. able perform following 32-bit word memory accesses: fixed external and/or internal address incremental external and/or internal address incremental address with fixed external and/or internal modifier ("jump" "stride") incremental address, wrapping around specified length external and/or internal address above mixed above, using last accessed external and/or internal addresses reloading them
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
temporary conditions bus, like loosing grant page fault retry/split condition, change channel that currently operating (i.e. arbitration). channels serially processed have fixed priority, highest channel number lowest number Highest priority channel used enabled), channel parameters have always considered scratched user application because they modified PMU. Several parameters (like chunck length, modifiers, external addresses) bootstrap they must kept fixed during program execution. Many parameters could fixed throughout entire application; moreover, thanks possibility redo transfer continue transfer with same parameters current addresses, could also convenient assign channel specific repetitive task, saving most programming costs (i.e access peripheral registers). NOTE: Only 32-bit word accesses supported.
7010A-DSP-07/08
ARM926EJ-S Processor Overview
Overview
ARM926EJ-S processor member ARM9family general-purpose microprocessors. ARM926EJ-S implements architecture version 5TEJ targeted multitasking applications where full memory management, high performance, size power important features. ARM926EJ-S processor supports 32-bit 16-bit THUMB instruction sets, enabling user trade between high performance high code density. also supports 8-bit Java instruction includes features efficient execution Java bytecode, providing Java performance similar (Just-In-Time compilers), next generation Javapowered wireless embedded devices. includes enhanced multiplier design improved performance. ARM926EJ-S processor supports debug architecture includes logic assist both hardware software debug. ARM926EJ-S provides complete high performance processor subsystem, including: ARM9EJ-Sinteger core Memory Management Unit (MMU) separate instruction data AMBAAHB interfaces separate instruction data interfaces
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Block Diagram
ARM926EJ-S Internal Functional Block Diagram
ARM926EJ-S
Interface Coprocessor Interface EInterface DEXT
Figure 7-1.
Droute
Data Interface
DCACHE Interface Unit
WDATA
RDATA
ARM9EJ-S
EmbeddedICE
Processor
Instruction Interface
INSTR Interface
ICACHE Iroute
IEXT
7.3.1
ARM9EJ-S Processor
ARM9EJ-S Operating States ARM9EJ-S processor operate three different states, each with specific instruction set: state: 32-bit, word-aligned instructions. THUMB state: 16-bit, halfword-aligned Thumb instructions. Jazelle state: variable length, byte-aligned Jazelle instructions. Jazelle state, instruction Fetches words.
7.3.2
Switching State operating state ARM9EJ-S core switched between: state THUMB state using instructions, loads
7010A-DSP-07/08
state Jazelle state using instruction exceptions entered, handled exited state. exception occurs Thumb Jazelle states, processor reverts state. transition back Thumb Jazelle states occurs automatically return from exception handler. 7.3.3 Instruction Pipelines ARM9EJ-S core uses kinds pipelines increase speed flow instructions processor. five-stage (five clock cycles) pipeline used Thumb states. consists Fetch, Decode, Execute, Memory Writeback stages. six-stage (six clock cycles) pipeline used Jazelle state consists Fetch, Jazelle/Decode (two clock cycles), Execute, Memory Writeback stages. 7.3.4 Memory Access ARM9EJ-S core supports byte (8-bit), half-word (16-bit) word (32-bit) access. Words must aligned four-byte boundaries, half-words must aligned two-byte boundaries bytes placed byte boundary. Because nature pipelines, possible value required before been placed register bank actions earlier instruction. ARM9EJ-S control logic automatically detects these cases stalls core forward data. 7.3.5 Jazelle Technology Jazelle technology enables direct efficient execution Java byte codes processors, providing high performance next generation Java-powered wireless embedded devices. Java feature ARM9EJ-S described hardware emulation (Java Virtual Machine). Java mode appears another state: instead executing Thumb instructions, executes Java byte codes. Java byte code decoder logic implemented ARM9EJ-S decodes executed byte codes turns them into instructions without overhead, while less frequently used byte codes broken down into optimized sequences instructions. hardware/software split invisible programmer, invisible application invisible operating system. existing registers re-used Jazelle state registers then have particular functions this mode. Minimum interrupt latency maintained across both state Java state. Since byte codes execution restarted, interrupt automatically triggers core switch from Java state state execution interrupt handler. This means that special provision made handling interrupts while executing byte codes, whether hardware software. 7.3.6 ARM9EJ-S Operating Modes states, there seven operation modes: User mode usual program execution state. used executing most application programs Fast Interrupt (FIQ) mode used handling fast interrupts. suitable high-speed data transfer channel process Interrupt (IRQ) mode used general-purpose interrupt handling
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Supervisor mode protected mode operating system Abort mode entered after data instruction prefetch abort System mode privileged user mode operating system Undefined mode entered when undefined instruction exception occurs Mode changes made under software control, brought about external interrupts exception processing. Most application programs execute User Mode. non-user modes, known privileged modes, entered order service interrupts exceptions access protected resources. 7.3.7 ARM9EJ-S Registers ARM9EJ-S core total registers. general-purpose 32-bit registers 32-bit status registers Table shows registers modes. Table 7-1.
User System Mode
ARM9TDMIModes Registers Layout
Supervisor Mode R13_SVC R14_SVC Undefined Mode R13_UNDEF R14_UNDEF Interrupt Mode R13_IRQ R14_IRQ Fast Interrupt Mode R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ
Abort Mode R13_ABORT R14_ABORT
CPSR
CPSR SPSR_SVC
CPSR SPSR_ABORT
CPSR SPSR_UNDEF
CPSR SPSR_IRQ
CPSR SPSR_FIQ
Mode-specific banked registers
7010A-DSP-07/08
state register contains directly-accessible registers, r15, additional register, Current Program Status Register (CPSR). Registers general-purpose registers used hold either data address values. Register used Link register that holds value (return address) when executed. Register used program counter (PC), whereas Current Program Status Register (CPSR) contains condition code flags current mode bits. privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers mode other modes) become available. corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und similarly used hold values (return address each mode) (PC) when interrupts exceptions arise, when instructions executed within interrupt exception routines. There another register called Saved Program Status Register (SPSR) that becomes available privileged modes instead CPSR. This register contains condition code flags current mode bits saved result exception that caused entry current (privileged) mode. modes software agreement, register used stack pointer. function registers described above should obey Procedure Call Standard (APCS) which defines: constraints registers stack conventions argument passing result return Thumb state register subset state set. programmer direct access Eight general-purpose registers r0-r7 Stack pointer, Link register, (ARM r14) CPSR There banked registers SPs, SPSRs each privileged mode (for more details ARM9EJ-S Technical Reference Manual, ref. DDI0222B, revision r1p2 page 2-12). 7.3.7.1 Status Registers ARM9EJ-S core contains CPSR, five SPSRs exception handlers use. program status registers: hold information about most recently performed operation control enabling disabling interrupts processor operation mode
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Figure 7-2. Status Register Format
Reserved
Mode
Jazelle state Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than
Mode bits Thumb state disable disable
Figure shows status register format, where: Negative, Zero, Carry, Overflow four flags Sticky Overflow flag certain multiply fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, SMLAWy needed achieve operations. flag sticky that, when instruction, remains until explicitly cleared instruction writing CPSR. Instructions cannot execute conditionally status flag. CPSR indicates when ARM9EJ-S core Jazelle state, where: processor Thumb state, depending processor Jazelle state. Mode: five bits encode current processor mode 7.3.7.2 Exceptions Exception Types Priorities
ARM9EJ-S supports five types exceptions. Each type drives ARM9EJ-S privi-
leged mode. types exceptions are: Fast interrupt (FIQ) Normal interrupt (IRQ) Data Prefetched aborts (Abort) Undefined instruction (Undefined) Software interrupt Reset (Supervisor) When exception occurs, banked version SPSR exception mode used save state. More than exception happen time, therefore ARM9EJ-S takes arisen exceptions according following priority order: Reset (highest priority) Data Abort Prefetch Abort BKPT, Undefined instruction, Software Interrupt (SWI) (Lowest priority)
7010A-DSP-07/08
BKPT, Undefined instruction, exceptions mutually exclusive. There exception priority scheme though, when FIQs enabled Data Abort occurs same time FIQ, ARM9EJ-S core enters Data Abort handler, proceeds immediately vector. normal return from causes Data Abort handler resume execution. Data Aborts must have higher priority than FIQs ensure that transfer error does escape detection. Exception Modes Handling Exceptions arise whenever normal flow program must halted temporarily, example, service interrupt from peripheral. When handling exception, ARM9EJ-S core performs following operations: Preserves address next instruction appropriate Link Register that corresponds mode that been entered. When exception entry from: Jazelle states, ARM9EJ-S copies address next instruction into (current PC(r15) depending exception). THUMB state, ARM9EJ-S writes value into offset value (current depending exception) that causes program resume from correct place return. Copies CPSR into appropriate SPSR. Forces CPSR mode bits value that depends exception. Forces fetch next instruction from relevant exception vector. register also banked across exception modes provide each exception handler with private stack pointer. ARM9EJ-S also interrupt disable flags prevent otherwise unmanageable nesting exceptions. When exception completed, exception handler must move both return value banked minus offset SPSR CPSR. offset value varies according type exception. This action restores both CPSR. fast interrupt mode seven private registers (banked registers) reduce remove requirement register saving which minimizes overhead context switching. Prefetch Abort aborts that indicates that current memory access cannot completed. When Prefetch Abort occurs, ARM9EJ-S marks prefetched instruction invalid, does take exception until instruction reaches Execute stage pipeline. instruction executed, example because branch occurs while pipeline, abort does take place. breakpoint (BKPT) instruction feature ARM9EJ-S that destined solve problem Prefetch Abort. breakpoint instruction operates though instruction caused Prefetch Abort. breakpoint instruction does cause ARM9EJ-S take Prefetch Abort exception until instruction reaches Execute stage pipeline. instruction executed, example because branch occurs while pipeline, breakpoint does take place. 7.3.8 Instruction Overview instruction divided into: Branch instructions
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Data processing instructions Status register transfer instructions Load Store instructions Coprocessor instructions Exception-generating instructions instructions executed conditionally. Every instruction contains 4-bit condition code field (bits[31:28]). Table gives instruction mnemonic list. Table 7-2.
Mnemonic
SMULL SMLAL LDRSH LDRSB LDRH LDRB LDRBT LDRT
Instruction Mnemonic List
Operation
Move Subtract Reverse Subtract Compare Test Logical Logical Exclusive Multiply Sign Long Multiply Signed Long Multiply Accumulate Move Status Register Branch Branch Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move Coprocessor Load Coprocessor Coprocessor Data Processing STRH STRB STRBT STRT SSWPB Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor
Mnemonic
UMULL UMLAL
Operation
Move with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Clear Logical (inclusive) Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch Link Software Interrupt Store Word
7010A-DSP-07/08
7.3.9
Instruction
Table 7-3.
Mnemonic
SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB
Instruction Mnemonic List
Operation
Branch exchange Java Branch, Link exchange Signed Multiply Accumulate Signed Multiply Accumulate Long Signed Multiply Accumulate Signed Multiply Signed Multiply Saturated Saturated with Double Saturated subtract Saturated Subtract with double
Mnemonic
MRRC MCR2 MCRR CDP2 BKPT STRD STC2 LDRD LDC2
Operation
Move double from coprocessor Alternative move coprocessor Move double coprocessor Alternative Coprocessor Data Processing Breakpoint Soft Preload, Memory prepare load from address Store Double Alternative Store from Coprocessor Load Double Alternative Load Coprocessor Count Leading Zeroes
Notes:
Thumb contains consecutive Thumb instructions, takes four cycles.
7.3.10
Thumb Instruction Overview Thumb instruction re-encoded subset instruction set. Thumb instruction divided into: Branch instructions Data processing instructions Load Store instructions Load Store multiple instructions Exception-generating instruction Table gives Thumb instruction mnemonic list. Table 7-4.
Mnemonic
Thumb Instruction Mnemonic List
Operation
Move Subtract Compare Test Logical Logical Exclusive
Mnemonic
Operation
Move with Carry Subtract with Carry Compare Negated Negate Clear Logical (inclusive)
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Table 7-4.
Mnemonic
LDRH LDRB LDRSH LDMIA PUSH
Thumb Instruction Mnemonic List (Continued)
Operation
Logical Shift Left Arithmetic Shift Right Multiply Branch Branch Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register stack Conditional Branch
Mnemonic
STRH STRB LDRSB STMIA BKPT
Operation
Logical Shift Right Rotate Right Branch, Link, Exchange Branch Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Register from stack Breakpoint
CP15 Coprocessor
Coprocessor System Control Coprocessor CP15, used configure control items list below: ARM9EJ-S Caches (ICache, DCache write buffer) Other system options control these features, CP15 provides additional registers. Table 7-5. Table 7-5.
Register
CP15 Registers
Name Code(1) Cache type(1) status Control Translation Table Base Domain Access Control Reserved Data fault Status
Read/Write Read/Unpredictable Read/Unpredictable Read/Unpredictable Read/write Read/write Read/write None Read/write Read/write Read/write Read/Write Unpredictable/Write Read/write
Instruction fault status(1) Fault Address Cache Operations operations Cache lockdown(2)
7010A-DSP-07/08
Table 7-5.
Register Notes:
CP15 Registers
Name region lockdown Reserved Reserved FCSE PID(1) Context Reserved Test configuration
Read/Write Read/write Read/write None None Read/write Read/Write None Read/Write
Register locations each provide access more than register. register accessed depends value opcode_2 field. Register location provides access more than register. register accessed depends value field.
7.4.1
CP15 Registers Access CP15 registers only accessed privileged mode (Move Coprocessor from Register) instruction used write register CP15. (Move Register from Coprocessor) instruction used read value CP15 register. Other instructions like CDP, LDC, cause undefined instruction exception. assembler code these instructions
MCR/MRC{cond} p15, opcode_1, CRn, CRm, opcode_2.
MCR, instructions pattern shown below:
cond
opcode_1
opcode_2
CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. value dependent CP15 register used. details, refer CP15 specific register behavior. opcode_2[7:5] Determines specific coprocessor operation code. default, Rd[15:12]: Register Defines register whose value transferred coprocessor. chosen, result unpredictable.
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
CRn[19:16]: Coprocessor Register Determines destination coprocessor register. Instruction instruction instruction opcode_1[23:20]: Coprocessor Code Defines coprocessor specific code. Value CP15. cond [31:28]: Condition more details, Chapter ARM926EJ-S TRM, ref. DDI0198B.
7010A-DSP-07/08
Memory Management Unit (MMU)
ARM926EJ-S processor implements enhanced architecture provide virtual memory features required operating systems like Symbian OS®, Windows CE®, Linux. These virtual memory features memory access permission controls virtual physical address translations. Virtual Address generated core converted Modified Virtual Address (MVA) FCSE (Fast Context Switch Extension) using value CP15 register13. translates modified virtual addresses physical addresses using single, two-level page table stored physical memory. Each entry contains access permissions physical address that correspond virtual address. first level translation tables contain 4096 entries indexed bits [31:20] MVA. These entries contain pointer either section physical memory along with attribute information (access permissions, domain, etc.) entry second level translation tables; coarse table fine table. second level translation tables contain subtables, coarse table fine table. entry coarse table contains pointer both large pages small pages along with access permissions. entry fine table contains pointer large, small tiny pages. Table shows different attributes each page physical memory. Table 7-6. Mapping Details
Mapping Size byte bytes bytes byte Access Permission Section separated subpages separated subpages Tiny Page Subpage Size bytes byte
Mapping Name Section Large Page Small Page Tiny Page
consists Access control logic Translation Look-aside Buffer (TLB) Translation table walk hardware 7.5.1 Access Control Logic access control logic controls access information every entry translation table. access control logic checks pieces access information: domain access permissions. domain primary access control mechanism memory region; there them. defines conditions necessary access proceed. domain determines whether access permissions used qualify access whether they should ignored. second access control mechanism access permissions that defined sections large, small tiny pages. Sections tiny pages have single access permissions whereas large small pages associated with sets access permissions, each subpage (quarter page). 7.5.2 Translation Look-aside Buffer (TLB) Translation Look-aside Buffer (TLB) caches translated entries thus avoids going through translation process every time. When contains entry (Modi-
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
fied Virtual Address), access control logic determines access permitted outputs appropriate physical address corresponding MVA. access permitted, signals core abort. does contain entry MVA, translation table walk hardware invoked retrieve translation information from translation table physical memory. 7.5.3 Translation Table Walk Hardware translation table walk hardware logic that traverses translation tables located physical memory, gets physical address access permissions updates TLB. number stages hardware table walking depending whether address marked section-mapped access page-mapped access. There three sizes page-mapped accesses size section-mapped access. Pagemapped accesses large pages, small pages tiny pages. translation process always begins with level fetch. section-mapped access requires only level fetch, page-mapped access requires additional level fetch. further details MMU, please refer chapter ARM926EJ-S Technical Reference Manual, ref. DDI0198B. 7.5.4 Faults generates abort following types faults: Alignment faults (for data accesses only) Translation faults Domain faults Permission faults access control mechanism detects conditions that produce these faults. fault result memory access, aborts access signals fault core.The retains status address information about faults generated data accesses data fault status register fault address register. also retains status faults generated instruction fetches instruction fault status register. fault status register (register CP15) indicates cause data prefetch abort, domain number aborted access when happens. fault address register (register CP15) holds associated with access that caused Data Abort. further details faults, please refer chapter ARM926EJ-S Technical Reference Manual, ref. DDI0198B.
Caches Write Buffer
ARM926EJ-S contains Instruction Cache (ICache), Data Cache (DCache), write buffer. Although ICache DCache share common features, each still some specific mechanisms. caches (ICache DCache) four-way associative, addressed, indexed tagged using Modified Virtual Address (MVA), with cache line length eight words with dirty bits DCache. ICache DCache provide mechanisms cache lockdown, cache pollution control, line replacement. feature supported ARM926EJ-S caches called allocate read-miss commonly known wrapping. This feature enables caches perform critical word first cache refilling. This means that when request word causes read-miss, cache performs
7010A-DSP-07/08
access. Instead loading whole line (eight words), cache loads critical word first, processor reach quickly, then remaining words, matter where word located line. caches write buffer controlled CP15 register (Control), CP15 register (cache operations) CP15 register (cache lockdown). 7.6.1 Instruction Cache (ICache) ICache caches fetched instructions executed processor. ICache enabled writing CP15 Register disabled writing this same bit. When enabled, instruction fetches subject translation permission checks. disabled, instructions fetches cachable, protection checks made physical address flat-mapped modified virtual address. With disabled, context switching incurs ICache cleaning and/or invalidating. When ICache disabled, instruction fetches appear external memory (AHB) (see Tables page ARM926EJ-S TRM, ref. DDI0198B). reset, ICache entries invalidated ICache disabled. best performance, ICache should enabled soon possible after reset. 7.6.2 Data Cache (DCache) Write Buffer ARM926EJ-S includes DCache write buffer reduce effect main memory bandwidth latency data access performance. operations DCache write buffer closely connected. DCache DCache needs enabled. data accesses subject permission translation checks. Data accesses that aborted cause linefills data accesses appear AMBA interface. disabled, data accesses noncachable, nonbufferable, with protection checks, appear bus. addresses flat-mapped, which incurs DCache cleaning and/or invalidating every time context switch occurs. DCache stores Physical Address Tag) from which every line loaded uses when writing modified lines back external memory. This means that involved write-back operations. Each line words) DCache dirty bits, first four words other second four words. These bits, set, mark associated half-lines dirty. cache line replaced linefill cache clean operation, dirty bits used decide whether all, half none written back memory. DCache enabled disabled writing either register CP15 (see Tables page ARM926EJ-S TRM, ref. DDI0222B). DCache supports write-through write-back cache operations, selected memory region using bits translation tables. DCache contains eight data word entry, single address entry write-back buffer used hold write-back data cache line eviction cleaning dirty cache lines.
7.6.2.1
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Write Buffer hold words data four separate addresses. DCache Write Buffer operations closely connected their configuration each section page descriptor translation table. 7.6.2.2 Write Buffer ARM926EJ-S contains write buffer that 16-word data buffer four- address buffer. write buffer used writes bufferable region, write-through region write-back region. also allows avoid stalling processor when writes external memory performed. When store occurs, data written write buffer core speed (high speed). write buffer then completes store external memory speed (typically slower than core speed). During this time, ARM9EJ-S processor preform other tasks. DCache Write Buffer support write-back write-through memory regions, controlled bits each section page descriptor within translation tables. Write-though Operation When cache write occurs, DCache line updated. updated data then written write buffer which transfers external memory. When cache write miss occurs, line, chosen round robin another algorithm, stored write buffer which transfers external memory. Write-back Operation When cache write occurs, cache line half line marked dirty, meaning that contents up-to-date with those external memory. When cache write miss occurs, line, chosen round robin another algorithm, stored write buffer which transfers external memory.
7.7.1
Tightly-Coupled Memory Interface
Description ARM926EJ-S processor features Tightly-Coupled Memory (TCM) interface, which enables separate instruction data TCMs (ITCM DTCM) directly reached processor. TCMs used store real-time performance critical code, they also provide support mechanism. Unlike accesses external memories, accesses TCMs fast deterministic incur penalties. user possibility independently configure each size with values within following ranges, ITCM size DTCM size. TCMs configured means: HMATRIX register region register (register CP15 both steps should performed. HMATRIX register sets size whereas region register (register CP15 maps TCMs enables them. data side ARM9EJ-S core able access ITCM. This necessary enable code loaded into ITCM, emulated instruction handlers, accesses PC-relative literal pools.
7.7.2
Enabling Disabling TCMs Prior enabling step, user should configure sizes HMATRIX register (see Section 14.5.6). Then enabling TCMs performed using region register (register
7010A-DSP-07/08
CP15. user should same sizes those HMATRIX register. further details programming tips, please refer chapter ARM926EJ-S TRM, ref. DDI0222B. 7.7.3 Mapping TCMs located anywhere memory map, with single region available ITCM separate region available DTCM. TCMs physically addressed placed anywhere physical address space. However, base address must aligned size, DTCM ITCM regions must overlap. mapping performed using region register (register CP15. user should input right mapping address TCMs.
Interface Unit
ARM926EJ-S features Interface Unit (BIU) that arbitrates schedules requests. implements multi-layer AHB, based AHB-Lite protocol, that enables parallel access paths between multiple masters slaves system. This achieved using more complex interconnection matrix gives benefit increased overall bandwidth, more flexible system architecture. multi-master architecture number benefits: allows development multi-master systems with increased bandwidth flexible architecture. Each layer becomes simple because only master, arbitration masterto-slave muxing required. layers, implementing AHB-Lite protocol, have support request grant, they have support retry split transactions. arbitration becomes effective when more than master wants access same slave simultaneously.
7.8.1
Supported Transfers ARM926EJ-S processor performs accesses single word, bursts four words, bursts eight words. ARM9EJ-S core request that words size split into packets these sizes. Note that Atmel AHB-Lite protocol compliant, hence does support split retry requests. Table gives overview supported transfers different kinds transactions they used for.
Table 7-7.
HBurst[2:0]
Supported Transfers
Description Single transfer word, half word, byte:
data write (NCNB, NCB, that missed DCache)
SINGLE Single transfer
data read (NCNB NCB) instruction fetch (prefetched non-prefetched) page table walk read
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
Table 7-7.
HBurst[2:0] INCR4 INCR8 WRAP8
Supported Transfers
Description Four-word incrementing burst Eight-word incrementing burst Eight-word wrapping burst Half-line cache write-back, Instruction prefetch, enabled. Four-word burst NCNB, NCB, write. Full-line cache write-back, eight-word burst NCNB, NCB, write. Cache linefill
7.8.2
Thumb Instruction Fetches instructions fetches, regardless state ARM9EJ-S core, made 32-bit accesses AHB. ARM9EJ-S Thumb state, then instructions fetched time. Address Alignment ARM926EJ-S performs address alignment checking aligns addresses necessary boundary. 16-bit accesses aligned halfword boundaries, 32-bit accesses aligned word boundaries.
7.8.3
7010A-DSP-07/08
Debug Test
Overview
D940HF features number complementary debug test capabilities. common JTAG/ICE (In-Circuit Emulator) port used standard debugging functions, such downloading code single-stepping through programs. dedicated MAGIC JTAG port provides same functions Magic DSP. JTAG ports also interoperate featuring crosstriggering capability. Debug Unit provides two-pin UART that used upload application into internal SRAM. manages interrupt handling internal COMMTX COMMRX signals that trace activity Debug Communication Channel. dedicated debug test input/output pins gives direct access these capabilities from PC-based test environment.
Block Diagram
Debug Test Block Diagram
A_TMS A_TCK A_TDI
Figure 8-1.
A_NTRST ICE/JTAG Test Access Port A_JCFG A_TDO
Boundary Port
A_RTCK
Reset Test
TEST
ARM926EJ-S M_JTAG M_TDI M_TDO ICE-RT ARM9EJ-S M_TMS MAGIC M_TCK M_NTRST
DBG_TXD DBG_RXD
DBGU
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
8.3.1
Application Examples
Debug Environment Figure page shows complete debug environment example. ICE/JTAG interface used standard debugging functions, such downloading code single-stepping through program. Trace Port interface used tracing information. software debugger running personal computer provides user interface configuring Trace Port interface utilizing ICE/JTAG interface. Figure 8-2. Application Debug Trace Environment Example
Host Debugger ICE/JTAG Interface MAGIC ICE/JTAG Interface
ICE/JTAG Connector
MAGIC ICE/JTAG Connector
ICE/JTAG Port
MAGIC ICE/JTAG Port
M_JTAG
RS232 Connector
Terminal
Cross-triggering
MAGIC
D940HF D940HF-based Application Board
8.3.2
Test Environment Figure page shows test environment example. Test vectors sent interpreted tester. this example, "board test" designed using number JTAG-compliant devices. These devices connected form single scan chain.
7010A-DSP-07/08
Figure 8-3.
Application Test Environment Example
Test Adaptor
Tester
JTAG Interface
ICE/JTAG Connector
Chip
Chip
D940HF
Chip
D940HF-based Application Board Test
Debug Test Description
Table 8-1.
Name
Debug Test List
Function Reset/Test Type Active Level
NRST TEST
Microcontroller Reset Test Mode Select ARM-ICE JTAG
Input/Output Input
High
A_TCK A_TDI A_TDO A_TMS A_NTRST A_RTCK A_JCFG
Test Clock Test Data Test Data Test Mode Select Test Reset Signal Returned Test Clock JTAG Selection MAGIC-ICE
Input Input Output Input Input Output Input
M_TCK M_TDI M_TDO M_TMS M_NTRST
Test Clock Test Data Test Data Test Mode Select Test Reset Signal Debug Unit
Input Input Output Input Input
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
AT572D940HF Preliminary
7010A-DSP-07/08
AT572D940HF Preliminary
8.5.1
Functional Description
Test dedicated pin, TEST, used define device operating mode. user must make sure this tied level ensure normal operating conditions. Other values associated with this reserved manufacturing test.
8.5.2
Embedded In-circuit Emulator ARM9EJ-S EmbeddedICE-RTis supported ICE/JTAG port. connected host computer interface. Debug support implemented using ARM9EJ-S core embedded within ARM926EJ-S. internal state ARM926EJ-S examined through ICE/JTAG port which allows instructions serially inserted into pipeline core without using external data bus. Therefore, when debug state, store-multiple (STM) inserted into instruction pipeline. This exports contents ARM9EJ-S registers. This data serially shifted without affecting rest system. There scan chains inside ARM9EJ-S processor which support testing, debugging, programming EmbeddedICE-RT. scan chains controlled ICE/JTAG port. EmbeddedICE mode selected when A_JCFG low. possible directly switch between JTAG operations. chip reset must performed after A_JCFG changed. further details EmbeddedICE-RT, document ARM9EJ-S Technical Reference Manual (DDI 0222A).
8.5.3
JTAG Signal Description A_TMS Test Mode Select input which controls transitions test interface state machine. A_TDI Test Data Input line which supplies data JTAG registers (Boundary Scan Register, Instruction Register, other data registers). A_TDO Test Data Output line which used serially output data from JTAG registers equipment controlling test. carries sampled values from boundary scan chain from other JTAG registers) propagates them next chip serial test circuit. A_NTRST (optional IEEE Standard 1149.1) Test-ReSeT input which mandatory cores used reset debug logic. Atmel ARM926EJ-S-based cores, A_NTRST Power Reset output. asserted power necessary, user also reset debug logic with A_NTRST assertion during periods. A_TCK Test ClocK input which enables test interface. pulsed equipment controlling test tested device. pulsed frequency. Note that maximum JTAG clock rate ARM926EJ-S cores 1/6th clock. This gives 5.45 maximum initial JTAG clock rate ARM9E running from 32.768 slow clock. A_RTCK Return Test Clock. IEEE Standard 1149.1 signal added better clock handling emulators. From some Interface probes, this return signal used synchronize clock without caring that given ratio between Interface clock system clock equal 1/6th. This signal only available JTAG Mode boundary scan mode.
7010A-DSP-07/08
8.5.4
MagicV In-circuit Emulator MagicV-Jtag block master that provides JTAG interface MagicV core. converts JTAG commands coming from JTAG probe into cycles. acting master access MagicV memories registers,
Other recent searches
WA06X - WA06X WA06X Datasheet
UC3854A - UC3854A UC3854A Datasheet
UC3855A - UC3855A UC3855A Datasheet
TM9522 - TM9522 TM9522 Datasheet
TN9522-3 - TN9522-3 TN9522-3 Datasheet
FP9522-4 - FP9522-4 FP9522-4 Datasheet
BX9522 - BX9522 BX9522 Datasheet
MSD6150 - MSD6150 MSD6150 Datasheet
MCAK104BSSSWPMM - MCAK104BSSSWPMM MCAK104BSSSWPMM Datasheet
ENA1173A - ENA1173A ENA1173A Datasheet
CSR13 - CSR13 CSR13 Datasheet
2N6098 - 2N6098 2N6098 Datasheet
2N6099 - 2N6099 2N6099 Datasheet
2N6100 - 2N6100 2N6100 Datasheet
2N6101 - 2N6101 2N6101 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
