Supply Voltage, 8-PIN, Synchronous Buck Controller Operating with

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Supply Voltage, 8-PIN, Synchronous Buck Controller Operating with

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APW7120A
Supply Voltage, 8-PIN, Synchronous Buck Controller
Operating with Single 5~12V Supply Voltage Supply Voltages Drive Dual Cost N-Channel MOSFETs Adaptive Shoot-Through Protection Built-in Feedback Compensation Voltage-Mode Control 0~100% Duty Ratio Fast Transient Response
General Description
APW7120A fixed 300kHz frequency, voltage mode, synchronous controller. device drives cost N-channel MOSFETs designed work with single 5~12V supply voltage(s), providing excellent regulation load transients. APW7120A integrates controls, monitoring protection functions into single 8-pin package provide cost perfect power solution. power-on-reset (POR) circuit monitors supply voltage prevent wrong logic controls. internal 0.8V reference provides output voltage down 0.8V further applications. built-in digital soft-start with fixed soft-start interval prevents output voltage from overshoot well limiting input current. controller' over-current protection monitors output current using voltage drop across low-side MOSFET' RDS(ON), eliminating need current sensing resistor. Additional under voltage over voltage protections monitor voltage short-circuit over-voltage protections. over-current protection cycles soft-start function until over-current events counted. Pulling holding voltage OCSET below 0.15V with open drain device shuts down controller.
0.8V Reference Over Line, Load Regulation, Operating Temperature
Programmable Over-Current Protection Using RDS(ON) Low-Side MOSFET Hiccup-Mode Under-Voltage Protection 118% Over-Voltage Protection Adjustable Output Voltage Small Converter Size 300kHz Constant Switching Frequency Small SOP-8 Package
Built-In Digital Soft-Start Shutdown Control using External MOSFET Lead Free Green Devices Available (RoHS Compliant)
Applications
Motherboard Graphics Card High Current, 20A, DC-DC Converters
Cinfiguration
BOOT UGATE LGATE PHASE OCSET
SOP-8
ANPEC reserves right make changes improve reliability manufacturability without notice, advise customers obtain latest version relevant information verify before placing orders. Copyright ANPEC Electronics Corp. Rev. Jun., 2008 www.anpec.com.tw
APW7120A
Ordering Marking Information
APW7120A Package Code SOP-8 Operating Ambient Temperature Range Assembly Material Handling Code Handling Code Tape Reel Temperature Range Assembly Material Package Code Lead Free Device Halogen Lead Free Device APW7120A XXXXX XXXXX Date Code
APW7120A
Note: ANPEC lead-free products contain molding compounds/die attach materials 100% matte plate termination finish; which fully compliant with RoHS. ANPEC lead-free products meet exceed lead-free requirements IPC/JEDEC J-STD-020C classification lead-free peak reflow temperature. ANPEC defines "Green" mean lead-free (RoHS compliant) halogen free does exceed 900ppm weight homogeneous material total does exceed 1500ppm weight).
Absolute Maximum Ratings
Symbol VBOOT Parameter Supply Voltage (VCC GND) BOOT Voltage (BOOT PHASE) UGATE Voltage (UGATE PHASE)
(Note
Rating -0.3 -0.3 Unit
<400ns pulse width >400ns pulse width LGATE Voltage (LGATE GND) <400ns pulse width >400ns pulse width PHASE Voltage (PHASE GND) <400ns pulse width >400ns pulse width VI/O Input Voltage (OCSET, GND) Maximum Junction Temperature TSTG TSDR Storage Temperature Maximum Lead Soldering Temperature, Seconds
VBOOT+0.3 -0.3 VBOOT+0.3 VCC+0.3 -0.3 VCC+0.3 -0.3
Note Absolute Maximum Ratings those values beyond which life device impaired. Exposure absolute maximum rating conditions extended periods affect device reliability.
Thermal Characteristics
Symbol Parameter Junction-to-Ambient Resistance Free
(Note
Typical Value
Unit
Note measured with component mounted high effective thermal conductivity test board free air.
Copyright ANPEC Electronics Corp. Rev. Jun., 2008
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APW7120A
Recommended Operating Conditions
Symbol VOUT IOUT Supply Voltage Converter Output Voltage Converter Input Voltage Converter Output Current Ambient Temperature Junction Temperature Parameter
(Note
Range 13.2 80%VIN 13.2 Unit
Note Please refer typical application circuit.
Electrical Characteristics
Unless otherswise specified, these specifications apply over 12V, VBOOT 70oC. Typical values 25oC.
APW7120A Symbol SUPPLY CURRENT IVCC Nominal Supply Current Shutdown Supply Current POWER-ON-RESET Rising Threshold Hysteresis OSCILLATOR FOSC VOSC Free Running Frequency Ramp Amplitude VP-P 0.45 UGATE LGATE Open Parameter Test Conditions Min. Typ. Max. Unit
REFERENCE VOLTAGE VREF Reference Voltage Accuracy Line Regulation ERROR AMPLIFIER Gain First Pole Frequency Zero Frequency Second Pole Frequency Average UGATE Duty Range Input Current Measured =-20~70°C VCC=12 -2.0 0.05 +2.0
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APW7120A
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over 12V, VBOOT 70oC. Typical values 25oC.
APW7120A Symbol Parameter Test Conditions Min. Typ. Max. Unit
CONTROLLER GATE DRIVERS UGATE Source UGATE Sink LGATE Source LGATE Sink Dead-Time VBOOT-PHASE =12V, VUGATE-PHASE VBOOT-PHASE =12V, VUGATE-PHASE=1V VCC=12V, VLGATE=6V VCC=12V, VLGATE=1V Guaranteed Design
PROTECTIONS IOCSET OCSET Current Source Over-Current Reference Voltage UVFB Under-Voltage Threshold Under-Voltage Hysteresis Over-Voltage Threshold SOFT-START SHUTDOWN Soft-Start Interval OCSET Shutdown Threshold OCSET Shutdown Hysteresis Falling VOCSET 0.15 VPHASE=0V, Normal Operation =-20~70°C Falling Rising Rising 0.37 0.43
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APW7120A
Function Description
BOOT (Pin This provides ground referenced bias voltage high-side MOSFET driver. bootstrap circuit with diode connected 5~12V used create voltage suitable drive logic-level N-channel MOSFET. UGATE (Pin Connect this high-side N-channel MOSFET' gate. This provides gate drive high-side MOSFET. (Pin terminal provides return path bias current low-side MOSFET driver' pull-low current. Connect system ground very impedance layout PCBs. LGATE (Pin Connect this low-side N-channel MOSFET' gate. This provides gate drive low-side MOSFET. (Pin Connect this 5~12V supply voltage. This provides bias supply control circuitry low-side MOSFET driver. voltage this monitored Power-On-Reset (POR) purpose. (Pin This inverting input internal amplifier. Connect this output (VOUT) converter external resistor divider closed-loop operation. output voltage resistor divider determined using following formula
0.8V
where resistor connected from VOUT resistor connected from GND. also monitored under over-voltage events. OCSET (Pin OCSET dual-function input overcurrent protection shutdown control. Connect resistor (ROCSET) from this Drain lowside MOSFET. This resistor, internal 40µA current source (IOCSET), MOSFET' on-resistance (RDSON) converter over-current trip level (IPEAK) according following formula:
PEAK OCSET 0.4V DSON
Pulling holding this below 0.15V with open drain device, with very parasitic capacitor, shuts down with floating output also resets over-current counter. Releasing OCSET initiates soft-start converter works again. PHASE (Pin provides return path high-side MOSFET driver' pull-low current. Connect this highs side MOSFET' source.
Copyright ANPEC Electronics Corp. Rev. Jun., 2008
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APW7120A
Block Diagram
3VCC 40uA
Regulator Power-OnReset
OCSET
0.4V 2.5V Enable Soft-Start Fault Logic 0.15V
3VCC 67%VREF
BOOT UGATE
Inhibit Gate Control
118%VREF Soft-Start
PHASE
Amplifier
COMP
VREF 0.8V
LGATE
FOSC 300kHz Oscillator
Application Circuit
VBIAS
+5V/12V
0.1µF
1N4148
820µF
+5/12V
BOOT
UGATE PHASE
APM2512 1.5uH APM2512
VOUT
1000µF
OCSET APW7120A
LGATE
1.8V/15A
1.5k
Shutdown
820µF/16V ESR=25 1000µF/6.3V, ESR=30
Copyright ANPEC Electronics Corp. Rev. Jun., 2008 www.anpec.com.tw
2N7002
1.2k 0.1µF
APW7120A
Typical Operating Characteristics
Reference Voltage Junction Temperature
Switching Frequency Junction Temperature
0.812 0.810
Reference Voltage, VREF
0.808 0.806 0.804 0.802 0.800 0.798 0.796 0.794 0.792 0.790 0.788
Switching Frequency, FOSC (kHz)
Junction Temperature (oC)
Junction Temperature (oC)
OCSET Current Junction Temperature
Threshold Voltage Junction Temperature
Threshold Voltage
OCSET Current IOCSET (µA)
Rising
Falling
Junction Temperature (oC)
Junction Temperature (oC)
Copyright ANPEC Electronics Corp. Rev. Jun., 2008
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APW7120A
Typical Operating Characteristics (Cont.)
OCSET Shutdown Threshold Voltage Junction Temperature
0.20
OCSET Shutdown Threshold Voltage
Falling VOCSET
0.18
0.16
0.14
0.12
0.10
Junction Temperature (oC)
Operating Waveforms
(Refer typical application circuit, VBAIS=VIN=+12V supplied Power Supply) Load Transient Response IOUT IOUT slew rate ±7.5A/µs
IOUT IOUT
VOUT=1.8V VOUT
IOUT
VOUT
VOUT VUGATE
VUGATE
VUGATE
IOUT
IOUT
IOUT
VOUT, 100mV/Div, IOUT, 10A/Div VUGATE, 20V/Div, Time 5µs/Div
VOUT, 100mV/Div, IOUT, 10A/Div VUGATE, 20V/Div, Time 40µs/Div
VOUT, 100mV/Div, IOUT, 10A/Div VUGATE, 20V/Div, Time 5µs/Div
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APW7120A
Operating Waveforms (Cont.)
(Refer typical application circuit, VBIAS=VIN=+12V supplied Power Supply) UGATE LGATE Switching Waveforms
Rising VUGATE
IOUT
VLGATE VLGATE
Falling VUGATE
VUGATE
VUGATE
VUGATE, 5V/Div, Time 20ns/Div
VLGATE, 2V/Div,
VUGATE, 5V/Div, VLGATE, 2V/Div, Time 20ns/Div
Powering
Powering VCC=VIN=5V RL=0.12 Powering VCC=VIN=5V RL=0.12
VOUT VOUT
VCC, 2V/Div, 10A/Div,
VOUT, 1V/Div, Time 5ms/Div
VCC, 2V/Div, 10A/Div,
VOUT, 1V/Div, Time 10ms/Div
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APW7120A
Operating Waveforms (Cont.)
(Refer typical application circuit, VBIAS=VIN=+12V supplied Power Supply) Powering (Cont.)
Powering VCC=VIN=12V RL=0.12 Powering VCC=VIN=12V RL=0.12
VOUT
VOUT
VCC, 5V/Div, 10A/Div,
VOUT, 1V/Div, Time 5ms/Div
VCC, 5V/Div, 10A/Div,
VOUT, 1V/Div, Time 10ms/Div
Enabling Shutting Down
Enabling Releasing OCSET Shutting Down Pulling OCSET
VOCSET
VOCSET
VUGATE
VUGATE
VOUT
VOUT
IOUT=2A
VOUT, 1V/Div, VUGATE, 20V/Div, VOCSET, 2V/Div, Time 2ms/Div Copyright ANPEC Electronics Corp. Rev. Jun., 2008
VOUT, 1V/Div, VOCSET, 2V/Div,
VUGATE, 20V/Div, Time 2ms/Div
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APW7120A
Operating Waveforms (Cont.)
(Refer typical application circuit, VBIAS=VIN=+12V supplied Power Supply) Over-Current Protection
Connecting shutdown MOSFET OCSET
ROCSET=15k APM2512
Connecting shutdown MOSFET (2N7002) OCSET
ROCSET=15k APM2512
VOUT
VOUT
VOUT, 1V/Div, Time 5ms/Div
10A/Div,
VOUT, 1V/Div, Time 5ms/Div
10A/Div,
OCSET Voltage Delay
Connecting shutdown MOSFET OCSET Connecting shutdown MOSFET (2N7002) OCSET
VOCSET
VOCSET
CProber=8pF
CProber=8pF C2N7002=44pF (measured)
VOCSET, 0.5V/Div, Time 2µS/Div
10A/Div,
VOCSET, 0.5V/Div, Time S/Div
10A/Div,
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APW7120A
Operating Waveforms (Cont.)
(Refer typical application circuit, VBIAS=VIN=+12V supplied Power Supply) OCSET Voltage Delay (Cont.)
Connecting shutdown MOSFET (APM2322) OCSET
Short-Circuit Test
Shorted wire
VOUT
VOCSET
CProber=8pF CAPM2322 =89pF (measured)
VOCSET, 0.5V/Div, 10A/Div, Time 2µS/Div
VOUT, 1V/Div, Time 5ms/Div
10A/Div,
Function Description
Power-On-Reset (POR) APW7120A monitors voltage (VCC) Power-On-Reset function, preventing wrong logic operation during powering When voltage ready, APW7120A starts start-up process then ramps output voltage target voltage. Soft-Start APW7120A built-in digital soft-start control output voltage rise limit current surge start-up. During soft-start, internal ramp connected positive inputs amplifier rises from replace reference voltage (0.8V) until ramp voltage reaches reference
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voltage. soft-start interval about 3.2ms typical, independent converter' input output voltages. Over-Current Protection (OCP) over-current function protects switching onver against over-current short-circuit conditions. controller senses inductor current detecting drain-to-source voltage, product inductor' current on-resistance, low-side MOSFET during on-state. This method enhances converter' efficiency reduces cost eliminating current sensing resistor. resistor (ROCSET), connected from OCSET
APW7120A
Function Description (Cont.)
Over-Current Protection (OCP) (Cont.) low-side MOSFET' drain, programs over-current trip level. internal 40µA (typical) current source flowing through ROCSET develops voltage (VROCSET) across ROCSET. When VOCSET (VROCSET+ low-side MOSFET) less than internal overcurrent reference voltage (0.4V, typical), shuts converter then initiates soft-start process. After over-current events counted, device turns both high-side low-side MOSFETs converter' output latched floating. Please attention delay effect. causes trip level function operating duty. parasitic capacitance (including capacitance inside OCSET, external trace capacitance COSS shutdown MOSFET) must minimized, especially selecting shutdown MOSFET with very small COSS. trip level follows duty increase little operating duty, very much high operating duty, like delay curve. load regulation current-limit, heavy load normally reduces converter' input voltage increases power loses. During heavy load, APW7120A regulates output voltage expending duty. This rises trip level same time. Under-Voltage Protection (UVP) under-voltage function monitors voltage (VFB) protect converter against short-circuit conditions. When falls below falling threshold (67% VREF), APW7120A shuts converter. After preceding delay, which starts beginning under-voltage shutdown, 7120A initiates soft-start resume regulating. under-voltage protection shuts then re-starts converter repeatedly without latching. function disabled during soft-start process. Over-Voltage Protection (OVP) over-voltage protection monitors voltage prevent output from over-voltage. When output voltage rises 118% nominal output voltage, 7120A turns low-side MOSFET until output voltage falls below threshold, regulating output voltage around thresholds. Adaptive Shoot-Through Protection gate driver incorporates adaptive shoot-through protection high-side low-side MOSFETs from conducting simultaneously shorting input supply. This accomplished ensuring falling gate turned MOSFET before other allowed rise. During turn-off low-side MOSFET, LGATE voltage monitored until reaches 1.5V threshold, which time UGATE released rise after constant delay. During turn-off high-side MOSFET, UGATE-to-PHASE voltage also monitored until reaches 1.5V threshold, which time LGATE released rise after constant delay. Shutdown Control Pulling OCSET voltage below 0.15V open drain transistor, shown typical application circuit, shuts down APW7120A controller. shutdown mode, UGATE LGATE pulled PHASE respectively, output floating.
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APW7120A
Application Information
Input Capacitor Selection small ceramic capacitors high frequency decoupling bulk capacitors supply surge current needed each time high-side MOSFET(Q1) turns Place small ceramic capacitors physically close MOSFETs between drain source low-side MOSFET(Q2). important parameters bulk input capacitor voltage rating current rating. reliable operation, select bulk capacitor with voltage current ratings above maximum input voltage largest current required circuit. capacitor voltage rating should least 1.25 times greater than maximum input voltage voltage rating times conservative guideline. current bulk input capacitor calculated following equation Output Capacitor Selection output capacitor required filter output supply load transient current. filtering requirements function switching frequency ripple current. output ripple voltages, having phase shift, across ideal output capacitor. peak-to-peak voltage calculated following equations
ICOUT
T=1/FOSC
UGATE
IOUT
IOUT
Figure Buck Converter Waveforms
IRMS IOUT
through hole design, several electrolytic capacitors needed. surface mount designs, solid tantalum capacitors used, caution must exercised with regard capacitor surge current rating.
.(2) .(3)
peak-to-peak voltage ideal output capacitor
UGATE
IOUT COUT
calculated following equation
COUT
LGATE
ICOUT
general applications using bulk capacitors, COUT much smaller than VESR ignored. Therefore, peak-to-peak output voltage shown below:
.(5)
load transient requirements function
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APW7120A
Application Information (Cont.)
Output Capacitor Selection (Cont.) slew rate (di/dt) magnitude transient load current. These requirements generally with capacitors careful layout. Modern components loads capable producing transient load rates above 1A/ns. High frequency capacitors initially supply transient slow current load rate seen bulk capacitors. bulk filter capacitor values generally determined (Effective Series Resistance) voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should placed close power pins load physically possible. careful inductance circuit board wiring that could cancel usefulness these inductance components. aluminum electrolytic capacitor' value lated case size with lower available larger case sizes. However, Equivalent Series Inductance (ESL) these capacitors increases with case size reduce usefulness capacitor high slew-rate transient loading. most cases, multiple electrolytic capacitors small case size perform better than single large case capacitor. Output Inductor Selection output inductor selected meet output voltage ripple requirements minimize converter' response time load transient. inductor value determines converter' ripple current ripple voltage, equations (5). Increasing value inductance reduces ripple current voltage. However, large inductance
values reduce converter' response time load
load transient time required change inductor current. Given sufficiently fast control loop design, APW7120A will provide either (Average) duty cycle response load transient. response time time required slew inductor current from initial current value transient current level. During this interval difference between inductor current transient current level must supplied output capacitor. Minimizing response time minimize output capacitance required. response time transient different application load removal load. following equations give approximate response time interval application removal transient load:
ITRAN ITRAN tFALL where: ITRAN transient load current step, tRISE response time application load, tFALL response time removal load. worst case response time either application removal load. sure check both these equations transient load current. These requirements minimum maximum output levels worst case response time. tRISE
MOSFET Selection APW7120A requires N-Channel power MOSFETs. These should selected based upon DS(ON) gate supply requirements, thermal management requirements. high-current applications, MOSFET power dissipation, package selection heatsink dominant design factors. power dissipation includes loss components, conduction loss switching loss. conduction losses largest component power dissipation both high-side
transient. parameters limiting converter' response
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APW7120A
Application Information (Cont.)
MOSFET Selection (Cont.) low-side MOSFETs. These losses distributed between MOSFETs according duty factor (see equations below). Only high-side MOSFET switching losses, since low-side MOSFETs body diode external Schottky rectifier across lower MOSFET clamps switching node before synchronous rectifier turns These equations assume linear voltage-current transitions adequately model power loss reverse-recovery low-side MOSFET' body diode. gates charge losses dissipated APW7120A don' heat MOSFETs. However, large gate-charge increases switching interval, which increases high-side MOSFET switching losses. Ensure that both MOSFETs within their maximum junction temperature high ambient temperature calculating temperature rise according package thermalresistance specifications. separate heatsink necessary depending upon MOSFET power, package type, ambient temperature flow.
A2(S)
A3(S) A1(S)
VCOMP
Internal Compensation Network
APW7120 VOSC=1.6V VPHASE Driver
LGATE
UGATE
VOUT
0.8V
Figure APW7120 Control System transfer functions defined following
VFB(S) VO(S)
VCOMP(S) (Internal Compensation) VFB(S)
VPHASE(S) VCOMP(S) VOSC
PHigh Side IOUT RDSON IOUT FOSC PLow Side IOUT RDSON
A4(S)
ACL(S)
VOUT(S) VPHASE(S)
Where switching interval Feedback Compensation figure shows control system APW7120, which consists internal voltage-mode modulator, output filter, resistor-divider internal compensation network. equivalent series resistance(ESR) capacitance output capacitor; inductance output inductor.
VOUT VO(S) VFB(S) VCOMP(S) VPHASE(S) VOUT(S) VO(S) VFB(S) VCOMP(S) VPHASE(S) A1(S) A2(S) A3(S) A4(S)
where A1(S) transfer function resistordivider, A2(S) transfer function feedback compensation network, A3(S) transfer function modulator, A4(S) transfer function output filter, ACL(S) transfer function closed-loop control system. Refer figure Pole Zero frequencies A1(S), A2(S), A3(S), ACL(S) shown calculated following equations:
FZA21 0.4kHz (FZ) FPA21 430kHz (FP2)
PA41,2
ZA41
xRxC
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Copyright ANPEC Electronics Corp. Rev. Jun., 2008
APW7120A
Application Information (Cont.)
Feedback Compensation (Cont.) where FPA21 FP2) FZA21 Pole Zero frequencies A2(S), FPA41,2 FZA41 double-Pole Zero frequencies (S), input voltage converter load resistance converter very large. good converter stability, values must selected meet following criteria: 1.Make sure double-pole frequency(FPA41,2) output filter bigger than zero frequency (FZA21) internal compensation network. following equation must true:
log( log( log( VOSC
Layout Consideration high power switching regulator, correct layout important ensure proper operation regulator. general, interconnecting impedances should minimized using short, wide printed circuit traces. Signal power grounds kept separate finally combined using ground plane construction single point grounding. Figure illustrates layout, with bold lines indicating high current paths. Components along bold lines should placed close together. Below checklist your layout: Begin layout placing power components first. Orient power circuitry chieve clean power flow path. possible, make connections side with wide, copper filled areas. Connect ground feedback divider directly using dedicated ground trace. decoupling capacitor should right next pins. Capacitor CBOOT should connected close BOOT PHASE pins possible. Minimize length increase width trace between UGATE/LGATE gates MOSFETs reduce impedance driving MOSFETs. dedicated trace connect ROCSET Drain low-side MOSFET, Kevin connection accurate current sensing. Keep switching nodes (UGATE, LGATE,
converter crossover frequency (FCO) must range 10%~30% minimum FOSC converter. calculated using following equations:
Gain FZA41 FOSC_MIN
FZA41 FOSC_MIN Gain FZA41 log( log( VOSC
log(
values selected must meet equations above over operaing temperature, voltage, current ranges.
FZA21
Compensation Gain
Gain (dB)
&Filter Gain
PHASE) away from sensitive small signal nodes
FPA21 PA41,2 FZA41
Converter Gain
since these nodes fast moving signals. Therefore, keep traces these nodes short possible. Place decoupling ceramic capacitor near Drain high-side MOSFET close possible. bulk capacitors also placed near Drain.
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100K
Frequency
Figure Converter Gain Frequency
Copyright ANPEC Electronics Corp. Rev. Jun., 2008
APW7120A
Application Information (Cont.)
Layout Consideration (Cont.) Place Source high-side MOSFET Drain low-side MOSFET close possible. Minimizing impedance with wide layout plane between pads reduces voltage bounce node. wide power ground plane, with impedance, connects OUT, Schottky diode Source low-side MOSFET provide impedance path between components large high frequency switching currents.
BOOT LGATE APW7120A
1UGATE
PHASE
COUT
VOUT
Figure Recommended Layout Digram
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APW7120A
Package Information
SOP-8
VIEW
0.25 GAUGE PLANE SEATING PLANE VIEW SOP-8 INCHES MIN. MAX.
MILLIMETERS MIN. MAX.
0.25 0.40 0.10 1.25 0.31 0.17 4.80 5.80 3.80 1.27
1.75 0.25 0.004 0.049 0.51 0.25 5.00 6.20 4.00 0.012 0.007 0.189 0.228 0.150 0.050 0.50 1.27 0.010 0.016
0.069 0.010
0.020 0.010 0.197 0.244 0.157
0.020 0.050
Note: Follow JEDEC MS-012 Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed side. Dimension does include inter-lead flash protrusions. Inter-lead flash protrusions shall exceed side.
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APW7120A
Carrier Tape Reel Dimensions
SECTION SECTION
Application
5.5± 0.05
330.0± 2.00 MIN. SOP-8 4.0± 0.10 8.0± 0.10
12.4+2.00 13.0+0.50 MIN. -0.00 -0.20 2.0± 0.05 1.5+0.10 -0.00 MIN.
20.2 MIN. 12.0± 0.30 1.75± 0.10
0.6+0.00 6.40± 0.20 5.20± 0.20 2.10± 0.20 -0.40 (mm)
Devices Unit
Package Type SOP-8 Unit Tape Reel Quantity 2500
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APW7120A
Reflow Condition
(IR/Convection Reflow)
Critical Zone Ramp-up
Temperature
Tsmax
Tsmin Ramp-down Preheat
25°C Peak
Time
Reliability Test Program
Test item SOLDERABILITY HOLT Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD Description 245°C, 1000 Bias @125°C Hrs, 100%RH, 121°C -65°C~150°C, Cycles VHBM 2KV, 200V 10ms, 100mA
Classification Reflow Profiles
Profile Feature Average ramp-up rate Preheat Temperature (Tsmin) Temperature (Tsmax) Time (min max) (ts) Time maintained above: Temperature (TL) Time (tL) Peak/Classification Temperature (Tp) Time within actual Peak Temperature (tp) Ramp-down Rate Time 25°C Peak Temperature Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds table 10-30 seconds 6°C/second max. minutes max. Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds table 20-40 seconds 6°C/second max. minutes max.
Note: temperatures refer topside package. Measured body surface.
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APW7120A
Classification Reflow Profiles (Cont.)
Table SnPb Eutectic Process Package Peak Reflow Temperatures Package Thickness <2.5 Volume <350 +0/-5°C +0/-5°C Volume +0/-5°C +0/-5°C
Table Pb-free Process Package Classification Reflow Temperatures Package Thickness Volume <350
Volume 350-2000
Volume >2000
<1.6 +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* +0°C* Tolerance: device manufacturer/supplier shall assure process compatibility including stated classification temperature (this means Peak reflow temperature +0°C. example 260°C+0°C) rated level.
Customer Service
Anpec Electronics Corp. Head Office No.6, Dusing Road, SBIP, Hsin-Chu, Taiwan, R.O.C. 886-3-5642000 886-3-5642050 Taipei Branch Lane 218, Jhongsing Rd., Sindian City City, Taipei County 23146, Taiwan 886-2-2910-3838 886-2-2917-3838
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Supply Voltage, 8-PIN, Synchronous Buck Controller Operating with

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