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Actel Fusion Mixed-Signal FPGAs
MicroBlade Advanced Mezzanine Card Solution Features Benefits
Targeted Advanced Mezzanine Card (AdvancedMCTM) Designs Designed Partnership with MicroBlade 8051-Based Module Management Controller (MMC) Fully Compliant with PICMG AMC.0.R2.0 IPMI v2.0 Specifications AdvancedMC Reference Design Starter
Crystal Oscillator Support MHz) Programmable Real-Time Counter (RTC) Clock Conditioning Circuits (CCCs) with Integrated PLLs Phase Shift, Multiply/Divide, Delay Capabilities Frequency: Input 1.5-350 MHz, Output 0.75-350
Power Consumption
Single Power Supply with On-Chip Regulator Sleep Standby Power Modes
High-Performance Reprogrammable Flash Technology
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process Nonvolatile, Retains Program when Powered Live Power-Up (LAPU) Single-Chip Solution System Performance
In-System Programming (ISP) Security
Secure with 128-Bit JTAG FlashLock® Secure FPGA Contents
Advanced Digital
Mixed-Voltage Operation Bank-Selectable Voltages Banks Chip Single-Ended Standards: LVTTL, LVCMOS /1.8 PCI-X, LVCMOS Input Differential Standards: LVPECL, LVDS, BLVDS, M-LVDS Built-In Registers Mbps Operation Hot-Swappable I/Os Programmable Output Slew Rate, Drive Strength, Weak Pull-Up/Down Resistor Pin-Compatible Packages across Fusion Family
Embedded Flash Memory
User Flash Memory Mbits Mbits Configurable 16-, 32-Bit Datapath Access Read-Ahead Mode kbit Additional FlashROM
Integrated Converter (ADC) Analog
12-Bit Resolution ksps Internal 2.56 External Reference Voltage ADC: Scalable Analog Input Channels High-Voltage Input Tolerance: -10.5 Current Monitor Temperature Monitor Blocks MOSFET Gate Driver Outputs N-Channel Power MOSFET Support Programmable Drive Strengths Accuracy Better than
SRAMs FIFOs
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks organizations available) True Dual-Port SRAM (except Programmable Embedded FIFO Control Logic
On-Chip Clocking Support
Internal Oscillator (accurate
MicroBlade Fusion Solutions Fusion Devices System Gates Tiles (D-flip-flops) General Information Secure (AES) PLLs Globals Flash Memory Blocks Mbits) Total Flash Memory Bits Memory FlashROM Bits Blocks (4,608 bits) kbits Analog Quads Analog Input Channels Analog I/Os Gate Driver Outputs Banks JTAG) Maximum Digital I/Os Analog I/Os Notes: Refer CoreMP7 datasheet more information. Refer Cortex-M1 product brief more information. U1AFS25 250,000 6,144 U1AFS600 600,000 13,824 U1AFS1500 1,500,000 38,400
October 2008 2008 Actel Corporation
Actel Fusion Mixed-Signal FPGAs MicroBlade AdvancedMC Solution
Fusion Device Architecture Overview
Bank Bank
SRAM Block 4,608-Bit Dual-Port SRAM FIFO Block I/Os CCC/PLL VersaTile
Bank Bank
Decryption
User Nonvolatile FlashROM
Charge Pumps
SRAM Block 4,608-Bit Dual-Port SRAM FIFO Block
Flash Memory Blocks
Flash Memory Blocks
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Bank
Figure Fusion Device Architecture Overview (U1AFS600)
Package I/Os: Single-/Double-Ended (Analog)
Fusion Devices FG256 U1AFS250 114/37 (24) U1AFS600 119/58 (40) U1AFS1500 119/58 (40) Note: devices same package compatible with exception PQ208 package (AFS250 AFS600).
Actel Fusion Mixed-Signal FPGAs MicroBlade AdvancedMC Solution
Product Ordering Codes
U1AFS600 Application (ambient temperature range) Blank Commercial +70°C) Industrial (-40 +85°C) Package Lead Count Lead-Free Packaging Options Blank Standard Packaging RoHS-Compliant (green) Packaging Package Type Fine Pitch Ball Grid Array (1.0 pitch) Speed Grade Blank Standard Part Number U1AFS250 250,000 System Gates U1AFS600 600,000 System Gates U1AFS1500 1,500,000 System Gates
Actel Fusion Mixed-Signal FPGAs MicroBlade AdvancedMC Solution
Temperature Grade Offerings
MicroBlade-Based Fusion Devices FG256 U1AFS250 U1AFS600 U1AFS1500 Notes: Commercial Temperature Range: 70°C Ambient Industrial Temperature Range: -40°C 85°C Ambient
Speed Grade Temperature Grade Matrix
Std. Notes: Commercial Temperature Range: 70°C Ambient Industrial Temperature Range: -40°C 85°C Ambient Contact your local Actel representative device availability
Fusion Device Family Overview
Introduction
Actel MicroBlade-based Fusion® mixed-signal FPGA satisfies demand from system architects device that simplifies design unleashes their creativity. world's first mixed-signal programmable logic family, MicroBlade-based Fusion integrates mixed-signal analog, flash memory, FPGA fabric monolithic device. Actel MicroBlade-based Fusion devices enable designers quickly move from concept completed design then deliver feature-rich systems market. This technology takes advantage unique properties Actel flash-based FPGAs, including high-isolation, triple-well process ability support high-voltage transistors meet demanding requirements mixed-signal system design. Actel Fusion mixed-signal FPGAs bring benefits programmable logic many application areas, including power management, smart battery charging, clock generation management, motor control. Until now, these applications have only been implemented with costly space-consuming discrete analog components mixed-signal ASIC solutions. Actel Fusion mixedsignal FPGAs present capabilities system development allowing designers integrate wide range functionality into single device, while same time offering flexibility upgrades late manufacturing process after device field. Actel Fusion devices provide excellent alternative costly time-consuming mixed-signal ASIC designs. addition, when used conjunction with Actel MicroTCA market. Actel Fusion technology represents definitive mixed-signal FPGA platform. Flash-based Fusion devices live power-up. soon system power applied within normal operating specifications, Fusion devices working. Fusion devices have 128-bit flashbased lock industry-leading decryption, used secure programmed intellectual property (IP) configuration data. Actel Fusion devices most comprehensive single-chip analog digital programmable logic solution available today. support this ground-breaking technology, Actel developed series major tool innovations help maximize designer productivity. Implemented extensions popular Actel Libero® Integrated Design Environment (IDE), these tools allow designers easily instantiate configure peripherals within design, establish links between peripherals, create import building blocks reference designs, perform hardware verification. This tool suite will also comprehensive hardware/software debug capability well suite utilities simplify development embedded soft-processor-based solutions. MicroBlade-based Fusion (U1AFS) devices targeted Actel's Advanced Mezzanine Card (AMC) design developed partnership with MicroBlade, Inc. design 8051-based Module Management Controller (MMC) fully compliant with PICMG Advanced Mezzanine Card AMC.0 R2.0 IPMI v2.0 specification, implementing reference design Starter complete board including variable load board payload. reference design available free download from Actel website, including board design files, documentation, FPGA design complete Libero® Integrated Design Environment (IDE) project, executable firmware image. Starter adds complete firmware source code format. Designs based Starter (part number UTCA-AMC-SK) design required U1AFS devices: U1AFS250, U1AFS600, U1AFS1500.
Fusion Device Family Overview
General Description
Actel MicroBlade-based Fusion family, based highly successful ProASIC®3 ProASIC3E Flash FPGA architecture, been designed high-performance, programmable, mixed-signal platform. combining advanced flash FPGA core with flash memory blocks analog peripherals, Fusion devices dramatically simplify system design and, result, dramatically reduce overall system cost board space. state-of-the-art flash memory technology offers high-density integrated flash memory blocks, enabling savings cost, power, board area relative external flash solutions, while providing increased flexibility performance. flash memory blocks integrated analog peripherals enable true mixed-mode programmable logic designs. examples using on-chip soft processor implement fully functional Flash using high-speed FPGA logic offer system power supervisory capabilities. Live power-up capable operating from single supply, Fusion family ideally suited system management control applications. devices Fusion family categorized FPGA core density. Each family member contains many peripherals, including flash memory blocks, analog-to-digital-converter (ADC), high-drive outputs, both crystal oscillators, real-time counter (RTC). This provides user with high level flexibility integration support wide variety mixed-signal applications. flash memory block capacity ranges from Mbits Mbits. integrated 12bit supports independently configurable input channels. on-chip crystal oscillators work conjunction with integrated phase-locked loops (PLLs) provide clocking support FPGA array on-chip resources. addition supporting typical uses such watchdog timer, Fusion control on-chip voltage regulator power down device (FPGA fabric, flash memory block, ADC), enabling low-power standby mode. Actel MicroBlade-based Fusion family offers revolutionary features, never before available FPGA. nonvolatile flash technology gives Fusion solution advantage being secure, low-power, single-chip solution that live power-up. Fusion reprogrammable offers time market benefits ASIC-level unit cost. These features enable designers create high-density systems using existing ASIC FPGA design flows tools. family system gates, supported with kbits true dual-port SRAM, Mbits flash memory, kbit user FlashROM, user I/Os. With integrated flash memory, Fusion family ultimate soft-processor platform.
Flash Advantages
Reduced Cost Ownership
Advantages designer extend beyond unit cost, high performance, ease use. Flashbased Fusion devices live power-up need loaded from external boot PROM. On-board security mechanisms prevent access programming information enable secure remote updates FPGA logic. Designers perform secure remote in-system reprogramming support future design iterations field upgrades, with confidence that valuable cannot compromised copied. Secure performed using industrystandard algorithm with data authentication device. Fusion family device architecture mitigates need ASIC migration higher user volumes. This makes Fusion family cost-effective ASIC replacement solution applications consumer, networking communications, computing, avionics markets.
Security
nonvolatile, flash-based Fusion family requires boot PROM, there vulnerable external bitstream. Fusion devices incorporate FlashLock, which provides unique combination reprogrammability design security without external overhead, advantages that only FPGA with nonvolatile flash programming offer. Fusion devices utilize 128-bit flash-based lock separate secure programmed configuration data. FlashROM data Fusion devices also encrypted prior loading. Additionally, Flash memory blocks programmed during runtime using industry-leading AES-128 block cipher encryption standard (FIPS Publication 192). standard
Actel Fusion Mixed-Signal FPGAs MicroBlade AdvancedMC Solution adopted National Institute Standards Technology (NIST) 2000 replaces standard, which adopted 1977. Fusion devices have built-in decryption engine flash-based that make Fusion devices most comprehensive programmable logic device security solution available today. Fusion devices with AES-based security allow secure remote field updates over public networks, such Internet, ensure that valuable remains hands system overbuilders, system cloners, thieves. additional security measure, FPGA configuration data programmed Fusion device cannot read back, although secure design verification possible. During design, user controls defines both internal external access flash memory blocks. Security, built into FPGA fabric, inherent component Fusion family. Flash cells located beneath seven metal layers, many device design layout techniques have been used make invasive attacks extremely difficult. Fusion with FlashLock security unique being highly resistant both invasive noninvasive attacks. Your valuable protected, making secure remote possible. Fusion device provides most impenetrable security programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information on-chip flash cells. Once programmed, configuration data inherent part FPGA structure, external configuration data needs loaded system power-up (unlike SRAM-based FPGAs). Therefore, flash-based Fusion FPGAs require system configuration components such EEPROMs microcontrollers load device configuration data. This reduces bill-of-materials costs area, increases security system reliability.
Live Power-Up
Flash-based Fusion devices Level live power-up (LAPU). LAPU Fusion devices greatly simplify total system design reduce total system cost eliminating need CPLDs. Fusion LAPU clocking (PLLs) replaces off-chip clocking resources. Fusion LAPU clocking analog resources makes these devices excellent choice both system supervisor system management functions. LAPU from single source enables Fusion devices initiate, control, monitor multiple voltage supplies while also providing system clocks. addition, glitches brownouts system power will corrupt Fusion device flash configuration. Unlike SRAMbased FPGAs, device will have reloaded when system power restored. This enables reduction complete removal expensive voltage monitor brownout detection devices from design. Flash-based Fusion devices simplify total system design reduce cost design risk, while increasing system reliability.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated upper atmosphere, strike configuration cell SRAM FPGA. energy collision change state configuration cell thus change logic, routing, behavior unpredictable way. Another source radiation-induced firm errors alpha particles. alpha cause soft firm error, source must very close proximity affected circuit. alpha source must package molding compound itself. While low-alpha molding compounds being used increasingly, this helps reduce does entirely eliminate alpha-induced firm errors. Firm errors impossible prevent SRAM FPGAs. consequence this type error complete system failure. Firm errors occur Fusion Flash-based FPGAs. Once programmed, flash cell configuration element Fusion FPGAs cannot altered highenergy neutrons therefore immune errors from them. Recoverable soft) errors occur user data SRAMs FPGA devices. These easily mitigated using error detection correction (EDAC) circuitry built into FPGA fabric.
Power
Flash-based Fusion devices exhibit power characteristics similar those ASIC, making them ideal choice power-sensitive applications. With Fusion devices, there power-on current surge high current transition, both which occur many FPGAs. Fusion devices also have dynamic power consumption support both power standby mode very power sleep mode, offering further power savings.
Fusion Device Family Overview
Advanced Flash Technology
Fusion family offers many benefits, including nonvolatility reprogrammability through advanced flash-based, 130-nm LVCMOS process with seven layers metal. Standard CMOS design techniques used implement logic control functions. combination fine granularity, enhanced flexible routing resources, abundant flash switches allows very high logic utilization (much higher than competing SRAM technologies) without compromising device routability performance. Logic functions within device interconnected through four-level routing hierarchy.
Advanced Architecture
proprietary Fusion architecture provides granularity comparable standard-cell ASICs. Fusion device consists several distinct programmable architectural features, including following (Figure page 1-6): Embedded memories Flash memory blocks FlashROM SRAM FIFO oscillator
Clocking resources
Crystal oscillator
No-Glitch (NGMUX)
Digital I/Os with advanced standards FPGA VersaTiles Analog components Analog I/Os supporting voltage, current, temperature monitoring
on-board voltage regulator
Real-time counter
FPGA core consists VersaTiles. Each VersaTile configured three-input logic lookup table (LUT) equivalent D-flip-flop latch (with without enable) programming appropriate flash switch interconnections. This versatility allows efficient FPGA fabric. VersaTile capability unique Actel families flash-based FPGAs. VersaTiles larger functions connected with four levels routing hierarchy. Flash switches distributed throughout device provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization possible virtually design. addition, extensive on-chip programming circuitry allows rapid (3.3 single-voltage programming Fusion devices IEEE 1532 JTAG interface.
Actel Fusion Mixed-Signal FPGAs MicroBlade AdvancedMC Solution
Unprecedented Integration
Integrated Analog Blocks Analog I/Os
Fusion devices offer robust flexible analog mixed-signal capability addition highperformance flash FPGA fabric flash memory block. many built-in analog peripherals include configurable 32:1 input analog MUX, independent MOSFET gate driver outputs, configurable ADC. supports 10-, 12-bit modes operation with cumulative sample rate samples second (ksps), differential nonlinearity (DNL) LSB, Total Unadjusted Error (TUE) 0.72 10-bit mode. used characterization conversion error includes errors from sources, such offset linearity. Internal bandgap circuitry offers voltage reference accuracy with flexibility utilizing external reference voltage. channel sampling sequence sampling rate programmable implemented FPGA logic using Designer Libero software tool support. channels 32-channel ADCMUX dedicated. Channel connected internally used monitor core power supply. Channel connected internal temperature diode which used monitor device temperature. remaining channels connected external analog signals. exact number I/Os available external connection signals device-dependent (refer "MicroBlade Fusion Solutions" table page details). With Fusion, Actel also introduces Analog Quad structure (Figure page 1-6). Each quad consists three analog inputs gate driver. Each quad configured various built-in circuit combinations, such three prescaler circuits, three digital input circuits, current monitor circuit, temperature monitor circuit. Each prescaler multiple scaling factors programmed FPGA signals support large range analog inputs with positive negative polarity. When current monitor circuit selected, adjacent analog inputs measure voltage drop across small external sense resistor. Built-in operational amplifiers amplify small voltage signals sensitivity) accurate current measurement. analog input each quad connected external temperature monitor diode achieves detection accuracy addition external temperature monitor diode(s), Fusion device monitor internal temperature diode using dedicated channel ADCMUX. Figure page illustrates typical Analog Quad structure. Analog Quad shown configured monitor control external power supply. measures source power supply. measures voltage drop across external sense resistor
Fusion Device Family Overview calculate current. MOSFET gate driver turns external MOSFET off. measures load-side voltage level.
Power Line Side Load Side
Off-Chip Pads Voltage Monitor Block
Rpullup Current Monitor Block Gate Driver Temperature Monitor Block
On-Chip
Analog Quad
Prescaler Prescaler Prescaler
Digital Input
Digital Input Current Monitor/Instr Amplifier
Power MOSFET Gate Driver
Digital Input
Temperature Monitor
FPGA (DAVOUTx) Analog
FPGA (DACOUTx)
From FPGA (GDONx)
FPGA (DATOUTx) Analog
Analog
Figure Analog Quad
Embedded Memories
Flash Memory Blocks
flash memory available each Fusion device composed four flash blocks, each Mbits density. Each block operates independently with dedicated flash controller interface. Fusion flash memory blocks combine fast access times random access access Read-Ahead mode) with configurable 16-, 32-bit datapath, enabling high-speed flash operation without wait states. memory block organized pages sectors. Each page bytes, with pages comprising sector sectors block. flash block support multiple partitions. only constraint size that partition boundaries must coincide with page boundaries. flexibility granularity enable many models allow added granularity programming updates. Fusion devices support methods external access flash memory blocks. first method serial interface that features built-in JTAG-compliant port, which allows in-system programmability during user monitor/test modes. This serial interface supports programming AES-encrypted stream. Secure data passed through JTAG interface, decrypted, then programmed flash block. second method soft parallel interface. FPGA logic on-chip soft microprocessor access flash memory through parallel interface. Since flash parallel interface implemented FPGA fabric, potentially customized meet special user requirements. more information, refer CoreCFI
Actel Fusion Mixed-Signal FPGAs MicroBlade AdvancedMC Solution Handbook. flash memory parallel interface provides configurable byte-wide word-wide dual-word-wide data port options. Through programmable flash parallel interface, on-chip off-chip memories cascaded wider deeper configurations. flash memory built-in security. user configure either entire flash block small blocks prevent unintentional intrusive attempts change destroy storage contents. Each on-chip flash memory block dedicated controller, enabling each block operate independently. flash block logic consists following sub-blocks: Flash block Contains stored data. flash block contains sectors each sector contains pages data. Page Buffer Contains contents current page being modified. page contains blocks data. Block Buffer Contains contents last block accessed. block contains data bits. Logic flash memory stores error correction information with each block perform single-bit error correction double-bit error detection data blocks.
User Nonvolatile FlashROM
addition flash blocks, Actel Fusion devices have kbit user-accessible, nonvolatile FlashROM on-chip. FlashROM organized pages. FlashROM used diverse system applications: Internet protocol addressing (wireless fixed) System calibration settings Device serialization and/or inventory control Subscription-based business models (for example, set-top boxes) Secure storage secure communications algorithms Asset management/tracking Date stamping Version management
FlashROM written using standard IEEE 1532 JTAG programming interface. Pages individually programmed (erased written). On-chip decryption used selectively over public networks securely load data such security keys stored FlashROM user design. FlashROM programmed (erased written) JTAG programming interface, contents read back either through JTAG programming interface direct FPGA core addressing. FlashPoint tool Actel Fusion development software solutions, Libero Designer, extensive support flash memory blocks FlashROM. such feature auto-generation sequential programming files applications requiring unique serial number each part. Another feature allows inclusion static data system version control. Data FlashROM generated quickly easily using Actel Libero Designer software tools. Comprehensive programming file support also included allow easy programming large numbers parts with differing FlashROM contents.
SRAM FIFO
Fusion devices have embedded SRAM blocks along north south sides device. Each variable-aspect-ratio SRAM block 4,608 bits size. Available memory configurations bits. individual blocks have independent read write ports that configured with different widths each port. example, data written through 4-bit port read single bitstream. SRAM blocks initialized from flash memory blocks device JTAG port (ROM emulation mode), using UJTAG macro. addition, every SRAM block embedded FIFO control unit. control unit allows SRAM block configured synchronous FIFO without using additional core VersaTiles. FIFO width depth programmable. FIFO also features programmable Almost Empty
Fusion Device Family Overview (AEMPTY) Almost Full (AFULL) flags addition normal EMPTY FULL flags. embedded FIFO control unit contains counters necessary generation read write address pointers. SRAM/FIFO blocks cascaded create larger configurations.
Clock Resources
PLLs Clock Conditioning Circuits (CCCs)
Fusion devices provide designers with very flexible clock conditioning capabilities. Each member Fusion family contains CCCs. larger family members, these CCCs also include PLL; smaller devices support PLL. inputs blocks accessible from FPGA core from several inputs with dedicated block connections. block following features: Wide input frequency range (fIN_CCC) Output frequency range (fOUT_CCC) 0.75 Clock phase adjustment programmable fixed delays from -6.275 +8.75 Clock skew minimization (PLL) Clock frequency synthesis (PLL) On-chip analog clocking resources usable inputs: on-chip oscillator Crystal oscillator
Additional specifications: Internal phase shift 90°, 180°, 270° Output duty cycle 1.5% output jitter. Samples peak-to-peak period jitter when single global network used: Worst case 2.5% clock period
Maximum acquisition time power consumption
Global Clocking
Fusion devices have extensive support multiple clocking domains. addition support described above, there on-chip oscillators well comprehensive global clock distribution network. integrated oscillator generates clock. used internally provide known clock source flash memory read write control. also used source PLLs. crystal oscillator supports following operating modes: Crystal (32.768 MHz) Ceramic (500 MHz) (32.768 MHz)
Each VersaTile input output port access nine VersaNets: main three quadrant global networks. VersaNets driven directly accessed from core MUXes. VersaNets used distribute low-skew clock signals rapid distribution high-fanout nets.
Actel Fusion Mixed-Signal FPGAs MicroBlade AdvancedMC Solution
Digital I/Os with Advanced Standards
Fusion family FPGAs features flexible digital structure, supporting range voltages (1.5 Fusion FPGAs support many different digital standards, both single-ended differential. I/Os organized into banks, with four five banks device. configuration these banks determines standards supported. banks along east west sides device support full range standards (single-ended differential). south bank supports Analog Quads (analog I/O). family's smaller devices, north bank supports multiple single-ended digital standards. family's larger devices, north bank divided into banks digital I/Os, supporting wide variety single-ended, differential, voltage-referenced standards. Each module contains several input, output, enable registers. These registers allow implementation following applications: Single-Data-Rate (SDR) applications Double-Data-Rate (DDR) applications-DDR LVDS chip-to-chip communications Fusion banks support LVPECL, LVDS, BLVDS, M-LVDS with multi-drop points.
VersaTiles
Fusion core consists VersaTiles, which also used successful Actel ProASIC3 family. Fusion VersaTile supports following: 3-input logic functions-LUT-3 equivalent Latch with clear D-flip-flop with clear optional enable
Refer Figure VersaTile configuration arrangement.
LUT-3 Equivalent
D-Flip-Flop with Clear
Data
Enable D-Flip-Flop with Clear
Data Enable
LUT-3
D-FF
D-FFE
Figure VersaTile Configurations
Fusion Device Family Overview
Related Documents
Datasheet
Core8051
Application Notes
Fusion FlashROM Fusion SRAM/FIFO Blocks Using Fusion Devices Fusion Security Using Fusion Multipliers Prototyping with AFS600 Smaller Devices UJTAG Applications Actel's Low-Power Flash Devices In-System Programming (ISP) Actel's Low-Power Flash Devices Using FlashPro3
Handbook
Fusion Handbook
User's Guides
Designer User's Guide Fusion, IGLOO/e ProASIC3/E Macro Library Guide SmartGen, FlashROM, Flash Memory System Builder, Analog System Builder User's Guide
White Papers
Fusion Technology
Actel Fusion Mixed-Signal FPGAs MicroBlade AdvancedMC Solution
Part Number Revision Date
Part Number 51700104-001-0 Revised October 2008
List Changes
following table lists critical changes that were made current version document. This datasheet based Actel Fusion Mixed-Signal FPGAs datasheet. past Fusion datasheet changes, refer Actel Fusion Programmable System Chips datasheet change table. Previous Version Advance v0.3 (August 2008) Changes Current Version (Preliminary v0.4) version number category changed from Advance Preliminary, which means datasheet contains information based simulation and/or initial characterization. information believed correct, changes possible. title datasheet changed from Actel Programmable System Chips MicroBlade Advanced Mezzanine Card Solution Actel Fusion MixedSignal FPGAs MicroBlade Advanced Mezzanine Card Solution. addition, instances programmable system chip were changed mixedsignal FPGA. Page
Advance v0.1 (July 2008)
Fusion Device Family Overview
Datasheet Categories
Categories
order provide latest information designers, some datasheets published before data been fully characterized. Datasheets designated "Product Brief," "Advance," "Preliminary," "Production." definition these categories follows:
Product Brief
product brief summarized version datasheet (advance production) contains general product information. This document gives overview specific device family information.
Advance
This version contains initial estimated information based simulation, other products, devices, speed grades. This information used estimates, production. This label only applies Switching Characteristics chapter datasheet will only used when data been fully characterized.
Preliminary
datasheet contains information based simulation and/or initial characterization. information believed correct, changes possible.
Unmarked (production)
This version contains information that considered final.
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Actel products described this advance status document have completed Actel's qualification process. Actel amend enhance products during product introduction qualification process, resulting changes device functionality performance. responsibility each customer ensure fitness Actel product (but especially product) particular purpose, including appropriateness safety-critical, life-support, other high-reliability applications. Consult Actel's Terms Conditions specific liability exclusions relating life-support applications. reliability report covering Actel's products available Actel website Actel also offers variety enhanced qualification acceptance screening procedures. Contact your local Actel sales office additional reliability information.
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