Radiation Performance SEU-Hardened Registers Eliminate Need Tripl

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Radiation Performance SEU-Hardened Registers Eliminate Need Tripl

Datasheet Thumbnail

Top Searches for this datasheet

RTAX-DSP Radiation-Tolerant FPGAs
Radiation Performance
SEU-Hardened Registers Eliminate Need TripleModule Redundancy (TMR) Immune Single-Event Upsets (SEU) LETTH MeV-cm2/mg Rate 10-10 Errors/Bit-Day Worst-Case Geosynchronous Orbit Expected SRAM Upset Rate <10-10 Errors/Bit-Day with Error Detection Correction (EDAC) (included) with Integrated SRAM Scrubber Single-Bit Correction, Double-Bit Detection Variable-Rate Background Refreshing Total Ionizing Dose krad (Si, Functional) Single-Event Latch-Up Immunity (SEL) LETTH MeV-cm2/mg TM1019 Test Data Available
Leading-Edge Performance
High-Performance Embedded FIFOs 350+ System Performance 500+ Internal Performance Mbps LVDS Capable I/Os
Specifications
Million Equivalent System Gates Equivalent ASIC Gates 16,800 SEU-Hardened Flip-Flops I/Os kbits Embedded SRAM Manufactured Advanced 0.15 CMOS Antifuse Process Technology, Layers Metal
Features
Single-Chip, Nonvolatile Solution Core Voltage Power Flexible, Multi-Standard I/Os: Mixed Voltage Operation Bank-Selectable I/Os Banks Chip Single-Ended Standards: LVTTL, LVCMOS, JTAG Boundary Scan Testing IEEE 1149.1) Differential Standards: LVPECL LVDS Voltage-Referenced Standards: GTL+, HSTL Class SSTL2 Class SSTL3 Class Hot-Swap Compliant with Cold-Sparing Support (Except PCI) Embedded Memory with Variable Aspect Ratio Organizations: Independent, Width-Configurable Read Write Ports Programmable Embedded FIFO Control Logic Emulation Capability Deterministic, User-Controllable Timing Unique In-System Diagnostic Debug Capability
Embedded Multiply/Accumulate Blocks
Multiply/Accumulate Blocks Fully SEU- SET-Hardened Performance throughout Military Temperature Range Flexible, Cascadable Accumulate Function
Processing Flows
B-Flow MIL-STD-883B E-Flow Actel Extended Flow EV-Flow Class Equivalent Flow Processing
Prototyping Options
RTAX-DSP PROTO Devices with Same Functional Timing Characteristics Flight Unit Non-Hermetic Package
Table
RTAX-DSP Family Product Profile RTAX2000D 2,000,000 250,000 8,960 17,920 17,920 2,052 1152 RTAX4000D 4,000,000 500,000 16,800 33,600 33,600 2,520 1272
Device Capacity Equivalent System Gates ASIC Gates Modules Register (R-cells) Combinatorial (C-cells) Flip-Flops (maximum) Embedded Multiply Accumulate Blocks Mathblocks Embedded RAM/FIFO (without EDAC) Core Blocks Core Bits 1,024) Clocks (segmentable) Hardwired Routed I/Os Banks User I/Os (maximum) Registers Package CCGA/LGA
2008 Actel Corporation
Actel website latest version datasheet.
RTAX-DSP Radiation-Tolerant FPGAs
Ordering Information
RTAX2000D 1152 Application MIL-STD-883 Class E-Flow (Actel Space-Level Flow) Class Equivalent Flow Processing Package Lead Count Package Type Ceramic Column Grid Array Land Grid Array Speed Grade Blank Standard Speed Part Number RTAX2000D 2,000,000 Equivalent System Gates RTAX4000D 4,000,000 Equivalent System Gates
Temperature Grade Offerings
Package CG1152/LG1152 CG1272/LG1272 RTAX2000D RTAX4000D
Note: *The CCGA offerings (1152 1272) offered with Sigma columns. MIL-STD-883 Class E-Flow (Actel Space-Level Flow) Actel Equivalent Flow
Speed Grade Temperature Grade Matrix
Std.
Contact your local Actel representative device availability.
Device Resources
Device CG484/LG1152 CG896/LG1272 User I/Os (including clock buffers) RTAX2000D RTAX4000D
Note: CCGA Ceramic Column Grid Array, Land Grid Array
RTAX-DSP Radiation-Tolerant FPGAs
Actel MIL-STD-883 Class Product Flow
Table Step Internal Visual Serialization Temperature Cycling Constant Acceleration Particle Impact Noise Detection Seal (Fine Gross Leak Test) Pre-Burn-In Electrical Parameters Dynamic Burn-In Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test Static Tests 25°C -55°C +125°C Functional Tests 25°C -55°C +125°C Switching Tests 25°C External Visual 1010, Condition cycles minimum 2001, Orientation Only Condition 2020, Condition 1014 accordance specification with applicable Actel device Actel MIL-STD-883 Class Product Flow RTAX-DSP* Screen 2010, Condition Method Requirement 100% 100% 100% 100% 100% 100% 100% 100% 100% Lots device 100%
1015, Condition hours 125°C hours 150°C minimum accordance specification accordance with applicable Actel specification, which includes 5005, Table Subgroup 5005, Table Subgroup with applicable Actel device
5005, Table Subgroup 5005, Table Subgroup 5005, Table Subgroup 2009 100%
Note: *For CCGA devices, Assembly, Screening, testing performed level. Only electrical mechanical visual tests performed after solder column attachment.
RTAX-DSP Radiation-Tolerant FPGAs
Actel Extended Flow
Table Step Destructive Bond Pull Internal Visual Serialization Temperature Cycling Constant Acceleration Particle Impact Noise Detection Radiographic (X-Ray) Pre-Burn-In Electrical Parameters Dynamic Burn-In 1010, Condition cycles minimum 2001, Orientation Only Condition 2020, Condition 2012, View Orientation) Only accordance with applicable Actel device specification 1015, Condition hours 125°C hours 150°C minimum 1015, Condition hours 150°C hours 125°C minimum accordance with applicable Actel device specification Overall, Functional Parameters 25°C accordance with applicable Actel specification, which includes 5005, Table Subgroup 5005, Table Subgroup device 100% 100% 100% 100% Lots 100% 100% 100% Actel Extended Flow RTAX-DSP1, Screen
Method 2011, Condition 2010, Condition
Requirement Extended Sample 100% 100% 100%
Interim (Post-Dynamic-Burn-In) Electrical Parameters accordance with applicable Actel device specification Static Burn-In Interim (Post-Static-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test
Static Tests 25°C -55°C +125°C Functional Tests 25°C -55°C +125°C Switching Tests 25°C Notes: Seal (Fine Gross Leak Test) External Visual
5005, Table Subgroup 5005, Table Subgroup 5005, Table Subgroup 1014 2009 100% 100%
Actel offers Extended Flow users requiring additional screening beyond MIL-STD-833, Class requirement. Extended Flow incorporates majority screening procedures outlined Method 5004 MIL-STD-883, Class Quality Conformance Inspection (QCI) Extended Flow devices still complies MIL-STD-833, Class requirement. CCGA devices, Assembly/Screening/TCI testing performed level. Only electrical mechanical visual tests performed after solder column attachment. Requirement 100% nondestructive bond pull Method 2003 substituted extensive destructive bond pull Method 2011 Condition extended sample basis.
RTAX-DSP Radiation-Tolerant FPGAs
Actel "EV" Flow (Class Flow Equivalent Processing)
Table Step Destructive Bond Pull Internal Visual Serialization Temperature Cycling Constant Acceleration Particle Impact Noise Detection Radiographic (X-Ray) Pre-Burn-In Electrical Parameters Dynamic Burn-In 1010, Condition cycles minimum 2001, Orientation Only Condition 2020, Condition 2012, View Orientation) Only accordance specification with applicable Actel device Actel "EV" Flow (Class Equivalent Flow Processing) RTAX-DSP1, Screen
Method 2011, Condition 2010, Condition
Requirement Extended Sample 100% 100% 100% 100% 100% 100% 100% 100%
1015, Condition hours 125°C hours 150°C minimum with applicable Actel device
Interim (Post-Dynamic-Burn-In) Electrical Parameters accordance specification Static Burn-In Interim (Post-Static-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test
100% 100% 100% Lots 100%
1015, Condition hours 150°C hours 125°C minimum accordance specification with applicable Actel device
Overall, Functional Parameters 25°C accordance with applicable Actel specification, which includes 5005, Table Subgroup 5005, Table Subgroup device
Static Tests 25°C -55°C +125°C Functional Tests 25°C -55°C +125°C Switching Tests 25°C Notes: Seal (Fine Gross Leak Test) External Visual Wafer Specific Life Test (Group
5005, Table Subgroup 5005, Table Subgroup 5005, Table Subgroup 1014 2009 MIL-PRF-38535, Appendix sec. B.4.2.c 100% 100% Wafer Lots
Actel offers "EV" flow users requiring full compliance MIL-PRF-38535 Class requirement. "EV" process flow expanded from existing E-flow requirement still meets full requirement current E-flow devices) with intention full compliance MIL-PRF-38535 Table Appendix requirement, without official Class certification from DSCC. CCGA devices, Assembly/Screening/TCI testing performed level. Only electrical mechanical visual tests performed after solder column attachment. requirement 100% nondestructive bond pull Method 2003 fulfilled substitution extensive extended sample basis. Read record performed -55°C +125°C delta calculation).
RTAX-DSP Radiation-Tolerant FPGAs
General Description
RTAX-DSP Mathblock Functional Description
flexible elements RTAX-DSP Mathblocks enable easy integration into many different signal processing topologies, such Fast Fourier Transforms, Inverse Fast Fourier Transforms, Finite Impulse Response Filters, Infinite Impulse Response Filters, Discrete Cosine Transforms. hardwired Mathblocks also enable acceleration high precision single- doublefloating point multiplications. Figure shows basic functional diagram Mathblock. multiplier fractured implement instances signed multiplication (Figure 1-3).
A1[8:0]
B1[8:0]
P1[17:0]
A2[8:0] ADD_SUB A[17:0] OVFL
B2[8:0]
P2[17:0]
B[17:0] SHIFT17 SEL_CONST CONST[40:0] SEL_CASC
+/>>17
SN[40:0]
Figure Mathblock Configured with Independent Signed multipliers
Adder/Subtractor plus Control
MUX2
adder/subtractor perform following functions: Accumulate using feedback. Create higher precision multipliers using SN-1 input 17-bit shift function. Create complex functions, such filters, cascading Mathblocks together using SN-1 input. initial value accumulate function using value defined CONST bus.
MUX1
SN-1[40:0]
Figure RTAX-DSP Mathblock
Mathblocks comprise following elements: Multiplier multiplier operates signed 18-bit factors, A[17:0] B[17:0] (Figure 1-2). multiplier produces signed 36-bit output, which provided input add/subtract function. output multiplier optionally bypass add/subtract function.
Overflow underflow add/subtract function indicated OVFL output. Figure shows Mathblock configured perform multiply accumulate functions. FPGA resources used extend accumulate width.
A[17:0]
ADD_SUB A[17:0] OVFL
B[17:0]
P[35:0] B[17:0]
SEL_CONST CONST[40:0]
SN[40:0]
Figure RTAX-DSP Mathblock Multiplier Configured Signed 18x18
Figure Mathblock Configured Perform Multiply Accumulate Functions
RTAX-DSP Radiation-Tolerant FPGAs
Output Register output adder/subtractor block presented 41-bit output register. register clock input, enable input, reset input, provides 41-bit output SN[40:0] exterior Mathblock. Signals SN[40:0] also back within Mathblock accumulator multiplexer stack enable various accumulation functions. Cascading Mathblocks Mathblocks cascaded together form complex structures such filters FFTs. Figure shows configuration Mathblocks cascaded together.
A[17:0]
Next Mathblock
B[17:0] CASC_CTL A[17:0]
+/Cascade
P2[40:0]
B[17:0]
+/Cascade
P1[40:0]
Previous Mathblock
Figure Mathblocks Cascaded Together Part Complex Function
RTAX-DSP Architecture
overall RTAX-DSP device architecture shown Figure 1-6. each core tile, there four Mathblocks, which located adjacent SRAM/FIFO blocks. Mathblocks evenly distributed across device, help achieve uniform performance functions.
SuperCluster
Core Tile
Mathblock RAM/FIFO
RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC
RAM/FIFO
RAM/FIFO
RAM/FIFO
Chip Layout
ADD_SUB
A[17:0]
OVFL
Structure
B[17:0]
SHIFT17
SN[40:0]
SEL_CONST CONST[40:0] SEL_CASC
MUX2
MUX1
SN-1[40:0]
Mathblock
Figure RTAX-DSP Device Architecture Overview
Actel Actel logo registered trademarks Actel Corporation. other trademarks property their owners.
Actel Corporation 2061 Stierlin Court Mountain View, 94043-4655 Phone 650.318.4200 650.318.4600 Actel Europe Ltd. River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 United Kingdom Phone 1276 1276 Actel Japan EXOS Ebisu Buillding 1-24-14 Ebisu Shibuya-ku Tokyo Japan Phone +81.03.3445.7671 +81.03.3445.7668 http://jp.actel.com Actel Hong Kong Room 2107, China Resources Building Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 +852 2185 6488 www.actel.com.cn
51700108-0/9.08

Radiation Performance SEU-Hardened Registers Eliminate Need Tripl

Top Searches for this datasheet

Other recent searches