Intended COordinate Rotation DIgital Computer (CORDIC) Rotator Fu
|
|
|
Top Searches for this datasheet
CoreCORDIC CORDIC Generator
Intended
COordinate Rotation DIgital Computer (CORDIC) Rotator Function Actel FPGAs Evaluation Version Supports CORDIC Engine Test Harness Generation with Limited Parameters. Fully Supported Libero IDE.
Synthesis Simulation Support
Libero Synthesis: Synplicity®, Synopsys® Compiler/FPGA Compiler), Exemplar(Design
Features
Vector Rotation Conversion Polar Coordinates Rectangular Coordinates Vector Translation Conversion Rectangular Coordinates Polar Coordinates Sine Cosine Calculation Vector Magnitude (arctan[X/Y]) Calculation
Simulation: OVI-Compliant Verilog Simulators Vital-Compliant VHDL Simulators.
Table Contents
General Description CoreCORDIC Device Requirements Architectures Formats CoreCORDIC Configuration Parameters Signal Description Interface Timing References Sample Configuration File Ordering Information Datasheet Categories Appendix Appendix
Phase
8-Bit 48-Bit Configurable Word Size Configurable Number Iterations Parallel Pipelined Architecture Fastest Calculation Bit-Serial Architecture Smallest Area Word-Serial Architecture Moderate Speed Area Word Parallel Data I/Os
Supported Families
Fusion ProASIC®3/E ProASICPLUS Axcelerator® RTAX-S SX-A RTSX-S
General Description
CoreCORDIC generator that produces Actel FPGA-optimized CORDIC engine. CORDIC algorithm Volder provides iterative method performing vector rotations using shifts adds only. articles listed "References" page present detailed description algorithm. Depending configuration defined user, resulting module implements pipelined parallel, wordserial, bit-serial architecture major modes: rotation vectoring. rotation mode, CORDIC rotates vector specified angle. This mode used convert polar coordinates Cartesian
Core Deliverables
Full Version CoreCORDIC Generator. Generates UserDefined CORDIC Model Test Harness. Fully Supported Actel Libero® Integrated Design Environment (IDE)
March 2006 2006 Actel Corporation
CoreCORDIC CORDIC Generator
coordinates, general vector rotation, also calculate sine cosine functions (see Figure "Appendix page presents mathematical coordinate conversion formulae, "Appendix page describes examples most used CORDIC modes.
Magnitude Phase
CORDIC Engine
gain compensated elsewhere many applications when system includes CORDIC engine. assist user doing CoreCORDIC software computes precise value gain displays screen. cases when only relative magnitude importance-for example, spectrum analysis demodulation-the constant gain neglected. When calculating sine/cosine, CORDIC gets initialized with constant reciprocal value processing gain 1/K. become
Figure CORDIC Engine Rotation Mode
vectoring mode, CORDIC rotates input vector towards axis while accumulating rotation angle. Vectoring mode used convert Cartesian vector coordinates polar coordinates; i.e., calculate magnitude phase input vector (Figure
Thus, gain does impact sine/cosine results phase output. perform conversions, CORDIC processor implements iterative CORDIC equations through
CORDIC Engine
Magnitude Phase
arctan
Figure CORDIC Engine Vectoring Mode
CORDIC results, such scaled inherent processing gain, which depends number iterations converges about 1.647 after iterations. gain constant given number iterations. When performing Cartesian/polar coordinate conversion, CORDIC computes results shown rotation mode.
sign-controlling function takes values shown rotation mode otherwise
vectoring mode
otherwise
show CORDIC results vectoring mode.
arctan
input output data represented n-bit words, where user-defined number range from number iterations also defined user same range. CORDIC result accuracy improves when number iterations increased, long number iterations does exceed data width. other words, width limits number meaningful iterations.
system that utilizes CORDIC engine (Figure page consists following: data source generating vector data converted CORDIC CORDIC module configured work either rotation vectoring mode data receiver accepting newly converted vector data
v2.0
CoreCORDIC CORDIC Generator
Master Clock
clkEn Data Source ldData Global Reset nGrst CORDIC Engine rdyOut Data Receiver
Figure CORDIC-Based System
negative nGrst signal resets CORDIC engine and, optionally, entire system. After reset (input nGrst taken high), CORDIC module ready receive data samples processed. module synchronous reset input used bring CORDIC unit ready state time after initial global reset. Note: CORDIC module will lose half-processed data when taken high system. data source supplies CORDIC engine with data converted. Depending mode (rotation vectoring), system uses different CORDIC inputs outputs enter obtain data. Table shows input/ output signals used each mode.
Table CORDIC Connection System Input Data CORDIC Input Common Rotation Modes Input vector magnitude Constant Input vector phase Output vector coordinate Output vector coordinate sin() cos() Output Data CORDIC Output
Rotation Mode: Sine/Cosine Table Generator Constant reciprocal value processing gain Constant Sine/cosine argument Vectoring Mode Input vector coordinate Input vector coordinate Constant Output vector magnitude Output vector phase
system accompanies every pair input data samples with one-bit ldData signal. Upon receiving ldData bit, module assumes vector coordinates present input data busses. Once CORDIC results ready, engine puts these out, accompanied one-bit rdyOut signal. Upon receiving rdyOut bit, system supply pair input data generate another ldData signal. CoreCORDIC generate three different CORDIC core implementation architectures appropriate testbench: Parallel pipelined Word-serial Bit-serial
parallel pipelined architecture provides fastest speed, whereas bit-serial architecture provides smallest area. word-serial architecture provides trade-off moderate speed area.
v2.0
CoreCORDIC CORDIC Generator
CoreCORDIC Device Requirements
Table provides typical utilization performance data CoreCORDIC, implemented various Actel devices with CORDIC engine resolution bits number iterations Device utilization performance will vary depending upon architecture chosen configuration parameters used. Time-driven settings were used when synthesizing parallel architectures; area optimization settings were used other cases. CORDIC core does utilize on-chip blocks.
Table CoreCORDIC Device Utilization Performance Cells Tiles Device Fusion AFS600 AFS600 AFS600 ProASIC3/E A3P250 A3P250 A3P1000 ProASICPLUS APA150 APA150 APA1000 Axcelerator AX125 AX125 AX500 RTAX-S RTAX250S RTAX250S RTAX1000S Bit-serial Word-serial Parallel Rotate Vector Rotate Vector Rotate Vector 4,633 4,617 Bit-serial Word-serial Parallel Rotate Vector Rotate Vector Rotate Vector 4,633 4,617 Bit-serial Word-serial Parallel Rotate Vector Rotate Vector Rotate Vector 14,301 16,594 Bit-serial Word-serial Parallel Rotate Vector Rotate Vector Rotate Vector 12,541 14,832 Bit-serial Word- serial Parallel Rotate Vector Rotate Vector Rotate 11,810 Engine Architecture Mode Comb Speed Grade 1,884 Speed Grade 1,906 1,981 1,889 1,936 Speed Grade 1,832 1,835 Speed Grade 1,832 1,835 6,465 6,452 6,283 5,780 11.2 12.3 6,465 6,452 5,115 5,026 14,447 16,813 16,190 18,530 6,964 6,215 21.7 16.1 9,475 9,175 1,250 1,316 31.3 27.0 13,694 6,568 6644 21.7 Total Utilization Clock Rate, Transform Time, nsec
Speed Grade
Note: above data were obtained typical synthesis place-and-route methods. Other core parameter settings result different utilization performance values.
v2.0
CoreCORDIC CORDIC Generator
Table CoreCORDIC Device Utilization Performance (Continued) Cells Tiles Device 54SX-A 54SX72A 54SX72A RT54SX-S RT54SX72S RT54SX72S Bit-serial Word-serial Rotate Vector Rotate Vector Bit-serial Word-serial Rotate Vector Rotate Vector Engine Architecture Mode Comb Speed Grade Speed Grade 10,509 10,509 8,627 8,141 Total Utilization Clock Rate, Transform Time, nsec
Note: above data were obtained typical synthesis place-and-route methods. Other core parameter settings result different utilization performance values.
Architectures
Word-Serial Architecture
Direct implementation CORDIC iterative equations (see "References" page yields block diagram shown Figure vector coordinates converted, initial values, loaded multiplexers into registers RegX, RegY, RegA. RegA, along with adjacent adder/subtractor, multiplexer, small arctan LUT, often called angle accumulator. Then each following clock cycles, registered values passed through adders/subtractors shifters. results described through page loaded back same registers. Every iteration takes clock cycle, that clock cycles, iterations performed converted coordinates stored registers.
arctan
RegX Sign Mode: Rotation/Vectoring
Figure Word-Serial CORDIC Block Diagram
RegY Sign Sign Controlling Logic
RegA
v2.0
CoreCORDIC CORDIC Generator
Depending CORDIC mode (rotation vectoring), sign-controlling logic watches either RegY RegA sign bit. Based page decides what type operation (addition subtraction) needs performed every iteration. arctan keeps pre-computed table arctan(2-i) values. number entries arctan equals desirable number iterations, word-serial CORDIC engine takes clock cycles complete single vector coordinate conversion.
xn-1 yn-1 dn-1 dn-1 dn-1
arctan (20)
Parallel Pipelined Architecture
This architecture presents unrolled version sequential CORDIC algorithm above. Instead reusing same hardware iteration stages, parallel architecture separate hardware processor every CORDIC iteration. example parallel CORDIC architecture configured rotation mode shown Figure Each processors performs specific iteration, particular processor always performs same iteration. This leads simplification hardware. shifters perform fixed shift, which means these implemented FPGA wiring. Every processor utilizes particular arctan value that also hardwired input every angle accumulator. another simplification absence state machine. parallel architecture obviously faster than sequential architecture described "Word-Serial Architecture" section page accepts input data puts results every clock cycle. architecture introduces latency clock cycles.
arctan (2-1)
arctan (2-2)
an-1
arctan (2n-1)
dn-1
Figure Parallel CORDIC Architecture
v2.0
CoreCORDIC CORDIC Generator
Bit-Serial Architecture
Whenever CORDIC conversion speed issue, this architecture provides smallest FPGA implementation. example, order initialize Sine/Cosine LUT, bit-serial CORDIC solution. Figure depicts simplified block diagram bitserial architecture. shift registers loaded with initial data presented bit-parallel form, i.e., bits once. data then shifts right, before arriving serial adders/subtractors. Every iteration takes clock cycles, where CORDIC resolution. Serial shifters implemented properly tapping bits shift registers. control circuitry (not shown Figure provides sign-padding shifted serial data realize correct sign extension. results from serial adders return back shift registers, that clock cycles results another iteration stored shift registers. single full CORDIC conversion takes clock cycles.
Formats
Format Fixed-Point Numbers
CoreCORDIC, virtually FPGA core does, utilizes fixed-point arithmetic. particular, numbers core operates with presented two's complement signed fractional numbers. identify position binary point separating integer fractional portions number, format commonly used. format number (n+1)-bit signed two's complement fixed-point number: sign followed significant bits with binary point placed immediately right most significant bits. MSBs represent integer part, (n-m) LSBs represent fractional part number, called mantissa. Table depicts example format number.
Table Format Number Sign 2n-1 Integer Position Binary Point Bits [2n-2 Mantissa
Table Format Number
Shift
Sign
Position Binary Point
Bits [2n-1 Mantissa
signX signY
Shift
following sections explain detail formats input output signals. linear angular values explained separately. linear signals include Cartesian coordinates vector magnitude. These come CORDIC engine inputs appear outputs Since sine cosine functions CORDIC calculates essentially Cartesian coordinates vector, angular signals include vector phase that comes CORDIC engine input appears output Both linear angular signals utilize formats appropriate conversion rules from floating-point formats.
Linear Format
Shift arctan Serial
Figure Bit-Serial CORDIC Architecture
CoreCORDIC engine utilizes format shown Table Though format numbers capable expressing fixed-point numbers range from (-2n) 2m-n), input linear data must limited smaller range from (-2n-1) (2n-1). terms floating-point numbers, input must range from -1.0 +1.0. example, format input data range limited following 10-bit numbers: input negative number -1.0: 1100000000 11.00000000
v2.0
CoreCORDIC CORDIC Generator
input positive number +1.0: 0100000000 01.00000000 This precaution taken prevent data overflow that otherwise could occur result CORDIC inherent processing gain. output data obviously have limited range. convert floating-point linear input data format, follow simple rule Fixed-Point Data
Here assumed floating-point data presented range from -1.0 1.0. product right-hand side contains integer fractional parts. fractional part truncated rounded. Table shows examples converting floating-point numbers format. convert format back floating-point format, Floating-Point Data Fixed-Point Data/2n-1
Floating-Point Data
Table Floating-Point Format Conversion Floating-Point Number 1.00 0.678915 0.047216 -1.00 -0.678915 -0.047216 2(n-1) 173.80224 12.087296 -256 -173.80224 -12.087296 Rounded -256 -174 Common Binary Format 0100000000 0010101101 0000001100 1100000000 1101010011 1111110100 Format 01.00000000 00.10101101 00.00001100 11.00000000 11.01010011 11.11110100
Angular Format
angle (phase) signals They presented format, shown Table page relation between floating-point angular value expressed radians format shown Fixed-Point Angle 2n-1 Floating-Point Angle/
floating-point angle measured radians. product right-hand side contains integer fractional parts. fractional part must truncated rounded. presents rule conversion from format back floating-point radian measure. Floating-Point Angle Fixed-Point Angle
conversion formulae support important feature that greatly simplifies sine cosine table calculations. Such tables usually have power entries (lines). same time, they often span angular values from radians. Therefore, beneficial represent angle radians with power fixed-point number. particular, when having CORDIC engine calculate sin() cos() table, sufficient increment fixed-point angular argument each cycle. angular value range from format: input negative number -/2: 1100000000 .1100000000 input positive number +/2: 0100000000 .0100000000
Table shows examples converting floating-point numbers format.
Table Examples Angular Value Fixed-Point Conversion Floating-Point Angle (rad) /256 1.5707963268 0.7853981634 0.0122718463 Common Binary Format 0100000000 0010000000 0000000010 Format (sign.mantissa) 0.100000000 0.010000000 0.000000010
This format means, literally, angle radians expressed floating-point value 1.0.
v2.0
CoreCORDIC CORDIC Generator
Table Examples Angular Value Fixed-Point Conversion -/256 -1.5707963268 -0.7853981634 -0.0122718463 -256 -128 1100000000 1110000000 1111111110 1.100000000 1.110000000 1.111111110
CoreCORDIC Configuration Parameters
CoreCORDIC generates CORDIC engine code based parameters user when generating module. core generator supports variations specified Table
Table Core Generator Parameters Parameter Name module_name architecture mode Description Name generated code module Bit-serial, word-serial, word parallel architecture Values (bit-serial), (word-serial), (parallel). Default value
Vector rotation (polar rectangular coordinate conversion sine/ (vector rotation), (vector cosine calculation) vector translation (rectangular polar translation). Default value conversion) data width Number iterations Family Actel FPGA device code language 8-48. Default value 8-48. Default value bit_width.* (Axcelerator), (ProASICPLUS), (ProASIC3), (SX-A), (Fusion) vhdl, verilog
bit_width iterations fpga_family lang
Note: warning issued number iterations greater than width.
Signal Description
Figure shows CoreCORDIC module pinout.
CORDIC IdData clkEn nGrst
Figure CoreCORDIC Signals
rdyOut
v2.0
CoreCORDIC CORDIC Generator
CoreCORDIC module signal functionality listed Table
Table Signal Descriptions Signal Name [bit_width Direction Description Input Input data abscissa input vector vectoring mode magnitude input vector rotation mode should placed this bus. [bit_width MSB. Data assumed presented two's complement format. other vector coordinates supplied simultaneously. Input data ordinate input vector vectoring mode should placed this bus. rotation mode, should grounded left idle. [bit_width MSB. Data assumed presented two's complement format. other vector coordinates supplied simultaneously. Input angle data phase input vector rotation mode should placed this bus. vectoring mode, should grounded left idle. [bit_width MSB. Data assumed presented two's complement format. other vector coordinates supplied simultaneously. System clock. Active rising edge. System asynchronous reset. Active low. System/module synchronous reset. Active high. Valid parallel architecture only. Resets registers core. Clock enable signal. Active high. Valid word-serial bit-serial architectures. Load input data. Indicates that input vector coordinates ready CORDIC engine processed. Active high. Valid word-serial bit-serial architectures. Output data (vector coordinates sine/cosine values) ready data receiver read. Active high. Valid word-serial bit-serial architectures. Output data abscissa output vector rotation mode magnitude output vector vectoring mode appears this bus. [bit_width MSB. Data presented two's complement format. other vector coordinates emerge their respective output busses simultaneously. Output data ordinate output vector rotation mode. [bit_width MSB. Data presented two's complement format. other vector coordinates emerge their respective output busses simultaneously. Output data phase output vector vectoring mode. [bit_width MSB. Data presented two's complement format. other vector coordinates emerge their respective output busses simultaneously.
[bit_width
Input
[bit_width
Input
nGrst clkEn ldData rdyOut [bit_width-1
Input Input Input Input Input Output Output
[bit_width-1
Output
[bit_width-1
Output
v2.0
CoreCORDIC CORDIC Generator
Interface Timing
Upon reset, CORDIC core returns initial state. Signal nGrst asynchronously resets architecture. Other interfaces timing depend core architecture.
computation cycle discards incomplete results interrupted cycle. Once CORDIC engine completes calculating result, generates rdyOut signal clock period width. result output busses (an, valid while rdyOut signal active. next ldData signal coincide with rdyOut signal. Obviously valid, fresh input data, shown Figure must ready then. cycle CORDIC computation (bit_width iterations clock cycles. Signal clkEn manipulated desired. While this signal low, CORDIC engine retains data collected processed far. Normally, bit-serial CORDIC engine used fill power-on event. Once CORDIC fulfills this function, high-level state machine disable clkEn signal.
Bit-Serial Architecture Interface Timing
Figure depicts typical timing diagram bitserial architecture. Signal ldData resets bit-serial CORDIC module loads data present input busses. input data shown Figure In0. Normally, next ldData signal come after current CORDIC cycle; i.e., after rdyOut signal appears module output. case that next ldData signal issued prior current cycle, CORDIC engine starts
CORDIC Cycle
IdData
rdyOut
Figure Bit-Serial Architecture Timing Diagram
Out0
Word-Serial Architecture Interface Timing
Figure page depicts timing diagram word-serial architecture. very similar bit-serial timing diagram. Signal ldData resets word-serial CORDIC module loads data present input busses. input data shown Figure page In0. Normally next ldData signal must come after current CORDIC cycle; i.e., after rdyOut signal appears module output. case that next ldData signal issued prior current cycle, CORDIC engine starts computation cycle discards incomplete results interrupted cycle.
Once CORDIC engine completes calculating result, generates rdyOut signal clock period width. result output busses (an, valid while rdyOut signal active. next ldData signal immediately follow rdyOut signal. Obviously valid, fresh input data, shown In1, must ready then. cycle CORDIC computation (iterations clock cycles.
v2.0
CoreCORDIC CORDIC Generator
Signal clkEn manipulated desired. While this signal low, CORDIC engine retains data collected processed far. example, word-serial CORDIC engine used fill power-on event. Once CORDIC completes task, high-level state machine disable clkEn signal.
CORDIC Cycle
IdData
rdyOut
Figure Word-Serial Architecture Timing Diagram
Out0
Parallel Architecture Interface Timing
Figure depicts timing diagram parallel architecture. beginning every clock cycle, fresh input arguments enters CORDIC engine. control signals accompany input data. CORDIC engine puts results beginning every clock cycle with latency iterations clock cycles. Signal synchronously resets parallel architecture; i.e., resets registers parallel engine.
CORDIC Latency
Figure Parallel Architecture Timing Diagram
Out0 Out1 Out2 Out3
References
J.E. Volder. 1959. "The CORDIC Trigonometric Computing Technique." Transaction Electronic Computers, EC8:330-334. Andraka, Survey CORDIC Algorithms FPGA Based Computers," 1998. Norbert Lindlbauer, "The CORDIC-Algorithm Computing Sine," node4.html, 2000. Grant Griffin, "CORDIC FAQ,"
v2.0
CoreCORDIC CORDIC Generator
Sample Configuration File
following example configuration file: module_name architecture mode bit_width iterations fpga_family lang Cordic_test verilog
Ordering Information
Order CoreCORDIC through your local Actel sales representative. following numbering convention when ordering: CoreCORDIC-XX, where listed Table
Table Ordering Codes Description Evaluation version unlimited Actel devices unlimited restricted Actel devices
Datasheet Categories
order provide latest information designers, some datasheets published before data been fully characterized. Datasheets designated "Product Brief," "Advanced," "Production." definitions these categories follows:
Product Brief
product brief summarized version advanced production datasheet containing general product information. This brief summarizes specific device family information unreleased products.
Advanced
This datasheet version contains initial estimated information based simulation, other products, devices, speed grades. This information used estimates, production.
Unmarked (production)
This datasheet version contains information that considered final.
v2.0
CoreCORDIC CORDIC Generator
Appendix
Polar Rectangular Coordinate Relations
Figure Cartesian Coordinate Definition
Cartesian coordinates defined terms polar coordinates (vector magnitude, radial coordinate) (vector phase, polar angle), given
terms Cartesian coordinates, polar coordinates expressed given
arctan
v2.0
CoreCORDIC CORDIC Generator
Appendix
Examples CORDIC Modes
CORDIC engine rotation mode. Input data represent magnitude phase vector whose polar coordinates converted Cartesian coordinates. CORDIC engine puts pair Cartesian coordinates (X*K, Y*K) scaled processing gain (Figure 12).
Polar Cartesian Coordinate Conversion
Polar Cartesian
Figure Polar Cartesian Vector Conversion
General Rotation
CORDIC engine rotation mode. Input data Angle) represent initial vector Cartesian coordinates, well angle rotate vector. CORDIC engine puts pair Cartesian coordinates (X*K, Y*K) resulting rotated vector scaled processing gain (Figure 13).
General Rotation
Angle Rotate
Figure CORDIC General Vector Rotation
v2.0
CoreCORDIC CORDIC Generator
CORDIC engine rotation mode. Input data phase represent initial vector polar coordinates. CORDIC engine puts pair Cartesian coordinates equal (cos, shown Figure
Sine Cosine CORDIC Calculator
Sin/Cos
Figure Sine Cosine CORDIC Computation
Cartesian Polar Coordinate Conversion
CORDIC engine vectoring mode. Input data represent Cartesian coordinates (X0, input vector. CORDIC engine puts pair polar coordinates: magnitude phase input vector (Figure 15).
Cartesian Polar
Figure Cartesian Polar Coordinate Conversion
v2.0
CoreCORDIC CORDIC Generator
CORDIC Square Root Calculator
CORDIC engine vectoring mode. Input data represent Cartesian coordinates (X0, input vector. CORDIC engine puts pair polar coordinates: magnitude (Figure 16).
phase
input vector
Square Root Calculator
Figure CORDIC Square Root Calculator
CORDIC Arctan Calculator
CORDIC engine vectoring mode. Input data represent Cartesian coordinates (X0, input vector. CORDIC engine puts pair polar coordinates: magnitude phase arctan(Y0 input vector.
Arctan Calculator
arctan(Y0/X0)
Figure CORDIC Arctan Phase Calculator
v2.0
Actel Actel logo registered trademarks Actel Corporation. other trademarks property their owners.
www.actel.com
Actel Corporation 2061 Stierlin Court Mountain View, 94043-4655 Phone 650.318.4200 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Camberley, Surrey GU15 United Kingdom Phone 1276 1276 Actel Japan www.jp.actel.com EXOS Ebisu Bldg. 1-24-14 Ebisu Shibuya-ku Tokyo Japan Phone +81.03.3445.7671 +81.03.3445.7668 Actel Hong Kong www.actel.com.cn Suite 2114, Pacific Place Queensway, Admiralty Hong Kong Phone +852 2185 6460 +852 2185 6488
51700064-0/3.06
Other recent searches
SPX2931 - SPX2931 SPX2931 Datasheet
SCS202PF - SCS202PF SCS202PF Datasheet
NDV8501 - NDV8501 NDV8501 Datasheet
MPC560xS - MPC560xS MPC560xS Datasheet
FR301 - FR301 FR301 Datasheet
FR307 - FR307 FR307 Datasheet
FFPF04U40S - FFPF04U40S FFPF04U40S Datasheet
C503D-WAN - C503D-WAN C503D-WAN Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
