RadTolerant Family Tested Total Ionizing Dose (TID) Survivability
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Family FPGAs RadTolerant HiRel
RadTolerant Family
Tested Total Ionizing Dose (TID) Survivability Level Radiation Performance Krads (Si) (ICC Standby Parametric) Devices Available from Tested Pedigreed Lots On-Chip Performance Offered Class E-Flow (Actel Space Level Flow) Certified Devices
High Density Devices
16,000 32,000 Available Logic Gates User I/Os 1,080 Dedicated Flip-Flops
Easy Logic Integration
Nonvolatile, User Programmable Highly Predictable Performance with 100% Automatic Place-and-Route 100% Resource Utilization with 100% Locking Mixed Voltage Support Operation with Input Tolerance Low-Power Operation JTAG Boundary Scan Testing Compliance with IEEE Standard 1149.1 Secure Programming Technology Prevents Reverse Engineering Design Theft Permanently Programmed Operation PowerUp Unique In-System Diagnostic Debug Facility with Silicon Explorer Software Design Support with Actel Designer Libero® Integrated Design Environment (IDE) Tools Predictable, Reliable, Permanent Antifuse Technology Performance
HiRel Family
Fastest HiRel FPGA Family Available On-Chip Performance Cost Prototyping Vehicle RadTolerant Devices Offered Commercial Military Temperature Tested Class Cost Effective MIL-Temp Plastic Packaging Options Standard Hermetic Packaging Offerings Certified Devices
Product Profile
Device Capacity System Gates Logic Gates Logic Modules Register Cells Combinatorial Cells User I/Os (Maximum) JTAG Packages count) CQFP RT54SX16 (Obsolete) 24,000 16,000 1,452 208, A54SX16 24,000 16,000 1,452 208, RT54SX32 (Obsolete) 48,000 32,000 2,880 1,080 1,800 208, A54SX32 48,000 32,000 2,880 1,080 1,800 208,
March 2005 2005 Actel Corporation
Actel's website latest version datasheet.
Family FPGAs RadTolerant HiRel
Ordering Information
RT54SX32 Application (Temperature Range) Blank Commercial +70°C) Military (-55 +125°C) MIL-STD-883 E-Flow (Actel Space Level Flow) Package Lead Count Package Type Ceramic Quad Flat Pack Speed Grade Blank Standard Speed Approximately Faster than Standard Part Number A54SX16 16,000 System Gates A54SX32 32,000 System Gates RT54SX16 16,000 System Gates RadTolerant (Obsolete) RT54SX32 32,000 System Gates RadTolerant (Obsolete)
Product Plan
Speed Grade RT54SX16 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) A54SX16 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) RT54SX32 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) A54SX32 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) Applications: Commercial Military MIL-STD-883 E-flow (Actel Space Level Flow) Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Application Obsolete Obsolete Obsolete Obsolete *Speed Grade: Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete
Availability: Available Planned Planned
Approx. faster than Standard
Ceramic Device Resources
User I/Os Device RT54SX16 A54SX16 RT54SX32 A54SX32 Note: Contact your Actel sales representative product availability. CQFP 208-Pin CQFP 256-Pin
Family FPGAs RadTolerant HiRel
Table Contents
Family FPGAs RadTolerant HiRel
General Description Family Architecture Other Architecture Development Tool Support 1-10 RTSX Probe Circuit Control Pins 1-10 Design Considerations 1-11 Related Documents 1-11 Operating Conditions 1-12 Electrical Specifications 1-13 Power-Up Sequencing 1-13 Power-Down Sequencing 1-13 Package Thermal Characteristics 1-14 Power Dissipation 1-15 Temperature Voltage Derating Factors 1-17 Timing Model 1-17 Timing Characteristics 1-19 A54SX16 Timing Characteristics 1-20 RT54SX16 Timing Characteristics 1-22 A54SX32 Timing Characteristics 1-24 RT54SX32 Timing Characteristics 1-26 Description 1-28
Package Assignments
208-Pin CQFP 256-Pin CQFP
Datasheet Information
List Changes Datasheet Categories Export Administration Regulations (EAR)
Family FPGAs RadTolerant HiRel
Family FPGAs RadTolerant HiRel
General Description
Actel RadTolerant (RT) HiRel versions Family FPGAs offer many advantages applications such commercial military satellites, deep space probes, types military high reliability equipment. HiRel versions fully pin-compatible, allowing designs migrate across different applications that have radiation requirements. Also, HiRel devices used cost prototyping tool designs. programmable architecture these devices offers high performance, design flexibility, fast inexpensive prototyping-all without expense test vectors, charges, long lead times, schedule cost penalties design modifications required ASIC devices.
Radiation Survivability
Total dose results summarized ways. First, maximum total dose level that reached when parts fail meet device specification remain functional. Actel FPGAs, parameter that exceeds specification first ICC, standby supply current. Second, maximum total dose that reached prior functional failure device. RTSX devices have varying total dose radiation survivability. ability these devices survive radiation effects both device- lot-dependent. customer must evaluate determine applicability these devices their specific design environmental requirements. Actel will provide total dose radiation testing data along with test data each pedigreed available sale. These reports available Actel website, contact your local sales representative receive copy. listing available lots devices will also provided. These results only provided reference customer information. radiation performance summary, Radiation Performance Actel Products. This summary will also show single event upset (SEU) single event latch-up (SEL) testing that been performed Actel FPGAs.
Device Description
RT54SX16 A54SX16 devices have 16,000 available gates I/Os. RT54SX32 A54SX32 have 32,000 available gates I/Os. these devices support JTAG boundary scan testability. these devices available Ceramic Quad Flat Pack (CQFP) packaging, with 208-pin 256-pin versions. 256-pin version offers user highest capability, while 208-pin version offers compatibility with commercial Plastic Quad Flat Pack (PQFP-208). This compatibility allows user prototype using very cost plastic package then switch ceramic package production. more information plastic packages, refer 54SX Family FPGAs datasheet. A54SX16 A54SX32 devices manufactured using 0.35 technology Chartered Semiconductor facility Singapore. These devices offer highest speed performance available FPGAs today. RT54SX16 RT54SX32 devices manufactured using technology Matsushita (MEC) facility Japan. These devices offer levels radiation survivability excess typical CMOS devices.
Certification
Actel achieved full certification, demonstrating that quality management, procedures, processes, controls place comply with MIL-PRF-38535, performance specification used Department Defense monolithic integrated circuits. certification good example Actel's commitment supplying highest quality products types high-reliability, military, space applications. Many suppliers microelectronics components have implemented their primary worldwide business system. Appropriate this system only helps implementation advanced technologies, also allows quality, reliable, cost-effective logistics support throughout life cycles products.
Family FPGAs RadTolerant HiRel
Disclaimer
radiation performance information provided information purposes only guaranteed. total dose effects lot-dependent, Actel does guarantee that future devices will continue exhibit similar radiation characteristics. addition, actual performance vary widely variety factors, including limited characteristics orbit, radiation environment, proximity satellite exterior, amount inherent shielding from other sources within satellite, actual bare variations. these reasons, Actel does guarantee level radiation survivability, solely responsibility customer determine whether device will meet requirements specific design.
Programmable Interconnect Element
Actel's family provides much more efficient silicon locating routing interconnect resources between Metal (M2) Metal (M3) layers (Figure 1-1). This completely eliminates channels routing interconnect resources between logic modules implemented SRAM FPGAs previous generations antifuse FPGAs), enables entire floor device spanned with uninterrupted grid logic modules. Interconnection between these logic modules achieved using Actel's patented metal-to-metal programmable antifuse interconnect elements, which embedded between layers. antifuses normally open circuit and, when programmed, form permanent low-impedance connection. extremely small size these interconnect elements gives family abundant routing resources provides excellent protection against design pirating. Reverse engineering virtually impossible, because extremely difficult distinguish between programmed unprogrammed antifuses, there configuration bitstream intercept. Additionally, interconnects (i.e., antifuses metal tracks) have lower capacitance lower resistance than other device similar capacity, leading fastest signal propagation industry.
Family Architecture
family architecture designed satisfy nextgeneration performance integration requirements production-volume designs broad range applications.
Routing Tracks
Metal Amorphous Silicon/ Dielectric Antifuse Tungsten Plug Metal
Metal Tungsten Plug Contact
Silicon Substrate
Figure Family Interconnect Elements
Family FPGAs RadTolerant HiRel
Logic Module Design
family architecture been called "sea-ofmodules" architecture because entire floor device covered with grid logic modules with virtually chip area lost interconnect elements routing (see Figure 1-2). Actel provides types logic modules, register cell (R-cell) combinatorial cell (C-cell). R-cell contains flip-flop featuring more control signals than previous Actel architectures, including asynchronous clear, asynchronous preset, clock enable (using lines). R-cell registers feature programmable clock polarity, selectable register-by-register basis (Figure page 1-4). This provides designer with additional flexibility while allowing mapping synthesized functions into FPGA. clock source R-cell chosen from hardwired clock routed clock. C-cell implements range combinatorial functions with five inputs (Figure page 1-4). Inclusion input associated inverter function dramatically increases number combinatorial functions that implemented single module from options previous architectures more than 4,000 architecture. example improved flexibility enabled inversion capability ability integrate three-input exclusive-OR function into single C-cell. This facilitates construction ninebit parity-tree functions with propagation delays. same time, C-cell structure extremely synthesisfriendly, simplifying overall design reducing synthesis time.
Channeled Array Architecture
Sea-of-Modules Architecture
Figure Channeled Array Sea-of-Modules Architectures
Family FPGAs RadTolerant HiRel
Routed Data Input PSETB Direct Connect Input
HCLK CLKA CLKB
Figure R-Cell
CLRB
Figure C-Cell
Family FPGAs RadTolerant HiRel
Chip Architecture
family's chip architecture provides unique approach module organization chip routing that delivers best register/logic wide variety emerging applications.
Module Organization
Actel arranged C-cell R-cell logic modules into horizontal banks called Clusters. There types Clusters: Type contains C-cells R-cell, Type contains C-cell R-cells.
increase design efficiency device performance, Actel further organized these modules into SuperClusters (see Figure 1-5). SuperCluster twowide grouping Type Clusters. SuperCluster twowide group containing Type Cluster Type Cluster. devices feature more SuperCluster modules than SuperCluster modules because designers typically require more combinatorial logic than flip-flops.
R-Cell
Routed Data Input PSETB Direct Connect Input
C-Cell
HCLK CLKA CLKB
CLRB
Cluster
Cluster
Cluster
Cluster
Type SuperCluster
Figure Cluster Organization
Type SuperCluster
Family FPGAs RadTolerant HiRel
Routing Resources
Clusters SuperClusters connected through innovative local routing resources called FastConnect DirectConnect that enable extremely fast predictable interconnections modules within Clusters SuperClusters (see Figure Figure page 1-7). This routing architecture also dramatically reduces number antifuses required complete circuit, ensuring highest possible performance. DirectConnect horizontal routing resource that provides connections from C-cell neighboring R-cell given SuperCluster. DirectConnect uses hardwired signal path requiring programmable interconnection achieve fast signal propagation time less than FastConnect enables horizontal routing between logic modules within given SuperCluster, vertical routing SuperCluster immediately below Only programmable connection used FastConnect path, delivering maximum pin-to-pin propagation addition DirectConnect FastConnect, architecture makes globally oriented routing resources known segmented routing high-drive routing. Actel's segmented routing structure provides variety track lengths extremely fast routing between SuperClusters. exact combination track lengths antifuses within each path chosen 100% automatic place-and-route software minimize signal propagation delays.
DirectConnect Antifuses
FastConnect Antifuse
Routing Segments Typically Antifuses Max. Five Antifuses
Type SuperClusters
Figure DirectConnect FastConnect Type SuperClusters
Family FPGAs RadTolerant HiRel
DirectConnect Antifuses
FastConnect Antifuse
Routing Segments Typically Antifuses Max. Five antifuses
Type SuperClusters
Figure DirectConnect FastConnect Type SuperClusters
Clock Resources
Actel's high-drive routing structure provides three clock networks. first clock, called HCLK, hardwired from HCLK buffer clock select each R-cell. HCLK cannot connected combinational logic. This provides fast propagation path clock signal, enabling clock-to-out (pad-to-pad) performance RTSX devices. hardwired clock tuned provide clock skew less than worst case. remaining clocks (CLKA CLKB) global clocks that sourced from external pins from internal logic signals within RTSX device. CLKA CLKB connected sequential cells combinational logic. CLKA CLKB sourced from internal logic signals, then external clock cannot used other input must tied high. Figure describes clock circuit used constant load HCLK. Figure describes CLKA CLKB circuit used RTSX devices with exception RT54SX72S device.
Constant Load Clock Network HCLKBUF
Figure RTSX Constant Load Clock
Clock Network
From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI
Figure RTSX Clock Pads
Family FPGAs RadTolerant HiRel
Other Architecture
Performance
combination architectural features described above enables RT54SX devices operate with internal clock frequencies exceeding MHz, enabling very fast execution complex logic functions. Thus, RTSX family optimal platform upon which integrate functionality previously contained multiple CPLDs. addition, designs that previously would have required gate array meet performance goals integrated into RTSX device with dramatic improvements cost time-to-market. Using timingdriven place-and-route tools, designers achieve highly deterministic device performance. With RTSX devices, there need complicated performance-enhancing design techniques such redundant logic reduce fanout critical nets, instantiation macros code achieve high performance.
Power Requirements
RTSX family supports either voltage operation designed tolerate inputs each case (Table 1-1). Power consumption extremely very short distances signals required travel complete circuit. Power requirements further reduced small number antifuses path, because resistance properties antifuses. antifuse architecture does require active circuitry hold charge SRAM EPROM), making lowest-power architecture market.
Table Supply Voltages Maximum Maximum Input Output Tolerance Drive
VCCA A54SX16 A54SX32 RTSX16 RTSX32
VCCI
VCCR
Modules
Each RTSX device configured input, output, tristate output, bidirectional pin. Even without inclusion dedicated registers, these I/Os, combination with array registers, achieve clock-to-out (PAD-to-PAD) timing fast cells including embedded latches flip-flops require instantiation code. This design complication encountered RTSX FPGAs. Fast PAD-to-PAD timing ensures that device will have little trouble interfacing with other device system, which turn enables parallel design system components reduces overall design time.
Boundary Scan Testing (BST)
RTSX devices IEEE 1149.1 (JTAG) compliant. They offer superior diagnostic testing capabilities providing probing capabilities. These functions controlled through special test pins conjunction with program fuse. functionality each described Table 1-2. Figure 1-10 page block diagram RTSX JTAG circuitry.
Table Boundary Scan Functionality Program Fuse Blown (Dedicated Test Mode) Program Fuse Blown (Flexible Mode)
TCK, TDI, dedicated TCK, TDI, flexible test pins used I/Os need pull-up resistor pull-up resistor
Family FPGAs RadTolerant HiRel
Data Registers (DRs)
Instruction Register (IR)
Output Stage
Clocks and/or Controls
TRST External Hardwired
Figure 1-10 RTSX JTAG Circuitry
Controller
Configuring Diagnostic Pins
JTAG Probe pins (TDI, TCK, TMS, TDO, PRA, PRB) placed desired mode selecting appropriate check boxes Variation dialog window. This dialog window accessible through Design Setup Wizard under Tools menu Actel Designer software.
Dedicated Test Mode
When Reserve JTAG check selected Designer software, RTSX placed Dedicated Test mode, which configures TDI, TCK, pins in-circuit verification with Silicon Explorer internal pull-up resistor automatically enabled both pins. dedicated test mode, TCK, TDI, dedicated test pins become unavailable assignment Editor. will function specified IEEE 1149.1 (JTAG) Specification.
TRST
TRST functions Boundary Scan Reset pin. TRST asynchronous, active-low input initialize reset circuit. internal pull-up resistor automatically enabled TRST pin.
Family FPGAs RadTolerant HiRel
Flexible Mode
When Reserve JTAG check cleared (the default setting Designer software), RTSX placed flexible mode, which allows TDI, TCK, pins function user I/Os pins. this mode internal pull-up resistors pins disabled. external pull-up resistor VCCI required pin. TDI, TCK, pins transformed from user I/Os into pins when rising edge detected while logical low. Once pins test mode they will remain mode until internal state machine reaches "logic reset" state. this point pins will released will function regular pins. "logic reset" state reached five cycles after logical HIGH. program fuse determines whether device Dedicated Test Flexible mode. default (fuse programmed) Flexible mode.
Actel Designer software place-and-route tool provides comprehensive suite back-end support tools FPGA development. Designer software includes timing-driven place-and-route world-class integrated static timing analyzer constraints editor. With Designer software, user lock his/her design pins before layout while minimally impacting results place-and-route. Additionally, backannotation flow compatible with major simulators simulation results cross-probed with Silicon Explorer Actel integrated verification logic analysis tool. Another tool included Designer software ACTgen macro builder, which easily creates popular commonly used logic functions implementation your schematic design. Actel Designer software compatible with most popular FPGA design entry verification tools from companies such Mentor Graphics, Synplicity, Synopsys, Cadence Design Systems. Designer software available both Windows UNIX
operating systems.
Development Tool Support
RTSX family FPGAs fully supported both Actel Libero® Integrated Design Environment (IDE) Designer FPGA Development software. Actel Libero design management environment that streamlines design flow. Libero provides integrated design manager that seamlessly integrates design tools while guiding user through design flow, managing design files, passing necessary design data among tools. Additionally, Libero allows users integrate both schematic synthesis into single flow verify entire design single environment. Libero includes Synplify® Actel from Synplicity®, ViewDraw® Actel from Mentor Graphics®, ModelSimHDL Simulator from Mentor Graphics, WaveFormer Litefrom SynaptiCADTM, Designer software from Actel. Refer Libero Design Flow (located Actel website) diagram more information.
RTSX Probe Circuit Control Pins
RTSX RadTolerant devices contain internal probing circuitry that provides built-in access every node design, enabling 100-percent real-time observation analysis device's internal logic nodes without design iteration. probe circuitry accessed using Silicon Explorer easy-to-use integrated verification logic analysis tool that sample data (asynchronous) (synchronous). Silicon Explorer attaches PC's standard port, turning into fully functional 18-channel logic analyzer. Silicon Explorer allows designers complete design verification process their desks reduces verification time from several hours cycle seconds. Silicon Explorer tool uses boundary scan ports (TDI, TRST, TCK, TMS, TDO) select desired nets verification. selected internal nets assigned PRA/PRB pins observation. Figure 1-11 page 1-11 illustrates interconnection between Silicon Explorer FPGA perform in-circuit verification.
Family FPGAs RadTolerant HiRel
Design Considerations
prototyping, TDI, TCK, TDO, PRA, pins should used input bidirectional ports. Because these pins active during probing, critical signals input through these pins available while probing. addition, security fuse should programmed during prototyping because doing disables probe circuitry.
Channels
RTSX-S FPGA TRST Serial Connection Silicon Explorer
Figure 1-11 Probe Setup
Related Documents
Datasheets
54SX Family FPGAs
Application Notes
Power-Up Power-Down Behavior 54SX RT54SX Devices
1-11
Family FPGAs RadTolerant HiRel
Operating Conditions
Recommended Operating Conditions
Table Absolute Maximum Ratings Symbol VCCR VCCA VCCI TSTG Notes: Stresses beyond those listed Table cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Device should operated outside Recommended Operating Conditions. source sink numbers refer tristated inputs outputs Table Recommended Operating Conditions Parameter Temperature Range1 Commercial Military +125 Units %VCC %VCC Supply Voltage Supply Voltage Supply Voltage Input Voltage Output Voltage Source Sink Current2 Storage Temperature +125 Parameter Limits -0.3 +6.0 -0.3 +4.0 -0.3 +4.0 -0.5 +5.5 -0.5 +3.6 +5.0 Units
Power2 Supply Tolerance Power Supply Tolerance Notes:
Ambient temperature (TA) used commercial industrial; case temperature (TC) used military. power supplies must recommended operating range more information, refer Power-Up Power-Down Behavior 54SX RT54SX Devices application note.
Family FPGAs RadTolerant HiRel
Electrical Specifications
Table Electrical Specifications Commercial Symbol Parameter (IOH (CMOS) (IOH (TTL) (IOH (TTL) (IOL (CMOS) (IOL (TTL) (IOL (TTL) ICC(D) Level Inputs High Level Inputs Input Transition Time Capacitance Standby Current, ICC(D) IDynamic Supply Current 0.10 0.50 0.50 Min. (VCCI 0.1) Max. VCCI VCCI VCCI Military Min. (VCCI 0.1) Max. VCCI Units
"Power Dissipation" section page 1-15.
Power-Up Sequencing
Table RT54SX16, A54SX16, RT54SX32, A54SX32 VCCA VCCR VCCI Power-Up Sequence First Second First Second Comments possible damage device Possible damage device
Power-Down Sequencing
Table RT54SX16, A54SX16, RT54SX32, A54SX32 VCCA VCCR VCCI Power-Down Sequence First Second First Second Comments Possible damage device possible damage device
1-13
Family FPGAs RadTolerant HiRel
Package Thermal Characteristics
device junction-to-case thermal characteristic junction-to-ambient characteristic thermal characteristics shown with different flow rates. Maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed RT54SX16 CQFP 256-pin package military temperature still shown 1-1: Max. junction temp. (°C) Max. ambient temp. (°C) 150°C 125°C Absolute Maximum Power Allowed 1.09 (°C/W) 23°C/W
Table Package Thermal Characteristics Package Type RT54SX16 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) RT54SX32 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) A54SX16 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) A54SX32 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Count Still Units
Family FPGAs RadTolerant HiRel
Power Dissipation
(ICCstandby ICCactive) VCCA (VCCA VOH)
Active Power Component
Power dissipation CMOS devices usually dominated active (dynamic) power dissipation. This component frequency-dependent, function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnects, unprogrammed antifuses, module inputs, module outputs, plus external capacitance traces load device inputs. additional component active power dissipation totem pole current CMOS transistor pairs. effect associated with equivalent capacitance that combined with frequency voltage represent active power dissipation.
where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. number outputs driving loads VOL. number outputs driving loads VOH. Accurate values difficult determine because they depend design system I/O. power divided into components: static active.
Equivalent Capacitance
power dissipated CMOS circuit expressed 1-3: Power (µW) VCCA2
Static Power Component
Power consumption standby current typically small component total power consumption. Standby power shown below military, worst-case conditions (70°C). Power
where: VCCA Equivalent capacitance Power supply volts Switching frequency
Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements have been made over range frequencies fixed value VCCA. Equivalent capacitance frequency-independent that results used over wide range operating conditions. Equivalent capacitance values shown Table 1-9.
Table Equivalent Capacitance Values RT54SX16 Equivalent Capacitance (pF) Modules Input Buffers Output Buffers Routed Array Clock Buffer Loads Dedicated Clock Buffer Loads Fixed Capacitance (pF) routed_Clk1 routed_Clk2 Fixed Clock Loads Clock Loads Dedicated Array Clock 1,080 1,080 CEQM CEQI CEQO CEQCR CEQCD 10.0 0.25 0.15 10.0 0.34 0.23 A54SX16 RT54SX32 A54SX32
1-15
Family FPGAs RadTolerant HiRel
Values (pF)
calculate active power dissipated complete design, switching frequency each part logic must known. shows piecewise linear summation over components. Power VCCA2 CEQM fm)modules CEQI fn)inputs+ (CEQO fp)outputs+ CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR fq2)routed_Clk2+ fq2)routed_Clk2 CEQCD fs1)dedicated_CLK]
Determining Average Switching Frequency
determine switching frequency design, must have detailed understanding data input values circuit. following guidelines meant represent worst-case scenarios they generally used predict upper limits power dissipation. Logic Modules Inputs Switching Outputs Switching modules inputs/4 output/4 sequential modules sequential modules F/10 F/10
where: CEQM CEQI CEQO CEQCR CEQCD Number logic modules switching Number input buffers switching Number output buffers switching Number clock loads first routed array clock Number clock loads second routed array clock Fixed capacitance first routed array clock Fixed capacitance second routed array clock Fixed number clock loads dedicated array clock (528 A54SX16) Equivalent capacitance logic modules Equivalent capacitance input buffers Equivalent capacitance output buffers Equivalent capacitance routed array clock Equivalent capacitance dedicated array clock Output lead capacitance Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate
First Routed Array Clock Loads (q1) Second Routed Array Clock Loads (q2) Load Capacitance (CL) Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp) Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2) Average Dedicated Array Clock Rate (fs1)
Family FPGAs RadTolerant HiRel
Temperature Voltage Derating Factors
Table 1-10 Temperature Voltage Derating Factors (Normalized Worst-Case Commercial, 70°C, VCCA Junction Temperature (TJ) VCCA 0.78 0.73 0.69 0.87 0.82 0.77 0.89 0.83 0.78 1.00 0.93 0.87 1.04 0.97 0.92 1.16 1.08 1.02
Timing Model
Input Delays Module tIRD2 tDHL tRD1 tRD4 tRD8 Internal Delays Combinatorial Cell Predicted Routing Delays Output Delays Module
Module tDLH
Register Cell
Register Cell
tSUD
tRD1
tRD1
tENZH
Routed Clock
tRCO tRCKH (100% Load) FMAX
tRCO
Hardwired Clock
tHCKH FHMAX
Note: Values shown A54SX16-1 worst-case commercial conditions. Figure 1-12 Timing Model
Hardwired Clock
External Setup Clock-to-Out (Pin-to-Pin) tINY tIRD1 tSUD tHCKH tHCKH tRCO tRD1 tDHL
Routed Clock
External Setup Clock-to-Out (Pin-to-Pin)
tINY tIRD1 tSUD tRCKH tRCKH tRCO tRD1 tDHL
1-17
Family FPGAs RadTolerant HiRel
TRIBUFF Test Loads (shown below)
tDLH tDHL
tENZL tENLZ
tENZH
tENHZ
Figure 1-13 Output Buffer Delays
Load (Used measure propagation delay) Output Under Test Output Under Test Load (Used Measure rising/falling delays)
tPLZ/tPZL tPHZ/tPZL
Figure 1-14 Test Loads
INBUF
tINY tINY
Figure 1-15 Input Buffer Delays
Figure 1-16 C-Cell Delays
Family FPGAs RadTolerant HiRel
PRESET
(Positive Edge Triggered)
tSUD tHPWH' tRPWH tHPWL' tRPWL
tRCO
tCLR tWASYN PRESET
tPRESET
Figure 1-17 Register Cell Timing Characteristics Flip-Flops
Timing Characteristics
Timing characteristics devices fall into three categories: family-dependent, device-dependent, design-dependent. input output buffer characteristics common family members. Internal routing delays device-dependent. Design dependence means actual delays determined until after placement routing user's design complete. Delay values then determined using Timer tool performing simulation with post-layout delays.
Long Tracks
Some nets design long tracks. Long tracks special routing resources that span multiple rows, columns, modules. Long tracks employ three sometimes five antifuse connections. This increases capacitance resistance, resulting longer delays macros connected long tracks. Typically percent nets fully utilized device require long tracks. Long tracks contribute approximately delay. This additional delay represented statistically higher fanout routing delays data sheet specifications section.
Critical Nets Typical Nets
Propagation delays expressed only typical nets, which used initial design performance evaluation. Critical delays then applied most timecritical paths. Critical nets determined property assignment prior placement routing. percent nets design designated critical, whereas percent nets design typical.
Timing Derating
devices manufactured CMOS process. Therefore, device performance varies according temperature, voltage, process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, worst-case processing.
1-19
Family FPGAs RadTolerant HiRel
A54SX16 Timing Characteristics
Table 1-11 A54SX16 (Worst-Case Military Conditions, VCCR 4.75 VCCA, VCCI 125°C) '-1' Speed Parameter C-Cell Propagation tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 tRD18 tRD24 R-Cell Timing tRCO tCLR tSUD tWASYN tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 tIRD18 tIRD24 Notes: dual-module macros, tRD1 tPDn, tRCO tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Sequential Clock-to-Q Asynchronous Clear-to-Q Flip-Flop Data Input Setup Flip-Flop Data Input Hold Asynchronous Pulse Width Delays1 Description Min. Max. 'Std' Speed Min. Max. Units
Internal Array Module Delays2
Predicted Routing
Routing Delay, Direct Connect Routing Delay, Fast Connect Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay
12.4
11.0 14.6
Module Input Propagation Delays Input Data Pad-to-Y HIGH Input Data Pad-to-Y Delays2 12.4 11.0 14.6
Predicted Input Routing
Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay
Family FPGAs RadTolerant HiRel
Table 1-12 A54SX16 (Worst-Case Military Conditions, VCCR 4.75 VCCA, VCCI 125°C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units
Module Output Timing* tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, HIGH Enable-to-Pad, Enable-to-Pad, HIGH Delta HIGH Delta HIGH 0.05 0.05 0.06 0.08 ns/pF ns/pF
Dedicated (Hardwired) Array Clock Network Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Note: *Delays based loading, except tENZL tENZH. tENZL tENZH, loading
1-21
Family FPGAs RadTolerant HiRel
RT54SX16 Timing Characteristics
Table 1-13 RT54SX16 (Worst-Case Military Conditions, VCCR 4.75 VCCA, VCCI 125°C) '-1' Speed Parameter C-Cell Propagation tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 tRD18 tRD24 R-Cell Timing tRCO tCLR tSUD tWASYN tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 tIRD18 tIRD24 Notes: dual-module macros, tRD1 tPDn, tRCO tRD1 tPDn tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Sequential Clock-to-Q Asynchronous Clear-to-Q Flip-Flop Data Input Setup Flip-Flop Data Input Hold Asynchronous Pulse Width Delays1 Description Min. Max. 'Std' Speed Min. Max. Units
Internal Array Module Delays2
Predicted Routing
Routing Delay, Direct Connect Routing Delay, Fast Connect Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay
10.1 17.0 22.4
11.9 19.8 26.3
Module Input Propagation Delays Input Data Pad-to-Y HIGH Input Data Pad-to-Y Delays2 10.1 17.0 22.4 11.9 19.8 26.3
Predicted Input Routing
Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay
Family FPGAs RadTolerant HiRel
Table 1-14 RT54SX16 (Worst-Case Military Conditions, VCCR 4.75 VCCA, VCCI 125°C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units
Module Output Timing* tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, HIGH Enable-to-Pad, Enable-to-Pad, HIGH Delta HIGH Delta HIGH 0.09 0.09 0.11 0.15 ns/pF ns/pF
Dedicated (Hardwired) Array Clock Network Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Note: *Delays based loading, except tENZL tENZH. tENZL tENZH loading
1-23
Family FPGAs RadTolerant HiRel
A54SX32 Timing Characteristics
Table 1-15 A54SX32 Timing Characteristics (Worst-Case Military Conditions, VCCR 4.75 VCCA, VCCI 125°C) '-1' Speed Parameter C-Cell Propagation tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 tRD18 tRD24 R-Cell Timing tRCO tCLR tSUD tWASYN tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 tIRD18 tIRD24 Notes: dual-module macros, tRD1 tPDn, tRCO tRD1 tPDn tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Sequential Clock-to-Q Asynchronous Clear-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Delays1 Description Min. Max. 'Std' Speed Min. Max. Units
Internal Array Module Delays2
Predicted Routing
Routing Delay, Direct Connect Routing Delay, Fast Connect Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay
12.4
11.0 14.6
Module Input Propagation Delays Input Data Pad-to-Y HIGH Input Data Pad-to-Y Delays2 12.4 11.0 14.6
Predicted Input Routing
Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay
Family FPGAs RadTolerant HiRel
Table 1-16 A54SX32 Timing Characteristics (Worst-Case Military Conditions, VCCR 4.75 VCCA, VCCI 125°C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units
Module Output Timing* tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, HIGH Enable-to-Pad, Enable-to-Pad, HIGH Delta HIGH Delta HIGH 0.05 0.05 0.06 0.08 ns/pF ns/pF
Dedicated (Hardwired) Array Clock Network Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Note: *Delays based loading, except tENZL tENZH. tENZL tENZH loading
1-25
Family FPGAs RadTolerant HiRel
RT54SX32 Timing Characteristics
Table 1-17 RT54SX32 Timing Characteristics (Worst-Case Military Conditions, VCCR 4.75 VCCA, VCCI 125°C) '-1' Speed Parameter C-Cell Propagation tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 tRD18 tRD24 R-Cell Timing tRCO tCLR tSUD tWASYN tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 tIRD18 tIRD24 Notes: dual-module macros, tRD1 tPDn, tRCO tRD1 tPDn tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Sequential Clock-to-Q Asynchronous Clear-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Delays1 Description Min. Max. 'Std' Speed Min. Max. Units
Internal Array Module Delays2
Predicted Routing
Routing Delay, Direct Connect Routing Delay, Fast Connect Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay
10.1 17.0 22.4
11.9 19.8 26.3
Module Input Propagation Delays Input Data Pad-to-Y HIGH Input Data Pad-to-Y Delays2 10.1 17.0 22.4 11.9 19.8 26.3
Predicted Input Routing
Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay Routing Delay
Family FPGAs RadTolerant HiRel
Table 1-18 RT54SX32 Timing Characteristics (Worst-Case Military Conditions, VCCR 4.75 VCCA, VCCI 125°C) '-1' Speed Parameter Description Min. Max. 'Std' Speed Min. Max. Units
Module Output Timing* tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, HIGH Enable-to-Pad, Enable-to-Pad, HIGH Delta HIGH Delta HIGH 0.09 0.09 0.11 0.15 ns/pF ns/pF
Dedicated (Hardwired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width
Note: *Delays based loading, except tENZL tENZH. tENZL tENZH loading
1-27
Family FPGAs RadTolerant HiRel
Description
CLKA/B Clock TDI, Test Data Input
These pins clock inputs clock distribution networks. Input levels compatible with standard TTL, LVTTL, PCI, specifications. clock input buffered prior clocking R-cells. used, this must HIGH board. must left floating. (For RT54SX72S, these clocks configured user I/O.)
Ground
Serial input boundary scan testing diagnostic probe. flexible mode, active when (refer Table page 1-8). This functions when boundary scan state machine reaches "logic reset" state.
TDO, Test Data Output
supply voltage.
HCLK Dedicated (Hardwired) Array Clock
Serial output boundary scan testing. flexible mode, active when (refer Table page 1-8). This functions when boundary scan state machine reaches "logic reset" state.
Test Mode Select
This clock input sequential modules. Input levels compatible with standard TTL, LVTTL, specifications. This input directly wired each R-cell offers clock speeds independent number R-cells being driven. used, this must HIGH board. must left floating.
Input/Output
functions input, output, tristate, bidirectional buffer. Based certain configurations, input output levels compatible with standard TTL, LVTTL, PCI, specifications. Unused pins automatically tristated Designer software.
Connection
controls IEEE 1149.1 boundary scan pins (TCK, TDI, TDO, TRST). flexible mode, when LOW, TCK, TDI, pins boundary scan pins (refer Table page 1-8). Once boundary scan pins test mode, they will remain that mode until internal boundary scan state machine reaches "logic reset" state. this point, boundary scan pins will released will function regular pins. "logic reset" state reached five cycles after HIGH. dedicated test mode, functions specified IEEE 1149.1 specifications.
TRST, Boundary Scan Reset
This connected circuitry within device. These pins driven voltage left floating with effect operation device.
PRA, I/O, Probe PRB,
Probe used output data from userdefined design node within device. This independent diagnostic used conjunction with other probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality.
TCK, Test Clock (Input)
Once configured JTAG Reset pin, TRST functions active-low input asynchronously initialize reset boundary scan circuit. TRST equipped with internal pull-up resistor. This functions when Reserve JTAG Reset check cleared Designer.
VCCI Supply Voltage
Supply voltage I/Os. Table page 1-8.
VCCA Supply Voltage
Supply voltage Array. Table page 1-8.
VCCR Supply Voltage
Supply voltage input tolerance (required internal biasing). Table page 1-8.
Test clock input diagnostic probe device programming. flexible mode, becomes active when (see Table page 1-8). This functions when JTAG state machine reaches "logic reset" state.
Family FPGAs RadTolerant HiRel
Package Assignments
208-Pin CQFP
Index
208-Pin CQFP
Figure 208-Pin CQFP (Top View)
Family FPGAs RadTolerant HiRel
208-Pin CQFP A54SX16 Number Function Notes: RT54SX16 RT54SX32-CQ208 TRST pin. A54SX32 RT54SX32-CQ208 Connect. TDI, VCCI VCCR VCCA RT54SX16 Function TDI, VCCI VCCR VCCA TRST A54SX32 RT54SX32 Function Function TDI, VCCI VCCR VCCA TDI, VCCI VCCR VCCA TRST A54SX16 Number Function VCCI VCCA VCCI
208-Pin CQFP RT54SX16 Function VCCI VCCA VCCI A54SX32 RT54SX32 Function Function VCCI VCCA VCCI VCCI VCCA VCCI
Family FPGAs RadTolerant HiRel
208-Pin CQFP A54SX16 Number Function Notes: PRB, VCCA VCCR HCLK VCCI TDO, RT54SX16 Function PRB, VCCA VCCR HCLK VCCI TDO, A54SX32 RT54SX32 Function Function PRB, VCCA VCCR HCLK VCCI TDO, PRB, VCCA VCCR HCLK VCCI TDO, A54SX16 Number Function VCCA VCCI VCCA VCCR
208-Pin CQFP RT54SX16 Function VCCA VCCI VCCA VCCR A54SX32 RT54SX32 Function Function VCCA VCCI VCCA VCCR VCCA VCCI VCCA VCCR
RT54SX16 RT54SX32-CQ208 TRST pin. A54SX32 RT54SX32-CQ208 Connect.
Family FPGAs RadTolerant HiRel
208-Pin CQFP A54SX16 Number Function Notes: VCCA VCCI VCCI CLKA RT54SX16 Function VCCA VCCI VCCI CLKA A54SX32 RT54SX32 Function Function VCCA VCCI VCCI CLKA VCCA VCCI VCCI CLKA A54SX16 Number Function CLKB VCCR VCCA PRA, VCCI TCK,
208-Pin CQFP RT54SX16 Function CLKB VCCR VCCA PRA, VCCI TCK, A54SX32 RT54SX32 Function Function CLKB VCCR VCCA PRA, VCCI TCK, CLKB VCCR VCCA PRA, VCCI TCK,
RT54SX16 RT54SX32-CQ208 TRST pin. A54SX32 RT54SX32-CQ208 Connect.
Family FPGAs RadTolerant HiRel
256-Pin CQFP
Index
256-Pin CQFP
Figure 256-Pin CQFP (Top View)
Family FPGAs RadTolerant HiRel
256-Pin CQFP Number A54SX16 Function TDI, VCCI VCCA RT54SX16 Function TDI, VCCI VCCA TRST A54SX32 Function TDI, VCCI VCCA RT54SX32 Function TDI, VCCI VCCA TRST Number A54SX16 Function VCCA
256-Pin CQFP RT54SX16 Function VCCA A54SX32 Function VCCA RT54SX32 Function VCCA
Note: RT54SX16 RT54SX32-CQ256 TRST pin.
Family FPGAs RadTolerant HiRel
256-Pin CQFP Number A54SX16 Function PRB, VCCI VCCA HCLK RT54SX16 Function PRB, VCCI VCCA HCLK A54SX32 Function PRB, VCCI VCCA HCLK RT54SX32 Function PRB, VCCI VCCA HCLK Number A54SX16 Function TDO, VCCA
256-Pin CQFP RT54SX16 Function TDO, VCCA A54SX32 Function TDO, VCCA RT54SX32 Function TDO, VCCA
Note: RT54SX16 RT54SX32-CQ256 TRST pin.
Family FPGAs RadTolerant HiRel
256-Pin CQFP Number A54SX16 Function VCCR VCCI VCCA RT54SX16 Function VCCR VCCI VCCA A54SX32 Function VCCR VCCI VCCA RT54SX32 Function VCCR VCCI VCCA Number A54SX16 Function CLKA CLKB VCCI
256-Pin CQFP RT54SX16 Function CLKA CLKB VCCI A54SX32 Function CLKA CLKB VCCI RT54SX32 Function CLKA CLKB VCCI
Note: RT54SX16 RT54SX32-CQ256 TRST pin.
Family FPGAs RadTolerant HiRel
256-Pin CQFP Number A54SX16 Function VCCR PRA, TCK, RT54SX16 Function VCCR PRA, TCK, A54SX32 Function VCCR PRA, TCK, RT54SX32 Function VCCR PRA, TCK,
Note: RT54SX16 RT54SX32-CQ256 TRST pin.
Family FPGAs RadTolerant HiRel
Datasheet Information
List Changes
following table lists critical changes that were made current version document.
Previous Version Changes Current Version v2.0 "Product Profile" updated. "Ordering Information" updated. "Product Plan" updated. Table updated. Preliminary v1.5 Page
Power-up -down sequencing information modified: damage device possible when powered-up first when powered-down first. last line previous version. been replaced existing version.
Preliminary v1.5.2
User I/Os changed.
following sections were updated: "Clock Resources", "Performance", "I/O Modules", "Power Requirements", "Boundary Scan Testing (BST)","Configuring Diagnostic Pins", "TRST Pin", "Dedicated Test Mode", "Flexible Mode", "Development Tool Support", "RTSX Probe Circuit Control Pins", "Design Considerations". "Pin Description" been updated.
Note that "Package Characteristics Mechanical Drawings" section been eliminated from data sheet. mechanical drawings contained separate document, Package Characteristics Mechanical Drawings, available Actel site.
Family FPGAs RadTolerant HiRel
Datasheet Categories
order provide latest information designers, some datasheets published before data been fully characterized. Datasheets designated "Product Brief," "Advanced," "Production," "Datasheet Supplement." definitions these categories follows:
Product Brief
product brief summarized version datasheet (advanced production) containing general product information. This brief gives overview specific device family information.
Advanced
This datasheet version contains initial estimated information based simulation, other products, devices, speed grades. This information used estimates, production.
Unmarked (production)
This datasheet version contains information that considered final.
Datasheet Supplement
datasheet supplement gives specific device information derivative family that differs from general family datasheet. supplement used conjunction with datasheet obtain more detailed information specifications that differ between families.
Export Administration Regulations (EAR)
product described this datasheet subject Export Administration Regulations (EAR). They could require approved export license prior export from United States. export includes release product disclosure technology foreign national inside outside United States.
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