8b10b Macro Gigabit Ethernet 8b10b Function Operation Transmit Re

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8b10b Macro Gigabit Ethernet 8b10b Function Operation Transmit Re

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8b10b Macro
Gigabit Ethernet 8b10b Function Operation Transmit Receive Function Disparity Illegal Code Error Checking Connects directly industry-standard Gigabit Ethernet Transceiver devices. Supports either single dual channel transceiver single device.
into 10-bit code that contains equal number 1's. addition, code built that more than five consecutive ever transmitted. 8b10b macro designed work with variety standard transceiver devices. generic signals provides data command interface with system logic. system-level block diagram describing 8b10b macro shown Figure 8b10b macro provides user interface transceiver interface. user interface consists transmit data, receive data, several control status signals used qualify data. simplify timing user interface, data transmission word-wide (16-bits) operates 62.5 MHz. This strategy provides simplified timing interface system logic still meets megabyte second requirements Gigabit Ethernet. transceiver interface designed connect directly most commercially-available Gigabit Ethernet transceiver devices. transceiver responsible serializing transmit data deserializing receive data. addition, receiver designed resynchronize serial stream whenever external device detects illegal coding errors.
This data sheet defines functionality Version 8b10b macro.
8b10b macro implements function physical coding sublayer Gigabit Ethernet defined IEEE 802.3z specification. 8b10b marriage sub-blocks, 5b6b 3b4b encoder/decoders (ENDECs). purpose ENDEC convert 8-bit data
8b10b Macro
TX_WORD[15:0] TX_K_CHAR[1:0] TX_WRn INVALID_K CLK125 RSTn RX_WORD[15:0] RX_K_CHAR[1:0] CODE_ERRORn[1:0] WORD_SYNCn RX_CLK Receiver RX_DATA[9:0] COMMA_DETECT RBC0 RBC1 COMMA_DET_EN Transmitter TX_DATA[9:0]
TRANSCEIVER
SERIAL_TX
SERIAL_RX
Figure System Block Diagram Depicting 8b10b Macro Usage
2000 Actel Corporation
Performance requirements 8b10b macro drives device selection. Table defines minimum device requirements A54SXA family.
Table Device Statistics 8b10b Macro
Device A54SX08A A54SX16A A54SX32A Speed Grade Standard Standard Utilization
8b10b macro signals defined Tables Table Transceiver Interface Signals
Name1 COMMA_DETECT Type Input Description
Active high pulse from transceiver indicating that comma character been detected received data aligned with rising edge RBC1 clock. Clock signals recovered from received data stream. These clocks degrees phase rising edge each clock qualifies receive data. 10-bit encoded input data from transceiver qualified rising edges RBC0 RBC1. Active high signal indicating that transceiver should align data stream with rising edge RBC1. This output asserted when 8b10b detects multiple consecutive encoding errors. 10-bit encoded output data transceiver.
RBC0, RBC1 RX_DATA[9:0] COMMA_DET_EN
Input Input Output
TX_DATA[9:0]
Output
Note: Active signals designated with trailing lower-case
8b10b transmitter pipelined structure that converts 16-bit command data information into 10-bit encoded values. Command data information qualified TX_K_CHAR[1:0] bus. TX_K_CHAR[1] corresponds upper data byte TX_WORD[15:0] TX_K_CHAR[0] lower byte. data TX_WORD continuously registered into transmitter; however, this data only transferred encoder when TX_WRn signal driven single cycle. transmitter will encode send upper byte first followed lower byte. Because pipelined nature transmitter, first encoded data will driven TX_DATA several cycles after TX_WRn pulse. data input information valid, though command possibilities limited. transmitter detects command, then will assert INVALID_K signal. When TX_WRn input inactive, transmitter will continuously send IDLE2 (K28.5/D16.2) command defined 802.3 specification. Figure page illustrates implementation transmitter function. core transmitter consists data encoder, command encoder, disparity calculator. Each encoder calculates code input data. correct code, command data, then selected based original input value TX_K_CHAR. disparity calculator
determines whether encoded values need inverted maintain correct running disparity. Finally, code registered sent transceiver TX_DATA bus.
8b10 receiver also pipelined structure that converts 10-bit encoded values qualified clocks RBC0 RBC1 converts them 16-bit command data information. Command information indicated RX_K_CHAR[1:0] signals asserted high. data upper byte RX_WORD first decoded value sequence. Several signals qualify validity information RX_WORD. RX_WORD contains good information whenever CODE_ERRORn inactive (high) WORD_SYNCn active (low). WORD_SYNCn high CODE_ERRORn low, this indicates some problem transmission. Whenever receiver loses sync (WORD_SYNCn high), asserts COMMA_DET_EN output that transceiver resynchronizes data subsequent K28.5 commands. When sync reestablished, WORD_SYNCn will again driven after pipeline been flushed potentially data. Figure page illustrates implementation 8b10b receive function. Receive data first loaded into parallel registers. first register active rising edge RBC0 second rising edge RBC1. RBC0 data then
Table System Interface Signals
Name1 CLK125 RSTn TX_K_CHAR[1:0] Type Input Input Input Description Primary 125MHz clock signal transmit block 8b10b macro. Asynchronous reset signal macro. Active high signal indicating that TX_WORD[15:0] contains command information. corresponds lower byte (bits 7:0) corresponds upper byte (bits 15:8) TX_WORD. 16-bit input data transmitter. Byte transmitted first followed byte Active signal that qualifies TX_WORD data. When this signal asserted, data defined TX_WORD will registered into 8b10b macro, encoded, sent transceiver consecutive 10-bit transfers. Active signal indicating that ENDEC detected error received data stream. corresponds lower byte (bits 7:0) corresponds upper byte (bits 15:8) RX_WORD. Active high signal indicating that upstream device requested ENDEC transmit invalid command character. This signal asserted when either TX_K_CHAR[1:0] active, associated byte lane TX_WORD[15:0] does correspond valid command character. receive clock. rising edge this clock qualifies RX_WORD[15:0], RX_K_CHAR[1:0], WORD_SYNCn, CODE_ERRORn[1:0]. Output from ENDEC transceiver indicating that received data command code. 16-bit decoded receive data. upper byte received first lower byte received second data sequence. Active signal indicating that received data correctly aligned.
TX_WORD[15:0] TX_WRn
Input Input
CODE_ERRORn[1:0]
Output
INVALID_K
Output
RX_CLK RX_K_CHAR[1:0] RX_WORD[15:0] WORD_SYNCn
Output Output Output Output
Note: Active signals designated with trailing lower-case
D-4B/6B TX_WORD[15:8] TX_K_CHAR1 Encode Data Encode Data TX_DATA[9:0]
K28.5 TX_WORD[7:0] TX_K_CHAR0 D16.2
Encode Command Encode Command
K-4B/6B SELECT_K INVERT_CODE INVALID_K
Disparity Calculation
TX_WRn
Data Steering
CLK_125MHZ
Figure 8b10b Transmitter Block Diagram resynchronized with RBC1 next RBC1 rising clock edge. From this point, codes decoded parallel move from stage stage based RBC1 clock input. error check block monitors incoming codes checks illegal codes and/or running disparity. When error 8b10b code detected, CODE_ERRORn asserted. several codes received with errors, then 8b10b will assume that synchronization with transceiver been lost will deactivate WORD_SYNCn assert COMMA_DET_EN signal. number
consecutive errors required force resynchronization programmable, from (default transceiver then resynchronizes data rising edge RBC1 using K28.5 codes. pulse COMMA_DETECT input indicates
that transceiver reacquired sync. 8b10b responds deasserting COMMA_DET_EN asserting WORD_SYNCn.
COMMA_DETECT Synchronization Block COMMA_DET_EN WORD_SYNCn
RX_DATA[9:0]
Decode Block CODE_ERRORn[1:0]
RBC0
RX_WORD[15:0] RX_K_CHAR[1:0]
RBC1
RX_CLK
Figure 8b10b Receiver Block Diagram
hierarchy 8b10b model shown Figure transmitter encoder. encoder subdivided into data encoder (enc_d), command encoder (enc_k), running disparity calculator (enc_flip). enc_d composed mux32x6, mux32x1, mux4x1 modules that create data encoding. receiver decoder, which subdivided into data decoder (dec_data), running disparity decoder (dec_rd), synchronization state machine (sync_fsm).
reference. Input setup requirements defined Table Output valid times defined Table Table
Inputs Valid
ENDEC
T_su
DECODER
TRANSMITTER
RESET_SYNC
Figure Input Timing 8b10b Signals
ENCODER
DEC_RD
DEC_DATA
SYNC_FSM
ENC_K
ENC_D
ENC_FLIP
DEC_ERR
MUX32X6 MUX32X1 MUX4X1
T_val
Output Delay
Figure Hierarchy 8b10b ENDEC.
8b10b macro uses approximately sequential modules combinatorial modules A54SX-A devices. macro also uses approximately I/Os requires clock networks CLK125 RBC1 inputs. Because light loading, clock input RBC0 regular input. possible implement dual channel 8b10b either A54SX16A A54SX32A device.
Figure Output Timing 8b10b Signals Table Internal Reg-Reg Delays max)
Name CLK125MHZ RBC1 RBC0 RBC1 SX08A 13.5 SX16A 15.0 SX32A-1 12.5
8b10b macro divided into functions, transmitter receiver. transmitter designed operate MHz, receiver 62.5 MHz. input setup time transmitter signals (TX_WORD, TX_K_CHAR, TX_WRn) measured with respect rising edge CLK125. input setup time receiver signal RX_DATA measured with respect rising edge both RBC0 RBC1. input setup time COMMA_DETECT signal measured with respect RBC1 only. Receiver output timing defined with respect rising edge RX_CLK, inverted version RBC1 (refer Figure Figure Table defines internal register-to-register delays CLK125MHZ domain (transmitter) RBC1 domain (receiver). RBC0 domain RBC1 domain timing provided
Notes: timing worst-case commercial conditions. Expected values from commercially available synthesis tools using standard design practices.
operation 8b10b macro illustrated following waveforms. function 8b10b illustrated using different waveforms: Normal transmission Transmission with invalid command Normal receive Loss synchronization with transceiver Synchronization with transceiver
Table Input Required Set-Up Times max)
Name COMMA_DETECT RX_DATA[9:0] TX_WRn TX_K_CHAR TX_WORD[15:0] SX08A SX16A SX32A-1
Table Receive Data Valid Prior RX_CLK max)
Name CODE_ERRORn RX_K_CHAR RX_WORD[15:0] WORD_SYNCn SX08A SX16A SX32A-1
Notes: timing worst-case commercial conditions. Expected values from commercially available synthesis tools using standard design practices.
Notes: timing worst-case commercial conditions. Expected values from commercially available synthesis tools using standard design practices. Hold times signals least after rising edge RX_CLK.
Table Output Valid Times max)
Name COMMA_DET_EN INVALID_K TX_DATA[9:0] RX_CLK SX08A SX16A SX32A-1
After several cycles, unencoded data command driven onto RX_WORD RX_K_CHAR buses. This information qualified rising edge RX_CLK. normal 8b10b receive depicted Figure page some cases, 8b10b detects error condition incoming data stream. When this occurs, output CODE_ERRORn asserted. several consecutive errors found, 8b10b will assume that lost synchronization with transceiver will attempt resynchronize asserting COMMA_DET_EN output shown Figure page When COMMA_DET_EN output asserted, transceiver will scan incoming data stream K28.5 command code will resynchronize RX_DATA rising edge RBC1. data stream synchronized K28.5 command detected, then transceiver will indicate synchronization asserting COMMA_DETECT signal. After pulses, 8b10b will again synchronized indicated WORD_SYNCn signal Figure page
Notes: timing worst-case commercial conditions. Expected values from commercially available synthesis tools using standard design practices.
normal transmission begins placing valid data/command information TX_WORD TX_K_CHAR while simultaneously asserting TX_WRn signal. After several cycles, encoded data driven onto TX_DATA bus. command information illegal, INVALID_K signal will assert cycle. Normal 8b10b transmission illustrated Figure invalid command waveform shown Figure page normal receive assumes that 8b10b encoded data RX_DATA aligned with RBC1. Encoded data registered into 8b10b rising edge both RBC1 RBC0.
CLK125 TX_WORD[15:0] TX_K_CHAR[1:0] TX_WRn TX_DATA[9:0] INVALID_K
FC01
0203
0405
0607
0809
0A0B
D0.0
D0.0
D0.0
D0.0
D0.0
D0.0
D0.0
D0.0
D0.0
K28.7
D1.0
D2.0
Figure Normal Transmit
CLK125 TX_WORD[15:0] TX_K_CHAR[1:0] TX_WRn TX_DATA[9:0] INVALID_K
0000
0102
0304
0506
0708
090A
d0.0
d0.0
d0.0
d0.0
d0.0
d0.0
d0.0
d0.0
d0.0
d0.0
d1.0
Figure Invalid Command
RBC1 RBC0 RX_DATA[9:0] RX_CLK RX_WORD[15:0] RX_K_CHAR[1:0] CODE_ERRORn[1:0] WORD_SYNCn COMMA_DET_EN COMMA_DETECT
0000 0000 0000 0001 0203 0405 D0.0 D1.0 D2.0 D3.0 D4.0 D5.0 D6.0 D7.0 D8.0 D9.0 D10.0 D11.0
Figure Normal Receive
RBC1 RBC0 RX_DATA[9:0] RX_CLK RX_WORD[15:0] RX_K_CHAR[1:0] CODE_ERRORn[1:0] WORD_SYNCn COMMA_DET_EN COMMA_DETECT
0000
Figure Receive Error
RBC1 RBC0 RX_DATA[9:0] COMMA_DETECT RX_CLK RX_WORD[15:0] RX_K_CHAR[1:0] CODE_ERRORn[1:0] WORD_SYNCn COMMA_DET_EN
0000 0000 0000 0000 BC00 0000 D0.0 D0.0 K28.5 D0.0 D0.0 D0.0 K28.5 D0.0 D0.0 D0.0 D0.0 D0.0
Figure Synchronization with Transceiver
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8b10b Macro Gigabit Ethernet 8b10b Function Operation Transmit Re

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