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Ai4100

Ver1.0
1 A1 PROs A1 PROs
FEATURES
Ai4100
CCD CDS / PGA / 10b-20M-ADC
Independent ADC input conversion clock and data output clock Independent CDS and PGA gain control - CDS : -1.94 / 0 / 6 / 12dB - PGA : 0~24dB Wide gain range : -1.94 ~ 36dB High speed sample and hold circuit : pulse width 11ns (Min.) 48-pin LQFP package
GENERAL DESCRIPTION
The Ai4100 is a CMOS single-chip signal processing devices for CCD area sensors. It consists of a clamp circuit, Correlated Double Sampler (CDS), Programmable Gain Amplifier (PGA), reference voltage generator, black level detection circuit, voltage generator, black level detection circuit, 20MHz 10-bit A / D converter (ADC), timing generator for internally required pulses and serial interface for internal function control and PGA gain control.
BLOCK DIAGRAM
OBP ADCLK BLK CLPCAP DC Clamp CCDCLP REFIN CCDIN CCD ADIN OBCAP OBP DAC Compare Black Level Register ADCLP -1.94 / 0 / 6 / 12dB 0~6dB 0 / 6 / 12 / 18dB (0.047dB / Step) ADCLP / CCDCLP CSN SCK SDATA MONOUT
Timing Generator
Serial Register BandGap Circuit VRP VCOM VRN CDS PGA Rough PGA Fine 10-Bit ADC DO0~DO9
RESET STBY SHP SHD
OUTCK
Ai4100
PIN ASSIGNMENT
DVDD2
DVSS2
NC AVDD4 NC REFB REFT AVDD3 AVDD2 AVSS3 AVSS2 CML CCDIN REFIN
OUTCK RESETN DVDD1 DVSS1 STBY
Ai4100
CSN SDATA SCK OBP CCDCLP BLK ADCLP SHD
ADCLK
MONOUT
AISET
AVSS1
AVDD1
OBCAP
CLPCAP
Ai4100
PIN DESCRIPTION
Pin No.
1, 3, 17, 21 2, 6~7, 19 4 5 8~9, 20 10 11 12 13 14 15 16 18 22 23 24 25 26 27 28 29 30 31 32 33, 42 34, 43 35 36 37~41, 44~48 NC AVDD REFB REFT AVSS CML CCDIN REFIN CLPCAP ADIN OBCAP MONOUT AISET ADCLK SHP SHD ADCLP BLK CCDCLP OBP SCK SDATA CSN STBY DVSS DVDD RESETN OUTCK D0~D9
Pin Name
Description
ADC Internal Bottom Reference Voltage ADC Internal Top Reference Voltage Analog Ground ADC Internal Common Reference Voltage CDS Input Data Input CDS Circuit Reference Input Clamp Level Output ADIN Signal Input Black Level Integration Voltage Monitor Output of CDS or PGA External Bias Current Setting ADC Sampling Clock Input Reference Sampling Pulse Input Data Sampling Pulse Input Pulse Input for ADIN Clamp and Black Calibration Control Blanking Pulse Input Clamp Control Input Black Level Period Pulse Input Serial Port Clock Input Serial Port Data Input Serial Port Chip Selection (Active Low) Power Down Control (Power Down at Low) Digital GND Digital Power (+3.3V) Reset Signal Input (Active Low) Clock Input for ADC Output Timing ADC Digital Output
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Input Voltage Storage Temperature Operating Temperature Symbol VCC VIN TSTG TOP Value GND-0.3 to GND+6.0 V VSS-0.3 to VDD+0.3 -55 to +150 -20 to +70 Unit
Note : These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Rating" may cause substantial damage to the devices. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability
Ai4100
DC CHARACTERISTICS
Parameter VDD
Min. Conditions
0.7VDD 0 -
VDD 0.3VDD 200 1 10 -
Note : Black calibration period is specified when CCAL is from 16 to 127LSB. Although black level codes of 1 to 15 could be set, tBLKCAL is not guaranteed for these codes.
Ai4100
AC CHARACTERISTICS
fS tCYC tR tF tL tH tWR tWD tDR tDD tPSUP tHOLD tSP tSUPE tHOLDE tSUPOC tHOLDOC tDLD tDLE tDL
Parameter VDD
Conversion Frequency Clock Cycle Time Clock Rising Time Clock Falling Time Clock Low Period Clock High Period SHP Pulse Width SHD Pulse Width SHP Pulse Width SHD Sampling Aperture Data Pulse Setup Data Pulse Hold Sampling Pulse Non-overlay Enable Pulse Setup Enable Pulse Hold OUTCK Setup OUTCK Hold 3-state Disable Delay 3-state Disable Delay ADC Output Data Delay 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V Active High-Z High-Z Active
Min. Conditions
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Ai4100
FUNCTIONAL DESCRIPTION
CDS ( Co rrelated Double Sampling) Circuit
Connect the CCDIN pin to the CCD sensor through a capacitor. Connect also the REFIN pin to VSS through a capacitor. The CDS circuit holds the pre-charge voltage of the CCD at SHP pulse and do sampling of the CCD pixel data at SHD pulse, Correlated noise is removed by subtracting the pre-charge voltage from the pixel data level. CDS could choose a gain setting from 0, 6.02, 12 or -1.94dB (Mode 3, register D4 and D5 bits). A CDS gain is controlled by PGA gain. It is recommended to increase the CDS gain then increase the PGA gain to reduce the noise level. Clamp target (Mode 2 register D5 and D4), input signal(REFIN and CCDIN) to be clamped are selected.
The DC clamping (CCDCLP) is allowed while the DBP pin is low. The black level cancellation is available at "ADIN signal to PGA" mode. The black level cancellation is available at the ADCLP period in this mode. The clamping function and black level canceling function are done simultaneously.
Clamp Circuits DC clamp
The DC level of the CCDIN / REFIN input is fixed by an internal DC clamp circuit. The DC level of the C-coupled CCD signal at the CDS input is set to CLPCAP by the internal DC clamp circuit. The clamp switches are usually turned on at the black level calibration period. The CLPCAP pin connects to VSS through a 0.1F capacitor.
ADIN signal clamp
Clamp operation can also be used for the ADIN path. The clamp voltage is different from the CCDIN / REFIN signal and it could be turned off by register setting. At "ADIN signal to ADC" mode, the ADCLP signal controls the "clamp circuit". Black level calibration circuit is also controlled by ADCLP at "ADIN signal to PGA" mode
Clamp control
Clamp current (Mode 2 register D7). Charge current can select normal or fast clamp.
CCD OB ADCLK Effective Pixel Blanking
CCDCLP
OUTCK
DO0~DO9
Data Output
Black Code
Ai4100
Blanking CCD Effective Pixel Signal Optical Black Period Blanking Effective Pixel Signal
ADCLK
OBP Previous Black Level
Resulting Black Calibration Level (Hold)
OBCAP
Black Level Calibration Timing High-speed Black Level Cancellation
CSN tSUCS OBP tHCS
Counter
Black loop gain
High gain
Low gain
High gain
Black Loop Setting Gain Boost Timing
Symbol tSUCS tHCS Parameter CSN Setup Time CSN Hold Time Condition Min. 10 10 Typ. Max. Unit ns ns
Gain Control Circuit
The total gain for a CCD input signal covers from -1.94dB to 36dB. The CDS range is 0 / 6 / 12 / -1.94 dB. The PGA rough is 0 / 6 / 12 / 18 dB and ADC fine is 0 to 6dB, 0.047dB / step. The CDS gain is controlled by a 2-bit register and the PGA gain is controlled by a 9-bit register
The signal from the CCDIN input through a CDS and PGA The signal from the ADIN input through an PGA at the ADIN mode. The signal from the ADIN input at the ADIN mode.
A / D Conversion Range
The analog input range of the ADC is determined by the internal reference voltage. The full scale of the ADC is 1.0 VPP
A / D Converter Circuit
The Ai4100 includes one 20MHz 10-bits AD converter. The ADC converters the following signals.
Ai4100
The format of an ADC digital output is a straight binary. When in the input zero reference voltage, the output code will be all zero and when the input is a full scale voltage, the output code will be all one the ADCLK input after a 5.5 clock of pipeline delay.
High-Z Control of ADC Digital Output
Clock, Pipeline Delay, Digital Data Output Timing
The ADCLK input is used for an A / D conversion. The ADC input signal is sampled at the falling edge of the ADCLK input and 10 bits parallel data is output at the rising edge of
ADC Data Output (Coding : Straight Binary) Miscellaneous Functions (ADC Direct Input, ADIN Mode)
Polarity Inversion
The following input polarities can be inverted by register setting: ADCLK (A / D converter sampling clock, Mode 1 register D6) SHP and SHD (CDS sampling clock, Mode 2 register D3 and D2) BLK, OBP, CCDCLP and ADCLP (Mode 2 register D3 and D2)
Data Output Clock
The ADCK input or the OUTCK input is selectable as an ADC data output clock.
Power Down Mode
The power mode can be set either by register setting or by the STBY pin.
Serial Interface Circuit
The internal registers of the Ai4110 are controlled by a 3wire serial interface. The data is a 16-bit length serial data that consists of a 2-bit operation code, 4 bits address and 10bits data. Each bit is fetched at the rising edge of the CSN input. Keep CSN to high when not access Ai4110. it is prohibited to write to a non-defined address. When a data length is below 16 bits, the data is not executed.
Monitor Output
When setting Mode 2 (D1 and D0), the signal from MONOUT is selectable. The alternatives are OFF, CDS output, PGA output or REFIN / CCDIN output. The MONOUT pin gain is fixed to 0dB regardless of the gain control register setting when the CDS output is selected. The MONOUT level becomes V COM at zero reference level. The signals are output in reverse for the CCD input
Registers
The Ai4100 has 10 bitsX7 registers that control the operations. All registers are write only, the serial registers are written by the serial interface.
Ai4100
Address R / W A3 W W W W W 0 0 0 0 0 A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0 Mode 1 Mode 2 Mode 3 / CDS gain PGA gain Black level DOUT timing control / OUTCK polarity / ADCLK polarity / ADIN connection / ADC output / Black level reset / Power down Clamp current / ADIN clamp / Clamp target / S / H, enable logic / Monitor selection CDS gain control / Black loop gain boost / Boost period PGA gain ADC code at black level (1 LSB step) Register Name Function Description
Register Map
Register Bit Assignment
D9 Mode 1 Default Functions DOUT timing control OUTCK polarity ADCLK polarity ADIN connection Reserved ADC output Black level reset Power down Mode 2 Default Functions Clamp current ADIN clamp Clamp target S / H, enable logic Monitor selection Mode 3 Default Functions CDS gain control Black loop gain boost Boost period PGA Gain Default Functions PGA gain Black Level Default Functions Black level -------------------------X X X 1 O O O O O O --------------------------------X O O O O O O O O O -- -------X X X X O O O O O O ------X X O O O O O O O O -- X O O O O O O O O O D8 D7 D6 D5 D4 D3 D2 D1 D0
Ai4100
Register Operations
Control D9 Mode 1 DOUT timing control OUTCK polarity 0 1 0 1 0 1 0 ADIN connection 0 1 Reserved 0 1 X 0 1 0 1 0 1 0 1 DOUT synchronizes to ADCLK DOUT synchronizes to OUTCK DOUT changes at OUTCK rising edge DOUT changes at OUTCK falling edge Normal operation as timing chart ADCLK clock inversion ADIN function OFF ADIN signal to PGA ADIN signal to ADC Reserved Reserved Normal operation, ADC data output ADC output high-Z, or logic of STBY Normal operation Black level reset, or logic of RESET Normal operation Power down, or logic of STBY D8 D7 D6 D5 D4 D3 D2 D1 D0 Operations
ADCLK polarity
ADC output
Black level reset
Power down Mode 2 Clamp current 0 1 0 1 0 Clamp target 0 1 1 0 1 0 1 0 S / H, enable logic 0 1 1 0 1 0 1 0 Monitor selection 0 1 1 Mode 3 0 CDS gain control 0 1 1 Black loop gain boost 0 1 0 1 0 1
ADIN clamp
Ai4100
Control Operations D9 D8 D7 D6 D5 D4 D3 0 0 0 0 Boost period 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 High gain for 4 OBP pulse High gain for 5 OBP pulse High gain for 6 OBP pulse High gain for 7 OBP pulse D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 1 Always low gain High gain for 1 OBP pulse High gain for 2 OBP pulse High gain for 3 OBP pulse
PGA Gain (dB) 0 0.046 0.093 0.142 0.187 2.915 2.962 3.011 3.056 5.972 6.021 6.058 9.031 11.994 12.041 12.087 15.05 18.14 18.061 18.108 21.071 23.987 24.032
100 101 140 17F 180 181 1C0 1FE 1FF
Ai4100
TIMING DIAGRAMS
tDR CCD Reference Sampling Data Sampling SHP tWD SHD tCYC ADCLK BLK OBP CCDCLP ADCLP OUTCK tOL DO0~DO9 tHOLDE tH tHOLDC tSUPOC tL tSUPE tHOLD tPSUP tSP tWR tDD
Ai4100
Falling Edge 0.7AVDD ADCLK 0.3AVDD N+5 N+4 N+6
N+1 ADCLK Input N
0.7AVDD OUTCK 0.3AVDD tDL Digital Output N-6 N-5 N-2 N-1 N
ADC Direct Input Chart
ADCK Rising Edge tHOLDC ADCK Input N N+1 OUTCK tSUPOC ADCK
Sampling Point
ADCLK Inversion Chart
OUTCK Timing Chart
ADCLK Clock Waveform
0.7VDD
0.3VDD tR tF tCYC
Ai4100
Control Interface Timing
CSN SSU SCYC SLO SHI SH
SSU SDATA O0 O1 A0.. SNUM
Serial I / F Timing Chart
Data Output Sequence
ADCLK OUTCK
DO0~DO9
Black Level Code
Pixel Data Readout Sequence (1) : Start of Conversion
Ai4100
CCD (N-1) SHP N
ADCLK OUTCK
DO0~DO9
Black Level Code
Pixel Data Readout Sequence (2) : End of Conversion
SHP SHD
ADCLK
OUTCK
DO0~DO9
Pulse Control (Default : No Inversion)
Ai4100
SHP SHD
ADCLK
OUTCK
DO0~DO9
SHP SHD
ADCLK
OUTCK
DO0~DO9
Pulse Control (SHR & SHD Inversion)
SHP SHD
ADCLK
OUTCK
DO0~DO9
Pulse Control (ADCLK, SHR & SHD Inversion)
Ai4100
APPLICATION CIRCUITS
0.1uF Power In
DVDD2
DVSS2
Power In NC AVDD4 0.1uF NC REFB REFT 0.1uF 0.1uF AVDD3 10uF 0.1uF AVDD2 AVSS3 AVSS2 CML 0.1uF 0.1uF CCD 0.1uF
OUTCK RESETN DVDD1 DVSS1 STBY
Power In
0.1uF
Ai4100
CSN SDATA SCK OBP CCDCLP BLK ADCLP SHD SHP ADCLK NC
CCDIN REFIN
MONOUT
CLPCAP
OBCAP
AISET
AVDD1
AVSS1
0.1uF
0.1uF 0.1uF
Note : "" Pin 18 can also connect to ground through a 4.7K resistor. "" The capacitor connecting to OBCAP pin may need adjustment depending on user application from 0.1uF to 1uF typically.
0.1uF
Power In
Ai4100
PKG DIMENSION
48-pin LQFP (7X7)
Dimensions in mm Symbol Min. A B C D E F G H I J K 8.90 6.90 8.90 6.90 -1.35 -0.45 0.10 0° Nom. --0.50 0.20 -0.10 --Max. 9.10 7.10 9.10 7.10 -1.45 1.60 -0.75 0.20 7°