Operating voltage 2.7V 3.6V power consumption 70mW (Typ.) Power down m
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Operating voltage 2.7V 3.6V power consumption 70mW (Typ.) Power down mode less than Accepts direct signal input (Typ.) signal input level VP-P (Max.) 10-bit 20MHz) ±0.6 (Typ.) Black level neutralizer, target setting 16~127 Built-in serial interface
Ai4100
CDS/PGA/10b-20M-ADC
Independent input conversion clock data output clock Independent gain control -1.94/ 12dB 0~24dB Wide gain range -1.94 36dB High speed sample hold circuit pulse width 11ns (Min.) 48-pin LQFP package
GENERAL DESCRIPTION
Ai4100 CMOS single-chip signal processing devices area sensors. consists clamp circuit, Correlated Double Sampler (CDS), Programmable Gain Amplifier (PGA), reference voltage generator, black level detection circuit, voltage generator, black level detection circuit, 20MHz 10-bit converter (ADC), timing generator internally required pulses serial interface internal function control gain control.
BLOCK DIAGRAM
ADCLK CLPCAP Clamp CCDCLP REFIN CCDIN ADIN OBCAP Compare Black Level Register ADCLP -1.94/0/6/12dB 0~6dB 0/6/12/18dB (0.047dB/Step) ADCLP/CCDCLP SDATA MONOUT
Timing Generator
Serial Register BandGap Circuit VCOM Rough Fine 10-Bit DO0~DO9
RESET STBY
OUTCK
Ai4100
ASSIGNMENT
DVDD2
DVSS2
AVDD4 REFB REFT AVDD3 AVDD2 AVSS3 AVSS2 CCDIN REFIN
OUTCK RESETN DVDD1 DVSS1 STBY
Ai4100
SDATA CCDCLP ADCLP
ADCLK
MONOUT
AISET
AVSS1
AVDD1
OBCAP
ADIN
CLPCAP
Ai4100
DESCRIPTION
6~7, 8~9, 37~41, 44~48 AVDD REFB REFT AVSS CCDIN REFIN CLPCAP ADIN OBCAP MONOUT AISET ADCLK ADCLP CCDCLP SDATA STBY DVSS DVDD RESETN OUTCK D0~D9
Name
Connection Analog Power (+3.3V)
Description
Internal Bottom Reference Voltage Internal Reference Voltage Analog Ground Internal Common Reference Voltage Input Data Input Circuit Reference Input Clamp Level Output ADIN Signal Input Black Level Integration Voltage Monitor Output External Bias Current Setting Sampling Clock Input Reference Sampling Pulse Input Data Sampling Pulse Input Pulse Input ADIN Clamp Black Calibration Control Blanking Pulse Input Clamp Control Input Black Level Period Pulse Input Serial Port Clock Input Serial Port Data Input Serial Port Chip Selection (Active Low) Power Down Control (Power Down Low) Digital Digital Power (+3.3V) Reset Signal Input (Active Low) Clock Input Output Timing Digital Output
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Input Voltage Storage Temperature Operating Temperature Symbol TSTG Value GND-0.3 GND+6.0 VSS-0.3 VDD+0.3 +150 Unit
Note These stress ratings only. Stresses exceeding range specified under "Absolute Maximum Rating" cause substantial damage devices. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability
Ai4100
CHARACTERISTICS
Test Conditions Symbol
VCCDIN Analog Input Range VADIN VCLPCAP tBLKCAL VBLKCAL GMIN GMAX GSTEP ERPA VCOM CCAL STCAL Clamp Voltage Black Calibration Time Maximum Calibration Offset Voltage Gain (Set Gain (Set 6.02 Gain (Set 12.04 Gain (Set -1.94 Gain (Minimum Gain) Gain (Maximum Gain) Gain (Gain Step) Total (CDS+PGA) Gain Monotony Resolution Differential Nonlinearity S/(N+D) Common Voltage Voltage (Positive) Voltage (Negative) Output Black Level Calibration Code Calibration Code Resolution Relative gain fS=20MHz 1.25 1.55 1.05 0.047 ±0.6 1.65 1.15 0.094 ±1.0 1.55 1.75 1.25 Bits Absolute gain Relative gain ADIN input, fIN=1MHz Absolute gain 5.52 11.54 -2.44 -1.2 22.906 ±200 6.02 12.04 -1.94 -0.2 23.906 6.52 12.04 -1.44 24.906 VP-P Pixel
Parameter
High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Operation Current Monitor Disable Supply Current Monitor Active Power Down Current VIL=0V VIH=3.0V fS=20MHz fS=20MHz CCDIN input, fIN=1MHz
Min. Conditions
0.7VDD
Typ.
Max.
0.3VDD
Unit
VP-P
Note Black calibration period specified when CCAL from 127LSB. Although black level codes could set, tBLKCAL guaranteed these codes.
Ai4100
CHARACTERISTICS
(VSS Test Conditions Symbol
tCYC tPSUP tHOLD tSUPE tHOLDE tSUPOC tHOLDOC tDLD tDLE
Parameter
Conversion Frequency Clock Cycle Time Clock Rising Time Clock Falling Time Clock Period Clock High Period Pulse Width Pulse Width Pulse Width Sampling Aperture Data Pulse Setup Data Pulse Hold Sampling Pulse Non-overlay Enable Pulse Setup Enable Pulse Hold OUTCK Setup OUTCK Hold 3-state Disable Delay 3-state Disable Delay Output Data Delay 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V Active High-Z High-Z Active
Min. Conditions
Typ.
Max.
Unit
Ai4100
FUNCTIONAL DESCRIPTION
rrelated Double Sampling) Circuit
Connect CCDIN sensor through capacitor. Connect also REFIN through capacitor. circuit holds pre-charge voltage pulse sampling pixel data pulse, Correlated noise removed subtracting pre-charge voltage from pixel data level. could choose gain setting from 6.02, -1.94dB (Mode register bits). gain controlled gain. recommended increase gain then increase gain reduce noise level. Clamp target (Mode register D4), input signal(REFIN CCDIN) clamped selected.
rrelated Double Sampling) Circuit purpose black level cancel circuit control level input. output code optical black period correspond black level code register. black level code to)16 available (the default LSB) While active black level cancel loop established. loop, comparison made between output code black level code, result controls voltage OBCAP capacitor. Hence, OBCAP voltage settles gradually signal level optical black period corresponds established value. following conditions will reset OBCAP capacitor: black level reset register (Mode register D1=1). RESETN Power down STBY register control
clamping (CCDCLP) allowed while low. black level cancellation available "ADIN signal PGA" mode. black level cancellation available ADCLP period this mode. clamping function black level canceling function done simultaneously.
Clamp Circuits clamp
level CCDIN/REFIN input fixed internal clamp circuit. level C-coupled signal input CLPCAP internal clamp circuit. clamp switches usually turned black level calibration period. CLPCAP connects through 0.1F capacitor.
ADIN signal clamp
Clamp operation also used ADIN path. clamp voltage different from CCDIN/REFIN signal could turned register setting. "ADIN signal ADC" mode, ADCLP signal controls "clamp circuit". Black level calibration circuit also controlled ADCLP "ADIN signal PGA" mode
Clamp control
Clamp current (Mode register D7). Charge current select normal fast clamp.
ADCLK Effective Pixel Blanking
CCDCLP
OUTCK
DO0~DO9
Data Output
Black Code
Ai4100
Blanking Effective Pixel Signal Optical Black Period Blanking Effective Pixel Signal
ADCLK
Previous Black Level
Resulting Black Calibration Level (Hold)
OBCAP
Black Level Calibration Timing High-speed Black Level Cancellation
Ai4100 high speed black level cancellation function, which means register setting enhances setting speed within fixed period from access serial interface, increases gain setting within fixed fixed period turn increases charge/discharge current OBCAP capacitor. Mode register data controls black level boost function. default setting always gain (D3~D0-5'b0). setting register D2~D0, gain becomes high times that pulse period after access serial interface. After that period, gain returns low. When setting 1'b1, gain always high. signal becomes starting point pulse count. following figure shows black loop setting gain boost timing chart when boost controls (D3="0") boost period
tSUCS tHCS
Counter
Black loop gain
High gain
gain
High gain
Black Loop Setting Gain Boost Timing
Symbol tSUCS tHCS Parameter Setup Time Hold Time Condition Min. Typ. Max. Unit
Gain Control Circuit
total gain input signal covers from -1.94dB 36dB. range 0/6/12/-1.94 rough 0/6/12/18 fine 6dB, 0.047dB/step. gain controlled 2-bit register gain controlled 9-bit register
signal from CCDIN input through signal from ADIN input through ADIN mode. signal from ADIN input ADIN mode.
Conversion Range
analog input range determined internal reference voltage. full scale
Converter Circuit
Ai4100 includes 20MHz 10-bits converter. converters following signals.
Ai4100
Converter Output Code (Mode Register D5=1)
format digital output straight binary. When input zero reference voltage, output code will zero when input full scale voltage, output code will ADCLK input after clock pipeline delay.
High-Z Control Digital Output
digital outputs become High-Z under following conditions output one. (Mode register D2=1) STBY power control (Mode register D0=1)
Clock, Pipeline Delay, Digital Data Output Timing
ADCLK input used conversion. input signal sampled falling edge ADCLK input bits parallel data output rising edge
Digital Output Code Input Full Scale Zero Scale
Data Output (Coding Straight Binary) Miscellaneous Functions (ADC Direct Input, ADIN Mode)
direct input path achieved means register setting. selectable paths follows: Function disable (default, Mode register D5=0, D4=0) ADIN input (Mode register D5=0, D4=1) ADIN input (Mode register D5=1, D4=Don't Care) BLK, inputs ignored ADIN mode.
Polarity Inversion
following input polarities inverted register setting: ADCLK (A/D converter sampling clock, Mode register (CDS sampling clock, Mode register BLK, OBP, CCDCLP ADCLP (Mode register
Data Output Clock
ADCK input OUTCK input selectable data output clock.
Power Down Mode
power mode either register setting STBY pin.
Serial Interface Circuit
internal registers Ai4110 controlled 3wire serial interface. data 16-bit length serial data that consists 2-bit operation code, bits address 10bits data. Each fetched rising edge input. Keep high when access Ai4110. prohibited write non-defined address. When data length below bits, data executed.
Monitor Output
When setting Mode D0), signal from MONOUT selectable. alternatives OFF, output, output REFIN/CCDIN output. MONOUT gain fixed regardless gain control register setting when output selected. MONOUT level becomes zero reference level. signals output reverse input
Registers
Ai4100 bitsX7 registers that control operations. registers write only, serial registers written serial interface.
Ai4100
Address Mode Mode Mode gain gain Black level DOUT timing control/OUTCK polarity/ADCLK polarity/ADIN connection/ADC output/Black level reset/Power down Clamp current/ADIN clamp/Clamp target/S/H, enable logic/Monitor selection gain control/Black loop gain boost/Boost period gain code black level step) Register Name Function Description
Register
Register Assignment
Mode Default Functions DOUT timing control OUTCK polarity ADCLK polarity ADIN connection Reserved output Black level reset Power down Mode Default Functions Clamp current ADIN clamp Clamp target S/H, enable logic Monitor selection Mode Default Functions gain control Black loop gain boost Boost period Gain Default Functions gain Black Level Default Functions Black level
Ai4100
Register Operations
Control Mode DOUT timing control OUTCK polarity ADIN connection Reserved DOUT synchronizes ADCLK DOUT synchronizes OUTCK DOUT changes OUTCK rising edge DOUT changes OUTCK falling edge Normal operation timing chart ADCLK clock inversion ADIN function ADIN signal ADIN signal Reserved Reserved Normal operation, data output output high-Z, logic STBY Normal operation Black level reset, logic RESET Normal operation Power down, logic STBY Operations
ADCLK polarity
output
Black level reset
Power down Mode Clamp current Clamp target S/H, enable logic Monitor selection Mode gain control Black loop gain boost
Normal clamp ±50A Fast clamp ±100A Clamp operation active ADIN clamp ADIN Normal mode, clamp both REFIN CCDIN Clamp REFIN only Clamp CCDIN only Clamp Normal operation timing chart control polarity inversion Enable control polarity inversion Both enable inversion Monitor signal monitor output monitor Output REFIN CCDIN
ADIN clamp
gain=0 gain=6.02 gain=12.04 gain=-1.94 Boost control Always high gain
Ai4100
Control Operations Boost period High gain pulse High gain pulse High gain pulse High gain pulse Always gain High gain pulse High gain pulse High gain pulse
Control gain
Decimal
Gain (dB) 0.046 0.093 0.142 0.187 2.915 2.962 3.011 3.056 5.972 6.021 6.058 9.031 11.994 12.041 12.087 15.05 18.14 18.061 18.108 21.071 23.987 24.032
Ai4100
Operation, Code Black level Decimal Forbidden Black Code Forbidden
TIMING DIAGRAMS
Reference Sampling Data Sampling tCYC ADCLK CCDCLP ADCLP OUTCK DO0~DO9 tHOLDE tHOLDC tSUPOC tSUPE tHOLD tPSUP
Ai4100
Conversion Timing ADIN (ADC) Input Mode Register D5=1)
Falling Edge 0.7AVDD ADCLK 0.3AVDD
ADCLK Input
0.7AVDD OUTCK 0.3AVDD Digital Output
Direct Input Chart
ADCK Rising Edge tHOLDC ADCK Input OUTCK tSUPOC ADCK
Sampling Point
ADCLK Inversion Chart
OUTCK Timing Chart
These figures shown when Mode "1", external clock input OUTCK pin. When setting "0", ADCLK used OUTCK. Note default condition ADIN mode, data sampled falling edge ADCK clock, output rising edge OUTCK clock. ADCLK polarity register when data sampled output falling edge ADCK clock. diagram upper portion this page shows default timing lower left figure shows inverted timing Delay from data sampling data output ADCLK normal Mode register D6=0; delay ADCLK inversion Mode register D6=1; delay ADIN input mode, above mentioned register setting available. ADIN (PGA) input Mode register D5=0 D4=1, digital data output delayed clks.
ADCLK Clock Waveform
0.7VDD
0.3VDD tCYC
Ai4100
Control Interface Timing
Test Conditions Symbol SCYC SNUM Parameter Clock Frequency Clock Level Width Clock High Level Width Data Setup Time Period Data Hold Time Period SCK, Rising Time Period SCK, Falling Time Period Number Serial Data 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V Conditions Min. Typ. Max. Unit
(VSS
SCYC
SDATA SNUM
Serial Timing Chart
Data Output Sequence
ADCLK OUTCK
DO0~DO9
Black Level Code
Pixel Data Readout Sequence Start Conversion
Ai4100
(N-1)
ADCLK OUTCK
DO0~DO9
Black Level Code
Pixel Data Readout Sequence Conversion
Clock Timing Variations Register Setting Clock timing variations when inverted register settings. inversion Mode register D6=0, Mode register D2=0; Default
ADCLK
OUTCK
DO0~DO9
Pulse Control (Default Inversion)
Ai4100
ADCK inversion Mode register D6=1, Mode register D2=0
ADCLK
OUTCK
DO0~DO9
Pulse Control (ADCLK Inversion) inversion Mode register D6=0, Mode register D2=1
ADCLK
OUTCK
DO0~DO9
Pulse Control (SHR Inversion)
ADCLK, inversion Mode register D6=1, Mode register D2=1
ADCLK
OUTCK
DO0~DO9
Pulse Control (ADCLK, Inversion)
Ai4100
APPLICATION CIRCUITS
0.1uF Power
DVDD2
DVSS2
Power AVDD4 0.1uF REFB REFT 0.1uF 0.1uF AVDD3 10uF 0.1uF AVDD2 AVSS3 AVSS2 0.1uF 0.1uF 0.1uF
OUTCK RESETN DVDD1 DVSS1 STBY
Power
0.1uF
Ai4100
SDATA CCDCLP ADCLP ADCLK
CCDIN REFIN
MONOUT
CLPCAP
OBCAP
AISET
AVDD1
AVSS1
ADIN
0.1uF
0.1uF 0.1uF
Note also connect ground through 4.7K resistor. "**" capacitor connecting OBCAP need adjustment depending user application from 0.1uF typically.
0.1uF
Power
Ai4100
DIMENSION
48-pin LQFP (7X7)
Dimensions Symbol Min. 8.90 6.90 8.90 6.90 -1.35 -0.45 0.10 Nom. -0.50 0.20 -0.10 -Max. 9.10 7.10 9.10 7.10 -1.45 1.60 -0.75 0.20
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