Main Features BATTERY CHARGER Complete Charge Management Solution
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TPS658610 Advanced Power Management Unit
Main Features
BATTERY CHARGER Complete Charge Management Solution Single Cell Li-Ion/Li-Pol Cell With Dynamic Power Management Thermal Foldback. Maximum 1.0A charge current Programmable Adapter Charge Operation INTEGRATED POWER SUPPLIES Programmable Step-Down converters Software Controlled Enable/Forced Mode Automatic Power Saving Mode Maximum 1.2A Outputs Programmable General Purpose LDOs With Output Voltages 1.25V 3.3V With Output Voltages 0.725V 1.5V 1.25V 2.586V (factory configurable) "Always With Output Voltages 1.25V 3.3V With Output Voltage 1.70V-2.475V DISPLAY SUPPORT FUNCTIONS Outputs With Programmable Frequency Duty Cycle Dual Drivers Constant Current WLED Driver 26.5V (max) 25mA Over-Voltage Protection Programmable Current Level Brightness Control HOST INTERFACE Interrupt Controller With Maskable Interrupts External Triggering Step-Down Converter Mode Control SYSTEM MANAGEMENT Dual Input Power Path Current Limiting Over-Voltage Protection Power Good Monitoring Supply Outputs Software Reset Function Hardware On/Off Reboot Control Channel With Operating Modes Single Conversion Peak Detection Averaging
Applications
Smart Phones Portable Navigation Devices Portable Media Players
1.2.1 Overview
TPS658610 provides easy use, fully integrated solution handheld devices, integrating charge management, multiple regulated power supplies, system management display functions small package. interface enables control wide range subsystem parameters. Internal registers have complete status information, enabling easy diagnostics host-controlled handling fault conditions.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this document.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2009, Texas Instruments Incorporated
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
ORDERING INFORMATION
-40°C 85°C PART NUMBER TPS658610
PACKAGE
PACKAGE DESIGNATOR
ORDERING TPS658610
PACKAGE MARKING TPS658610
TPS658610 only available taped reeled. Quantities 2,500 devices reel. Devices with distinct part numbers have unique factory configurations supply defaults, sequencing other functions. Consult factor configuration information each part number. This product RoHS compatible, including lead concentration that does exceed 0.1% total product weight, suitable specified lead-free soldering processes. addition, this product uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
Electrical Specifications
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
with respect AGND1 ANLG1, ANLG2, ANLG3 with respect AGND2 V(SYS), V(VIN_CHG) with respect AGND1
VALUE UNITS -0.3 -0.3 -0.3 -0.3 -0.3 -5.5 -0.3 -0.3 -0.3 -2.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +0.3 Defined ILIM Defined ILIM 2500 -3000 1500 1000 2000 -40°C 85°C 125°C -65°C 150°C 260°C
VIN_LDO01, VIN_LDO23, VIN_LDO4, VIN_LDO678, VIN_LDO9 with respect AGND1 ADC_REF with respect AGND2 RTC_OUT with respect V(SYS) RTC_OUT with respect AGND1 LDO0, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9, V2V2 with respect AGND1 V32K with respect AGND1 with respect V2V2 SM0, VIN_SM0 with respect PGND0 SM1, VIN_SM1 with respect PGND1 SM2, VIN_SM2 with respect PGND2 with respect PGND3 SM3SW with respect PGND3 with respect PGND3 V(BAT) with respect AGND1, Battery power only other pins (except AGNDn PGNDn) with respect AGND1 AGND2, AGND3, DGND1, DGND2DT, PGND0, PGND1, PGND2, PGND3 with respect AGND1 Input Current, Input Current, Output continuous current, SYS, VIN_CHG pins Output continuous current, Continuous Current PGND0, PGND1 Continuous Current PGND3 Continuous Current PGND2 Operating free-air temperature, Maximum junction temperature, Storage temperature, TSTG Lead temperature (1/16-inch) from case seconds rating pins rating, pins
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
Electrical Specifications
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TPS658610 Advanced Power Management Unit
DISSIPATION RATINGS
PACKAGE Psi_Jb 25°C/W 25°C POWER RATING 4000 DERATING FACTOR ABOVE 25°C 40.0°C/W 55°C POWER RATING 2800 70°C POWER RATING 2200 85°C POWER RATING 1600
RECOMMENDED OPERATING CONDITIONS
16.5 UNIT
over operating free-air temperature range (unless otherwise noted)
with respect AGND1 V(SYS) with respect AGND1 V(BAT) with respect AGND1, battery power only V(BAT) with respect AGND1, battery connected, power selected, Selected power source >2.9V ANLG1,ANLG2, ANLG3 with respect AGND2 VIN_LDO01, VIN_LDO23, VIN_LDO678, VIN_LDO4, VIN_LDO9 with respect AGND1 VIN_SM0 with respect PGND0 4.30 2.15 Greater 1.7V Minimum input voltage required LDO/Converter operation outside dropout region Greater 2.3V Minimum input voltage required LDO/Converter operation outside dropout region. 2.9V meet parametric specifications.
VIN_SM1 with respect PGND1 VIN_SM2 with respect PGND2 VIN_SM4 with respect PGND4 with respect PGND3 GPIOx with respect AGND1 other pins (except AGNDn PGNDn) with respect AGND1 Operating free-air temperature, Maximum junction temperature, functional operation Maximum junction temperature, electrical characteristics External supply ramp rate, pins V/mSec
V/µSec
Thermal operating restrictions reduced avoided input voltage does exceed
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Electrical Specifications
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
ELECTRICAL CHARACTERISTICS
PARAMETER TEST CONDITIONS UNIT
over operating free-air temperature range (unless otherwise noted)
QUIESCENT CURRENT V(BAT) 4.2V EXTERNAL LOADS SUPPLY OUTPUTS IQ(ON) IQ(DIGITAL) Quiescent current, 6586x normal sleep mode. supplies, peripherals charger Quiescent current, control logic Power path active, control logic power mode Control logic high power mode
SM0, SM1: enabled, mode, from SM2: enabled, mode, from IQ(SMn) SM0, SM1, operating quiescent current SM0, SM1, SM2: enabled, mode, from VINSMn disabled I(LDOx) external load IQ(LDOx) quiescent current, LDOx disabled I(LDOx) I(LDOx) disabled, 85°C enabled, switching IQ(SM3) operating quiescent current Enabled, switching Disabled Conversion active IQ(ADC) operating quiescent current converting, waiting trigger disabled RTC_OUT enabled IQ(RTC) RTC_OUT quiescent current RTC_OUT disabled I2C, 85°C Externally applied V(RTC_OUT) supplies real time clock counters xtal oscillator buffer enabled, external load IQ(V32K) V32K supply bias current buffer enabled Disabled Charger enabled, termination detected IQ(CHG) Charger quiescent current Charger enabled, termination disabled, charge current=0 Charger disabled INTERFACE TIMING SDA, PSDA, PSCLK, SCLK TW(H) TW(L) TSU(STA) TH(STA) TSU(DAT) TH(DAT) TSU(STOP) T(BUF) FSCL
SCLK/SDATA rise time SCLK/SDATA fall time SCLK pulse width high SCLK Pulse Width Setup time START condition START condition hold time after which first clock pulse generated Pull-up resistors connected 2.2V Data setup time Data hold time Setup time STOP condition free time between START STOP condition Clock Frequency
BUFFERS SDA, PSDA, PSCLK, SCLK VIL(I2C) VIH(I2C) VOL(I2C) IO(I2C) ILKG(I2C) CI2C CI2CBUS level input voltage High level input voltage level output voltage Maximum load current Input current Input capacitance capacitance SDA, PSDA configured output, IOL=3mA SDA, PSDA configured output V(pin)=5V SDAT, SCLK, PSDAT, PSCLK pins SDAT, SCLK, PSDAT, PSCLK 1.15
Control logic power mode when functions communication going Control logic high power mode when following events happen: 6586x power-up/rtc/rtc_on/supplyseq states, converter mode, enabled, driver enabled, conversion on-going, communication on-going, voltage transition supplies on-going, charger supply detected. External voltage supplied supercap coin cell connected RTC_OUT pin, application diagram details.
Electrical Specifications
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TPS658610 Advanced Power Management Unit
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS UNIT DIGITAL INPUT BUFFERS: RESUME, SM0EN, SM1EN, SM2EN, HOTRST, LDO4EN, SYNCEN VIL(DIG) VIH(DIG) ILKG(DIG) RDIG level input voltage High level input voltage Input current Internal resistor V(pin)=5V RESUME pull-down AGND HOTRST pin, pull-up V2V2 PUSH-PULL OUTPUT BUFFERS, USER SELECTABLE OUTPUT VOLTAGE NORTC,nNOPOWER VBFRPWR VOL(OBFR) Buffer positive supply level output voltage Internally connected V32K V32K V32K VOH(OBFR) High level output voltage, referenced output buffer supply, NORTC, WAKEUP High level output voltage, referenced output buffer supply,NOPOWER Maximum level sink current load Maximum high level source current load V32K V32K V32K V32K V(pin) V(pin) V32K-0.6 V32K-0.11 V32K-0.6 V32K-0.11 1.15
VOH(OBFR)
IOL(OBFR) IOH(OBFR)
OPEN DRAIN OUTPUT BUFFERS VOL(OBFR) level output voltage V32K V32K ILKG(OBFR) Output leakage current Output buffer, open-drain mode, V(pin)=5.5V
PUSH-PULL OUTPUT BUFFERS LDO4PG, SM0PG, SM1PG, CHGSTAT VOL(DBFR) level output voltage VOH(DBFR) High level output voltage buffer configured push-pull Maximum level sink current load Maximum high level source current load V(pin) V(pin)
IOL(DBFR) IOH(DBFR)
32kHz OUTPUT BUFFER V(32K)=1.7V (min), UNLESS OTHERWISE STATED V32B Externally applied bias rail output driver Output level Buffer supply voltage V(32K) V(32K) V(32K) Normal operation V(32K) V(32K) VJITTER Rise/fall time Output jitter clock driving 50pF load Peak peak 32kHz CLOCK SWITCHING TIMING TXTAL F32K XTAL oscillator stabilization time Internal clock Frequency within typical value, frequency defined XTAL characteristics Frequency V32K-0.05 V32K-0.5 0.05
INTERNAL REFERENCES VUVLO VUVLO_HYS VO(2V2) ISH2V2 Internal UVLO detection threshold UVLO detection hysteresis Output Voltage Short Circuit current limit V(2V2) decreasing V(2V2) increasing from decreasing trigger point Always V(2V2)=0v 1.85
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Electrical Specifications
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER RTC_OUT VO(RTC_OUT) RTC_OUT output voltage Output Voltage, Selectable Dropout voltage, I(RTC_OUT) V(SYS) Total accuracy, V(AC):2V 4.7V, -15mA load, V(BAT1)=V(BAT2)=V(USB)=0V Load regulation, V(AC)=3.5V, load: -15mA Line regulation, load,V(AC): 3.5V18V, V(BAT1) =V(BAT2) =V(USB) ISHRTC V(RTCGOOD) Short Circuit current limit RTC_OUT power good fault detection threshold Falling RTC_OUT voltage, Power good fault detection hysteresis Internal UVLO detection threshold UVLO detection hysteresis Rising RTC_OUT voltage (Referenced V(RTCGOOD) threshold) VRTC Decreasing VRTC Increasing VHYS(RTC) VUVLO_RTC VUVLO_RTC_HYS BOOT-UP TIMING TPOR TBOOT Power-on-reset delay Boot-up time Fixed time, measured from 2V2>UVLO Fixed time Accuracy, referenced TBOOT(tTYP) THOTPLUG TWAKEUP TCHECK TMAX TNORTC plug deglitch time Wakeup pulse width check wait time RTC_ON watchdog timer NORTC pulse width value Fixed time Fixed time Fixed time Fixed time Fixed time Accuracy, relative TNORTC (TYP) KNOPOWER NOPOWER pulse width const. TNOPOWER KNOPOWER CNOPOWER Pulse width accuracy, CNOPOWER 400nF TWAIT TWAIT1 TSYNCEND TSYNCDLY Synchronization complete delay Supply sync delay time Measured from supplies synchronized Regulator specific. Table 3-17 Accuracy, relative TSYNCDLY(TYP) POWER GOOD THERMAL FAULT DETECTION TDGL(PGFLT) TSHUT THYS(SHUT) TDGL(TSHUT) Power good deglitch time Thermal shutdown Thermal shutdown hysteresis Thermal shutdown detection delay Applies non-masked power good signals, output voltage falling edge. Increasing junction temperature Decreasing junction temperature Rising temperature Reboot sleep request timeout Fixed time -25% -10% 0.25 -10% ms/nF -10% 2.35 1.90 2.45
TEST CONDITIONS
UNIT
:VO(RTC_OUT)TYP=1.25, 1.50, 1.8, 2.5, 2.7,2.85,3.1,3.3
TSYNCDLY(TYP) 1.25, 2.5, 3.75,
RESUME CONTROL TIMING TRESUME(H) TRESUME(L) RESUME pulse width high RESUME pulse width 1500
SEQUENCER REBOOT CONTROL VHOTRST Reboot control threshold Reboot started when normal state V(HOT_RST) VREBOOT TDT(HRST)
THRST(H) TDT(HRST)
HOT_RST pulse width HOT_RST detection pulse width HOT_RST deglitch
Setting RTC_OUT output voltage below RTC_OUT power good threshold will result NORTC pulse being always generated during reboot cycles when exiting sleep. Setting RTC_OUT output voltage below VUVLO_RTC disables internal real time clock counter xtal oscillator.
Electrical Specifications
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TPS658610 Advanced Power Management Unit
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER EXTERNAL SUPPLY DETECTION STATUS VLOWSYS Minimum system voltage detection threshold System voltage V(SYS) decreasing. Total accuracy, referenced V(LOWSYS)TYP VHYS(LOWSYS) TDGL(LOWSYS) VIN(DT) VIN(NDT) Minimum system voltage detection hysteresis V(SYS) increasing from decreasing trigger point TEST CONDITIONS UNIT
Minimum system voltage detection deglitch time V(SYS) decreasing Input voltage detection threshold. Input voltage increasing, referenced battery voltage Input voltage removal threshold. Input voltage decreasing, referenced battery voltage detection threshold, relative detected when V(AC)-V(BAT) VIN(DT) V(AC) VACMIN detected when V(USB)-V(BAT) VIN(DT) detected: when V(AC)-V(BAT) VIN(NDT) detected when V(USB)-V(BAT)< VIN(NDT) voltage decreasing detected when V(AC) VACMIN Hysteresis, voltage increasing
VACMIN
22.5
TDGLAC(DT) TDGLUSB(DT) VIN(OVP) TDLY(INOVP)
Power detected deglitch Power detected deglitch Input over voltage detection Input over voltage detection delay
voltage increasing voltage increasing
Rising voltage
ANALOG COMPARATOR VCOMPDET IQCDET Voltage threshold Bias current Propagation time Enabled sleep mode Always V(COMP):01.5V0, measured from input NOPOWER:HILO 1.21 1.245 1.28
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Electrical Specifications
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
ELECTRICAL CHARACTERISTIC
PARAMETER TEST CONDITIONS UNIT
over operating free-air temperature range (unless otherwise noted)
POWER PATH CURRENT LIMIT PROTECTION FUNCTIONS IUSB100 Selected input current limit, applies input only IUSB500 Selected input current limit, applies input IINLIM Selected input current limit, applies input Total accuracy, relative IINLIM(TYP) TOVSH Input current limit transient time Load pin: current limit value 120% regulation value (IINLIM, IUSB100 IUSB500). Time measured from load transient input current within regulation limits. Load pin: current limit value 120% regulation value (IINLIM, IUSB100 IUSB500), TOVSH power path switches V(SYS) VSH(SYS) V(SYS) VSH(SYS), internal resistor connected from V(SYS) VSH(SYS), internal resistor connected from 2.18 Short circuit detection blanked TDGL(BATSYS), measured from batt switch: OFF->ON initial power path enable Battery switch already turned power path enabled IFLT(SYS) VSUP(SYS) Battery switch over-current recovery pull-up current V(BAT) -V(SYS) VOC(SYS), internal current source connected from source Supplement detection threshold Battery switch V(BAT)-V(SYS) VSUP(SYS) Battery switch V(BAT)-V(SYS)<VSUPNDT(SYS) -12.5% 12.5% Total accuracy, relative IINLIM(TYP) Input current limit range, input configured with USBMODE=LO -20% 2.11 Selected Input switch dropout. settings: USBMODE=HI, USBLIMIT=LO -40°C 85°C -25°C 85°C 2.75
Selected Input switch dropout. settings: USBMODE=HI, USBLIMIT=HI Input current limit range, input
IOVSHPKUSB VSH(SYS) RFLT(USB) RFLT(AC) IBATSYS
Input current limit overshoot power path Short Circuit detection threshold short circuit recovery pull-up resistor short circuit recovery pull-up resistor Battery switch over-current detection
2.54
TDGL(BATSYS) Battery switch over-current detection delay
VSUPNDT(SYS) Supplement mode detected threshold POWER PATH INTEGRATED MOSFETS CHARACTERISTICS VACDO VUSBDO VBATDODCH switch dropout voltage switch dropout voltage Battery Switch dropout voltage, discharge charge
VACDO V(AC)-V(SYS); V(AC)=4V input current limit 2.0A (typ) IO(SYS) 1.0A VUSBDO V(USB)-V(SYS); V(USB)=4.6V VBATDODCH V(BAT)-V(SYS), V(BAT)=3V, I(BAT)= I(SYS)+I(BAT)= 0.425A I(SYS)+I(BAT)= 85mA
POWER PATH TIMING CHARACTERISTICS TSW(ACBAT) TSW(USBBAT) Switching from Switching from USB, power removed power removed
POWER PATH DISCHARGE SWITCHES IDCH(AC) IDCH(USB) discharge current discharge current Always V(AC) Always V(USB)
SM0, SM1, DC/DC CONVERTERS VSMUV input voltage detection threshold, input voltage Converter turned V(VIN_SMn) VSMUV decreasing Hysteresis rising input voltage High side MOSFET on-resistance RDS(ON) ILK_HS ILK_LS ILIM VSMPG side MOSFET on-resistance High side leakage current side leakage current High side side current limit Oscillator frequency Power good threshold 85°C 2.9V VIN_SMx 5.5V mode Power fault detection, Voltage decreasing, referenced programmed output voltage Hysteresis, voltage increasing, referenced VSMPG SM0, (snubber enabled) 1550 1550 2.025 -13.0% 1860 1860 2.25 -10% 2.475 -7.0% VIN_SMx 3.6V, 100% duty cycle VIN_SMx 3.6V, duty cycle
Electrical Specifications
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TPS658610 Advanced Power Management Unit
ELECTRICAL CHARACTERISTIC (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS SM0, range, 25mV steps Adjustable output voltage range, Selectable VIN_SMx 2.9V 5.5V SM1, high range, 50mV steps SM2, high range, 50mV steps Output Voltage Accuracy, relative VO(SMx)TYP output voltage load regulation output voltage line regulation VIN_SMx 2.9V 5.5V, mode VIN_SMx 2.9V 5.5V, mode, IOUT< mode, VIN_SMn>2.7V, Load<1A VIN_SMx VOUT 0.5V (min. 2.5V), mode VIN_SMn>2.7V, Load<1A UNIT VO(SMx)TYP 0.725 1.50 VO(SMx)TYP =1.45 VO(SMx)TYP =3.0 4.55 0.25 SM0, SM1: typical values:Instantaneous, 0.11, 0.22, 0.44, 0.88, 1.76, 3.52, 7.04 VIN_SM
VO(SMx)
KRAMP(SMx)
Voltage change ramp constant
Value I2C, available options:
mV/µs
tStart tRamp RDCH IPFM(ENTER) CSMINP
Start-up time VOUT Ramp time Discharge switch resistance Load current enter mode External capacitor External inductor External Input capacitor
Time start switching, measured from command enabling converter Time ramp from VOUT disabled VIN_SMx 2.9V 5.5V, duty cycle
LDO'S LDO0, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9 Electrical characteristics over output current range IO(LDOx) VINMIN IO(LDOx) Input voltage range Electrical characteristics specified load current 75mA Output current Output Voltage, Selectable I2C. LDO6, LDO0, LDO3, LDO5, LDO7,LDO8,LDO9 LDO1 Output Voltage, Selectable LDO4 Output Voltage, Selectable LDO2 Output Voltage, Selectable V(LDOx) LDOx Output Voltage, Selectable range, 25mV steps High range, 25mV steps range, 25mV steps Available output voltages: V(LDO6)TYP 1.25, 1.5, 1.8, 2.5, 2.7, 2.85, 3.1,3.3 V(LDO1)TYP 0.725 V(LDO4)TYP 2.475 V(LDO2)TYP= 0.725
Dropout, V(IN)= V(LDOx)TYP 0.1V V(IN)=2.3V, 250mA load. active time input group Total accuracy, V(VIN_LDOx)= V(LDOx)TYP 0.5V, 10mA Line Regulation, 100mA load, V(VIN_LDOx): V(LDOx) 0.5V 4.7V Load regulation, load change from 10mA V(VIN_LDOx)> V(LDOx) 0.5V
3.5% 0.5%
-0.5%
PSRR(LDOx) PSRR ISC(LDOx) RDCH(LDOx) KRAMP(LDOx) CCOMP Short circuit current limit Discharge resistor Voltage change ramp constant External output capacitor value Power good threshold PGOOD(LDO) Hysteresis
250mA load, input output 100mA load, 0.5V input output, Output grounded LDOx disabled LDO2, LDO4 only. Fixed value, hardwired level load <100 Stable operation load>100 output voltage increasing Decreasing voltage from increasing trigger
LDOnILIM=HI
7.04
mV/µs
0.01µF/mA, value
Dropout measured devices with V(IN)<2.3V because minimum 2.3V -3.2 (0.105 ILOAD V(LDOX)TYP), ILOAD load current -2.5 (0.105 ILOAD, ILOAD load current
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Electrical Specifications
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
ELECTRICAL CHARACTERISTIC (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER BATTERY VOLTAGE THRESHOLDS CHARGER TIMING TCHGDLY VLOWBAT TDGL(PRE) VRCH TDGL(RCH) Charger turn-off delay Precharge fast-charge transition selectable Time delay turn charger suspend mode Fast charge V(BAT) VLOWBAT Total accuracy, relative selected value Deglitch time fast charge precharge transition Decreasing battery voltage Recharge threshold voltage Deglitch time battery recharge detection charge cycle starts V(BAT) VO(BATREG) VRCH, after termination detected Selectable I2C, 2.9V 2.5V TEST CONDITIONS UNIT
PACK INSERTION PACK TEMPERATURE FAULT DETECTION V(VTSBIAS)>2V KTHOT KTCOLD KNOPACK TDGLTEMP TDGL(DT) TDLY(NDT) RDSTSBIAS ITS(DET) Pack temperature detection constant Pack cold temperature detection constant Pack detected threshold Pack temperature fault/no fault detection deglitch Pack insertion detection deglitch Pack removal detection delay Integrated switch resistance bias current Measured from VTSBIAS V2V2 VTSBIAS V2V2 switch open Pack temp detected charge suspended V(TS) V(2V2) KTHOT Pack cold temp detected charge suspended V(TS) V(2V2) KTCOLD V(TS) V(2V2) KNOPACK 0.189 0.610 0.935 0.203 0.625 0.95 0.222 0.641 0.965
CHARGER INTEGRATED MOSFET CHARACTERISTICS VBATDODCH IDCH(BAT) Battery Switch dropout voltage, discharge charge VBATDODCH V(VIN_CHG) V(BAT) V(BAT) :3V, I(BAT) discharge current battery detected discharge switch enabled (BATDCH=HI), V(BAT)
CHARGER PROTECTION RECOVERY FUNCTIONS VSH(VIN_CHG) VIN_CHG Short Circuit detection threshold VSH(BAT) RSH(BAT) TCHG Short Circuit detection threshold short circuit recovery pull-up resistor BATCHG switch V(VIN_CHG) VSH(VIN_CHG) BATCHG switch V(BAT) VSH(BAT) V(BAT) VSH(BAT), Internal resistor connected between VIN_CHG BAT2 Safety timer value, thermal DPPM loops active function disabled Total accuracy TPRECHG RTMR(FLT) TSTRCHG Precharge timer Timer fault recovery pull-up resistor Charger thermal loop threshold charge timer range, thermal DPPM loops active function disabled TPCH=LO TPCH=HI Selectable I2C: 5,6,8 hours -15% hours
Charge safety timer
Internal resistor connected from VIN_CHG when timer fault detected Charge current reduced TSTRCHG
Electrical Specifications
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TPS658610 Advanced Power Management Unit
ELECTRICAL CHARACTERISTICS
PARAMETER TEST CONDITIONS UNIT
over operating free-air temperature range (unless otherwise noted)
FAST CHARGE CURRENT V(VIN_CHG) V(BAT) 0.2V V(BAT) VLOWBAT, TCHG IO(BAT) Charge current range IO(BAT) KSET/RISET DPPM/Thermal loops active 100% scaling KSET Charge current factor RISET scalable I2C, (ISET_1, ISET_0) scaling scaling scaling CHARGE CURRENT V(VIN_CHG) V(BAT) 0.1V VSH(BAT) V(BAT) VLOWBAT TPRECHG IO(PRECHG) Precharge current range IO(PRECHG) KPRECHG/RISET DPPM/Thermal loops active KPRECHG Precharge current factor 0C<TJ<125°C RISET=I k,scalable I2C, (IPCH_1, IPCH_0)= CHARGE CURRENT REDUCTION THERMAL, DPPM LOOPS ACTIVE TSTRCHG, V(SYS) VSYSDPPM KTHERMAL KDPPM Thermal loop factor DPPM loop factor Charge Current (ICHG) IO(BAT) KTHERM TSTRCHG)/100) Charge Current (ICHG IO(BAT) KDPPM (VSYS(DPPM) V(SYS))) %/°C %/mV 1.03 1020
CHARGE REGULATION VOLTAGE V(VIN_CHG) VO(BATREG) 0.3V RSVD4B4=HI Voltage options, Selection VO(BATREG) Battery charge voltage, selectable Accuracy, 25°C, relative selected value Total Accuracy, relative selected value Total Accuracy range selected value CHARGE TERMINATION, V(BAT) VRCH, TTERM, VOLTAGE REGULATION MODE ITERM Charge termination current range ITERM KTERM/RISET input selected USBMODE=HI 170mA input selected, (USBMODE=LO USBLIM=LO)(2) TDGL(TERM) Deglitch time, termination detection I(BAT) ITERM RSVD4B4=LO 4.3, 4.35, 4.4, 4.45 4.1, 4.15, 4.2, 3.95 -0.55% -0.85 4.16 0.95% 4.25
KTERM
Charge termination detection factor
40mA<ITERM</=170mA, scalable (ITERM_1, ITERM_0)=
CHARGER DPPM LOOP CONTROL VSYS(DPPM DPPM detection threshold selectable Charge current reduced V(SYS)<VSYS(DPPM), VSYS(DPPM) I2C, (SYSDPPM_1, SYSDPPM_0) VSM2TRK output voltage Battery tracking enabled V(BAT)+value 3.413 3.656 4.144 0.17 3.75 4.25 0.265 3.588 3.844 4.356 0.37
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Electrical Specifications
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
ELECTRICAL CHARACTERISTICS
PARAMETER TEST CONDITIONS V(VIN) V(SM3) detected V(SM3) V(OVP3) detected V(SM3) V(OVP3) VHYS(OVP3) V(FB3) below regulation point V(FB3) V(SM3REF) 1.237 VVIN(SM3) 26.5 1.25 1.26 26.5 UNIT
over operating free-air temperature range (unless otherwise noted)
BOOST CONVERTER CONTROL CIRCUIT POWER STAGE VVIN(SM3) VO(SM3) V(OVP3) VHYS(OVP3) Input Voltage range Output voltage range Output over-voltage trip Output over-voltage hysteresis
V(SM3REF)
voltage sense threshold
IO(SM3)
current Current range,
IO(SM3)
V(SM3REF) RFB3
D(SM3SW)
switch duty cycle, selectable switch duty cycle pattern repetition rate, selectable switch on-resistance switch leakage Power stage on-resistance Power stage leakage Power stage current limit Maximum time detection threshold Minimum time detection threshold Output buffer switch resistance Leakage current Maximum switching frequency
Duty cycle range 2048 pulses within repetition rate time, repetition rate Total accuracy, relative F(REP_SM3)TYP V(VIN)=3.8 I(SM3SW)=20 V(VIN)=3.8 I(L3)=200 2.5V< V(IN) <5.5V
D(SM3SW) 99.96%, I2C, 2048 steps 0.05% minimum step F(REP_SM3)TYP 550Hz, 366Hz, 275Hz 220Hz -12%
F(REP_SM3) RDSON(SM3SW) ILKG(SM3SW) RDSON(L3) ILKG(L3) IMAX(L3) TSM3PWR(ON) TSM3PWR(OFF)
HIGH/LOW BRIGHTNESS CONTROL RDSON(ISM3G) ILKG(ISM3G) FSM3 V(VIN)=2.5V, I(ISM3G)=25mA Hi-Z mode, V(ISM3G)=5V nominal load V(GPIOn)=2.5V 1.15 V(GPIOn)=5V GPIO configured, GPIO input current sink TPS658610 sleep mode GPIO configured.
SWITCHING FREQUENCY GPIO1-4 DIGITAL OUTPUT BUFFER VOL(GPIO) VOH(GPIO) IOL(GPIO) IOH(GPIO) VIL(GPIO) VIH(GPIO) ILKG(GPIO) level output voltage High level output voltage GPIO Maximum level sink current
Maximum high level source current V(GPIOn)=0V level input voltage High level input voltage Input current
GPIO1-4 DIGITAL INPUT BUFFER
GPIO1-4 INPUT CURRENT SINK ISNK(GPIO) Input current sink
Electrical Specifications
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TPS658610 Advanced Power Management Unit
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER TEST CONDITIONS UNIT
over operating free-air temperature range (unless otherwise noted)
DRIVER, OPEN DRAIN OUTPUT IPWM F(PWM) D(PWM) ILKG(PWM) Maximum operating current level output voltage driver frequency driver duty cycle Output leakage current driver 100mA V(AVDD6)=3V Frequency range Duty cycle range Output voltage driver
F(PWM)TYP 0.75, 1.5, 2.3, 3.0, 4.5, 6.7,11.7,23.4 D(PWM) 6.25% 100%, I2C, steps, 6.25% minimum step
LED_PWM DRIVER, LED_PWM OPEN DRAIN OUTPUT ILEDPWM D(LEDPWM) VOL(LEDPWM) ILKG(LEDPWM) Maximum operating current driver Duty cycle range, 128Hz repetition rate LED_PWM driver duty cycle Total accuracy, relative selected value level output voltage Output leakage current 50mA V(AVDD6) Output voltage driver D(LEDPWM) 99.6%, I2C, steps, 0.4% minimum step -10%
DRIVER, RED/GREEN/BLUE OPEN DRAIN OUTPUTS TFLASH(RGB) TFLASH(ON) D(RGB) RGB1, RGB2 Flashing period RGB1, RGB2 Flash Time RGB1, RGB2 Duty Cycle Flashing period range Flash time range, value selectable Duty cycle range, value selectable Sink current, ISINK(RGB1) RGB1 output sink current V(RED1) V(GREEN1) V(BLUE1) 0.25V Absolute accuracy relative selected value Relative accuracy between sink current outputs Sink current, ISINK(RGB2) RGB2 output sink current V(RED2) V(GREEN2) V(BLUE2) 0.25V Absolute accuracy relative selected value Relative accuracy between sink current outputs VLO(RGB1) level output voltage Output voltage, RED1/GREEN1/BLUE1 pins, current source 12mA source) time, V(AVDD6)=3V Output voltage, 16mA load, RED2/GREEN2/BLUE2 pins, current source 16mA source) time, V(AVDD6)=3V Output voltage driver TFLASH(RGB) sec, I2C, 0.5sec minimum step, steps I2C, TFLASH(ON) 0.1, 0.15, 0.2, 0.25, 0.3, 0.4, 0.5, D(RGB) 96.875%, I2C, 3.125% minimum step ISINK(RGB1)TYP 3.7, 7.4, 11.1 -20% -10%
ISINK(RGB 3.7, 7.4, 11.1, 14.9, 18.6, 23.2, 27.3, -20% -10%
0.25
VLO(RGB2) ILKG(RGB)
level output voltage Output leakage current
0.25
DIG_PWM DIG_PWM1 DRIVER PUSH PULL OUTPUT Frequency range F(PWM) driver frequency Total accuracy, relative selected value V(DIG_PWM) I(DIG_PWM) VHI(DIGPWM) Output level, V(DIG_PWM) I(DIG_PWM) V(DIG_PWM) I(DIG_PWM) VLO(DIGPWM) Output level, V(DIG_PWM) I(DIG_PWM) -10%
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Electrical Specifications
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
ELECTRICAL CHARACTERISTICS
PARAMETER TEST CONDITIONS 25°C Over full temp range V(ADC_REF)=AGND1 2.595 2.577 2.595 2.605 2.607 UNIT
over operating free-air temperature range (unless otherwise noted)
REFERENCE VREF(ADC) ISHRT(ADCREF) CREFADC Internal reference voltage Internal reference short circuit limit Maximum capacitance internal reference supply Full scale input range Channels Full scale input range Channels Full scale input range Channels Input capacitance (all channels) Input resistance (all channels) AVDD6-V(ANLG) 500mV disabled None None Deviation from first code transition (00.00) (00.001) ideal AGND 1LSB None Positive inputs, Full scale 2.60 Positive inputs, Full scale 4.622 Positive inputs Full scale 5.54
ANALOG INPUTS VRNG(CH1_6) VRNG(CH7_10) VRNG(CH8_9) CIN(ADC) RINADC(CH1_6) VREF(ADC) VREF(ADC) 1.78 VREF(ADC) 2.13 Bits
ILKGADC(CH1_6) Leakage current (all channels) ACCURACY RES(ADC) MCD(ADC) INL(ADC) DNL(ADC) Resolution Missing codes Integral Linearity Error Differential non-linearity error
OFFZERO(ADC) Offset error
OFFCH(ADC) GAIN(ADC) GAINCH(ADC) ADCCLK ADCTCONV
Offset error match between channels Gain error Gain error match Sampling Clock Sampling conversion time Sampling time ADCCLK conversion settling time -11X ADCCLK Deviation code from ideal full scale code (11.111) full scale voltage channels
THROUGHPUT SPEED
ANLGx (USER_DEFINED INPUTS) BIAS CURRENTS I(ANLGx) ANLG1, internal pull-up current source channel bias current, register ADC_WAIT bits (ADICH2_1, ADICH2_2) Total Accuracy -20%
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TPS658610 Advanced Power Management Unit
DESCRIPTION, REQUIRED EXTERNAL COMPONENTS 2.9.1 Package Pinout (TOP VIEW)
NAME
DESCRIPTION
EXTERNAL REQUIRED COMPONENTS (See Application Diagram) 1uF(minimum) capacitor AGND1 minimize over-voltage transients during power hot-plug events. 1µF(minimum) capacitor AGND1 pin, minimize over-voltage transients during power hot-plug events. Connect battery positive terminal. Connect 4.7µF capacitor (minimum) from BAT2 clean analog ground plane 10µF capacitor AGND1
SYSTEM POWER PATH A11, C10, D11, A10, Adapter Charge Input Voltage, connect AC_DC adapter positive output terminal voltage) charge input voltage, connect port positive power output Battery power
AC/BAT/USB Power path output. Connect System main power rail (system power bus) NOPOWER pulse width Internal supply rail
REFERENCE SYSTEM TNOPOWER AVDD6 Capacitor AGND1. Capacitor value sets pulse width Connect 4.7µF capacitor AGND1 Electrical Specifications
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NAME V2V2 1V25 CHARGER ISET VTSBIAS VIN_CHG CHG_STAT FLTDPPM
F10,
DESCRIPTION Internal 2.2V supply rail Internal 1.25V reference filter capacitor Temperature Sense Input, current source output Current point when charging with selected. Thermistor network bias supply, internally connected integrated switch Charger supply. Charger Status DPPM loop filter capacitor Drain integrated boost power stage switch White duty cycle switch output, current setting Integrated White duty cycle switch input General purpose input/output White driver output over-voltage detection Power ground, converter Programmable driver, open drain output, current sink output when active.
EXTERNAL REQUIRED COMPONENTS (See Application Diagram) (minimum) decoupling capacitor AGND1 100nF (minimum) decoupling AGND1 Connect battery pack thermistor sense battery pack temperature External resistor from ISET AGND1 sets charge current value Connect external thermistor pull-up resistor Connect converter output pin, charger section Push-pull output, level used, should left open 4.7µH inductor pin, external Schottky diode External resistor from PGND3 sets peak current. Connect 100pF (minimum) filter capacitor PGND3 pin.
BOOST CONVERTER
SM3_SW SM3IG PGND3 DRIVERS RED2 GREEN2 BLUE2 RED1 GREEN1 BLUE1 LED_PWM DIG_PWM DIG_PWM2 VIN_SM0 PGND0 VIN_SM1 PGND1
HI-Z Output, controlled I2C. used current gain step, implementing high/low brightness control Connect capacitor PGND3 pin. Connect positive side white ladder. Connect power ground plane Connect input Connect GREEN input Connect BLUE input Connect input Connect GREEN input Connect BLUE input
LED_PWM driver output, open drain, programmable duty cycle. DRIVER, open drain output PWM, digital push-pull output PWM, digital push-pull output synchronous buck converter positive supply input synchronous buck converter output voltage sense synchronous buck converter power stage output Power ground, converter synchronous buck converter positive supply input synchronous buck converter output voltage sense synchronous buck converter power stage output Power ground, converter
used drive keyboard backlight other external functions used control external vibrator motor output voltage level output voltage level 10µF capacitor PGND0 filter: 1.5µH Inductor 10µF Capacitor.Connect capacitor PGND0 1.5µH inductor Connect power ground plane 10µF capacitor PGND1 filter: 1.5µH Inducto 10µF Capacitor.Connect capacitor PGND1 1.5µH inductor Connect power ground plane Submit Documentation Feedback
DC/DC CONVERTERS
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TPS658610 Advanced Power Management Unit
NAME VIN_SM2 PGND2 AGND2 ANLG1 ANLG2 ANLG3 ADC_REF
DESCRIPTION synchronous buck converter positive supply input synchronous buck converter output voltage sense synchronous buck converter power stage output Power ground pin, converter Analog ground, subsystem Analog input1 ADC, programmable current source output
EXTERNAL REQUIRED COMPONENTS (See Application Diagram) 10µF capacitor PGND2 filter: 1.5µH Inductor, 10µF Capacitor.Connect capacitor PGND2 1.5µH inductor Connect power ground plane Connect analog ground plane used monitor additional system pack parameters
internal reference filter external reference input Power supply host interface buffers Interruption nINT when interrupt requested TPS658XX. 32kHz clock from external XTAL Host reset output, level, adjustable width RTC_OUT pulse, level, fixed width Reboot cycle request Sleep on/off request LDO4 enable control Supply enable control Supply enable control Supply enable control Power clock line interface data line interface clock line Xtal oscillator
Connect maximum capacitance 6.8uF referenced AGND2 pin.
EXTERNAL SYSTEM RESET CLOCK OUTPUTS, ADJUSTABLE LEVEL V32K OUT32K NOPOWER NORTC HOT_RST RESUME LDO4EN SM0EN (CORECTRL) SM1EN SYNCEN INTERFACE PSDAT PSCLK SDAT SCLK XTAL1 XTAL2 INPUT OUTPUT GPIO1 GPIO2 GPIO3 GPIO4 COMP SM0PG SM1PG LDO4PG General purpose comparator input, input power good status power good status LDO4 power good status General purpose input/output General purpose input/output Input: SM0, SM1, power saving mode output voltage setting control Input: external trigger LDO0, LDO1 enable Input: LDO2, LDO3 enable Input: external trigger LDO6, LDO7, LDO8 enable Connect external host power clock. Connect external pull-up resistor. Connect used Connect external pull-up resistor.
Open drain output Push-pull output, V32K level
SEQUENCING CONTROL INPUTS Hardware reboot cycle control Hardware sleep on/off control Active signal.
OSCILLATOR Connect external xtal
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TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
NAME
DESCRIPTION
EXTERNAL REQUIRED COMPONENTS (See Application Diagram) (minimum) decoupling capacitor AGND1 1µF(minimum) capacitor AGND1 1µF(minimum) capacitor AGND1 (minimum) decoupling capacitor AGND1 1µF(minimum) capacitor AGND1 1µF(minimum) capacitor AGND1 (minimum) decoupling capacitor AGND1 1µF(minimum) capacitor AGND1 1µF(minimum) capacitor AGND1 (minimum) decoupling capacitor AGND1 1µF(minimum) capacitor AGND1 1µF(minimum) capacitor AGND1 1µF(minimum) capacitor AGND1 (minimum) decoupling capacitor AGND1 1µF(minimum) capacitor AGND1 (minimum) capacitor AGND1 supercap
LINEAR REGULATORS VIN_LDO01 LDO0 LDO1 VIN_LDO23 LDO2 LDO3 VIN_LDO4 LDO4 LDO5 VIN_LDO678 LDO6 LDO7 LDO8 VIN_LDO9 LDO9 RTC_OUT Positive supply input LDO0, LDO1 LDO0 output LDO1 output Positive supply input LDO2, LDO3 LDO2 output LDO3 output Positive supply input LDO4 LDO4 output LDO5output Positive supply input LDO0, LDO1 LDO6 output LDO7 output LDO8 output Positive supply input LDO9 LDO9 output leakage output. connected super-capacitor secondary cell, used backup output. Digital ground Analog ground Analog ground Digital ground
ANALOG DIGITAL GROUND PINS DGND1 AGND1 AGND3 DGND2DT Packag Drawing Connect digital ground plane Connect analog ground plane Connect analog ground plane Connect analog ground plane
There internal electrical connection between PINS pins must connected same potential AGND1 printed circuit board. pins primary ground input
Electrical Specifications
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TPS658610 Advanced Power Management Unit
2.9.2
BLOCK DIAGRAM
TNOPOWER AVDD6 1V25 FLTDPPM LED_PWM DIGPWM BLUE2 ISET VTSBIAS VIN_CHG GREEN2 RED2 BLUE1 GREEN1 RED1 DIGPWM2
VINLDO9 LDO9 SM3IG WHITE DRIVER SM3_SW PGND3 VIN_SM0 PGND0 VIN_SM1 PGND1 VIN_SM2 PGND2 ANLG1 ANLG2 ANLG3 COMP ADC_REF AGND2 RTC_OUT AGND1 AGND3 COMP HOST INTERFACE SEQUENCING INTERFACE INTERRUPT CONTROLLER
TPS6586x
PROCESSOR POWER PATH, INPUT CURRENT LIMIT, REFSYS VINLDO678 LDO6
LINEAR CHARGER
DRIVERS
LDO6 1.25-3.3V LDO7 1.25-3.3V LDO8 1.25-3.3V
LDO9 1.25-3.3V
LDO7
LDO8
RTC_OUT
RTC_OUT 1.25-3.3V
LDO5
LDO5 1.25-3.3V
0.725 1.5V 31x25mv steps, 1.45 3.0V, 31x50mV steps Peak 0.4A 1.2A
VINLDO4 LDO4
LDO4 1.7-2.475V, 1.7-2.0V, 31X25mV steps,
CONTROL LOGIC
0.725 1.5V 31x25mv steps, 1.45 3.0V, 31x50mV steps Peak 0.4A 1.2A 2.475V 31x25mv steps 4.55V 31x50mV steps, VBAT+0.265v, Peak 0.4A 1.6A
INTERNAL CHANNELS
VINLDO23
LDO2
LDO2 0.725-1.5V 31x25mV steps, 1.25V-2.586V, 31x43mV steps LDO3 1.25-3.3V
LDO3
VINLDO01 LDO0
LDO0 1.25-3.3V LDO1 0.725 -1.5V 31x25mV steps, 1.25 2.586V, 31X43mV steps
CHANNEL
LDO1
CONVERTER
DGND1 DGND2DT
SEQUENCING RESET CONTROLLER
SYNCEN
HOTRST
LDO4PG
SM0EN
SM1EN
SM0PG SM1PG
SCLK
SDAT
GPIO1 GPIO2 GPIO3 GPIO4
XTAL1
NOPOWER 32KOUT
PSDAT PSCLK
NORTC
CHG_STAT
RESUME
LDO4EN
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V32K
XTAL2
Electrical Specifications
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
2.10 TYPICAL CHARACTERISTICS
LDO9 Vout Iout (Temp. 25°C) 1.250V 1.28 1.27 1.26 3.30
LDO9 Vout Iout (Temp. 25°C) 3.30V 3.40
3.35
1.25
Vout
1.24 1.23 1.22 1.21 1.20 0.10 Vin=2.3v, Ta=25C Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C
3.25
3.20
Vin=Vout 0.5, Ta=25C Vin=4.65v, Ta=25C
3.15
Vin=5.5v, Ta=25C
1.00
10.00 Iout [ma]
100.00
1000.00
3.10 0.10
1.00
10.00 Iout [ma]
100.00
1000.00
Figure 2-1.
LDO0 Vout Iout (Temp. 25°C) 1.250V 1.28 1.27 3.35 1.26 3.30 1.25 Vout Vout 1.24 1.23 1.22 1.21 1.20 0.10 3.10 1.00 10.00 Iout [ma] 100.00 1000.00 0.10 1.00 Vin=2.3v, Ta=25C Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C 3.15 3.25 3.40
Figure 2-2.
LDO0 Vout Iout (Temp. 25°C) 3.30V
Vin=Vout 0.5, Ta=25C 3.20 Vin=4.65v, Ta=25C Vin=5.5v, Ta=25C
10.00 Iout [ma]
100.00
1000.00
Figure 2-3.
Figure 2-4.
Electrical Specifications
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TPS658610 Advanced Power Management Unit
LDO1 Vout Iout (Temp. 25°C) Range 0.75 0.74 0.73 0.72 2.64 2.62 2.60
Vout
LDO1 Vout Iout (Temp. 25°C) High Range
Vout
0.71 0.70 0.69 Vin=2.3v, Ta=25C 0.68 0.67 0.66 0.10 Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C
2.58 2.56 2.54 2.52 2.50 Vin=Vout+0.5, Ta=25C Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C
1.00
10.00 Iout [ma]
100.00
1000.00
0.10
1.00
10.00 Iout [ma]
100.00
1000.00
Figure 2-5.
LDO2 Vout Iout (Temp. 25°C) Range 0.75 0.74 0.73 0.72
Vout
Figure 2-6.
LDO2 Vout Iout (Temp. 25°C) High Range 2.65
2.63
0.70 0.69 0.68 0.67 0.66 0.10 1.00 10.00 Iout [ma] 100.00 1000.00 Vin=2.3v, Ta=25C Vin=3.9v, Ta=25C] Vin=5.5, Ta=25C
Vout
0.71
2.61
2.59 Vin=Vout+0.5v, Ta=25C 2.57 Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C 2.55 0.10 1.00 10.00 Iout [ma] 100.00 1000.00
Figure 2-7.
Figure 2-8.
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Electrical Specifications
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
LDO3 Vout Iout (Temp. 25°C) 1.250V 1.28 1.27 1.26 3.30
LDO3 Vout Iout (Temp. 25°C) 3.30V 3.40
3.35
1.25
Vout
1.24 1.23 1.22 1.21 1.20 0.10 Vin=2.3v, Ta=25C Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C
3.25
3.20 Vin=Vout 0.5, Ta=25C 3.15 Vin=4.65v, Ta=25C Vin=5.5v, Ta=25C 3.10
1.00
10.00 Iout [ma]
100.00
1000.00
0.10
1.00
10.00 Iout [ma]
100.00
1000.00
Figure 2-9.
LDO4 Vout Iout (Temp. 25°C) 1.700V 1.74 2.54
Figure 2-10.
LDO4 Vout Iout (Temp. 25°C) 2.475V
1.73
2.52
Vout
2.50 1.72
Vout
2.48 Vin=Vout 0.5, Ta=25C Vin=4.65v, Ta=25C 2.46 Vin=5.5v, Ta=25C
Vin=2.3v, Ta=25C 1.71 Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C 1.70 0.10
1.00
10.00 Iout
100.00
1000.00
2.44 0.10
1.00
10.00 Iout [ma]
100.00
1000.00
Figure 2-11.
Figure 2-12.
Electrical Specifications
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TPS658610 Advanced Power Management Unit
LDO5 Vout Iout (Temp. 25°C) 1.250V 1.28 1.27 1.26 3.30
LDO5 Vout Iout (Temp. 25°C) 3.30V 3.40
3.35
1.25
1.24 1.23 1.22 1.21 1.20 0.10 Vin=2.3v, Ta=25C Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C
3.25
3.20 Vin=Vout 0.5, Ta=25C Vin=4.65v, Ta=25C 3.15 Vin=5.5v, Ta=25C
3.10 1.00 10.00 Iout [ma] 100.00 1000.00 0.10 1.00 10.00 Iout [ma] 100.00 1000.00
Figure 2-13.
LDO6 Vout Iout (Temp. 25°C) 1.250V 1.28 1.27 3.35 1.26 1.25 1.24 1.23 1.22 1.21 1.20 0.10 1.00 10.00 Iout [ma] 100.00 1000.00 3.30 3.40
Figure 2-14.
LDO6 Vout Iout (Temp. 25°C) 3.30V
Vout
Vin=2.3v, Ta=25C Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C
Vout
3.25
3.20
Vin=Vout 0.5, Ta=25C Vin=4.65v, Ta=25C Vin=5.5v, Ta=25C
3.15
3.10 0.10 1.00 10.00 Iout [ma] 100.00 1000.00
Figure 2-15.
Figure 2-16.
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TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
.250V LDO7 Vout Iout (Temp. 25°C) 1.28 1.27 3.35 1.26 1.25 1.24 1.23 1.22 1.21 1.20 0.10 1.00 10.00 Iout [ma] 100.00 1000.00 Vin=2.3v, Ta=25C Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C 3.15 3.20 3.30 3.40
LDO7 Vout Iout (Temp. 25°C) 3.30V
Vout
Vout
3.25 Vin=Vout 0.5, Ta=25C Vin=4.65v, Ta=25C Vin=5.5v, Ta=25C
3.10 0.10
1.00
10.00 Iout [ma]
100.00
1000.00
Figure 2-17.
LDO8 Vout Iout (Temp. 25°C) 1.250V 1.28 1.27 3.35 1.26 1.25 3.30 3.40
Figure 2-18.
LDO8 Vout Iout (Temp. 25°C) 3.30V
Vout
Vout
1.24 1.23 1.22 1.21 1.20 0.10 Vin=2.3v, Ta=25C Vin=3.9v, Ta=25C Vin=5.5v, Ta=25C
3.25
3.20
Vin=Vout 0.5, Ta=25C Vin=4.65v, Ta=25C Vin=5.5v, Ta=25C
3.15
1.00
10.00 Iout [ma]
100.00
1000.00
3.10 0.10
1.00
10.00 Iout [ma]
100.00
1000.00
Figure 2-19.
Figure 2-20.
Electrical Specifications
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TPS658610 Advanced Power Management Unit
LDO2 0.725V DropOut 25°C 0.80 0.78 0.76 0.74
LDO0 1.25V DropOut 25°C 1.40 1.30 1.20 1.10 1.00 0.90 0.70 0.68 0.80 0.70 0.60 Temp. 25°C Iout Temp. 25°C Iout 100mA Temp. 25°C Iout 250mA 0.50 0.40 0.30 0.20 0.10 0.00 2.30 2.20 2.10 2.00 1.90 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00
Temp 25°C Iout Temp 25°C Iout 100mA Temp 25°C Iout =250mA
0.66 0.64 0.62
2.20
2.00
1.80
1.60
1.40
1.20
0.60 1.00
Figure 2-21.
LDO0 3.3V DropOut 25°C 3.50 3.40 3.30 3.20 3.10 3.00
Vout
Figure 2-22.
Efficiency Auto Vout 1.8V 25°C
Efficiency
2.90 2.80 2.70 2.60 Temp. 25°C Iout Temp. 25°C Iout 100mA Temp. 25°C Iout 250mA 2.50 2.40 2.30 2.20 2.10
0.0001
2.00 3.80 3.70 3.60 3.50 3.40 3.30 3.20 3.10 3.00 2.90 2.80 2.70 2.60 2.50
Vout
0.001
0.01 Iout
10.0
Figure 2-23.
Figure 2-24.
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Electrical Specifications
Vout
0.72
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
Efficiency Vout 1.8V 25°C
Efficiency Auto Vout 1.25V 25°C
Efficiency
Efficiency
0.00010
0.00100
0.10000 0.01000 Iout
1.00000
10.00000
0.00010
0.00100
0.01000 0.10000 Iout
1.00000
10.00000
Figure 2-25.
Efficiency Vout 1.250V 25°C
Figure 2-26.
Efficiency Auto Vout 3.25V 25°C
Efficiency
0.0001
Efficiency
0.001 0.01 Iout 10.0 0.001 0.01 0.10 Iout 10.0
Figure 2-27.
Figure 2-28.
Electrical Specifications
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TPS658610 Advanced Power Management Unit
Efficiency Vout 3.25V 25°C
Efficiency
0.0001 0.001 0.01 Iout
10.0
Figure 2-29.
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TPS658610 Advanced Power Management Unit
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DETAILED DESCRIPTION
INTERFACE
configurations implemented TPS658610 device: -Standard interface (SDAT/SCLK engine) single communication port provides simple compatible host access system status information, reset fault modes, supply output voltages. port functions SLAVE enabling compatible hosts (MASTER) perform WRITES READS to/from internal registers. port 2-wire bidirectional interface using SCLK (clock) SDAT (data) pins. designed operate SCLK frequencies kHz. standard command supported. part sequence register address read write. Power interface (PSDAT/PSCLK engine): TPS658610 supports processors that dedicated dynamically adjust critical supply voltages adding second (Power I2C) connected second, dedicated engine. Power port 2-wire bidirectional interface using PSCLK (clock) PSDAT (data) pins. Power designed operate PSCLK frequencies kHz. multiple-byte data-register pair command protocol, compatible with standard protocol, supported Power engine. Power engine does support read operations.
NOTE Standard Power engines always reset sequencer when TPS658610 POWER-UP state when SLEEP state set.
ADDRESS
TPS658610 will acknowledge (ACK) addresses 0x68 (writes) 0x69 (reads) will NACK other address.
REGISTER ACCESS
sequencer state machine disables write access specific supply voltage setting registers when TPS658610 initially powered when integrated supplies being sequenced. sequencer functional description details.
SCLK/SDAT PSCLK/PSDAT TIMEOUT
TPS658610 monitors SCLK/PSCLK clock lines, identifies timeout condition clock line held logic longer than 30ms. engine reset when clock line timeout identified. TPS658610 monitors SDAT/PSDAT data lines. engine will reset when data line held logic more than 30ms.
RELEASE
TPS658610 engine does create START STOP states during normal operation.
ERROR RECOVERY
specification does define method used when recovering from host side error. During read operation SDAT left state host sent enough SCLK pulses complete transaction (i.e. host side error). TPS658610 will clear SDAT condition SCLK pulses sent host, enabling recovery from host side error events.
DETAILED DESCRIPTION
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TPS658610 Advanced Power Management Unit
COMMUNICATION PROTOCOL
following conventions will used when describing communication protocol:
CONDITION START sent from host STOP sent from host TPS658610 slave address sent from host (WRITE) TPS658610 register address sent from TPS658610 (READ) Non-valid slave address sent from host Valid TPS658610 register address sent from host Non-valid TPS658610 register address sent from host data byte bits) sent from host TPS658610 data byte bits) sent from TPS658610 host Acknowledge (ACK) from host acknowledge (NACK) from host Acknowledge (ACK) from TPS658610 acknowledge (NACK) from TPS658610
CODE hA_N HCMD HCMD_N hDATA bqDATA
Figure 3-1. Conditions normal data transfers, data line (SDAT PSDAT) allowed change only when clock line (SCLK PSCLK) low, clock pulse used data. data line must remain stable whenever clock line high, data changes when clock high reserved indicating start stop conditions. Each data transfer initiated with start condition terminated with stop condition. When addressed, TPS658610 device generates acknowledge after reception each byte pulling data line Low. master device (microprocessor) must generate extra clock pulse that associated with acknowledge bit. After acknowledge/not acknowledge bit, TPS658610 leaves data line high, enabling STOP condition generation.
READ WRITE OPERATIONS
TPS658610 supports standard byte Write. basic read protocol following steps: Host sends start sends TPS658610 address
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TPS658610 ACK's that this valid address that configured write Host sends TPS658610 register address TPS658610 ACK's that this valid register stores register address read Host sends repeated start TPS658610 slave address, reconfiguring read TPS658610 ACK's that this valid address that reconfigured read mode, TPS658610 starts sending data from selected register
write protocol similar read, without need repeated start being write mode. WRITE, necessary each byte WRITE command with STOP START will have same effect (repeated start). host complete READ WRITE sequence with either STOP START.
NOTE Read operations supported PSDAT/PSCLK engine.
Figure 3-2. Read/Write Example
VALID WRITE SEQUENCES (SDAT/SCLK, PSDAT/PSCLK)
TPS658610 will always address. points allowable READ WRITE address, device writes address into address register sends ACK. points non-allowed address, device does write address into address register sends NACK.
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hCMD
hCMD_N
3.10 BYTE WRITE (SDAT/SCLK, PSDAT/PSCLK)
data written addressed register ACK, ending byte write sequence when address data byte stored registers. host cancel WRITE sending STOP START before trailing edge clock pulse.
hCMD
hDATA
3.11 VALID READ SEQUENCES (SDAT/SCLK ONLY)
TPS658610 will always address.
Upon receiving hA1, TPS658610 starts current location address register. START STOP both priority interrupts. host been interrupted sure where left off, send STOP reset TPS658610 state machine WAIT state; once WAIT state, TPS658610 will ignore activity SCLK SDAT lines until receives START. repeated START START specification both treated START.
hCMD
hCMD
bqDATA
3.12 VALID READ SEQUENCES (SDAT/SCLK ONLY)
bqDATA
Incremental read sequences
bqData bqDATA bqDATA
3.13 NON-VALID SEQUENCES
START non-hA0 non-hA1 Address: START followed address which will NACKED.
hA_1
Attempt Specify Non-Allowed READ Address points non-allowed READ address (reserved registers), will send NACK back host will load address address register. Note that TPS658610 NACKS whether stop sent not.
hCMD_N hCMD_N
Attempt Specify Non-Allowed WRITE Address host attempts WRITE READ-ONLY non-accessible address, TPS658610 ACKS containing allowed READ address, loads address into address register ACKS after host sends next data byte. subsequent READ could read this address, data sent host will have been written.
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hCMD
hDATA
3.14 INCREMENTAL READ (SDAT/SCLK ONLY)
SDAT/SCLK interface supports incremental read operations. Each register must accessed single read operation. valid WRITE address required write RAM, valid READ address required specify initial address where READ starts. Once read command received, data specified address output host. host chooses, loop through remaining addresses; address automatically incremented each read. loop gets address, automatically rolls over address 0x00 sequence stops.
3.15 COMMUNICATION PROTOCOL POWER INTERFACE, PINS PSDAT/PSCLK
Power interface designed support fast write operations using multiple register-data pair sequences. Power engine write-only engine, does support read operations. During write sequence, host sends start command, followed TPS658610 address. Then host sends register address byte, followed eight bits data respective register (Register1 Address/Data Figure 3-3). From this point TPS658610 will accept following byte pairs random register address, followed data content written that register. This process continues until host sends valid stop condition after last register (Register Figure 3-3) written. typical multi-byte sequence shown Figure 3-3.
Figure 3-3. Power Protocol
3.16 SIMULTANEOUS STANDARD POWER OPERATION
TPS658610 individual address pointers Power engine Standard engine. value written register will defined relative timing between read/write pulses when simultaneous read/write operations happen. Simultaneous write/read operations same register will handled follows: Both Standard Power executing operations accessing distinct registers same time (simultaneous read/read, read/write, write/read write/write): conflict exists this case. Power writes Standard reads same register same time Standard will read register value Standard read pulse generated least 110nsec (typ) before Power write pulse happens. Standard will read register value Standard read pulse generated least 110nsec (typ) after Power write pulse happens. Power Standard write same register same time both write operations more than 110nsec (typ) apart, register final value will engine that executes last write operation. both write operations less than 110nsec (typ) apart, priority will given Power engine. value from Power engine will written into register, data received Standard operation written TPS658610 internal memory.
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THERE CLOCK STRETCH FUNCTION EITHER SCLK PSCLK WHEN CONFLICT SITUATION HAPPENS. CONFLICT HANDLED INTERNALLY GIVING PRIORITY PSDAT/PSCLK ENGINE.
3.17 POWER PATH 3.17.1 CONTROL BITS
power path circuit connects power sources plugged into pins pin. supply selection made based system parameters monitored power path circuit internal control bits register 0x4C. Table 3-1. Power Path Control
PPATH1 [Addr 0x4C] Number Name Function USBSUSP SUSPEND MODE SUSPEND USBDCH SPARE ACDCH SPARE RSVD4B4 BOOTOFF USBLIMIT INPUT CURRENT LIMIT SETTING 100mA USBMODE INPUT CURRENT LIMIT USBLIMIT Defaults BOLD PWRSYS AUTO POWER SELECTION AUTO MODE ENABLED
CHARGE INPUT ILIMIT VOLTAGE RANGE BOOT PHASE 3.95V-4.2V USBLIMIT ONLY USBMODE USBLIMIT
When
USED
USED
When
SUSPEND
USED
USED
4.3V-4.45V
500mA
2.25
input power priority hard-wired internally, with input having higher priority, followed input (2nd) battery pack (3rd). voltage regulated will equal input voltage (AC, value) minus voltage drop across switch that when selected input current limit active. Setting control PWRSYS (bit user override power path priority, connecting battery even detected. When PWRSYS battery removed, will connected back inputs thereby will discharge ground. power will ignored when USBSUSP (bit connecting only power sources pin. neither connected pin, will discharge ground. input current limited maximum value programmed host interface setting bits USBLIMIT (bit USBMODE (bit shown Table 3-2. Table 3-2. Power Path Current Limit
USBMODE USBLIMIT INPUT CURRENT LIMIT 2.1A INPUT CURRENT LIMIT
system current requirements exceed input current limit, voltage will reduced until power path supplement mode pack connected).
3.18 SYSTEM STATUS DETECTION
TPS658610 integrated comparators that monitor BAT, voltages. data generated comparators used power path control logic define which integrated power path switches will active. Table lists system power detection conditions:
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Table 3-3. Power Path Detection Functions
SYSTEM STATUS input voltage detected input voltage detected over-voltage detected over-voltage detected short detected Battery switch over-current detection Supplement mode detection DETECTION CONDITIONS VIN(OVP) V(AC) V(BAT) VIN(DT) VIN(OVP) V(USB) V(BAT) VIN(DT) V(AC) VIN(OVP) V(USB) VIN(OVP) V(SYS) VSH(SYS) I(BAT) IBATSYS V(SYS)<V(BAT)-VSUP(SYS) I(BAT)< IBATSYS
VIN(DT), VSH(SYS), VBATSH, VIN(OVP), VSUP(SYS) TPS658610 internal references, refer electrical characteristics additional details
Figure 3-4. Simplified Power Path Block control bits system status used power path control logic define state power path switches shown below; fault condition will detected when shorted battery switch over-current condition detected.
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Table 3-4. Power Path Control
Detected 6586x MODE UVLO UVLO UVLO UVLO UVLO UVLO UVLO PWRSYS USBSUSP Detected FAULT Detecte Switch Switch BATTERY Switch CONNECTED NONE PULL-UP RES/ISRC BATTERY BATTERY BATTERY
Supplement mode required, otherwise
When fault condition detected, fault recovery method (resistor current source) defined input power supply detection: Table 3-5. Power Path Fault Recovery Control
DETECTED DETECTED RECOVERY METHOD PULL-UP RESISTOR PULL-UP RESISTOR 30mA CURRENT SOURCE
3.19 POWER PATH STATUS
power path status available register 0xB9, bits BATSYSON, ACSWON, USBSWON register 0xBB, bits LOWSYS, ACDET, USBDET, AC_OVP USB_OVP. STATUS REGISTER section function description.
3.20 BATTERY CHARGER
TPS658610 integrated linear charger that designed enable implementation distinct configurations. TPS658610 been configured such that Charger input power supplied output. this mode, acts pre-regulator charger input. Charger active when device SLEEP state. Charger input power supplied power path output voltage voltage programmed host register SUPPLYV2 control bits VSM2[4:0] times. charger input VIN_CHG must connected power path output pin. This topology lower efficiency when compared pre-regulator configuration, enables stand alone converter systems where lower charge rates required.
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Figure 3-5. Linear Charger Configured Stand-Alone acting pre-regulator linear charger input: charger internal control logic configured work together such that during fast charge, voltage down-converted VBAT+ 0.26V (typ), tracking battery voltage increases during charge process This topology achieves overall efficiency close switched mode charger topology. When system battery power operation, pre-charge thermistor removed, tracking mode disabled down converts battery voltage voltage programmed host register SUPPLYV2 control bits VSM2[4:0]. When charger configured turn sleep mode, output voltage should using SUPPLY2 control bits VSM2[4:0] voltage 250mV (typ) above charge regulation voltage.
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Figure 3-6. Linear Charger Configured with Pre-Regulator
3.21 OPERATING MODES
TPS658610 supports charging single-cell Li-Ion Li-Pol battery packs. charge process executed three phases: pre-charge pre-conditioning), constant current constant voltage. Protection circuits reduce charge current when junction temperature exceeds 125°C (typ, thermal loop), when voltage drops below user-selectable threshold (DPPM loop). When charger enabled, control loops limit current programmed charge current value (charge current loop) regulates voltage programmed charge voltage value (charge voltage loop). V(BAT) VLOWBAT, current internally programmed pre-charge current value. typical charge profile shown below, operation condition when thermal DPPM loops active. operating conditions cause junction temperature exceed 125°C voltage collapses, charge cycle modified, with activation additional control loops. DPPM thermal loops will override other charger control loops reduce charge current. modified charge cycle, with thermal DPPM loop active, shown Figure Figure 3-8.
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Figure 3-7. Charge Phases Without Thermal Foldback
Figure 3-8. Charge Phases With Thermal Foldback
3.22 DETECTING SYSTEM STATUS
TPS658610 integrated comparators that monitor voltages BAT, VIN_CHG pins, well charge current. data generated those comparators used control logic detect fault conditions control operation. Table lists system power detection conditions. VSH(VIN_CHG), VLOWBAT, VSH(BAT) TPS658610 internal references (refer electrical characteristics additional details). Table 3-6. System Status Detection Conditions
STATUS VIN_CHG short detected Battery voltage below pre-charge threshold Battery short detected DETECTION REQUIREMENTS V(VIN_CHG) VSH(VIN_CHG) V(BAT) VLOWBAT V(BAT) VSH(BAT)
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DPPM THERMAL CONTROL VIN_CHG TSON VISET DCHGOFF
VTSBIAS
VTSBIAS
VIN_CHG
DBATRON
0.95 VTSBIAS
NOBAT COMP
CHARGE CURRENT
BATCHG SWITCH
Charge Current Loop IO(BAT)
COMP 0.625*VTSBIAS COLD
DISRCON
VBAT
VBAT CHARGE VOLTAGE TERM
Charge Voltage Loop
IO(BAT) K(SET)
VISET
ISET
0.203*VTSBIAS COMP
VBATVSUP(BATCHG) SUPPLEMENT
DBATDCH DISRCON DBATRON DCHGOFF VBAT-VOC(VINCHG) BATOC COMP
DBATDCH
V(VINCHG)
COMP
V(VINCHG)
TERMINATION CURRENT VISET PRE-CHARGE VOLTAGE VBAT COMP COMP
TERM
VINSHORT
CHARGE CONTROL LOGIC
VSH(VINCHG) V(VINCHG) VO(BATREG) VRCH
COMP
PRECHG
RECHARGE VBAT BATSHORT
VSH(BAT)
VBAT
Figure 3-9. Simplified Charger Block Diagram
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3.23 CHARGER REGISTERS
charger control bits that enable user configuration multiple charger parameters, shown below: Table 3-7. Charger control
CHG1 [Addr 0x49] Number Name Function CHGTMR[1] CHTMR[0] BATDCH BATTERY DISCHARGE SWITCH ENABLED TSON THERMISTOR BIAS CONTROL ISET[1] ISET[0] TERMOFF CHARGE TERMINATION STATE TERM TERM Defaults BOLD CHSUSP SUSPEND CHARGE SUSPENDED SUSPENDED Defaults BOLD DTCON DYNAMIC TIMER FUNCTION VPCHG PRE-CHARGE VOLTAGE 2.5V 2.9V TSBYP ENABLE CHARGER MODE CHTMREN CHARGE SAFETY TIMER VCHG[1] VCHG[0] CHGON[1] CHARGER ON/OFF CHARGE ENABLE TABLE CHBOOT CHARGER OPERATION DURING BOOT Defaults BOLD CHGON[0] CHARGER ON/OFF CHARGE ENABLE TABLE SYSDPPM[1] SYSDPPM[0] TPCHG PRE-CHARGE TIMER SCALING ITERM[1] ITERM[0] IPCHG[1] IPCHG[0]
CHARGE SAFETY TIMER VALUE
CHARGE CURRENT SCALING FACTOR 0.25 0.75 0.50 1.00
When When CHG2 [Addr 0x4A] Number Name
Function
CHARGE VOLTAGE SELECTION VCHG SETTING TABLE VCHG SETTING TABLE
When When CHG3 [Addr 0x4B] Number Name Function When When
SYSTEM POWER PATH DPPM THRESHOLD 00=3.5V 01=3.75V 10=4.0V 11=4.25V
TERMINATION CURRENT FACTOR 00=0.04 01=0.10 10=0.15 11=0.20
PRE-CHARGE CURRENT FACTOR 00=0.04 01=0.1 10=0.15 11=0.2
Table 3-8. VCHG Settings
RSVD4B4
VCHG[1]
VCHG[0]
CHARGER REGULATION VOLTAGE 4.10 4.15 4.20 3.95 4.30 4.35 4.40 4.45
charge voltage range RSVD4B4, located register PPATH1, 0x4C (bit
Table 3-9. Charge Enable Control
CHGON[1] CHGON[0] CHARGER MODE SLEEP CHARGER MODE NORMAL
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3.24 SUPPLEMENT MODE DETECTION
TPS658610 charger does have supplement mode. charger power mosfet will turn when charger disabled V(VIN_CHG) V(BAT).
3.25 SHORT CIRCUIT DETECTION
monitored short circuit condition. V(BAT) VSH(BAT) BATCHG switch turned internal resistor connected from VIN_CHG pin.
3.26 DDPM FUNCTION
Internal circuits monitor voltage reduce charge current when V(SYS) VSYS(DPPM). This function assures that external power used system. threshold VSYS(DPPM) programmed using bits SYSDPPM<1:0> register CHG3.
3.27 BATTERY DETECTION, TEMPERATURE QUALIFICATION
Battery pack insertion battery pack temperature detected three comparators that monitor thermistor voltage. thermistor supply enabled when control TSON=HI register CHG1. This control enables host software turn thermistor bias when charger pack temperature needs measured ADC, minimizing system quiescent current when operating under battery power. When charger activated, thermistor power enabled independent state TSON. host software must disable charger setting CHGON(1)=0 when battery pack removal detected TPS658610. This procedure required order avoid undesired transients when battery pack hot-plugged system.
3.28 BATTERY PRE-CONDITIONING
TPS658610 applies pre-charge current Io(PRECHG) battery battery voltage below VLOWBAT threshold, pre-conditioning deeply discharged cells. resistor, RISET, connected between ISET AGND pins, determines pre-charge rate. pre-charge rate programmed RISET always applied deeply discharged battery pack, independent input power selection USB). pre-charge current calculated shown Equation 3-1:
IO(PRECHG) KPRECHG RISET
(3-1)
where KPRECHG pre-charge current scaling factor pre-charge current resistor ISET scaled register CHG3 bits IPCH_1, IPCH_0 percentage (20%, 15%, 10%, value RISET. pre-charge voltage selectable VPCHG, register CHG2.
3.29 CONSTANT CURRENT CHARGING
constant charge current mode (fast charge) when battery voltage higher than pre-charge voltage threshold. fast charge current regulation point defined external resistor, RISET, connected ISET shown Equation 3-2.
IO(BAT) RISET
(3-2)
where KSET charge current scaling factor charge current resistor ISET scaled register CHG1 bits ISET1[1:0] percentage (100%, 75%, 25%) value RISET.
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ISET resistor will always maximum charge current input selected. When input selected maximum charge current will defined input current limit programmed charge current. input current limit lower than IO(BAT) value, battery switch will dropout region charge current will defined input current limit value system load, shown Figure 3-10.
Figure 3-10. Supplement Mode
3.30 BATTERY VOLTAGE REGULATION, CHARGE VOLTAGE
Voltage regulation feedback implemented sensing voltage, which connected positive side battery pack. TPS658610 monitors battery-pack voltage between AGND1 pins. When battery voltage rises VO(BATREG) threshold, voltage regulation phase begins charging current tapers down. charging voltage selected I2C, with bits VCHG<1:0> (register VCHG1) RSVD4B4 (register PPATH1, 0x4C)
3.31 MODE OPERATION
mode makes possible critical subsystems connected directly battery node (BAT pin) when battery removed equipment powered input. voltage must programmed host register SUPPLYV2 control bits VSM2<4:0> value 100mv above programmed charge voltage before mode enabled, should left that value while mode use. voltage other value after mode disabled. charger Mode operation enabled when termination disabled (TERMOFF CHG1) thermistor removal detection ignored (setting TSBYP CHG2). When mode set, termination disabled, safety timers held reset, battery discharge switch disabled. voltage will regulate VO(BATREG) when following conditions true: charger enabled (VIN_CHG VO(BATREG)) input power present input power detected). Under these conditions voltage will regulated charge voltage VO(BATREG) charger current loops active. charger current limit loop will still enabled, current that supplied mode will dependent voltage, shown Table 3-10.
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Table 3-10. Battery Charge Current
VOLTAGE VLOWBAT VLOWBAT BATTERY CHARGE CURRENT IO(PRECHG) IO(BAT)
mode, both thermal loop DPPM loop also enabled. These loops, when active, limit current available pin. voltage will collapse charge current available lower than current required subsystems connected pin. battery tracking function disabled when thermistor detected; will, result, track output voltage when V(SM2) below VO(BATREG).
3.32 CHARGER CONTROL LOGIC OPERATING MODES
charger control logic monitors system parameters control signals define when charger enabled. table below lists charger operating modes. Note that when charger timers reset. charge enabled setting CHGON register CHG2. timer fault termination detection events latched internally charger control logic, after that charger OFF. only reset timer fault termination detection start charge cycle. Table 3-11. Charger Mode Control
TPS658610 MODE UVLO INPUT POWER DETECTED UVLO MODE CHARGER THSHUT DETECTED CHARGE ENABLED CHARGE SUSPEND TIMER FAULT DETECTED PACK TEMP FAULT TERM DETECTED CHARGER MODE SUSPEND SUSPEND
When configured charger pre-regulator mode does affect charger mode.
3.33 CHARGE SUSPEND
charge suspended anytime setting CHSUSP register CHG1 when pack temperature range control TSBYP This will disable charger stage hold safety timers their current count. Normal operation resumes when temperature fault detected.
3.34 CHARGE TERMINATION
TPS658610 monitors charging current during voltage regulation phase. Charge terminated when charge current lower than internal threshold, (typ) fast charge current rate. termination point applies both charging, calculated shown Equation 3-3.
ITERM TERM RISET
(3-3)
where KTERM termination constant detection factor. termination current scaled using register CHG3 bits ITERM[1:0].
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termination detection internally deglitched TDGL(TERM) 25ms typ. When charge current drops below internal termination threshold TDGL(TERM), ITERM status register STAT, indicating that termination detected. ITERM affected state TERMOFF control bit, will always report charge current status. termination enabled (TERMOFF cleared termination detected, charge cycle ends charger turned off. Table 3-12. Termination Detection Conditions
CHARGE CURRENT BELOW TERMINATION THRESHOLD DPPM THERMAL LOOP ACTIVE CHARGER MODE SUSPEND TERMINATION DETECTION ENABLED TERMINATION DETECTED, I(BAT) ITERM
termination detection latched will reset only when charge cycle starts. charge status bits STAT2 register only indicate DONE state when termination detected.
3.35 STARTING CHARGE CYCLE
charge cycle will start only voltage falls below V(RCH) threshold time longer than TDGL(RCH), 25ms (typ). charge cycle also starts when CHGON (CHG1 register) changes from both input power removed then both re-inserted. After termination detected battery pack insertion detection will start charge cycle, even V(BAT) V(RCH).
3.36 PRE-CHARGE SAFETY TIMER
TPS658610 activates internal safety timer during battery pre-conditioning phase. pre-charge safety timer value internally fixed value, TPRECHG, typ, selectable I2C. pre-charge safety timer disabled when termination disabled (bit TERMOFF=HI, register CHG1) when CHTMREN=0 register CHG2. When charger suspend mode pre-charge safety timer hold (i.e., charge safety timer reset). Normal operation resumes when charger exits suspend mode. V(BAT) does reach internal voltage threshold V(PRECHG) within pre-charge timer period fault condition detected charger turned off.
3.37 CHARGE SAFETY TIMER
safety mechanism TPS658610 user-selectable timer that measures total fast charge time. This timer (charge safety timer) started pre-conditioning period. following values available: hours, selectable register CHG1 bits CHGTMR. charge safety timer kept reset mode when CHTMREN=0 register CHG2. charge safety timer disabled when TERMOFF=1, register CHG1. When charger suspend mode, register CHG_CONFIG CHGON pack temperature fault, charge safety timer hold (i.e., charge safety timer reset). Normal operation resumes when charger exits suspend mode. charge termination reached within timer period fault condition detected, charger turned off.
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3.38 TIMER FAULT RECOVERY
TPS658610 provides recovery method deal with timer fault conditions. following summarizes this method: Condition Charge voltage above recharge threshold (V(RCH)) timeout fault occurs. Recovery method: waits battery voltage fall below recharge threshold. This could happen result load battery, self-discharge battery removal. Once battery falls below recharge threshold, clears fault starts charge cycle. Under this scenario, connects internal pull-up resistor from VIN_CHG pin. This pull-up resistor used detect battery removal condition remains long battery voltage stays below recharge threshold. battery voltage goes above recharge threshold, disables pull-up resistor connection executes recovery method described condition
Condition Charge voltage below recharge threshold (V(RCH)) timeout fault occurs. Recovery method:
timers will reset timer fault conditions cleared when charge cycle started either (toggling CHGON register CHG1) cycling input power. timers reset timer fault conditions cleared when TPS658610 enters UVLO mode mode set.
3.39 DYNAMIC TIMER CONTROL
When charger, thermal loop DPPM loop active charge current reduced. avoid false termination detection when those loops active charger logic doubles period clock used charge safety timer. clock frequency divided when those loops active DTCON=1. dynamic timer control disabled setting control DTCON=0, CHG2 register.
3.40 BATTERY DISCHARGE SWITCH
internal switch will discharge ground when battery detected. This switch enabled control BATDCH register CHG1.
3.41 CHARGER STATUS
Charger status information available registers 0xB9, bits PACK_HOT, PACK_COLD, BATDET BATCHGSWON; register 0xBA, bits TMRFLT, DPPM_ON, TH_ON, ITERM, STAT1 STAT2 STATUS REGISTERS section functional description. charger status also indicated CHG_STAT this used logic level output (2v2 level) connected external LED. Table 3-13. Charger Status States
0xBA[2] (STAT1) 0xBA[1] (STAT2) CHARGER STATE Pre-Charge Charge Done Fast Charge Charge Suspend, Timer fault CHG_STAT LEVEL
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3.42 TPS658610 OPERATING MODES
TPS658610 internal state machine that sets operating modes based system status host commands. state machine directly controls state integrated supplies during power-up sequences normal operation. also change on/off state integrated power supplies peripherals implement protection functions execute external hardware control host software commands.
3.43 STATE MACHINE DIAGRAM
V(AC) VUVLO V(USB) VUVLO V(BAT) VUVLO
POWER
SUPPLIES TPS6585X UVLO MODE
POWER
REGISTERS RESET DEFAULT ENABLE POWER PATH OPERATION nNOPOWER=LO
V(SYS) VLOWSYS t>TPOR
V(2V2) VUVLO
CYCLE= INITIAL POWER
STATE
CYCLE POWER DONE
SUPPLIES FORCE RTC_OUT NNOPOWER=LO RESET/START TCHECK TIMER >TWAIT V(SYS) VLOW_SYS TCHECK (CYCLE MODE ENABLED CYCLE=POWER-UP DONE)
CYCLE INITIAL POWER CYCLE MODE ENABLED V(SYS) VLOW_SYS TCHECK DRESUME=HI DETECTED SLEEP THERMAL FAULT] WAIT RTC_ON FORCE RTC_OUT SUPPLIES CYCLE MODE NNOPWER=LO FORCE RTC_OUT SLEEP STATE SUPPLIES ENABLE nNOPOWER TIMER nNOPOWER=LO REGISTERS RESET DEFAULT RESET/START TMAX TIMER SUPPLIES RESET/START TIMERS: TNORTC, REGISTERS RESET RTC_OUT THOTPLUG, TBOOT VUVLO_RTC EEPROM-LOADABLE REGISTERS RESET, KEEP VALUES OTHER REGISTERS RESET DEFAULT BOOT TIMER EXPIRES V(RTC_OUT) VRTCLOW TMAX COMMUNICATION HOTPLUG TIMER EXPIRES SUPPLYSEQ V(SYS) VLOW_SYS 5mSEC FORCE RTC_OUT SLEEP LOWSYS ENABLED] TWAIT TWAIT1 REGISTERS RESET, KEEP VALUES OTHER REGISTERS RESET DEFAULT RESET/START TIMERS: TNORTC THOTPLUG, TBOOT EXECUTE SUPPLY SEQUENCING nNOPOWER=LO RESET/START TIMER TSYNCEND WHEN BOOT TIMER EXPIRES HOTPLUG TIMER EXPIRES V(SYS) VLOW_SYS 5mSEC SLEEP LOWSYS ENABLED] SUPPLY SEQUENCING COMPLETE
HARD REBOOT
SYNC SUPPLIES nNOPOWER=LO RESET/START TWAIT TIMER
TWAIT REBOOT REQUEST HARD REBOOT ENABLED
TWAIT1
POWER GOOD CHECK
FORCE RTC_OUT PGOOD FAULT THERMAL FAULT SLEEP EXIT REBOOT nHOTRST PULSE DETECTED
NORMAL MODE
ENABLE WRITE REGISTERS REGISTERS RESET RTC_OUT VUVLO_RTC TURN ENABLE PULL-DOWN REGISTERS ENABLE SUPPLY OUTPUT DISCHARGE RESISTORS
SLEEP REQUEST RESET/START TWAIT TIMER
REBOOT REQUEST RESET/START TWAIT TIMER nNOPOWER=LO
THERMAL FAULT
STATE
RESUME DETECTED [PGOOD FAULT NORMAL MODE SET] SLEEP MODE HOTPLUG TIMER EXPIRED V(SYS) VLOW_SYS 5mSEC SLEEP LOWSYS ENABLED
WHEN BOOT PHASE
STATES SET:
WRITE REGISTERS DISABLED SM0EN, SM1EN, SYNCEN,LDO4EN PULL-DOWN RESISTORS SUPPLY OUTPUT DISCHARGE RESISTORS
Figure 3-11. TPS658610 Operation Mode State Machine
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state machine transitions TPS658610 have been defined shown below. Supply sequencing started only when LDO4EN voltage level logic high REBOOT REQUEST state transitions HARD REBOOT state Supply sequencing considered complete only turned Sequencer goes into sleep during initial power-up cycle ONLY RESUME trigger exit from sleep state
3.44 STATE MACHINE DESCRIPTION
normal power-up sequence state machine will step through following states: POWER-UP: internal digital supply (2V2) below internal UVLO threshold, VUVLO typ), blocks disabled TPS658610 operational. When supply voltage rises above VUVLO, POWER-UP state entered, internal delay (TPOR, typ) started power path enabled. voltage sensed internal comparator, compared internal threshold VLOW_SYS. When power-on-reset delay expires V(SYS) VLOW_SYS TPS658610 enters mode. RTC: When state nNOPOWER pulled ground, discharging external capacitor connected TNOPOWER resetting NOPOWER timer. RTC_OUT turned off, voltage RTC_OUT flagged V(RTC_OUT) VRTCLOW state ends when timer TCHECK expires. RTC_ON: When state RTC_ON integrated current source connected TNOPOWER RTC_OUT enabled. RTC_OUT voltage flagged state TNORTC timer enabled, NORTC pulled until V(RTC_OUT) VRTC_PGOOD. TNORTC timer starts counting when RTC_OUT VRTCLOW, NORTC will when TNORTC. TNOPOWER current source will remain until reboot cycle sleep cycle set, charging external capacitor connected TNOPOWER pin. NOPOWER will logic level until TNOPOWER voltage above internal threshold (1.23v typ). When NOPOWER transitions from LOHI, 250µsec (typ) positive going pulse generated CHG_STAT pin. TNOPOWER external capacitor discharged whenever sequencer sets NOPOWER state. RTC_ON state ends when V(RTC_OUT) VRTC_PGOOD when internal watchdog timer TMAX expires. WAIT: TPS658610 will into WAIT state when exiting state during initial power-up cycle. avoid undesired lockup conditions this operational mode should used only when boot timer enabled. Three internal timers started when state machine enters WAIT state. These timers independent sequencing state have following functionality: BOOT Timer (TBOOT): Sets TPS658610 SLEEP REQUEST state expires during WAIT state. HOTPLUG Timer (THOTPLUG): SLEEP REQUEST state V(SYS) VLOWSYS inhibited until this timer expires NORTC Timer (TNORTC): NORTC will logic level until this timer expires BOOT timer value 500ms NORTC pulse width 10ms. SUPPLYSEQ: During SUPPLYSEQ state internal supplies, with exception RTC_OUT, initially turned then turned according pre-programmed internal sequencing. Three internal timers started when state machine enters SUPPLYSEQ state. These timers independent sequencing state have following functionality: BOOT Timer (TBOOT): Sets TPS658610 SLEEP REQUEST state expires during SUPPLYSEQ state.
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TPS658610 Advanced Power Management Unit
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HOTPLUG Timer (THOTPLUG): SLEEP REQUEST state V(SYS) VLOWSYS inhibited until this timer expires NORTC Timer (TNORTC): NORTC will logic level until this timer expires
BOOT timer value 500ms NORTC pulse width 10ms. engines available while device SUPPLYSEQ state, however write operations registers disabled, refer register section more details. TPS658610 remains this state until supplies sequenced internal delay TSYNCEND (5ms typ) expired. POWER GOOD CHECK: Supplies that were powered during SUPPLYSEQ state will have their power good flags checked during POWER GOOD CHECK state (with exception RTC_OUT ldo). POWER GOOD CHECK state ends NORMAL state when power good fault present host writes SETNORMAL (register 0x14, B2). power good fault detected, POWER GOOD CHECK state will move SLEEP REQUEST state when boot timer expires. NORMAL STATE: this state write operations registers enabled external host controls TPS658610 functions. normal state operation ends fault condition (defined either thermal fault, V(SYS) VLOW_SYS supply power good fault) detected hardware software commands trigger sleep reboot request. While NORMAL mode, host mask power supply power good fault detection registers PGFLTMASK1 PGFLTMASK2. Supplies that have their power good fault detection masked will normal state operation. However, status supply indicates that output voltage regulation. RTC_OUT power good fault does trigger transition SLEEP REQUEST. Table 3-14. Sequencer Power Good Fault Masking
PGFLTMASK1 [Addr 0x4D] Number Name Function When When MASK_PLDO8 MASK PGOODLDO8 UNMASKED MASKED MASK_PLDO7 MASK PGOODLDO7 UNMASKED MASKED MASK_PLDO6 MASK PGOODLDO6 UNMASKED MASKED MASK_PLDO4 MASK PGOODLDO4 UNMASKED MASKED MASK_PLDO3 MASK PGOODLDO3 UNMASKED MASKED MASK_PLDO2 MASK PGOODLDO2 UNMASKED MASKED MASK_PLDO1 MASK PGOODLDO1 UNMASKED MASKED Defaults BOLD MASK_PLDO0 MASK PGOODLDO0 UNMASKED MASKED Defaults BOLD MASK_PSM2 MASK PGOODSM2 UNMASKED MASKED MASK_PSM1 MASK PGOODSM1 UNMASKED MASKED MASK_PSM0 MASK PGOODSM0 UNMASKED MASKED MASK_PLDO9 MASK PGOODLDO9 UNMASKED MASKED MASK_PLDO5 MASK PGOODLDO5 UNMASKED MASKED RSVD4E1 USED USED USED RSVD4E0 USED USED USED
PGFLTMASK2 [Addr 0x4E] Number Name Function When When MASK_PSM3 MASK PGOODSM3 UNMASKED MASKED
SLEEP REQUEST: SLEEP REQUEST state anytime when thermal fault condition detected. also when TPS658610 NORMAL state followed events shown below. hardware sleep request detected RESUME pin. power good fault detected integrated supplies V(SYS_IN) VLOW_SYS HOTPLUG timer expired THOTPLUG) SLEEP MODE (register 0x14, When SLEEP REQUEST state internal timer started SLEEPREQ=1 register STAT3 (address 0xBB). Writing EXITSLREQ (0x14, returns TPS658610 NORMAL state. action taken host, while SLEEP_REQUEST state set, NOPOWER pulled when TWAIT1 expires SLEEP state entered after TWAIT timer expires.
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Table 3-15. Sequencer Control, LDO5/LDO9 Enable
SUPPLYENE [Addr 0x14] Number Name LDO9_ON LDO9 ON/OFF CONTROL LDO5_ON LDO5 ON/OFF CONTROL SYSINEN SYS_IN VOLTAGE SETS SLEEP MODE DISABLED HOTDLY RESET DEGLITCH SLEEP MODE TPS658610 SLEEP MODE SETNORMAL TPS658610 NORMAL MODE NORMAL MODE ENABLE NORMAL MODE EXITSLREQ SLEEP REQUEST EXIT CONTROL SLEEP T>Twait FORCE TRANSITION NORMAL STATE Defaults BOLD SOFT SOFTWARE RESET CONTROL
Function
When
5µsec min, 16µsec
ACTIVE
ACTIVE
When
ENABLED
SLEEP
REBOOT REQUEST
SLEEP STATE: When SLEEP state supplies mode (with exception RTC_LDO) NOPOWER output pulled low. internal blocks still active, enabling detection system status changes that trigger SLEEP state exit. engines reset registers reset their default condition when SLEEP state set. bits that have default non-volatile memory will keep value they before SLEEP state set. SLEEP state ends when following sequences executed: SLEEP thermal fault: SLEEP state will only when external input supplies battery pack removed UVLO condition detected TPS658610, setting POWER state. SLEEP thermal fault: SLEEP state will when hardware sleep exit request detected RESUME EXITING SLEEP STATE: figure below shows timing relationship needed RESUME exit sleep mode. This applies cases where sleep mode entry triggered event other than thermal fault. Note that only RESUME used exit SLEEP state.
TRESUME(H) TRESUME(L) TRESUME(H)
RESUME TPS6586x MODE ENTER/EXIT SLEEP
NORMAL MODE
SLEEP MODE SLEEP
NORMAL MODE
EXIT SLEEP
Figure 3-12. Entering Exiting Sleep Mode Resume REBOOT REQUEST: REBOOT REQUEST state entered from NORMAL state. software (SOFT_RST register 0x14 level detection HOTRST pin. When reboot request state internal timer TWAIT (10ms typ) started, NOPOWER pulled ground. reboot request ends when TWAIT. REBOOT REQUEST will transition device state machine HARD REBOOT state. REBOOT REQUEST HOTRST pulse width greater than 10µsec (typ).
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status COMPDET=1 (register STAT2, address 0xBA) when NORMAL state entered after reboot cycle triggered HOTRST pin. status COMPDET=0 when NORMAL state entered, after power-up, sleep cycle software triggered reboot cycle. COMPDET reset when SPARECC0=1, register SPARE2 (address 0xCC). After resetting COMPDET host needs SPARECC0=0 enable detection another reboot cycle HOTRST pin. interrupt generated when TPS658610 transitions from POWER GOOD CHECK state NORMAL state COMPDET=1 IMASK_COMP=0 register INTMASK4 (address 0xB3). interrupt request generated after NORMAL state IMASK_COMP=0 COMPDET value changes from Table 3-16. Reboot Flag Control
SPARE2 [Addr 0xCC] Number Name Function SPARECC7 SPARE SPARECC6 SPARE SPARECC5 SPARE SPARECC4 SPARE SPARECC3 SPARE SPARECC2 SPARE SPARECC1 SPARE Defaults BOLD SPARECC0 RESET REBOOT HOTRST STATUS RESET RESET
When When
USED USED
USED USED
USED USED
USED USED
USED USED
USED USED
USED USED
HARD REBOOT: HARD REBOOT state powers down TPS658610 supplies, with exception RTC_OUT LDO. SUPPLYLOAD: When SUPPLYLOAD state registers reset their defaults, non-volatile memory reloaded into RAM. supplies sequenced, they will return their on/off output voltage defaults upon entering SUPPLYLOAD state (on/off, default voltages). timers TBOOT, THOTPLUG TSYNCEND reset started. SUPPLYSEQ state ends when TSYNCEND, POWER GOOD CHECK state set.
3.45
CNOPOWER CAPACITOR DISCHARGE
external capacitor connected TNOPOWER always discharged when sequencer sets NOPOWER=LO following states: POWER-UP, RTC, REBOOT REQUEST, HARD REBOOT SLEEP. large capacitance values (above 330nF) external capacitor fully discharged during reboot cycles, result NOPOWER pulse width slightly reduced when compared value indicated parametric tables.
3.46 SEQUENCER STATUS
Sequencer status information available registers 0xBA, COMPDET register 0xBB bits SLEEPREQ RESUME. STATUS REGISTERS section functional description these bits.
3.47 SUPPLY SEQUENCING HOST INTERFACE 3.47.1 INTEGRATED SUPPLY SEQUENCING
TPS658610 enables implementation complex supply sequencing. With exception RTC_OUT, integrated power-up sequencing starts when TPS658610 state machine enters SUPPLYSEQ state. RTC_OUT always enabled state, which occurs before SUPPLYSEQ state, output this used power external processor circuitry systems where supply sequencing controlled externally using pins SM0EN, SM1EN SYNCEN. Each supply rail controlled combination default status OFF), assigned sequencing trigger group (INTERNAL, SM0EN, SM1EN SYNCEN), delay time.
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TPS658610 Advanced Power Management Unit
default status OFF) each rail shown Table 3-17. default supply rail trigger group associated supply determines control signal that initiates delay time start rail power There four trigger groups, internal three external pins: INTERNAL SM0EN SM1EN SYNCEN This group controlled internal signal that goes high when TPS658610 goes from RTC_ON state SUPPLYSEQ state. This group controlled falling edge SM0EN starts when voltage below level. This group controlled rising edge SM1EN starts when voltage above level. This group controlled rising edge SYNCEN starts when voltage above level.
trigger group each rail associated delay shown Table 3-17. supply rail default state appropriate trigger high, rail will turned after delay time that rail expired. delay time starts when trigger signal that supply gone high, while SUPPLYSEQ state set. delays available after NORMAL mode set. Table 3-17. TPS658610 Integrated Supply Power-Up Defaults
TPS658610 SETTINGS SUPPLY LDO0 LDO1 LDO2 LDO3 LDO4 LDO6 LDO7 LDO8 LDO5 LDO9 DEFAULT STATE DEFAULT VOLTAGE 3.3V 1.2V 1.2V 3.3V 2.475V 3.3V 2.85V 2.85V 2.85V 2.85V 1.2V 1.8V 4.4V TRIGGER SM1EN SYNCEN INTERNAL SM1EN INTERNAL SYNCEN INTERNAL SYNCEN SYNCEN Trigger applies both LDO5 LDO9 SM0EN SM1EN INTERNAL 3.75ms Value applies LDO5, LDO9 2.5ms 3.75ms 15ms 15ms Value applies LDO6, LDO7 LDO8 DELAY Value applies LDO0, LDO1 Value applies LDO2, LDO3
3.48 INTEGRATED SUPPLY SEQUENCING SUPPLY ENABLE CONTROL
mode each supply defined supply enable control bits enable pins SM0EN, SM1EN LDO4EN. supply enable bits located registers SUPPLYENA, SUPPLYENB, SUPPLYENC, SUPPLYEND, SUPPLYENE (see supply functional description more details). functionality bits enable pins dependent state state machine follows: When NORMAL state pins SM1EN SM0EN LDO4EN will always control modes supplies that them triggers. supply enable bits will control modes supplies. When NORMAL state set: supply enable bits will always control modes supplies. pins SM1EN, SM0EN LDO4EN control modes supplies SM1, LDO4. enable pins control modes other supplies.
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During sequencing, following bits control supply ON/OFF mode: LDO2 bits, LDO4 bits, bits bits. When NORMAL mode set, SM0EN controls ON/OFF mode, SM1EN controls ON/OFF mode LDO4EN controls LDO4 ON/OFF mode.
3.49 INTEGRATED SUPPLY SEQUENCING POWER-DOWN
start power down sequence SLEEP REQUEST REBOOT REQUEST states must set. Once those states trigger pins active again they will control ON/OFF state supplies associated with that trigger group. device will enter SLEEP HARD REBOOT state 10ms after SLEEP REQUEST REBOOT REQUEST initiated. supply still active when SLEEP HARD REBOOT state entered will immediately disabled. This default turn condition supply associated with INTERNAL sequencing trigger group. example, supply default state SM1EN selected factory trigger: this supply will power during SUPPLYSEQ state when SM1EN goes high. enabled during NORMAL state still enabled when SLEEP REQUEST REBOOT REQUEST states entered, this supply will turned falling edge SM1EN this assigned trigger group programmed factory. LDO4EN host when TPS658610 enters SLEEP REQUEST REBOOT REQUEST states, LDO4 supply will turn only when HARD REBOOT SLEEP states set. LDO4PG will pulled when LDO4EN below VIL, with delay. supplies turned same time when TPS658610 enters SLEEP HARD REBOOT state.
3.50 HOST INTERFACE
TPS658610 devices have multiple signals that used external system execute power sequencing operations verify system status. Those signals generated follows: Power supply status (2V2 logic level) SM0PG, SM1PG, LDO4PG level indicates that supply regulation voltage valid. level indicates either that supply voltage regulation that supply been disabled. External system host control (V32K logic level): NOPOWER, NORTC, OUT32K pins used interface external hosts, controlling host reset executing host-controlled power-up sequencing.
3.51 EXTERNAL
TPS658610 outputs clock (pin OUT32K) that used external system. OUT32K output starts when NORTC above V32K valid. derived either from internal 32kHz oscillator from crystal-based clock, selectable using RTC_CTRL (Addr 0xC0) register (see Real Time Clock section). However, only crystal-based clock output OUT32K pin.
3.52 SUPPLY INPUT CONNECTION
input pins supplies (VIN_LDO01, VIN_LDO23, VIN_LDO4, VIN_LDO678, VIN_LDO9) enable optimization overall system power architecture connecting lower output voltage supplies intermediate rails external rails. Care must taken ensure that input each integrated supply powered when supply enabled during power-up sequencing. Failure will result power good fault detection with potential lock-up situation. input pins VIN_SM0, VIN_SM1, VIN_SM2 must connected
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3.53 HOST INTERFACE
TPS658610 used systems where sequencing controlled external host housekeeping circuit, well systems where stand-alone sequencing requirement. host controlled systems RTC_OUT used supply that powers external sequencing control NOPOWER NORTC signals used resets external circuit.
Power applied
VUVLO
RTC_OUT/BBAT
VLOW_SYS
HOST CONTROLLED SEQUENCING RTC_OUT SUPPLIES EXTERNAL CIRCUIT THAT DRIVES SUPPLY POWER-UP USING TRIGGER PINS SM0EN, SM1EN, SYNCEN
VRTCLOW
32KHZ_OUT
32kHZ
ENABLE PINS NOPOWER NORTC
TPOR=8mSec
TNOPOWER TNORTC
6586X POWER-UP
EXTERNAL CONTROL CIRCUIT RESET
HOST-BASED SEQUENCING SUPPLIES
SEQUENCING COMPLETED
Figure 3-13. Host Controlled Startup
Power applied
VUVLO
6586X SEQUENCING
RTC_OUT/BBAT VLOW_SYS
VRTCLOW
32KHZ_OUT ENABLES
32kHZ
HOST KEPT RESET MODE UNTIL 6586X SEQUENCES SUPPLIES FOLLOWING INTERNAL, PRE-DEFINED TIMING. ENABLE PINS CONNECTED
NOPOWER NORTC
TPOR=8mSec TNORTC
TNOPOWER
6586X POWER-UP
HOST RESET TPS6585X SEQUENCES INTEGRATED SUPPLIES
SEQUENCING COMPLETED
Figure 3-14. TPS658610 Controlled Startup
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3.54 INTEGRATED SUPPLIES ENABLE CONTROL, CONTROL 3.54.1 NON-DVM SUPPLIES
TPS658610 types voltage control integrated supplies: supplies: SM0, SM1, LDO2 LDO4 supplies with dedicated register sets that enable controlled transition from initial voltage final voltage. initial voltage, final voltage, voltage transition start time I2C. have programmable slew rate. NON-DVM supplies: LDO0, LDO1, LDO3, LDO5, LDO6, LDO7, LDO8, LDO9, RTC_OUT outputs changed, without slew rate transition start time control. output these supplies will changed value soon TPS658610 sends command setting output voltage.
3.54.2 NON-DVM SUPPLY ENABLE
integrated supplies turned on/off enable bits. supplies (with exception LDO5, LDO9 RTC_OUT LDO's) have enable bits distinct registers (registers 0x10, 0x11, 0x12, 0x13, 0x14). supply will enabled when enable bits, registers below, Each supply will disabled when enable bits that supply example: enabled: SM0_ENA=1 SM0_ENB=1, disabled: SM0_ENA=0 SM0_ENB=0 Table 3-18. SM0-2, LDO0-9 Control
SUPPLYENA [Addr 0x10] Number Name Function RSVD107 USED RSVD106 USED RSVD105 USED RSVD104 USED LDO2_ENA1 LDO2 CONTROL LDO2_ENA0 LDO2 CONTROL SM0_ENA CONTROL Defaults BOLD SM1_ENA CONTROL
SUPPLYENB [Addr 0x11] Number Name Function RSVD117 USED RSVD116 USED RSVD115 USED RSVD114 USED LDO2_ENB1 LDO2 CONTROL LDO2_ENB0 LDO2 CONTROL
Defaults BOLD SM1_ENB CONTROL SM0_ENB CONTROL
SUPPLYENC [Addr 0x12] Number Name Function SM2_ONC CONTROL LDO8_ONC LDO8 CONTROL LDO7_ONC LDO7 CONTROL LDO6_ONC LDO6 CONTROL LDO4_ONC LDO4 CONTROL LDO3_ONC LDO3 CONTROL LDO1_ONC LDO1 CONTROL LDO0_ONC LDO0 CONTROL
SUPPLYEND [Addr 0x13] Number Name Function SM2_OND CONTROL LDO8_OND LDO8 CONTROL LDO7_OND LDO7 CONTROL LDO6_OND LDO6 CONTROL LDO4_OND LDO4 CONTROL LDO3_OND LDO3 CONTROL LDO1_OND LDO1 CONTROL LDO0_OND LDO0 CONTROL
SUPPLYENE [Addr 0x14] Number Name LDO9_ON LDO9 ON/OFF CONTROL LDO5_ON LDO5 ON/OFF CONTROL SYSINEN SYS_IN VOLTAGE SETS SLEEP MODE DISABLED HOTDLY RESET DEGLITCH 5µsec min, 16µsec SLEEP MODE TPS658610 SLEEP MODE ACTIVE SETNORMAL TPS658610 NORMAL MODE NORMAL MODE
Defaults BOLD SOFT SOFTWARE RESET CONTROL ACTIVE
EXITSLREQ SLEEP REQUEST EXIT CONTROL SLEEP T>Twait
Function
When
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Table 3-18. SM0-2, LDO0-9 Control (continued)
When ENABLED SLEEP ENABLE NORMAL MODE FORCE TRANSITION NORMAL STATE REBOOT REQUEST
LDO5 LDO9 will turned when LDO5_ON LDO9_ON respectively. RTC_OUT enable bits located control register, real time clock section details. supply enable defaults unique each device. Notes device specific settings.
3.54.3 SUPPLIES VOLTAGE TRANSITION CONTROL
output voltage supplies values programmed voltage setting registers SM0V1, SM0V2, SM1V1, SM2V2, LDO2AV1, LDO2AV2, LDO2BV1, LDO2BV2, LDO4V1 LDO4V2 registers VCC1 VCC2. voltage change supplies usually done with write commands: host writes voltage voltage setting register supply(s) that will have output voltage modification. voltage change starts setting specific control bits registers VCC1 VCC2. Bits registers VCC1 VCC2 select next voltage supplies. voltage change started when bits supply voltage transition bits cleared internal logic. Table 3-19. supply control
VCC1 [Addr 0x20] Number Name Function LDO4VS LDO4GO LDO2AVS2 LDO2AGO2 SM0VS1 SM0GO1 SM1VS1 Defaults BOLD SM1GO1
LDO4 VOLTAGE SELECTION SELECT VOLTAGE LDO4V1 SELECT VOLTAGE LDO4V2 HOLD CURRENT VOLTAGE RAMP VOLTAGE SELECTED LDO4VS
LDO2 VOLTAGE SELECTION HOLD CURRENT VOLTAGE RAMP VOLTAGE SELECTED LDO2BVS1
VOLTAGE SELECTION VOLTAGE SELECTION SELECT VOLTAGE SM0V1 SELECT VOLTAGE SM0V2 HOLD CURRENT VOLTAGE RAMP VOLTAGE SELECTED SM0VS1 SELECT VOLTAGE SM1V1 SELECT VOLTAGE SM1V2 HOLD CURRENT VOLTAGE RAMP VOLTAGE SELECTED SM1VS1
When
USED
When
USED
VCC2 [Addr 0x21] Number Name Function LDO2BVS1 LDO2BGO1 LDO2AVS1 LDO2AGO1 SM0VS2 SM0GO2 SM1VS2
Defaults BOLD SM1GO2
LDO2 VOLTAGE SELECTION SELECT VOLTAGE LDO2BV1 SELECT VOLTAGE LDO2BV2 HOLD CURRENT VOLTAGE RAMP VOLTAGE SELECTED LDO2BVS1
LDO2 VOLTAGE SELECTION VOLTAGE SELECTION VOLTAGE SELECTION HOLD CURRENT VOLTAGE RAMP VOLTAGE SELECTED LDO2BVS1 SELECT VOLTAGE SM0V1 SELECT VOLTAGE SM0V2 HOLD CURRENT VOLTAGE RAMP VOLTAGE SELECTED SM0VS2 SELECT VOLTAGE SM1V1 SELECT VOLTAGE SM1V2 HOLD CURRENT VOLTAGE RAMP VOLTAGE SELECTED SM1VS2
When
USED
When
USED
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Table 3-20. Voltage Selection Register Settings
OUTPUT VOLTAGE SELECTION SM0VS1 SM0VS2 SM0GO1=1 SM0GO2=1 STARTS VOLTAGE TRANSITION VALUE REGISTER SM0V1 SM0V2 SM0V2 SM0V2 SM0VS1 OUTPUT VOLTAGE SELECTION SM0VS2 SM1GO1=1 SM1GO2=1 STARTS VOLTAGE TRANSITION VALUE REGISTER SM1V1 SM1V2 SM1V2 SM1V2
Table 3-21. Voltage Selection SM0EN
ACTIVE LEVEL SM0EN OUTPUT VOLTAGE 1.2V
output voltage value transition controlled SM0EN SM0VS1/SMVS2.
NOTE During transition SM0EN (enabling SM0), output will power pre-defined default state regardless setting prior being disabled.
Table 3-22. Output Voltage Settings Available SM0EN Selection
RANGE 0.725V-1.50V [4:0] 00000 00001 00010 00011 00100 00101 00110 00111 VOUT 0.725 0.750 0.775 0.800 0.825 0.850 0.875 0.900 [4:0] 01000 01001 01010 01011 01100 01101 01110 01111 VOUT 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 [4:0] 10000 10001 10010 10011 10100 10101 10110 10111 VOUT 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 [4:0] 11000 11001 11010 11011 11100 11101 11110 11111 VOUT 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500
Table 3-23. LDO4 Voltage Selection Register Settings
LDO4 OUTPUT VOLTAGE SELECTION LDO4VS LDO4GO=1 STARTS VOLTAGE TRANSITION VALUE REGISTER LDO4V1 LDO4V2
LDO2 output voltage selection functionality shown below. LDO2AGOn bits active LDO2BGO1=1 starts voltage transition voltage selected LDO2BV1, LDO2BV2 LDO2BVS1 LDO2 voltage transition starts when SM0EN When LDO2 output voltage controlled SM0EN (CORECTRL) pin, registers LDO2AV2 LDO2AV1 define output voltage:
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3.54.4 SUPPLY VOLTAGE TRANSITION
During voltage transition output voltage will stepped from currently programmed voltage target voltage shown below. slew rate from initial voltage final voltage selected using registers SM0SL (ADDRESS 0x25) SM1SL (ADDRESS 0x28) respectively. LDO2 LDO4 have slew rate fixed internally 7mV/µSec(typ).
Figure 3-15. Dynamic Voltage Slew Rate Example
3.55 SM0, SM1, CONVERTERS
TPS658610 three highly efficient step down synchronous converters. integration power stage switching FETs reduces external component count, only external output inductor filter capacitor required. integrated power stage supports 100% duty cycle operation. converters have possible modes operation: 2.25MHz fixed frequency pulse width modulation (PWM) mode moderate heavy loads, pulse frequency modulation (PFM) mode light loads. converters SM0, output voltages programmable registers SMnV1 SMnV2 (SM0 SM1) SUPPLYV2 (SM2):
NOTE VIN_SM0, VIN_SM1 VIN_SM2 PINS SHOULD ALWAYS EXTERNALLY CONNECTED
3.55.1 SM0, BUCK CONVERTERS OUTPUT VOLTAGE REGISTERS
Table 3-24. Supply Voltage Slew Rate Selection
SM1V1 [Addr 0x23] Number Name Function RSVD237 USED RSVD236 USED RSVD235 USED SM1V1[4] SM1V1[3] SM1V1[2] SM1V1[1] SM1V1[0]
SUPPLY OUTPUT VOLTAGE
SM1V2 [Addr 0x24]
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Number Name Function
RSVD247 USED
RSVD246 USED
RSVD245 USED
SM1V2[4]
SM1V2[3]
SM1V2[2]
SM1V2[1]
SM1V2[0]
SUPPLY OUTPUT VOLTAGE
SM1SL [Addr 0x25] Number Name Function RSVD257 USED RSVD256 USED RSVD255 USED RSVD254 USED RSVD253 USED SM1SL[2] SM1SL[1] SUPPLY RAMP RATE SM1SL[0]
SM0V1 [Addr 0x26] Number Name Function RSVD267 USED RSVD266 USED RSVD265 USED SM0V1[4] SM0V1[3] SM0V1[2] SM0V1[1] SM0V1[0]
SUPPLY OUTPUT VOLTAGE
SM0V2 [Addr 0x27] Number Name Function RSVD277 USED RSVD276 USED RSVD275 USED SM0V2[4] SM0V2[3] SM0V2[2] SM0V2[1] SM0V2[0]
SUPPLY OUTPUT VOLTAGE
SM0SL [Addr 0x28] Number Name Function RSVD287 USED RSVD286 USED RSVD285 USED RSVD284 USED RSVD283 USED SM0SL[2] SM0SL[1] SUPPLY RAMP RATE SM0SL[0]
available output voltages slew rates shown below. Table 3-25. SM0V1[4:0] SM0V2[4:0] Output Voltage Settings
RANGE 0.725V-1.50V [4:0] 00000 00001 00010 00011 00100 00101 00110 00111 VOUT 0.725 0.750 0.775 0.800 0.825 0.850 0.875 0.900 [4:0] 01000 01001 01010 01011 01100 01101 01110 01111 VOUT 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 [4:0] 10000 10001 10010 10011 10100 10101 10110 10111 VOUT 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 [4:0] 11000 11001 11010 11011 11100 11101 11110 11111 VOUT 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500
Table 3-26. SM1V1[4:0] SM1V2[4:0] Output Voltage Settings
RANGE 1.45V-3.0V [4:0] 00000 00001 00010 00011 00100 00101 00110 00111 VOUT 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 [4:0] 01000 01001 01010 01011 01100 01101 01110 01111 VOUT 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 [4:0] 10000 10001 10010 10011 10100 10101 10110 10111 VOUT 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 [4:0] 11000 11001 11010 11011 11100 11101 11110 11111 VOUT 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00
Table 3-27. SM0SL[2:0] SM1SL[2:0] Slew Rate Settings
SMxSL [2:0] SLEW RATE (mV/µs) INSTANTLY SMxSL [2:0] SLEW RATE (mV/µs) 0.11 SMxSL [2:0] SLEW RATE (mV/µs) 0.22 SMxSL [2:0] SLEW RATE (mV/µs) 0.44
DETAILED DESCRIPTION
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TPS658610 Advanced Power Management Unit
0.88
1.76
3.52
7.04
Table 3-28. Non-DVM supply Voltage selection SM2, LDO8
SUPPLYV2 [Addr 0x42] Number Name Function VLDO8[2] VLDO8[1] LDO8 OUTPUT VOLTAGE VLDO8[0] VSM2[4] VSM2[3] VSM2[2] OUTPUT VOLTAGE VSM2[1] VSM2[0]
Table 3-29. VSM2[4:0] Output Voltage Settings
RANGE 3.0V-4.55V [4:0] 00000 00001 00010 00011 00100 00101 00110 00111 VOUT 3.000 3.050 3.100 3.150 3.200 3.250 3.300 3.350 [4:0] 01000 01001 01010 01011 01100 01101 01110 01111 VOUT 3.400 3.450 3.500 3.550 3.600 3.650 3.700 3.750 [4:0] 10000 10001 10010 10011 10100 10101 10110 10111 VOUT 3.800 3.850 3.900 3.950 4.000 4.050 4.100 4.150 [4:0] 11000 11001 11010 11011 11100 11101 11110 11111 VOUT 4.200 4.250 4.300 4.350 4.400 4.450 4.500 4.550
3.55.2 OPERATION
During operation converters fast response voltage mode controller scheme with input voltage feed-forward, enabling small ceramic input output capacitors. beginning each clock cycle high side channel MOSFET switch turned oscillator starts voltage ramp. inductor current will ramp-up until ramp voltage reaches error amplifier output voltage, when comparator trips high-side channel MOSFET switch turned off. Internal adaptive break-before-make circuits turn integrated low-side MOSFET switch after internal, fixed dead-time delay, inductor current ramps down, until next cycle started. When next cycle starts ramp voltage reset value high-side channel MOSFET switch turned again.
Figure 3-16. Control
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DETAILED DESCRIPTION
TPS658610 Advanced Power Management Unit
SLVS884 JUNE 2009 www.ti.com
3.55.3 MODE OPERATION
TPS658610 SM0, buck converters operate only mode switch automatically between modes, interface. While Pulsed Frequency Mode converters operate with reduced switching frequency with minimum quiescent current maintain high efficiency. mode converter will regulate output voltage above nom
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