W/Channel Mono Class-D Audio Subsystem with DirectPathHeadphone Amplif
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TPA2051D3
W/Channel Mono Class-D Audio Subsystem with DirectPathHeadphone Amplifier SpeakerGuard
FEATURES
DESCRIPTION
TPA2051D3 audio subsystem with mono Class-D power amplifier, stereo DirectPath headphone amplifier, bypass switches. DirectPath headphone amplifier eliminates need external dc-blocking output capacitors. built-in charge pump creates negative supply voltage headphone amplifier, allowing bias output. DirectPath headphone amplifier drives into speakers from supply. subsystem includes three inputs: differential mono input stereo single-ended (SE) inputs. stereo inputs also configurable differential mono inputs. Each input channel independent volume control. Seven operating modes provide input-to-output combinations shutdown control. Operating mode volume levels controlled over compatible interface. TPA2051D3 uses SpeakerGuardtechnology prevent output clipping distortion excessive power speaker headphones. Class-D amplifier includes bypass mode. This allows baseband (BB) directly drive speaker. This useful dual-mode speaker phones voice-only mode. Class-D amplifier uses DirectPath amplifier uses typical quiescent current. Total supply current reduces less than shutdown. TPA2051D3 available 25-bump 2,16 2,11 pitch WCSP with less than height.
Bypass+
Mono Class-D Amp: into from Supply THD) Class-D Bypass Switches DirectPathStereo Headphone Amplifier Output Capacitors Required SpeakerGuardAutomatic Gain Control (AGC) Differential Mono Stereo Single-Ended Inputs Input with Mode Control 32-Step Volume Control Both Input Channels Independent Volume Controls Inputs Independent Shutdown Headphone Class-D Amplifiers I2CInterface Short-Circuit Thermal-Overload Protection Operates from 25-Ball 2,16 2,11 pitch WCSP
APPLICATIONS
Smart Phones Cellular Phones Portable Media Players Portable Gaming Multimedia Platforms
BypassMono+ Mono8 Dual-Mode Speaker
Left (SE) Codec (MP3) Right (SE) Left (SE) Tuner Right (SE)
TPA2051D3 Mono Class-D plus DirectPath
Stereo Headphone Jack
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. DirectPath, SpeakerGuard trademarks Texas Instruments. trademark Phillips Electronics.
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PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
FUNCTIONAL BLOCK DIAGRAM
PVDD
BYPASS+ MONO+ MONOBYPASS-
Voice- Mode Bypass
PVDD
Volume Control Gain Select:
HBridge
OUT+ OUT-
PGND Voice Mode Bypass
Mode Control
SpeakerGuard
HPVDD
Gain Select: step
INL1
Volume Control
HPVSS HPVDD
INL2 INR2 DVDD
Interface
Volume Control
HPVSS
Bias Control Suppression Charge Pump
VREF
AGND
HPVDD
HPVSS
PGND
AVDD
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DEVICE PINOUT
AOUT+
PVDD
PGND
OUT-
BAVDD
BYPASS+
BYPASS-
DVDD
CMONO-
DMONO+
INL2
HPVDD
HPVSS
EINR2
VREF
AGND
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FUNCTIONS
NAME OUT+ PVDD PGND OUT- AVDD BYPASS+ BYPASS- DVDD MONO- MONO+ INL2 INL1 HPVDD HPVSS INR2 INR1 VREF AGND BALL WCSP INPUT/ OUTPUT/ POWER (I/O/P) DESCRIPTION Speaker positive output; connect terminal loudspeaker Supply Class-D amplifier. Connect voltage supply Ground Class-D amplifier; connect directly ground plane Speaker negative output; connect terminal loudspeaker Charge pump flying capacitor negative terminal. Connect negative side capacitor between Connect voltage supply Bypass Mode positive input Bypass Mode negative input Connect supply voltage Charge pump flying capacitor positive terminal. Connect positive side capacitor between Mono negative differential input data input clock input Master shutdown Headphone left channel output Mono positive differential input Input channel left input Input channel left input Headphone reference voltage. Connect capacitor ground Negative supply generated charge pump. Connect ground reduce voltage ripple Input channel right input Input channel right input Reference voltage. Connect capacitor ground Connect ground plane Headphone right channel output
ORDERING INFORMATION
-40°C 85°C PACKAGED DEVICES 25-ball WSCP PART NUMBER TPA2051D3YFFR TPA2051D3YFFT SYMBOL TPA2051 TPA205
most current package ordering information, Package Option Addendum this document, site www.ti.com. package only available taped reeled. suffix indicates reel 3000, suffix indicates reel 250.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range, 25°C (unless otherwise noted)
VALUE UNIT Supply voltage, AVDD, PVDD Supply Voltage DVDD Tstg Input Voltage Output Continuous total power dissipation Operating free-air temperature range Operating junction temperature range Storage temperature range -0.3 -0.3 -0.3 AVDD Dissipation Rating Table -40°C 85°C -40°C 150°C -65°C 85°C
DISSIPATION RATINGS
PACKAGE (WCSP) 25°C POWER RATING OPERATING FACTOR ABOVE 25°C 6.757 mW/°C 70°C POWER RATING 85°C POWER RATING
RECOMMENDED OPERATING CONDITIONS
Supply voltage, AVDD, PVDD supply voltage, DVDD High-level input voltage Low-level input voltage Operating free-air temperature SDA, SCL, DVDD SDA, SCL, DVDD SDA, SCL, DVDD SDA, SCL, DVDD UNIT
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, 25°C (unless otherwise noted)
PARAMETER Power supply rejection ratio (Class-D amplifier) Power supply rejection ratio (headphone amplifiers) High-level input current (SDA, SCL, Low-level input current (SDA, SCL, AVDD PVDD Class-D headphone amplifiers active, load AVDD PVDD Class-D headphone amplifiers active, load Supply current AVDD PVDD headphone active, Class-D deactivated, load AVDD PVDD Class-D active, headphone deactivated, load AVDD PVDD Full shutdown mode TEST CONDITIONS AVDD PVDD Single-ended modes AVDD PVDD Single-ended modes 5.25 UNIT
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TIMING REQUIREMENTS
Interface Signals voltage power sequence, over recommended operating conditions (unless otherwise noted)
PARAMETER fSCL tW(H) tW(L) tsu1 t(buf) tsu2 tsu3 tpws tens tSWS Frequency, Pulse duration, high Pulse duration, Setup time, Hold time, free time between stop start condition Setup time, start condition Hold time, start condition Setup time, stop condition Power delay time, AVDD PVDD DVDD power sequence Enable wait time enable wait time Spk_Enable, HPL_Enable, HPR_Enable wait time 1000 TEST CONDITIONS wait states UNIT
tw(H)
tw(L)
Figure Timing
tsu2 t(buf) tsu3
Start Condition
Stop Condition
Figure Start Stop Conditions Timing
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PVDD AVDD tpws DVDD
tens
Figure Supply Voltage Timing
tSWS
Write
Other Write
Figure Enable Register Timing
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OPERATING CHARACTERISTICS
25°C, Input gain Class-D gain Headphone gain RSPEAKER RHEADPHONES (unless otherwise noted)
PARAMETER CLASS-D POWER AMPLIFIER AVDD PVDD AVDD PVDD 10%, AVDD PVDD 10%, AVDD PVDD kHz, RSPEAKER THD+N PSRR Signal-to-noise ratio Noise output voltage Total harmonic distortion plus noise AC-Power supply rejection ratio Thermal shutdown Output impedance shutdown HEADPHONE AMPLIFIER THD+N PSRR fOSC BYPASS MODE INPUT SECTION VIN_MAX Input impedance (per input pin) Maximum differential input signal swing Volume Control gain Volume Control gain Volume Control gain Volume Control gain Gain matching Crosstalk Start-up time from shutdown A-weighted output channel GAIN 0.22 VP-P Bypass switch impedance Total harmonic distortion attenuation AVDD PVDD VDIFF VP-P, AVDD/2, Temp 25°C VDIFF VP-P, kHz, RSERIES 0.02% Headphone output power Output Offset Voltage Output impedance shutdown Signal-to-noise ratio Noise output voltage Total harmonic distortion plus noise AC-Power supply rejection ratio Charge pump switching frequency Gain matching Electrostatic discharge Between Left Right channels HPLEFT HPRIGHT A-weighted into mVpp ripple, mVpp ripple, AVDD PVDD kHz, in-phase Volume ±0.6 0.02% 0.01% 1200 µVRMS A-weighted AVDD PVDD mVpp ripple, mVpp ripple, Threshold Hysteresis 1000 2900 0.06% 0.04% µVRMS TEST CONDITIONS UNIT
Speaker output power
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TYPICAL CHARACTERISTICS
AVDD PVDD CVREF CHPVDD CHPVSS 25°C, unless otherwise specified
TOTAL HARMONIC DISTORTION NOISE (SP) FREQUENCY
THD+N Total Harmonic Distortion Noise Mono Input Mode Total Gain THD+N Total Harmonic Distortion Noise Mono Input Mode Total Gain
TOTAL HARMONIC DISTORTION NOISE (SP) OUTPUT POWER
0.001 Frequency
0.01
100m
Output Power
Figure TOTAL HARMONIC DISTORTION NOISE (HP) FREQUENCY
THD+N Total Harmonic Distortion Noise Stereo Input Mode Total Gain Phase THD+N Total Harmonic Distortion Noise Stereo Input Mode Total Gain Phase
Figure TOTAL HARMONIC DISTORTION NOISE (HP) FREQUENCY
0.001 Frequency
0.001 Frequency
Figure TOTAL HARMONIC DISTORTION NOISE (HP) OUTPUT POWER
THD+N Total Harmonic Distortion Noise Stereo Input Mode Total Gain In-Phase THD+N Total Harmonic Distortion Noise Stereo Input Mode Total Gain Phase
Figure TOTAL HARMONIC DISTORTION NOISE (HP) OUTPUT POWER
0.01 100u
Output Power
0.01 100u
Output Power
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
AVDD PVDD CVREF CHPVDD CHPVSS 25°C, unless otherwise specified
TOTAL HARMONIC DISTORTION NOISE (HP) OUTPUT POWER
THD+N Total Harmonic Distortion Noise Stereo Input Mode Total Gain In-Phase THD+N Total Harmonic Distortion Noise Stereo Input Mode Total Gain Phase
TOTAL HARMONIC DISTORTION NOISE (HP) OUTPUT POWER
0.01 100u
Output Power
0.01 100u
Output Power
Figure POWER SUPPLY REJECTION RATIO (SP) FREQUENCY
PSRR Power Supply Rejection Ratio PSRR Power Supply Rejection Ratio Mono Input Mode Input Level Total Gain
Figure POWER SUPPLY REJECTION RATIO (HP) FREQUENCY
Stereo Input Mode Input Level Total Gain
-100 Frequency
-100 Frequency
Figure SUPPLY CURRENT (HP) TOTAL OUTPUT POWER
100m Stereo Input Mode Total Gain Phase 100m Stereo Input Mode Total Gain Phase
Figure SUPPLY CURRENT (HP) TOTAL OUTPUT POWER
Supply Current
Supply Current
100u
100u Total Output Power
Total Output Power
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Figure
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TYPICAL CHARACTERISTICS (continued)
AVDD PVDD CVREF CHPVDD CHPVSS 25°C, unless otherwise specified
TOTAL POWER DISSIPATION (SP) TOTAL OUTPUT POWER
140m 120m 100m Mono Input Mode Total Gain Supply Current 500m 450m 400m 350m 300m 250m 200m 150m 100m Mono Input Mode Total Gain
SUPPLY CURRENT (SP) TOTAL OUTPUT POWER
Total Power Dissipation
Total Output Power
Total Output Power
Figure EFFICIENCY (SP) OUTPUT POWER
Efficiency Mono Input Mode Total Gain Output Power Mono Input Mode Total Gain
Figure OUTPUT POWER (SP) SUPPLY VOLTAGE
Output Power
Supply Voltage
Figure OUTPUT POWER CHANNEL (HP) SUPPLY VOLTAGE
Output Power Channel Output Power Channel
Figure OUTPUT POWER CHANNEL (HP) SUPPLY VOLTAGE
Stereo Input Mode Total Gain Phase
Stereo Input Mode Total Gain Phase
Supply Voltage
Supply Voltage
Figure
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TYPICAL CHARACTERISTICS (continued)
AVDD PVDD CVREF CHPVDD CHPVSS 25°C, unless otherwise specified
SPEAKER HEADPHONE CROSSTALK FREQUENCY
CMRR Common-Mode Rejection Ratio Crosstalk -100 -120 -140 -160 Frequency Mono Input Mode Speaker Headphone
COMMON-MODE REJECTION RATIO (SP) FREQUENCY
Input Level Total Gain
-100 Frequency
Figure DIFFERENTIAL INPUT IMPEDANCE VOLUME CONTROL GAIN
100k Single-Ended Input Impedance Differential Input Impedance Volume Control Gain
Figure SINGLE-ENDED INPUT IMPEDANCE VOLUME CONTROL GAIN
Volume Control Gain
Figure SUPPLY CURRENT SUPPLY VOLTAGE
SPKR SPKR Total Gain Total Gain SPKR Enabled Only Enabled Only SPKR Enabled Output Level Mono Input Mode Total Gain
Figure SPEAKER LIMITER OUTPUT LEVEL INPUT LEVEL
Supply Current
Limiter Limiter 1.65 Limiter Limiter Input Level
Supply Voltage
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Figure
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TYPICAL CHARACTERISTICS (continued)
AVDD PVDD CVREF CHPVDD CHPVSS 25°C, unless otherwise specified
SPEAKER OUTPUT STARTUP TIME
Voltage -0.5 -1.0 -1.5 Time Voltage Speaker Output Startup Time -0.5 -1.0 -1.5 Time Speaker Output
SPEAKER OUTPUT SHUTDOWN TIME
Figure HEADPHONE OUTPUT STARTUP TIME
Output Startup Time Voltage Voltage Output
Figure HEADPHONE OUTPUT SHUTDOWN TIME
-0.5
-0.5
-1.0 Time
-1.0 Time
Figure
Figure
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APPLICATION CIRCUIT
VBATT VBATT
AVDD
Voice-Mode Bypass
PVDD
TPA2051D3
BYPASS+
MONO+ MONO BYPASS9.
-66dB +18dB Volume Control
Gain Select:
PGND
OUTHBridge OUT+
Dual-Mode Speaker
Voice-Mode Bypass
INL1 CODEC INL2 Tuner INR2 DVDD Interface Bias Control Suppression -66dB +18dB Volume Control INR1 -66dB +18dB Volume Control
Mixer Mode Control
Gain Select -12dB 1.5dB/ step
HPLEFT Stereo Headphone Jack HPRIGHT
Charge Pump
VREF
AGND
HPVDD
HPVSS
PGND
Figure Typical Apps Configuration with Differential Input Signals
GENERAL OPERATION
employs signals, (data) (clock), communicate between integrated circuits system. transfers data serially time. address data 8-bit bytes transferred most significant (MSB) first. addition, each byte transferred acknowledged receiving device with acknowledge bit. Each transfer operation begins with master device driving start condition ends with master device driving stop condition bus. uses transitions data terminal (SDA) while clock logic high indicate start stop conditions. high-to-low transition indicates start low-to-high transition indicates stop. Normal data-bit transitions bust occur within time clock period. Figure shows typical sequence. master generates 7-bit slave address read/write (R/W) open communication with another device then waits acknowledge condition. TPA2051D3 holds during acknowledge clock period indicate acknowledgment. When this occurs, master transmits next byte sequence. Each device addressed unique 7-bit slave address plus byte). compatible devices share same signals bidirectional using wired-AND connection. TPA2051D3 operates slave. voltage exceed TPA2051D3 supply voltage, AVDD. external pull-up resistor must used signals logic high level bus. When level pull-up resistors between
Data Register Data Register (N+1)
Figure Typical Sequence
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There limit number bytes that transmitted between start stop conditions. When last word transfers, master generates stop condition release bus. generic data transfer sequence shown Figure
SINGLE-AND MULTIPLE-BYTE TRANSFERS
serial control interface supports both single-byte multi-byte read/write operations registers. During multiple-byte read operations, TPA2051D3 responds with data, byte time, starting register assigned, long master device continues respond with acknowledges. TPA2051D3 supports sequential addressing. write transactions, register issued followed data that register remaining registers that follow, sequential write transaction taken place. sequential write transactions, register issued then serves starting point, amount data subsequently transmitted, before stop start transmitted, determines many registers written.
SINGLE-BYTE WRITE
shown Figure single-byte data write transfer begins with master device transmitting start condition followed device address read/write bit. read/write determines direction data transfer. write data transfer, read/write must After receiving correct device address read/write bit, TPA2051D3 responds with acknowledge bit. Next, master transmits register byte corresponding TPA2051D3 internal memory address being accessed. After receiving register byte, TPA2051D3 again responds with acknowledge bit. Finally, master device transmits stop condition complete single-byte data write transfer.
Start Condition Acknowledge Acknowledge Acknowledge
Device Address Read/Write
Register
Data Byte
Stop Condition
Figure Single-Byte Write Transfer
MULTIPLE-BYTE WRITE INCREMENTAL MULTIPLE-BYTE WRITE
multiple-byte data write transfer identical single-byte data write transfer except that multiple data bytes transmitted master device TPA2051D3 shown Figure After receiving each data byte, TPA2051D3 responds with acknowledge bit.
Register
Figure Multiple-Byte Write Transfer
SINGLE-BYTE READ
shown Figure single-byte data read transfer begins with master device transmitting start condition followed device address read/write bit. data read transfer, both write followed read actually done. Initially, write done transfer address byte internal memory address read. result, read/write After receiving TPA2051D3 address read/write bit, TPA2051D3 responds with acknowledge
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bit. master then sends internal memory address byte, after which TPA2051D3 issues acknowledge bit. master device transmits another start condition followed TPA2051D3 address read/write again. This time, read/write indicating read transfer. Next, TPA2051D3 transmits data byte from memory address being read. After receiving data byte, master device transmits not-acknowledge followed stop condition complete single-byte data read transfer.
Start Condition Repeat Start Condition Acknowledge Acknowledge Acknowledge Acknowledge
Device Address Read/Write
Register
Device Address Read/Write
Data Byte
Stop Condition
Figure Single-Byte Read Transfer
MULTIPLE-BYTE READ
multiple-byte data read transfer identical single-byte data read transfer except that multiple data bytes transmitted TPA2051D3 master device shown Figure With exception last data byte, master device responds with acknowledge after receiving each data byte.
Start Condition Repeat Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
Device Address Read/Write
Register
Device Address Read/Write
First Data Byte
Other Data Bytes
Last Data Byte
Stop Condition
Figure Multiple-Byte Read Transfer
REGISTER MAPS
REGISTER BIT7 Version[3] LIM_SEL ATK_time[4] REL_time[4] Mode[2] SPK_Gain HP_Gain[2] BIT6 Version[2] LIM_EN ATK_time[3] REL_time[3] Mode[1] HP_0dB HP_Gain[1] BIT5 Version[1] Reserved ATK_time[2] REL_time[2] Mode[0] Reserved HP_Gain[0] BIT4 Version[0] ATK_time[1] REL_time[1] MON_Vol[4] ST1_Vol[4] ST2_Vol[4] BIT3 Reserved HPL_Enable ATK_time[0] REL_time[0] MON_Vol[3] ST1_Vol[3] ST2_Vol[3] BIT2 Reserved HPR_Enable LIMSPK[2] LIMHP[2] MON_Vol[2] ST1_Vol[2] ST2_Vol[2] BIT1 Spk_Fault Spk_Enable LIMSPK[1] LIMHP[1] MON_Vol[1] ST1_Vol[1] ST2_Vol[1] BIT0 Thermal VM_Bypass LIMSPK[0] LIMHP[0] MON_Vol[0] ST1_Vol[0] ST2_Vol[0]
Bits labeled "Reserved" reserved future enhancements. They written change function device. read, these bits assume value. TPA2051D3 address 0xE0 (binary 11100000) writing 0xE1 (binary 11100001) reading. Refer General Operation section more details Fault Register (Address:
Function Reset Value Version[3] Version[2] Version[1] Version[0] Reserved Reserved Spk_Fault Thermal
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Version[3:0] Spk_Fault Thermal Reserved
Read-only bits that indicate silicon revision. Logic high indicates output over-current event occurred Class-D channel output. This clear-on-write. Logic high indicates thermal shutdown activated. automatically clears when thermal condition lowers past hysteresis threshold. These bits reserved future enhancements. read these bits assume value.
Amplifier Control Register (Address:
Function Reset Value LIM_SEL LIM_EN Reserved HPL_Enable HPR_Enable Spk_Enable VM_Bypass
LIM_SEL LIM_EN HPL_Enable HPR_Enable Spk_Enable VM_Bypass
Selects which limiter register value used. logic high LIMSPK[2:0]. logic LIMHP[2:0]. Default (speaker limiter selected). limiter function enable. logic high enable limiter function. Software Shutdown Mode. logic high deactivate amplifier. Headphone left channel enable. logic deactivate left channel. Headphone right channel enable. logic deactivate right channel. Class-D power amplifier enable. logic deactivate speaker Class-D power amplifier. Speaker bypass mode. logic deactivate speaker bypass. Setting VM_Bypass forces SPK_Enable bypasses volume control. headphone amplifiers still enabled/disabled volume control inputs still active. These bits reserved future enhancements. read these bits assume value.
Reserved
Attack Time Speaker Limiter Control Register (Address:
Function Reset Value ATK_time[4] ATK_time[3] ATK_time[2] ATK_time[1] ATK_time[0] LIMSPK[2] LIMSPK[1] LIMSPK[0]
ATK_time [4:0] LIMSPK[2:0]
Five attack time (gain decrease) control AGC. 00000 sets lowest attack time. Default setting power 00100 (6.4 step) Three-bit limiter level control speaker amplifier. sets lowest limiter level. Default setting power-up (4.2 Vpeak)
Release Time Headphone Limiter Level Control Register (Address:
Function Reset Value REL_time[4] REL_time[3] REL_time[2] REL_time[1] REL_time[0] LIMHP[2] LIMHP[1] LIMHP[0]
_time [4:0] LIMHP [2:0]
Five release time (gain increase) control AGC. 00000 sets lowest release time. Default setting power 01010 (451 step) Three-bit limiter level control headphone amplifier. sets lowest limiter level. Default setting power-up (highest setting)
Mode Mono Input Volume Control Register (Address:
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Function Reset Value
Mode[2]
Mode[1]
Mode[0]
MON_Vol[4]
MON_Vol[3]
MON_Vol[2]
MON_Vol[1]
MON_Vol[0]
Mode[2:0]
Sets output mode. Refer Modes Operation section details. Default mode (Mono Input selected) power-up.
MON_Vol[4:0] Five-bit volume control Mono input mode (mode 11111 sets device highest channel gain; 00000 sets device lowest channel gain. Default setting power-up 01101 dB). Stereo Input Output Gain Control Register (Address:
Function Reset Value SPK_Gain HP_0dB Reserved ST1_Vol[4] ST1_Vol[3] ST1_Vol[2] ST1_Vol[1] ST1_Vol[0]
SPK_Gain HP_0dB Reserved ST1_Vol[4:0]
Class-D speaker amplifier gain. logic high Class-D gain. logic Class-D gain. gain regardless HP_Gain[2:0] setting. default These bits reserved future enhancements. write these bits writing these bits change device function. read these bits assume value. Five-bit volume control Stereo Input (modes INL1 INR1. 11111 sets device highest gain; 00000 sets device lowest gain. Default setting power-up 01101 dB).
Stereo Input Headphone Gain Control Register (Addresses:
Function Reset Value HP_Gain[2] HP_Gain1] HP_Gain[0] ST2_Vol[4] ST2_Vol[3] ST2_Vol[2] ST2_Vol[1] ST2_Vol[0]
HP_Gain [2:0] Headphone gain select. Sets gain headphone output amplifiers according Table default 000. ST2_Vol[4:0] Five-bit volume control Stereo Input (modes INL2 INR2. 11111 sets device highest gain; 00000 sets device lowest gain. Default setting power-up 01101 dB).
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MODES OPERATION
TPA2051D3 supports numerous modes operation. "Stereo refers INL1 INR1 input pair; "Stereo refers INL2 INR2 input pair. "Mono Diff input refers differential input INL1 INR1 "Mono Diff refers differential input INL2 INR2, which typically connected differential output baseband "Mono" refers Mono+ Mono- differential input. following sequence prevent when changing modes: Change Mode[2:0] bits (Mute) Change desired Mode[2:0] Output Mode input selects which device input directed both Class-D headphone amplifiers. summing output after channel volume controls, shown Simplified Functional Diagram page Control through Mode[2:0] bits Output Control (Register Bits according table below.
MODE BYTE: MODE[2:0] [000] [001] [010] [011] [100] [101] [110] [111] MODE Mono Input Mono Diff Input Mono Diff Input Stereo Input Stereo Input Mono Diff Input Mono Input MUTE SPEAKER OUTPUT Mono+ Mono- L2-R2 MUTE HEADPHONE OUTPUT LEFT Mono+ Mono- L2-R2 MUTE L2-R2 MUTE RIGHT Mono+ Mono-
Voice-Mode Bypass Enable Voice-Mode Bypass mode setting VM_Bypass (Register logic high. This deactivates Class-D amplifier regardless Spk_Enable status, enables bypass mode around Class-D amp, connecting BYPASS+ OUT+ BYPASS- OUT-. This allows baseband drive dual-mode loudspeaker directly without using Class-D amplifier, saving power reducing noise low-power voice-only phone modes.
POWER-UP SEQUENCE TIMING
TPA2051D3 startup sequence shown Figure important minimize time delay between powering AVDD/PVDD powering DVDD order minimize potential spikes supply current. important observe minimum delay time between powering DVDD enabling TPA2051D3 (changing from HIGH) order prevent spikes supply current. After changing from logic HIGH (amplifier disabled) logic (amplifier enabled) wait µsec, before next write (refer Figure After changing Spk_Enable, HPL_Enable, HPR_Enable from logic (amplifier disabled) logic HIGH (amplifier enabled) wait µsec, before next write (refer Figure When enabling Class-D amplifier (Spk_Enable from HIGH) and/or headphone amplifiers (HPL_Enable HPR_Enable from HIGH) first time after changing from HIGH follow this sequence: Mode[2:0] Change VM_Bypass Spk_Enable (and/or HPx_Enable) Change desired Mode[2:0]
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OPERATION WITH DELAYED DVDD SUPPLY
case DVDD supply available within tpws(refer Figure supply TPA2051D3 (AVDD PVDD) power DVDD. Refer Figure application diagram. TPA2051D3 DVDD supply must less than equal SDA/SCL VIH. SDA/SCL higher than DVDD must lower than PVDD.
PVDD/AVDD DVDD DVDD
TPA2051D3
Dual-Mode Speaker
GPIO (EN)
Stereo Headphone Jack
Figure Operation With Delayed DVDD Supply
SHUTDOWN CONTROL POWER MANAGEMENT
Power management TPA2051D3 divided into four sections: Class-D power amplifier, headphone left amplifier, headphone right amplifier, bypass mode. Each section enable Amplifier Control byte (Register Register Bits through logic turn amplifier software control. software shutdown mode also achieved changing logic high (Register This will turn sections amplifier also reference bias circuitry, regardless settings Register Bits through lowest current consumption shutdown mode change logic change logic HIGH. This will turn sections amplifier including reference, bias. register contents maintained provided supply voltage powered down. supply power-down, information programmed into registers user lost, returning registers back their default state once power reapplied. Charge Pump Enable charge pump generates negative voltage supply headphone amplifiers. This allows bias amplifier outputs, eliminating need output coupling capacitor. charge pump will automatically activate either HPL_Enable HPR_Enable bits logic high. Class-D Output Amplifier input Class-D amplifier always mono output, regardless mode. Spk_Enable (Register logic high enable Class-D power amplifier. Class-D amplifier draws typical supply current when active less than when deactivated. gain Class-D amplifier selected between register logic select gain logic high select gain
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Table Class-D Amplifier Gain Levels
CLASS-D GAIN REGISTER BYTE: SPK_GAIN NOMINAL GAIN
DirectPath Headphone Amplifier HPL_Enable (Register logic high enable headphone left output HPR_Enable (Register logic high enable headphone right output. headphone amplifier draws typical supply current with both left right outputs active less than when deactivated. Voice Bypass Mode VM_Bypass (Register logic high bypass mode from BYPASS+ BYPASS-to speaker pins (OUT+ OUT-pins). This will automatically disable Class-D speaker amplifier.
HEADPHONE AMPLIFIER GAIN
Headphone amplifier gain differentiated from default volume control gain. Register bits register used attenuate gain headphone amplifier. This function useful differentiate channel gain speaker amplifier from channel gain headphone amplifier. same input signal different output voltage levels speaker headphone amplifier selected. following table shows gain values. This feature required since headphone does require same output voltage level speaker amplifier. Table Headphone Amplifier Gain Levels
HEADPHONE GAIN REGISTER BYTE: HP_0dB, HP_GAIN[2:0] 0000 0001 0010 0011 0100 NOMINAL GAIN -10.5 -7.5 HEADPHONE GAIN REGISTER BYTE: HP_0DB, HP_GAIN[2:0] 0101 0110 0111 1xxx NOMINAL GAIN -4.5 -1.5
VOLUME CONTROL
TPA2051D3 three independent volume controls: mono input configurations (Mode STEREO1 input pair (INL1 INR1, when Mode STEREO2 input pair (INL2 INR2, when Mode Each have 5-bit (32-step) resolution audio tapered; gain step changes become smaller higher gain settings. volume controls range from Class-D speaker amplifier gain selected between volume control. Thus total gain speaker channel (volume control plus Class-D amplifier) range from headphone amplifiers have secondary volume control (see Headphone Amplifier Gain section) besides main volume control. secondary volume control ranges from steps. Thus total gain headphone channel (volume control plus headphone amplifier) range from Mono Input volume control byte located Register Bits Stereo Input volume control byte located Register Bits Stereo Input volume control byte Register Bits Gain matching between left right channels STEREO1 STEREO2 presented operating characteristics table. input impedance TPA2051D3 changes gain changes. Operating Characteristics section specifications. Values listed Table nominal values. When SpeakerGuard(Automatic Gain Control) enabled volume changes rate dictated attack time (volume decrease) release time (volume increase).
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AUDIO TAPER GAIN VALUES
MONO, STEREO1, STEREO2 inputs. Table Volume Control Gain Table
VOLUME CONTROL REGISTER BYTE: VOL[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 NOMINAL GAIN -4.5 -1.5 VOLUME CONTROL REGISTER BYTE: VOL[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 NOMINAL GAIN
AUTOMATIC GAIN CONTROL
automatic gain control (AGC) limiter function only (SpeakerGuardTM). works automatically adjusting amplifier gain based audio signal level. This prevents speaker damage from audio that loud. function also used improve audio loudness without increasing peak power delivered speaker. audio signal higher than limiter level, gain will decrease until audio signal just below limiter setting. gain decrease rate (attack time) interface. audio signal below limiter level gain below fixed gain, gain will increase. gain increase rate (release time) interface. There register settings limiter level. first speaker amplifier, second headphone amplifier. speaker headphone amplifiers enabled same time, limiter level setting speaker amplifier takes precedence setting gain. only amplifier enabled, then channel with highest signal level dictates gain. Table shows selectable limiter levels Class-D amplifier when SPK_Gain (Register dB).
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INPUT SIGNAL
Attack Time
Release Time
GAIN
Gain Step
OUTPUT SIGNAL
LIMITER LEVEL
Figure SpeakerGuardOperation Table Speaker Output Limiter Levels
SPEAKER LIMITER REGISTER BYTE: LIMSPK [2:0] DIFFERENTIAL OUTPUT PEAK VOLTAGE
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headphone amplifier limiter settings depend setting HP_gain bits. Table shows limiter values different headphone amplifier gains. Table Typical Headphone Output Limiter Levels
HEADPHONE LIMITER REGISTER BYTE: LIMHP [2:0] HEADPHONE OUTPUT PEAK VOLTAGE (HP_GAIN 0dB) 0.65 0.75 0.83 0.90 0.97 1.05 HEADPHONE OUTPUT PEAK VOLTAGE (HP_GAIN -6dB) 0.325 0.375 0.415 0.45 0.485 0.525 0.60 0.65 HEADPHONE OUTPUT PEAK VOLTAGE (HP_GAIN -12dB) 0.163 0.188 0.208 0.225 0.244 0.263 0.300 0.325
attack release time selected interface. Table gives possible selections attack time. Table Attack Time Selection
ATTACK TIME REGISTER BYTE: ATK_TIME[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 ATTACK TIME (MS/STEP) 1.28 2.56 3.84 5.12 7.68 8.96 10.24 11.52 12.8 14.08 15.36 16.64 17.92 19.2 20.48 ATTACK TIME REGISTER BYTE: ATK_TIME[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 ATTACK TIME (MS/STEP) 21.76 23.04 24.32 25.6 26.88 28.16 29.44 30.72 33.28 34.56 35.84 37.12 38.4 39.68 40.96
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Table gives possible selections release time. Table Release Time Selection
RELEASE TIME REGISTER BYTE: REL_TIME[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 RELEASE TIME (MS/STEP) RELEASE TIME REGISTER BYTE: REL_TIME[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 RELEASE TIME (MS/STEP) 1025 1066 1107 1148 1189 1230 1271 1312
DECOUPLING CAPACITOR
TPA2051D3 high-performance Class-D audio amplifier that requires adequate power supply decoupling ensure efficiency high total harmonic distortion (THD) low. higher frequency transients, spikes, digital hash line good equivalent-series-resistance (ESR) ceramic capacitor, typically placed close possible device PVDD lead works best. Placing this decoupling capacitor close TPA2051D3 important efficiency Class-D amplifier, because resistance inductance trace between device capacitor cause loss efficiency. filtering lower-frequency noise signals, greater capacitor placed near audio power amplifier would also help, required most applications because high PSRR this device.
INPUT CAPACITORS
TPA2051D3 does require input coupling capacitors design uses differential source that biased within common mode input range. input signal biased within recommended common-mode input range, high pass filtering needed, using single-ended source, input coupling capacitors required. input capacitors input resistors form high-pass filter with corner frequency, determined Equation value input capacitor important consider directly affects bass (low frequency) performance circuit. Speakers wireless phones cannot usually respond well frequencies, corner frequency block frequencies this application. using input capacitors increase output offset. Equation used solve input coupling capacitance. corner frequency within audio band, capacitors should have tolerance ±10% better, because mismatch capacitance causes impedance mismatch corner frequency below.
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corner frequency within audio band, capacitors should have tolerance ±10% better, because mismatch capacitance causes impedance mismatch corner frequency below.
BOARD LAYOUT
making size WCSP balls, recommended that layout nonsolder mask defined (NSMD) land. With this method, solder mask opening made larger than desired land area, opening size defined copper width. Figure Table shows appropriate diameters WCSP layout. TPA2051D3 evaluation module (EVM) layout shown next section layout example.
Figure Land Pattern Dimensions
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Table Land Pattern Dimensions
SOLDER DEFINITIONS Nonsolder mask defined (NSMD) COPPER (+0.0, SOLDER MASK OPENING (+0.0, COPPER THICKNESS STENCIL OPENING (rounded corners) STENCIL THICKNESS thick
Circuit traces from NSMD defined lands should wide exposed area inside solder mask opening. Wider trace widths reduce device stand impact reliability. Best reliability results achieved when laminate glass transition temperature above operating range intended application. Recommend solder paste Type Type using Ni/Au surface finish, gold thickness should less avoid reduction thermal fatigue performance. Solder mask thickness should less than copper circuit pattern Best solder stencil performance achieved using laser stencils with electro polishing. chemically etched stencils results inferior solder paste volume control. Trace routing away from WCSP device should balanced directions avoid unintentional component movement solder wetting forces.
COMPONENT LOCATION
Place external components very close TPA2051D3. Placing decoupling capacitor, close TPA2051D3 important efficiency Class-D amplifier. resistance inductance trace between device capacitor cause loss efficiency. Trace Width Recommended trace width solder balls 75-µm 100-µm prevent solder wicking onto wider traces. high current pins (PVDD, PGND, audio output pins) TPA2051D3, 100-µm trace widths solder balls least 500-µm traces ensure proper performance output power device. remaining signals TPA2051D3, 75-µm 100-µm trace widths solder balls. audio input pins (INR± INL±) must side-by-side maximize common-mode noise cancellation.
EFFICIENCY THERMAL INFORMATION
maximum ambient temperature depends heat-sinking ability system. derating factor packages shown dissipation rating table. Converting this WCSP package: 148°C/W Derating Factor 0.0068 Given 148°C/W, maximum allowable junction temperature 150°C, internal dissipation load, supply, maximum ambient temperature calculated with Equation TJMAX PDmax 148(0.2) 120oC Equation shows that calculated maximum ambient temperature 120°C maximum power dissipation with supply load. TPA2051D3 designed with thermal protection that turns device when junction temperature surpasses 150°C prevent damage
OPERATION WITH DACS CODECS
using Class-D amplifiers with CODECs DACs, sometimes there increase output noise floor from audio amplifier. This occurs when mixing output frequencies CODEC/DAC with switching frequencies audio amplifier input stage. noise increase solved placing low-pass filter between CODEC/DAC audio amplifier. This filters high frequencies that cause problem allow proper performance. Figure application diagram.
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Bypass+
BypassMono+ Mono8 Dual-Mode Speaker
Left (SE) Codec (MP3) Right (SE) Left (SE) Tuner Right (SE)
TPA2051D3 Mono Class-D plus DirectPath
Stereo Headphone Jack
Figure Example Pass Input Filter Application
FILTER FREE OPERATION FERRITE BEAD FILTERS
ferrite bead filter often used design failing radiated emissions without filter frequency sensitive circuit greater than MHz. This filter functions well circuits that just have pass because only test radiated emissions greater than MHz. When choosing ferrite bead, choose with high impedance high frequencies, very impedance frequencies. addition, select ferrite bead with adequate current rating prevent distortion output signal. output filter there frequency MHz) sensitive circuits and/or there long leads from amplifier speaker. Figure shows typical ferrite bead output filters.
Figure Typical Ferrite Bead Filter (Chip bead example: TDK: MPZ1608S221A)
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device TPA2051D3YFFR TPA2051D3YFFT
Status ACTIVE ACTIVE
Package Type DSBGA DSBGA
Package Drawing
Pins Package Plan 3000 Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish SNAGCU SNAGCU
Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
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TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing DSBGA
Reel Reel Diameter Width (mm) (mm) 180.0
(mm)
(mm)
(mm)
(mm)
Pin1 (mm) Quadrant
TPA2051D3YFFR
3000
2.38
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
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*All dimensions nominal
Device TPA2051D3YFFR
Package Type DSBGA
Package Drawing
Pins
3000
Length (mm) 190.5
Width (mm) 212.7
Height (mm) 31.8
Pack Materials-Page
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