TMS320DM6437 Digital Media Processor High-Performance Digital Med
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TMS320DM6437 Digital Media Processor
TMS320DM6437 Digital Media Processor
High-Performance Digital Media Processor (DM6437) 2.5-, 2.-, 1.67-, 1.51-, 1.43-ns Instruction Cycle Time 400-, 500-, 600, 660-, 700-MHz C64x+Clock Rate Eight 32-Bit C64x+ Instructions/Cycle 3200, 4000, 4800, 5280, 5600 MIPS Fully Software-Compatible With C64x Commercial Automotive suffix) Grades Low-Power Device suffix) VelociTI.2Extensions VelociTIAdvanced Very-Long-Instruction-Word (VLIW) TMS320C64x+DSP Core Eight Highly Independent Functional Units With VelociTI.2 Extensions: ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, Quad 8-Bit Arithmetic Clock Cycle Multipliers Support Four 16-Bit Multiplies (32-Bit Results) Clock Cycle Eight 8-Bit Multiplies (16-Bit Results) Clock Cycle Load-Store Architecture With Non-Aligned Support 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size Instructions Conditional Additional C64x+Enhancements Protected Mode Operation Exceptions Support Error Detection Program Redirection Hardware Support Modulo Loop Auto-Focus Module Operation C64x+ Instruction Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation, Bit-Counting VelociTI.2 Increased Orthogonality C64x+ Extensions Compact 16-bit Instructions Additional Instructions Support Complex Multiplies C64x+ L1/L2 Memory Architecture 256K-Bit (32K-Byte) Program RAM/Cache [Flexible Allocation] 640K-Bit (80K-Byte) Data RAM/Cache [Flexible Allocation] 1M-Bit (128K-Byte) Unified Mapped RAM/Cache [Flexible Allocation] Supports Little Endian Mode Only Video Processing Subsystem (VPSS) Front Provides: CMOS Imager Interface BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface Preview Engine Real-Time Image Processing Glueless Interface Common Video Decoders Histogram Module Auto-Exposure, Auto-White Balance Auto-Focus Module Resize Engine Resize Images From 1/4x Separate Horizontal/Vertical Control Back Provides: Hardware On-Screen Display (OSD) Four 54-MHz DACs Combination Composite NTSC/PAL Video Luma/Chroma Separate Video (S-video) Component (YPbPr RGB) Video (Progressive) Digital Output 8-/16-bit 24-Bit Resolution Video Windows External Memory Interfaces (EMIFs) 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O) Supports 333-MHz (data rate) Interfaces With DDR2-400 SDRAM Asynchronous 8-Bit Wide EMIF (EMIFA) With 64M-Byte Address Reach Flash Memory Interfaces (8-Bit-Wide Data) NAND (8-Bit-Wide Data)
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PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2006-2008, Texas Instruments Incorporated
TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Enhanced Direct-Memory-Access (EDMA) Controller Independent Channels) 64-Bit General-Purpose Timers (Each Configurable 32-Bit Timers) 64-Bit Watch Timer UARTs (One with Flow Control) Master/Slave Inter-Integrated Circuit (I2C BusTM) Multichannel Buffered Serial Ports (McBSPs) AC97 Audio Codec Interface Standard Voice Codec Interface (AIC12) Telecom Interfaces ST-Bus, H-100 Channel Mode Multichannel Audio Serial Port (McASP0) Four Serializers SPDIF (DIT) Mode 16-Bit Host-Port Interface (HPI) High-End Controller (HECC) 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface 10/100 Mb/s Ethernet (EMAC) IEEE 802.3 Compliant
Supports Media Independent Interface (MII) Management Data (MDIO) Module VLYNQInterface (FPGA Interface) Three Pulse Width Modulator (PWM) Outputs On-Chip Bootloader Individual Power-Savings Modes Flexible Clock Generators IEEE-1149.1 (JTAGTM) Boundary-Scan-Compatible General-Purpose (GPIO) Pins (Multiplexed With Other Device Functions) Packages: 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch 376-Pin Plastic Package (ZDU Suffix), 1.0-mm Ball Pitch 0.09-µm/6-Level Metal Process (CMOS) 3.3-V 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-Q5/-Q4) 3.3-V 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5) Applications Digital Media Networked Media Encode/Decode Video Imaging
TMS320DM6437 Digital Media Processor
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TMS320DM6437 Digital Media Processor
Description
TMS320C64x+DSPs (including TMS320DM6437 device) highest-performance fixed-point generation TMS320C6000DSP platform. DM6437 device based third-generation high-performance, advanced (VLIW) architecture developed Texas Instruments (TI), making these DSPs excellent choice digital media applications. C64x+devices upward code-compatible from previous devices that part C6000DSP platform. C64xDSPs support added functionality have expanded instruction from previous devices. reference C64x C64x also applies, unless otherwise noted, C64x+ C64x+ CPU, respectively. With performance 5600 million instructions second (MIPS) clock rate MHz, C64x+ core offers solutions high-performance programming challenges. core possesses operational flexibility high-speed controllers numerical capability array processors. C64x+ core processor general-purpose registers 32-bit word length eight highly independent functional units-two multipliers 32-bit result arithmetic logic units (ALUs). eight functional units include instructions accelerate performance video imaging applications. core produce four 16-bit multiply-accumulates (MACs) cycle total 2800 million MACs second (MMACS), eight 8-bit MACs cycle total 5600 MMACS. more details C64x+ DSP, TMS320C64x/C64x+ Instruction Reference Guide (literature number SPRU732). DM6437 also application-specific hardware logic, on-chip memory, additional on-chip peripherals similar other C6000 platform devices. DM6437 core uses two-level cache-based architecture. Level program memory/cache (L1P) consists 256K-bit memory space that configured mapped memory direct mapped cache, Level data (L1D) consists 640K-bit memory space -384K-bit which mapped memory 256K-bit which configured mapped memory 2-way set-associative cache. Level memory/cache (L2) consists 1M-bit memory space that shared between program data space. memory configured mapped memory, cache, combinations two. peripheral includes: configurable video ports; 10/100 Mb/s Ethernet (EMAC) with management data input/output (MDIO) module; 4-bit transmit, 4-bit receive VLYNQ interface; inter-integrated circuit (I2C) interface; multichannel buffered serial ports (McBSPs); multichannel audio serial port (McASP0) with serializers; 64-bit general-purpose timers each configurable independent 32-bit timers; 64-bit watchdog timer; user-configurable 16-bit host-port interface (HPI); 111-pins general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; UARTs with hardware handshaking support UART; pulse width modulator (PWM) peripherals; high-end controller area network (CAN) controller [HECC]; peripheral component interconnect (PCI) MHz]; glueless external memory interfaces: asynchronous external memory interface (EMIFA) slower memories/peripherals, higher speed synchronous memory interface DDR2. DM6437 device includes Video Processing Subsystem (VPSS) with configurable video/imaging peripherals: Video Processing Front-End (VPFE) input used video capture, Video Processing Back-End (VPBE) output. Video Processing Front-End (VPFE) comprised Controller (CCDC), Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), Resizer. CCDC capable interfacing common video decoders, CMOS sensors, Charge Coupled Devices (CCDs). Previewer real-time image processing engine that takes imager data from CMOS sensor converts from Bayer Pattern YUV422. Histogram modules provide statistical information color data DM6437. Resizer accepts image data separate horizontal vertical resizing from 1/4x increments 256/N, where between 1024.
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TMS320DM6437 Digital Media Processor
TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Video Processing Back-End (VPBE) comprised On-Screen Display Engine (OSD) Video Encoder (VENC). engine capable handling separate video windows separate windows. Other configurations include video windows, window, attribute window allowing levels alpha blending. VENC provides four analog DACs that MHz, providing means composite NTSC/PAL video, S-Video, and/or Component video output. VENC also provides bits digital output interface RGB888 devices. digital output capable 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal vertical syncs. Ethernet Media Access Controller (EMAC) provides efficient interface between DM6437 network. DM6437 EMAC support both 10Base-T 100Base-TX, Mbits/second (Mbps) Mbps either half- full-duplex mode, with hardware flow control quality service (QOS) support. Management Data Input/Output (MDIO) module continuously polls MDIO addresses order enumerate devices system. VLYNQ ports allow DM6437 easily control peripheral devices and/or communicate with host processors. high-end controller area network (CAN) controller [HECC] module provides network protocol harsh environment communicate serially with other controllers, typically automotive applications. rich peripheral provides ability control external peripheral devices communicate with external processors. details each peripherals, related sections later this document associated peripheral reference guides. DM6437 complete development tools. These include compilers, assembly optimizer simplify programming scheduling, Windowsdebugger interface visibility into source code execution.
TMS320DM6437 Digital Media Processor
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TMS320DM6437 Digital Media Processor
Functional Block Diagram
Figure shows functional block diagram DM6437 device.
BT.656, Y/C, (Bayer) JTAG Interface System Control Input Clock(s) PLLs/Clock Generator Power/Sleep Controller Multiplexing Subsystem C64x+ Data Video Processing Subsystem (VPSS) Front Back On-Screen Video Display Encoder (OSD) (VENC) BT.656, Y/C, NTSC/ PAL, S-Video, RGB, YPbPr
Resizer Controller Histogram/ Video Preview Interface
Boot
Switched Central Resource (SCR)
Peripherals
Serial Interfaces System
McASP
McBSP
HECC
UART
GeneralPurpose Timer
Watchdog Timer
GPIO
EDMA
Connectivity
Program/Data Storage
MHz)
VLYNQ
EMAC With MDIO
DDR2 Ctlr (32b)
Async EMIF/ NAND/ (8b)
Figure 1-1. TMS320DM6437 Functional Block Diagram
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TMS320DM6437 Digital Media Processor
TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Contents
TMS320DM6437 Digital Media Processor
Features Description Functional Block Diagram
Peripheral Information Electrical Specifications
6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 Parameter Information Recommended Clock Control Signal Transition Behavior. Power Supplies Enhanced Direct Memory Access (EDMA3) Controller Reset
Revision History Device Overview
Device Characteristics (DSP Core) Description C64x+ CPU.
Assignments Terminal Functions Device Support
Memory Summary
Device Development-Support Tool Nomenclature Documentation Support System Module Registers Power Considerations Clock Considerations Boot Sequence Configurations Reset Configurations After Reset Multiplexed Configurations Device Initialization Sequence After Reset Debugging Considerations System Interconnect Block Diagram Absolute Maximum Ratings Over Operating Temperature Range (Unless Otherwise Noted) Recommended Operating Conditions Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Temperature (Unless Otherwise Noted)
Clock PLLs Interrupts External Memory Interface (EMIF) Video Processing Sub-System (VPSS) Overview
External Clock Input From MXI/CLKIN
Universal Asynchronous Receiver/Transmitter (UART) Inter-Integrated Circuit (I2C) Host-Port Interface (HPI) Peripheral Multichannel Buffered Serial Port (McBSP). Multichannel Audio Serial Port (McASP0) Peripheral High-End Controller Area Network Controller (HECC) Ethernet Media Access Controller (EMAC) Management Data Input/Output (MDIO)
Device Configurations.
System Interconnect
Device Operating Conditions.
6.19 Timers 6.20 Peripheral Component Interconnect (PCI) 6.21 Pulse Width Modulator (PWM). 6.22 VLYNQ 6.23 General-Purpose Input/Output (GPIO). 6.24 IEEE 1149.1 JTAG Mechanical Data. Thermal Data 7.1.1 Thermal Data 7.1.2 Packaging Information.
Contents
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TMS320DM6437 Digital Media Processor
Revision History
NOTE: Page numbers previous revisions differ from page numbers current version.
This data manual revision history highlights technical changes made SPRS345C device-specific data manual make SPRS345D revision. Scope: Applicable updates TMS320DM643x DMP, specifically relating TMS320DM6437 device, have been incorporated. Added 660- 700-MHz C64x+device speeds. Added designators low-power (-L) devices.
Global Section Section
Updated/Changed signal name from "C_WE" "C_WE" Updated/Changed signal name from "C_WEN" "C_WE"
Added "5280, 5600 MIPS" "High-Performance Digital Signal Processor (DM6437)" bullet first paragraph, updated/changed following: First sentence from "With performance 4800 million instructions second (MIPS) clock rate MHz." "With performance 5600 million instructions second (MIPS) with clock rate MHz." Fifth sentence from "The core produce.for total 2400 million MACs second.or total 4800 MMACS."to "The core produce.for total 2800 million MACs second.or total 5600 MMACS."
Section
Table 2-24, Multichannel Audio Serial Port (McASP0) Terminal Functions: Updated/Changed AFSR0/DR0/GP[100] description from frame synchronization AFSX0." ".frame synchronization AFSR0." Updated/Changed AFSX0/DX1/GP[107] description from ".frame synchronization AFSR0." ".frame synchronization AFSX0." Table 2-21, [Part VPBE] Terminal Functions: Updated/Changed VDDA_1P1V description
Section Section Section Section 6.7.1
Updated/Changed Figure 2-10, Device Nomenclature, reflect device speeds low-power designator suffix). Added footnote Section 5.1, Absolute Maximum Ratings Over Operating Temperature Range (Unless Otherwise Noted). Updated/Changed ICDD IDDD test conditions footnote Section 5.3, Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Temperature (Unless Otherwise Noted). Table 6-15, PLLC1 Clock Frequency Ranges: Updated/Changed PLLOUT 1.2V-CVDD value from "700 MHz" "600 MHz" -6/-5/-4/-L/-Q6/-Q5/-Q4 devices. Updated/Changed SYSCLK1 1.05V-CVDD value from "560 MHz" "520 MHz" devices. Deleted "Future variants." footnote from table Updated/Changed sentence from requires filter manufacturer Murata." recommends filter manufacturer Murata." Deleted "(-4, -4Q, -4S, -5Q, -5S, -6)" from Table 6-19 title, Timing Requirements MXI/CLKIN.
Section Section 6.7.1 Section 6.7.4
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Revision History
TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Device Overview
Device Characteristics
Table 2-1, provides overview TMS320DM6437 DSP. tables show significant features DM6437 device, including capacity on-chip RAM, peripherals, frequency, package type with count. Table 2-1. Characteristics DM6437 Processor
HARDWARE FEATURES DDR2 Memory Controller Asynchronous EMIF [EMIFA] EDMA3 Timers UARTs Peripherals peripherals pins available same time (For more detail, Device Configurations section). McBSPs McASP 10/100 Ethernet (EMAC) with Management Data Input/Output (MDIO) VLYNQ General-Purpose Input/Output Port (GPIO) (16-bit) (32-bit), [33-MHz] Configurable Video Ports HECC Size (Bytes) On-Chip Memory DM6437 (16-/32-bit width) [1.8 I/O] Asynchronous (8-bit width), RAM, Flash, (8-bit 8-bit NAND) independent channels, QDMA channels) 64-bit General Purpose (configurable 64-bit 32-bit) 64-bit Watch (one with flow control) (Master/Slave) serailizers) pins outputs Input (VPFE) Output (VPBE) 240KB RAM, 64KB 32K-Byte (32KB) Program (L1P) RAM/Cache (Cache 32KB) 80KB Data (L1D) RAM/Cache (Cache 32KB) 128KB Unified Mapped RAM/Cache (L2) 64KB Boot TMS320DM6437/35/33/31 Digital Media Processor (DMP) [Silicon Revisions 1.0] Silicon Errata (literature number SPRZ250). Section 6.24.1, JTAG (JTAGID) Register Description(s) (-7) (-Q6) (-6/-L) (-5/-Q5) (-4/-Q4) (-4/-Q4) (-5/-Q5) 1.67 (-6/-L) 1.51 (-Q6) 1.43 (-7)
Organization
MegaModule JTAG BSDL_ID
Revision Register (MM_REVID.[15:0]) (address location: 0x0181 2000) Control Status Register (CSR.[31:16]) JTAGID register (address location: 0x01C4 0028)
Frequency
Cycle Time
Performance numbers assume core voltage 1.2V. Applies "tape reel" part number counterparts well. more information, Section 2.8, Device Development-Support Tool Nomenclature. Device Overview Submit Documentation Feedback
TMS320DM6437 Digital Media Processor
Table 2-1. Characteristics DM6437 Processor (continued)
HARDWARE FEATURES DM6437 (-7/ -6/-5/ -4/-L/-Q6/-Q5/-Q4) 1.05 (-7/-6/-5/-4/-L/-Q5) (Bypass), 361-Pin (ZWT) 376-Pin (ZDU) 0.09
Voltage
Core
Options Package(s) Process Technology Product Status
MXI/CLKIN frequency multiplier reference) pitch pitch Product Preview (PP), Advance Information (AI), Production Data (PD)
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
(DSP Core) Description
C64x+ Central Processing Unit (CPU) consists eight functional units, register files, data paths shown Figure 2-1. general-purpose register files each contain 32-bit registers total registers. general-purpose registers used data data address pointers. data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, 64-bit data. Values larger than bits, such 40-bit-long 64-bit-long values stored register pairs, with LSBs data placed even register remaining MSBs next upper register (which always odd-numbered register). eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, .S2) each capable executing instruction every clock cycle. functional units perform multiply operations. units perform general arithmetic, logical, branch functions. units primarily load data from memory register file store results from register file into memory. C64x+ extends performance C64x core through enhancements features. Each C64x+ unit perform following each clock cycle: multiply, multiply, multiplies, multiplies, multiplies with add/subtract capabilities, four multiplies, four multiplies with operations, four multiplies with add/subtract capabilities (including complex multiply). There also support Galois field multiplication 8-bit 32-bit data. Many communications algorithms such FFTs modems require complex multiplication. complex multiply (CMPY) instruction takes 16-bit inputs produces 32-bit real 32-bit imaginary output. There also complex multiplies with rounding capability that produces 32-bit packed output that contain 16-bit real 16-bit imaginary values. multiply instructions provide extended precision necessary audio other high-precision algorithms variety signed unsigned 32-bit data types. (Arithmetic Logic Unit) incorporates ability parallel add/subtract operations pair common inputs. Versions this instruction exist work 32-bit data pairs 16-bit data performing dual 16-bit subtracts parallel. There also saturated forms these instructions. C64x+ core enhances unit several ways. C64x core, dual 16-bit MIN2 MAX2 comparisons were only available units. C64x+ core they also available unit which increases performance algorithms that searching sorting. Finally, increase data packing unpacking throughput, unit allows sustained high performance quad 8-bit/16-bit dual 16-bit instructions. Unpack instructions prepare 8-bit data parallel 16-bit operations. Pack instructions return parallel results output precision including saturation support. Other features include:
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Device Overview
TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
SPLOOP small instruction buffer that aids creation software pipelining loops where multiple iterations loop executed parallel. SPLOOP buffer reduces code size associated with software pipelining. Furthermore, loops SPLOOP buffer fully interruptible. Compact Instructions native instruction size C6000 devices bits. Many common instructions such MPY, AND, ADD, expressed bits C64x+ compiler restrict code certain registers register file. This compression performed code generation tools. Instruction Enhancement noted above, there instructions such 32-bit multiplications, complex multiplications, packing, sorting, manipulation, 32-bit Galois field multiplication. Exceptions Handling Intended programmer isolating bugs. C64x+ able detect respond exceptions, both from internally detected sources (such illegal op-codes) from system events (such watchdog time expiration). Privilege Defines user supervisor modes operation, allowing operating system give basic level protection sensitive resources. Local memory divided into multiple pages, each with read, write, execute permissions. Time-Stamp Counter Primarily targeted Real-Time Operating System (RTOS) robustness, free-running time-stamp counter implemented which sensitive system stalls.
more details C64x+ enhancements over C64x architecture, following documents: TMS320C64x/C64x+ Instruction Reference Guide (literature number SPRU732) TMS320C64x+ Megamodule Reference Guide (literature number SPRU871) TMS320C64x TMS320C64x+ Migration Guide Application Report (literature number SPRAA84) TMS320C64x+ Cache User's Guide (literature number SPRU862)
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register file (A1, A5.A31)
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src1
src2
even ST1b ST1a
long
long even src1 src2
Data path
dst2 dst1 src1 src2
LD1b LD1a
src1 src2
src2
src1
LD2a LD2b
src2 src1 dst2 dst1
src2 src1
Data path
even long ST2a ST2b
long even src2
src1
unit, dst2 MSB. unit, dst1 LSB. C64x unit, src2 bits; C64x+ unit, src2 bits. units, connects register files even connects even register files.
Figure 2-1. TMS320C64x+CPU (DSP Core) Data Paths
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Even register file (A0, A4.A30)
register file (B1, B5.B31) Even register file (B0, B4.B30)
Control Register
Device Overview
TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
C64x+
C64x+ core uses two-level cache-based architecture. Level Program memory/cache (L1P) consists memory space that configured mapped memory direct mapped cache. Level Data memory/cache (L1D) consists KB-48 which mapped memory which configured mapped memory 2-way associated cache. Level memory/cache (L2) consists memory space that shared between program data space. memory configured mapped memory, cache, combination both. Table shows memory C64x+ cache registers device. Table 2-2. C64x+ Cache Registers
ADDRESS RANGE 0x0184 0000 0x0184 0020 0x0184 0024 0x0184 0040 0x0184 0044 0x0184 0048 0x0184 0FFC 0x0184 1000 0x0184 1004 0x0184 1FFC 0x0184 2000 0x0184 2004 0x0184 2008 0x0184 200C 0x0184 2010 0x0184 3FFF 0x0184 4000 0x0184 4004 0x0184 4010 0x0184 4014 0x0184 4018 0x0184 401C 0x0184 4020 0x0184 4024 0x0184 4030 0x0184 4034 0x0184 4038 0x0184 4040 0x0184 4044 0x0184 4048 0x0184 404C 0x0184 4050 0x0184 4FFF 0x0184 5000 0x0184 5004 0x0184 5008 0x0184 500C 0x0184 5027 0x0184 5028 0x0184 502C 0x0184 5039 0x0184 5040 0x0184 5044 0x0184 5048 Device Overview REGISTER ACRONYM L2CFG L1PCFG L1PCC L1DCFG L1DCC EDMAWEIGHT L2ALLOC0 L2ALLOC1 L2ALLOC2 L2ALLOC3 L2WBAR L2WWC L2WIBAR L2WIWC L2IBAR L2IWC L1PIBAR L1PIWC L1DWIBAR L1DWIWC L1DWBAR L1DWWC L1DIBAR L1DIWC L2WB L2WBINV L2INV L1PINV L1DWB L1DWBINV L1DINV DESCRIPTION Cache configuration register Size Cache configuration register Freeze Mode Cache configuration register Size Cache configuration register Freeze Mode Cache configuration register Reserved EDMA access control register Reserved allocation register allocation register allocation register allocation register Reserved writeback base address register writeback word count register writeback invalidate base address register writeback invalidate word count register invalidate base address register invalidate word count register invalidate base address register invalidate word count register writeback invalidate base address register writeback invalidate word count register Reserved Block Writeback Block Writeback invalidate base address register invalidate word count register Reserved writeback register writeback invalidate register Global Invalidate without writeback Reserved Global Invalidate Reserved Global Writeback Global Writeback with Invalidate Global Invalidate without writeback Submit Documentation Feedback
TMS320DM6437 Digital Media Processor
Table 2-2. C64x+ Cache Registers (continued)
ADDRESS RANGE 0x0184 8000 0x0184 80BC 0x0184 80C0 0x0184 80FC 0x0184 8100 0x0184 8104 0x0184 8108 0x0184 8124 0x0184 8128 0x0184 812C 0x0184 8130 0x0184 813C 0x0184 8140- 0x0184 81FC 0x0184 8200 0x0184 823C 0x0184 8240 0x0184 83FC REGISTER ACRONYM MAR0 MAR47 MAR48 MAR63 MAR64 MAR65 MAR66 MAR73 MAR74 MAR75 MAR76 MAR79 MAR80 MAR127 MAR128 MAR143 MAR144 MAR255 DESCRIPTION Reserved (corresponds byte address 0x0000 0000 0x2FFF FFFF) Memory Attribute Registers Data (corresponds byte address 0x3000 0000 0x3FFF FFFF) Reserved (corresponds byte address 0x4000 0000 0x41FF FFFF) Memory Attribute Registers EMIFA (corresponds byte address 0x4200 0000 0x49FF FFFF) Reserved (corresponds byte address 0x4A00 0000 0x4BFF FFFF) Memory Attribute Registers VLYNQ (corresponds byte address 0x4C00 0000 0x4FFF FFFF) Reserved (corresponds byte address 0x5000 0000 0x7FFF FFFF) Memory Attribute Registers DDR2 (corresponds byte address 0x8000 0000 0x8FFF FFFF) Reserved (corresponds byte address 0x9000 0000 0xFFFF FFFF)
Memory Summary
Table shows memory address ranges device. Table depicts expanded Configuration Space (0x0180 0000 through 0x0FFF FFFF). device multiple on-chip memories associated with processors various subsystems. help simplify software development unified memory used where possible maintain consistent view device resources across masters.
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Table 2-3. Memory Summary
START ADDRESS 0x0000 0000 0x0010 0000 0x0011 0000 0x0080 0000 0x0082 0000 0x00E0 8000 0x00E1 0000 0x00F0 4000 0x00F1 0000 0x00F1 8000 0x0180 0000 0x01C0 0000 0x0200 0000 0x1010 0000 0x1011 0000 0x1080 0000 0x1082 0000 0x10E0 8000 0x10E1 0000 0x10F0 4000 0x10F1 0000 0x10F1 8000 0x1100 0000 0x2000 0000 0x2000 8000 0x3000 0000 0x4000 0000 0x4200 0000 0x4300 0000 0x4400 0000 0x4500 0000 0x4600 0000 0x4700 0000 0x4800 0000 0x4900 0000 0x4A00 0000 0x4C00 0000 0x5000 0000 0x8000 0000 0x9000 0000 ADDRESS 0x000F FFFF 0x0010 FFFF 0x007F FFFF 0x0081 FFFF 0x00E0 7FFF 0x00E0 FFFF 0x00F0 3FFF 0x00F0 FFFF 0x00F1 7FFF 0x017F FFFF 0x01BF FFFF 0x01FF FFFF 0x100F FFFF 0x1010 FFFF 0x107F FFFF 0x1081 FFFF 0x10E0 7FFF 0x10E0 FFFF 0x10F0 3FFF 0x10F0 FFFF 0x10F1 7FFF 0x10FF FFFF 0x1FFF FFFF 0x2000 7FFF 0x2FFF FFFF 0x3FFF FFFF 0x41FF FFFF 0x42FF FFFF 0x43FF FFFF 0x44FF FFFF 0x45FF FFFF 0x46FF FFFF 0x47FF FFFF 0x48FF FFFF 0x49FF FFFF 0x4BFF FFFF 0x4FFF FFFF 0x7FFF FFFF 0x8FFF FFFF 0xFFFF FFFF 7M-64K 128K 6048K 976K 9120K 225M 7M-48K 128K 6048K 976K 1M-96K 240M 256M-32K 256M 768M 256M 1792M SIZE (Bytes) C64x+ MEMORY Reserved Boot Reserved RAM/Cache Reserved RAM/Cache Reserved RAM/Cache Reserved Space Peripherals Reserved Boot Reserved RAM/Cache Reserved RAM/Cache Reserved RAM/Cache Reserved Reserved DDR2 Control Regs Reserved Data Reserved EMIFA Data (CS2) Reserved EMIFA Data (CS3) Reserved EMIFA Data (CS4) Reserved EMIFA Data (CS5) Reserved Reserved VLYNQ (Remote Data) Reserved DDR2 Memory Controller Reserved RAM/Cache Reserved RAM/Cache Reserved Reserved RAM/Cache Reserved Reserved DDR2 Control Regs Reserved Data Reserved EMIFA Data (CS2) Reserved EMIFA Data (CS3) Reserved EMIFA Data (CS4) Reserved EMIFA Data (CS5) Reserved Reserved VLYNQ (Remote Data) Reserved DDR2 Memory Controller Reserved DDR2 Memory Controller Reserved DDR2 Memory Controller Reserved RAM/Cache Reserved Reserved DDR2 Control Regs Reserved RAM/Cache Reserved RAM/Cache Reserved Reserved Reserved Peripherals Peripherals Reserved Reserved EDMA PERIPHERAL MEMORY VPSS MEMORY MEMORY
boot modes that default DSPBOOTADDR 0x0010 0000 (i.e., boot modes except EMIFA Direct Boot, BOOTMODE[3:0] 0100, FASTBOOT bootloader code disables C64x+ cache (L2, L1P, L1D) that upon exit from bootloader code, C64x+ memories configured (L2CFG.L2MODE L1PCFG.L1PMODE L1DCFG.L1DMODE 0h). cache required, application code must explicitly enable cache. more information boot modes, Section 3.4.1, Boot Modes. more information bootloader, Using TMS320DM643x Bootloader Application Report (literature number SPRAAG0). EMIFA Direct Boot (BOOTMODE[3:0] 0100, FASTBOOT bootloader executed-that RAM/Cache defaults (L2CFG.L2MODE 0h); RAM/Cache defaults cache (L1PCFG.L1PMODE 7h); RAM/Cache defaults cache (L1DCFG.L1DMODE 7h). EMIFA functionally supported DM6437 device, therefore, pinned out.
Device Overview
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TMS320DM6437 Digital Media Processor
Table 2-4. Configuration Memory Summary
START ADDRESS 0x0180 0000 0x0181 0000 0x0181 1000 0x0181 2000 0x0182 0000 0x0183 0000 0x0184 0000 0x0185 0000 0x0188 0000 0x01BC 0000 0x01BC 0100 0x01BC 0400 0x01C0 0000 0x01C1 0000 0x01C1 0400 0x01C1 0800 0x01C1 0C00 0x01C1 A000 0x01C1 A800 0x01C2 0000 0x01C2 0400 0x01C2 0800 0x01C2 1000 0x01C2 1400 0x01C2 1800 0x01C2 1C00 0x01C2 2000 0x01C2 2400 0x01C2 2800 0x01C2 2C00 0x01C2 3000 0x01C2 4000 0x01C2 5400 0x01C4 0000 0x01C4 0800 0x01C4 0C00 0x01C4 1000 0x01C4 2000 0x01C6 7000 0x01C6 7800 0x01C6 8000 0x01C7 0000 0x01C7 4000 0x01C8 0000 ADDRESS 0x0180 FFFF 0x0181 0FFF 0x0181 1FFF 0x0181 2FFF 0x0182 FFFF 0x0183 FFFF 0x0184 FFFF 0x0187 FFFF 0x01BB FFFF 0x01BC 00FF 0x01BC 01FF 0x01BF FFFF 0x01C0 FFFF 0x01C1 03FF 0x01C1 07FF 0x01C1 0BFF 0x01C1 9FFF 0x01C1 A7FF 0x01C1 FFFF 0x01C2 03FF 0x01C2 07FF 0x01C2 0FFF 0x01C2 13FF 0x01C2 17FF 0x01C2 1BFF 0x01C2 1FFF 0x01C2 23FF 0x01C2 27FF 0x01C2 2BFF 0x01C2 2FFF 0x01C2 3FFF 0x01C2 53FF 0x01C3 FFFF 0x01C4 07FF 0x01C4 0BFF 0x01C4 0FFF 0x01C4 1FFF 0x01C6 6FFF 0x01C6 77FF 0x01C6 7FFF 0x01C6 FFFF 0x01C7 3FFF 0x01C7 FFFF 0x01C8 0FFF SIZE (Bytes) 192K 3328K 255K 107K 148K C64x+ C64x+ Interrupt Controller C64x+ Powerdown Controller C64x+ Security C64x+ Revision C64x+ Reserved C64x+ Memory System Reserved Reserved Reserved Manager Trace Reserved EDMA EDMA EDMA EDMA Reserved Control Register Reserved UART0 UART1 Reserved Timer0 Timer1 Timer2 (Watchdog) PWM0 PWM1 PWM2 Reserved HECC Control HECC Reserved System Module Controller Controller Power Sleep Controller Reserved GPIO Reserved VPSS Registers Reserved EMAC Control Registers
Access certain registers when there active clock hang device. more information, TMS320DM643x Peripheral Component Interconnect (PCI) Reference Guide (literature number SPRU985). Software must access "Reserved" locations HECC. Access HECC "Reserved" locations hang device. Device Overview
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Table 2-4. Configuration Memory Summary (continued)
START ADDRESS 0x01C8 1000 0x01C8 2000 0x01C8 4000 0x01C8 4800 0x01D0 0000 0x01D0 0800 0x01D0 1000 0x01D0 1400 0x01D0 1800 0x01E0 0000 0x01E0 1000 0x01E0 2000 ADDRESS 0x01C8 1FFF 0x01C8 3FFF 0x01C8 47FF 0x01CF FFFF 0x01D0 07FF 0x01D0 0FFF 0x01D0 13FF 0x01D0 17FF 0x01DF FFFF 0x01E0 0FFF 0x01E0 1FFF 0x0FFF FFFF SIZE (Bytes) 494K 1018K 226M-8K C64x+ EMAC Control Module Registers EMAC Control Module MDIO Control Registers Reserved McBSP0 McBSP1 McASP0 Control McASP0 Data Reserved EMIFA Control VLYNQ Control Registers Reserved
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TMS320DM6437 Digital Media Processor
Assignments
Extensive multiplexing used accommodate largest number peripheral functions smallest possible package. multiplexing controlled using combination hardware configuration device reset software programmable register settings. more information muxing, Section 3.7, Multiplexed Configurations this document.
2.5.1
(Bottom View)
Figure through Figure show bottom view package assignments four quadrants Figure through Figure show bottom view package assignments four quadrants
DDR_D[7]
DDR_D[9]
DDR_D[12]
DDR_D[14]
DDR_CLK
DDR_CLK
DDR_A[12]
DDR_A[11]
DVDDR2
DDR_D[4]
DDR_D[6]
DDR_D[8]
DDR_D[11]
DDR_D[13]
DDR_D[15]
DDR_CKE
DDR_BA[1]
DDR_A[8]
DDR_D[2]
DDR_D[3]
DDR_D[5]
DDR_DQS[0]
DDR_D[10]
DDR_DQS[1]
DDR_RAS
DDR_BA[0]
DDR_BA[2]
DDR_A[10]
DDR_D[0]
DDR_D[1]
PCIEN
DDR_DQM[0]
DVDDR2
DDR_DQM[1]
DDR_CAS
DDR_WE
DDR_CS
DDR_ZN
TRST
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDD33
EMU0
DVDDR2
DVDDR2
DVDDR2
EMU1
RESETOUT
DVDD33
CVDD
CVDD
CLKOUT0/ PWM2/ GP[84]
RESET
DVDD33
CVDD
CVDD
UCTS0/ GP[87]
URXD0/ GP[85]
URTS0/ PWM0/ GP[88]
HECC_RX/ TINP1L/ URXD1/ GP[56]
RSV3
DVDD33
CVDD
CVDD
CLKS1/ TINP0L/ GP[98]
UTXD0/ GP[86]
HECC_TX/ TOUT1L/ UTXD1/ GP[55]
RSV2
CVDD
CVDD
Figure 2-2. [Quadrant
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DDR_A[6]
DDR_A[5]
DDR_A[0]
DDR_D[16]
DDR_D[18]
DDR_D[21]
DDR_D[27]
DVDDR2
DVDDR2
DDR_A[7]
DDR_A[4]
DDR_A[2]
DDR_D[17]
DDR_D[19]
DDR_D[22]
DDR_D[24]
DDR_D[29]
DDR_A[9]
DDR_A[3]
DDR_A[1]
DDR_DQS[2]
DDR_D[20]
DDR_DQS[3]
DDR_D[25]
DDR_D[28]
DDR_D[30]
DDR_ZP
DDR_VDDDLL DDR_VSSDLL
DDR_DQM[2]
DDR_VREF
DDR_DQM[3]
DDR_D[23]
DDR_D[26]
DDR_D[31]
DVDDR2
RSV5
DVDDR2
DVDDR2
DVDDR2
DVDDR2
VSSA_1P1V
VSSA_1P8V
VDDA_1P8V
DAC_IOUT_B
DAC_IOUT_A
CVDD
VDDA_1P1V
DAC_RBIAS
DAC_IOUT_D
DAC_IOUT_C
DAC_VREF
CVDD
CVDD
DVDD33
CVDD
DVDDR2
RSV4
PLLPWR18
CVDD
CVDD
DVDD33
DVDD33
MXI/ CLKIN
Figure 2-3. [Quadrant
Device Overview
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CVDD
DVDD33
DVDD33
CVDD
CVDD
YOUT7/ GP[29]
YOUT6/ GP[28]
YOUT5/ GP[27]
DVDD33
DVDD33
DVDD33
YOUT3/ YOUT4/ YOUT2/ GP[26]/ GP[24]/ GP[25]/ (BOOTMODE2) (BOOTMODE3) (FASTBOOT)
VPBECLK/ GP[30]
DVDD33
DVDD33
YOUT1/ GP[23]/ (BOOTMODE1)
COUT6/ EM_D[6]/ GP[20]
COUT7/ EM_D[7]/ GP[21]
YOUT0/ GP[22]/ (BOOTMODE0)
HSYNC/ EM_CS5/ GP[33]
AD28
AD30
EM_WE
EM_WAIT/ (RDY/BSY)
COUT3/ EM_D[3]/ GP[17]
COUT5/ EM_D[5]/ GP[19]
COUT4/ EM_D[4]/ GP[18]
VSYNC/ EM_CS4/ GP[32]
CI2(CCD10)/ EM_A[18]/ PRST/ EM_D[5]/ GP[46] CI4(CCD12)/ EM_A[16]/ PGNT/ EM_D[3]/ GP[48] CI5(CCD13)/ EM_A[15]/ AD29/ EM_D[2]/ GP[49] CI3(CCD11)/ EM_A[17]/ AD31/ EM_D[4]/ GP[47]
C_FIELD/ EM_A[21]/ GP[34]
C_WE/ EM_R/W/ GP[35]
YI4(CCD4)/ GP[40]
EM_OE
COUT0/ EM_D[0]/ GP[14]
COUT2/ EM_D[2]/ GP[16]
COUT1/ EM_D[1]/ GP[15]
VCLK/ GP[31]
CI0(CCD8)/ EM_A[20]/ PINTA/ EM_D[7]/ GP[44] CI1(CCD9)/ EM_A[19]/ PREQ/ EM_D[6]/ GP[45]
YI5(CCD5)/ GP[41]
YI2(CCD2)/ GP[38]
YI0(CCD0)/ GP[36]
EM_BA[1]/ GP[5]/ (AEM0) EM_A[2]/ (CLE)/GP[8]/ (AEAW0/ PLLMS0) EM_A[1]/ (ALE)/GP[9]/ (AEAW1/ PLLMS1)
EM_BA[0]/ GP[6]/ (AEM1) EM_A[0]/ GP[7]/ (AEM2) EM_A[4]/ GP[10]/ (AEAW2/ PLLMS2)
LCD_OE/ EM_CS3/ GP[13]
EM_CS2/ GP[12]
YI6(CCD6)/ GP[42]
YI3(CCD3)/ GP[39]
YI1(CCD1)/ GP[37]
LCD_FIELD/ EM_A[3]/ GP[11]
YI7(CCD7)/ GP[43]
GP[53]
PCLK/ GP[54]
GP[52]
DVDD33
Figure 2-4. [Quadrant
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DVDD33
AHCLKR0/ CLKR0/ GP[101]
AXR0[1]/ DX0/ GP[104]
CLKS0/ TOUT0L/ GP[97]
DVDD33
CVDD
CVDD
ACLKR0/ CLKX0/ GP[99]
AXR0[0]/ FSR1/ GP[105]
AXR0[2]/ FSX0/ GP[103]
AFSR0/ DR0/ GP[100]
DVDD33
CVDD
CVDD
AHCLKX0/ CLKR1/ GP[108]
AFSX0/ DX1/ GP[107]
AMUTE0/ DR1/ GP[110]
AXR0[3]/ FSR0/ GP[102]
DVDD33
DVDD33
DVDD33
ACLKX0/ CLKX1/ GP[106]
AMUTEIN0/ FSX1/ GP[109]
GP[4]/ PWM1
DVDD33
DVDD33
DVDD33
AD0/ GP[0]
AD1/ GP[1]
AD2/ GP[2]
AD4/ GP[3]
RSV1
DVDD33
DVDD33
AD26
HAS/ MDIO/ AD3/ GP[83] HCS/ MDCLK/ AD5/ GP[81]
HRDY/ MRXD2/ PCBE0/ GP[80] HINT/ MRXD3/ AD6/ GP[82] HDS1/ MRXD1/ AD7/ GP[79]
HCNTL1/ MTXEN/ AD11/ GP[75] HDS2/ MRXD0/ AD9/ GP[78]
HD14/ MTXD0/ AD15/ GP[72] HHWIL/ MRXDV/ AD13/ GP[74] HD13/ MTXD1/ AD14/ GP[71]
HD12/ MTXD2/ PPAR/ GP[70] HD11/ MTXD3/ PCBE1/ GP[69] HD10/ MCRS/ PSERR/ GP[68]
HD6/ HD1/ VLYNQ_TXD1/ VLYNQ_RXD0/ PTRDY/ AD16/ GP[64] GP[59] HD9/ MCOL/ PSTOP/ GP[67] HD4/ VLYNQ_RXD3/ PFRAME/ GP[62]
EM_A[6]/ AD20/ GP[95]
EM_A[9]/ PIDSEL/ GP[92]
EM_A[12]/ PCBE3/ GP[89]
HD0/ VLYNQ_ SCRUN/ AD18/ GP[58]
EM_A[7]/ AD22/ GP[94]
EM_A[11]/ AD24/ GP[90]
HCNTL0/ MRXER/ AD10/ GP[76]
HD7/ HD3/ VLYNQ_TXD2/ VLYNQ_RXD2/ PDEVSEL/ PCBE2/ GP[65] GP[61]
EM_A[5]/ AD19/ GP[96]
EM_A[8]/ AD21/ GP[93]
CI7(CCD15)/ EM_A[13]/ AD25/ EM_D[0]/ GP[51] CI6(CCD14)/ EM_A[14]/ AD27/ EM_D[1]/ GP[50]
DVDD33
DVDD33
HR/W/ MRXCLK/ AD8/ GP[77]
HD15/ MTXCLK/ AD12/ GP[73]
HD8/ HD5/ VLYNQ_TXD3/ VLYNQ_TXD0/ PPERR/ PIRDY/ GP[66] GP[63]
VLYNQ_ CLOCK/ PCICLK/ GP[57]
HD2/ VLYNQ_RXD1/ AD17/ GP[60]
EM_A[10]/ AD23/ GP[91]
Figure 2-5. [Quadrant
Device Overview
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DDR_D[6]
DDR_D[8]
DDR_D[12]
DDR_D[15]
DDR_CLK0
DDR_CLK0
DDR_BS[1]
DDR_BS[2]
DDR_A[10]
DVDDR2
DDR_D[3]
DDR_D[4]
DDR_DQS[0]
DDR_D[10]
DDR_D[13]
DDR_DQS[1]
DDR_CKE
DDR_BS[0]
DDR_A[12]
DDR_A[11]
DDR_D[0]
DDR_D[1]
DDR_D[5]
DDR_DQM[0]
DDR_D[11]
DDR_D[14]
DDR_DQM[1]
DDR_RAS
DDR_CAS
DDR_WE
DDR_CS
DDR_D[2]
PCIEN
DDR_D[7]
DDR_D[9]
DVDDR2
DVDDR2
DVDDR2
DVDDR2
TRST
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
EMU0
EMU1
RESETOUT
DVDD33
CLKOUT0/ PWM2/ GP[84]
RESET
DVDD33
UCTS0/ GP[87]
HECC_RX/ TINP1L/ URXD1/ GP[56] HECC_TX/ TOUT1L/ UTXD1/ GP[55]
DVDD33
CVDD
CVDD
UTXD0/ GP[86]
DVDD33
CVDD
URXD0/ GP[85]
URTS0/ PWM0/ GP[88]
RSV3
CVDD
CVDD
Figure 2-6. [Quadrant
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TMS320DM6437 Digital Media Processor
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DDR_A[7]
DDR_A[4]
DDR_A[1]
DDR_A[0]
DDR_D[18]
DDR_D[21]
DDR_D[22]
DDR_D[25]
DDR_D[28]
DVDDR2
DVDDR2
DDR_A[9]
DDR_A[6]
DDR_A[3]
DDR_DQS[2]
DDR_D[16]
DDR_D[19]
DDR_DQS[3]
DDR_D[23]
DDR_D[26]
DDR_D[30]
DDR_A[8]
DDR_A[5]
DDR_A[2]
DDR_DQM[2]
DDR_D[17]
DDR_D[20]
DDR_DQM[3]
DDR_D[24]
DDR_D[27]
DDR_D[29]
DDR_D[31]
DDR_ZN
DDR_ZP
DDR_VDDDLL
DDR_VSSDLL
RSV5
DVDDR2
DDR_VREF
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
VDDA_1P8V
DAC_IOUT_A
DAC_VREF
VSSA_1P8V DAC_RBIAS DAC_IOUT_B
VSSA_1P1V
VDDA_1P1V
DAC_IOUT_C DAC_IOUT_D
CVDD
CVDD
DVDD33
RSV4
DVDD33
DVDD33
CVDD
DVDD33
PLLPWR18
MXI/ CLKIN
CVDD
DVDD33
DVDD33
Figure 2-7. [Quadrant
Device Overview
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CVDD
CVDD
YOUT5/ GP[27]
YOUT2/ GP[24]/
(BOOTMODE2)
DVDD33
CVDD
DVDD33
YOUT4/ YOUT1/ GP[26]/ GP[23]/ (FASTBOOT) (BOOTMODE1)
YOUT7/ GP[29]
VPBECLK/ GP[30]
CVDD
CVDD
DVDD33
YOUT0/ GP[22]/
(BOOTMODE0)
YOUT6/ GP[28]
HSYNC/ EM_CS5/ GP[33]
DVDD33
COUT7/ EM_D[7]/ GP[21]
YOUT3/ GP[25]/
(BOOTMODE3)
VSYNC/ EM_CS4/ GP[32]
DVDD33
COUT1/ EM_D[1]/ GP[15]
COUT4/ EM_D[4]/ GP[18]
VCLK/ GP[31]
DVDD33
COUT3/ EM_D[3]/ GP[17] EM_BA[0]/ GP[6]/ (AEM1)
COUT6/ EM_D[6]/ GP[20]
COUT5/ EM_D[5]/ GP[19]
DVDD33
DVDD33
DVDD33
DVDD33
COUT0/ EM_D[0]/ GP[14]
COUT2/ EM_D[2]/ GP[16]
AD26
AD28
AD30
DVDD33
DVDD33
EM_OE
EM_WAIT/ (RDY/BSY)
LCD_FIELD/ EM_A[3]/ GP[11] EM_A[0]/ GP[7]/ (AEM2) EM_A[4]/ GP[10]/ (AEAW2/ PLLMS2)
LCD_OE/ EM_CS3/ GP[13]
EM_A[11]/ AD24/ GP[90]
EM_A[12]/ PCBE3/ GP[89] CI7(CCD15)/ EM_A[13]/ AD25/ EM_D[0]/ GP[51]
CI5(CCD13)/ EM_A[15]/ AD29/ EM_D[2]/ GP[49] CI4(CCD12)/ EM_A[16]/ PGNT/ EM_D[3]/ GP[48] CI6(CCD14)/ EM_A[14]/ AD27/ EM_D[1]/ GP[50]
CI1(CCD9)/ EM_A[19]/ PREQ/ EM_D[6]/ GP[45] CI3(CCD11)/ EM_A[17]/ AD31/ EM_D[4]/ GP[47] CI2(CCD10)/ EM_A[18]/ PRST/ EM_D[5]/ GP[46]
CI0(CCD8)/ EM_A[20]/ PINTA/ EM_D[7]/ GP[44]
C_FIELD/ EM_A[21]/ GP[34]
C_WE/ EM_R/W/ GP[35]
YI4(CCD4)/ GP[40]
EM_WE
EM_BA[1]/ GP[5[/ (AEM0) EM_A[1]/ (ALE)/GP[9]/ (AEAW1/ PLLMS1) EM_A[2]/ (CLE)/GP[8]/ (AEAW0/ PLLMS0)
EM_CS2/ GP[12]
YI6(CCD6)/ GP[42]
YI5(CCD5)/ GP[41]
YI2(CCD2) GP[38]
YI1(CCD1)/ GP[37]
YI0(CCD0)/ GP[36]
YI7(CCD7)/ GP[43]
YI3(CCD3)/ GP[39]
GP[53]
PCLK/ GP[54]
GP[52]
DVDD33
Figure 2-8. [Quadrant
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DVDD33
CLKS1/ TINP0L/ GP[98]
CLKS0/ TOUT0L/ GP[97]
RSV2
DVDD33
CVDD
AHCLKR0/ CLKR0/ GP[101]
AXR0[1]/ DX0/ GP[104]
AFSR0/ DR0/ GP[100]
DVDD33
CVDD
ACLKR0/ CLKX0/ GP[99]
AXR0[2]/ FSX0/ GP[103]
AXR0[3]/ FSR0/ GP[102]
DVDD33
CVDD
CVDD
AHCLKX0/ CLKR1/ GP[108]
AXR0[0]/ FSR1/ GP[105]
AMUTE0/ DR1/ GP[110]
DVDD33
ACLKX0/ CLKX1/ GP[106]
AFSX0/ DX1/ GP[107]
AMUTEIN0/ FSX1/ GP[109]
DVDD33
AD2/ GP[2]
AD4/ GP[3]
GP[4]/ PWM1
DVDD33
AD0/ GP[0]
AD1/ GP[1]
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
HCS/ MDCLK/ AD5/ GP[81] HAS/ MDIO/ AD3/ GP[83]
HINT/ MRXD3/ AD6/ GP[82] HDS2/ MRXD0/ AD9/ GP[78] HCNTL0/ MRXER/ AD10/ GP[76]
HHWIL/ MRXDV/ AD13/ GP[74] HRDY/ MRXD2/ PCBE0/ GP[80] HDS1/ MRXD1/ AD7/ GP[79] HR/W/ MRXCLK/ AD8/ GP[77]
RSV1
DVDD33
DVDD33
DVDD33
HCNTL1/ MTXEN/ AD11/ GP[75] HD13/ MTXD1/ AD14/ GP[71] HD15/ MTXCLK/ AD12/ GP[73]
HD12/ MTXD2/ PPAR/ GP[70] HD14/ MTXD0/ AD15/ GP[72] HD11/ MTXD3/ PCBE1/ GP[69]
HD9/ MCOL/ PSTOP/ GP[67] HD10/ MCRS/ PSERR/ GP[68] HD8/ PPERR/ GP[66]
HD6/
VLYNQ_TXD1/
HD4/
VLYNQ_RXD3/
HD1/
VLYNQ_RXD0
PTRDY/ GP[64] HD7/
VLYNQ_TXD2/
PFRAME/ GP[62] HD3/
VLYNQ_RXD2/
AD16/ GP[59] HD0/ VLYNQ_ SCRUN/ AD18/ GP[58] HD2/
VLYNQ_RXD1/
EM_A[7]/ AD22/ GP[94]
EM_A[9]/ PIDSEL/ GP[92]
DVDD33
PDEVSEL/ GP[65] HD5/ RDY/ GP[63]
PCBE2/ GP[61] VLYNQ_ CLOCK/ PCICLK/ GP[57]
EM_A[6]/ AD20/ GP[95]
EM_A[10]/ AD23/ GP[91]
DVDD33
VLYNQ_TXD3/ VLYNQ_TXD0/
AD17/ GP[60]
EM_A[5]/ AD19/ GP[96]
EM_A[8]/ AD21/ GP[93]
Figure 2-9. [Quadrant
Device Overview
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TMS320DM6437 Digital Media Processor
Terminal Functions
terminal functions tables (Table through Table 2-32) identify external signal names, associated (ball) numbers along with mechanical package designator, type, whether internal pullup pulldown resistors, functional description. more detailed information device configuration, peripheral selection, multiplexed/shared pin, debugging considerations, Device Configurations section this data manual. device boot configuration pins (except PCIEN) multiplexed configuration pins- meaning they multiplexed with functional pins. These pins function device boot configuration pins only during device reset. input states these pins sampled latched into BOOTCFG register when device reset deasserted (see Note below). After device reset deasserted, values these multiplexed pins longer have hold configuration. PCIEN standalone configuration pin. value latched into BOOTCFG register when device reset deasserted (see Note below). Unlike multiplexed device boot configuration pins, value PCIEN even after device reset deasserted must hold configuration. proper device operation, external pullup/pulldown resistors required these device boot configuration pins. Section 3.9.1, Pullup/Pulldown Resistors discusses situations where external pullup/pulldown resistors required. Note: Internal chip, device reset pins RESET logically AND'd together purpose latching device boot configuration pins. values device boot configuration pins latched into BOOTCFG register when logical RESET transitions from low-to-high.
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Table 2-5. BOOT Terminal Functions
SIGNAL NAME TYPE OTHER BOOT YOUT3/GP[25]/ (BOOTMODE3) YOUT2/GP[24]/ (BOOTMODE2) YOUT1/GP[23]/ (BOOTMODE1) YOUT0/GP[22]/ (BOOTMODE0) YOUT4/GP26]/ (FASTBOOT) R0/EM_A[4]/ GP[10]/ (AEAW2/PLLMS2) G1/EM_A[1]/ (ALE)/GP[9]/ (AEAW1/PLLMS1) B1/EM_A[2]/ (CLE)/GP[8]/ (AEAW0/PLLMS0) R1/EM_A[0]/ GP[7]/(AEM2) R2/EM_BA[0]/ GP[6]/(AEM1) I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 Fast Boot Fast Boot Fast Boot EMIFA Address Width (AEAW) Fast Boot Multiplier Select (PLLMS). These configuration pins serve purposes which based AEM[2:0] settings. AEM[2:0] [8-bit EMIFA (Async) Pinout Mode AEAW/PLLMS pins serve AEAW function select EMIFA Address Width. other modes, AEAW/PLLMS pins select multiplier fast boot. more details, Section 3.5.1.2, EMIFA Address Width Select (AEAW) Fast Boot Multipler Select (PLLMS). Selects EMIFA Pinout Mode DM6437 supports following EMIFA Pinout Modes: AEM[2:0] AEM[2:0] AEM[2:0] AEM[2:0] AEM[2:0] 000, 001, 011, 100, 101, EMIFA 8-bit EMIFA (Async) Pinout Mode 8-bit EMIFA (Async) Pinout Mode 8-bit EMIFA (NAND) Pinout Mode 8-bit EMIFA (NAND) Pinout Mode I/O/Z DVDD33 Bootmode configuration bits. These bootmode functions along with FASTBOOT function determine what device bootmode configuration selected. DM6437 device supports several types bootmodes along with FASTBOOT option; more details types/options, Section 3.4.1, Boot Modes. DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
I/O/Z I/O/Z
B2/EM_BA[1]/ GP[5]/(AEM0)
I/O/Z
DVDD33
This signal doesn't actually affect EMIFA module. only affects EMIFA pinned out. YOUT6/ GP[28] DVDD33 proper DM6437 device operation, this both routed 3-stated (not driven) during device reset, must pulled down external resistor. more detailed information pullup/pulldown resistors, Section 3.9.1, Pullup/Pulldown Resistors. Enable function disabled [default] function enabled proper DM6437 device operation, this both routed 3-stated (not driven) during device reset, must pulled external resistor. more detailed information pullup/pulldown resistors, Section 3.9.1, Pullup/Pulldown Resistors.
I/O/Z
PCIEN
DVDD33 DVDD33
YOUT5/GP[27]
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-6. Oscillator/PLL Terminal Functions
SIGNAL NAME TYPE OTHER OSCILLATOR, MXI/ CLKIN MXVDD MXVSS PLLPWR18 MXVDD MXVDD
DESCRIPTION
Crystal input oscillator (system oscillator, typically MHz). internal oscillator bypassed, this external oscillator clock input. Crystal output oscillator power supply oscillator. board, this connected same power supply DVDDR2. Ground oscillator power supply PLLs
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information external board connections, Section 6.6, External Clock Input From MXI/CLKIN Pin. more information, Recommended Operating Conditions table
Table 2-7. Clock Generator Terminal Functions
SIGNAL NAME TYPE OTHER CLOCK GENERATOR CLKOUT0/ PWM2/GP[84] DVDD33 This multiplexed between System Clock generator (PLL1), PWM2, GPIO. System Clock generator (PLL1), clock output CLKOUT0. This configurable other MHz-divided-down /32) clock outputs. DESCRIPTION
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-8. RESET JTAG Terminal Functions
SIGNAL NAME TYPE OTHER RESET RESET RESETOUT DVDD33 DVDD33 DVDD33 JTAG TRST EMU1 EMU0 I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 JTAG test-port mode select input. proper device operation, oppose this pin. JTAG test-port data output JTAG test-port data input JTAG test-port clock input JTAG test-port reset. IEEE 1149.1 JTAG compatibility, IEEE 1149.1 JTAG compatibility statement portion this data sheet Emulation Emulation Device reset Reset output status pin. RESETOUT indicates when device reset. Power-on reset. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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TMS320DM6437 Digital Media Processor
Table 2-9. EMIFA Terminal Functions (Boot Configuration)
SIGNAL NAME TYPE OTHER EMIFA: BOOT CONFIGURATION R0/EM_A[4]/ GP[10]/ (AEAW2/PLLMS2) G1/EM_A[1]/ (ALE)/GP[9]/ (AEAW1/PLLMS1) B1/EM_A[2]/ (CLE)/GP[8]/ (AEAW0/PLLMS0) B2/EM_BA[1]/ GP[5]/(AEM0) R2/EM_BA[0]/ GP[6]/(AEM1) EM_A[0]/ GP[7]/(AEM2) I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 These pins multiplexed between VPBE (VENC), EMIFA, GPIO. When RESET asserted, these pins function EMIFA configuration pins. reset AEM[2:0] (EMIFA 8-bit Async mode), then input states AEAW[2:0] sampled EMIFA Address Width. After reset, these pins function VPBE (VENC), EMIFA, GPIO functions based selection. more details AEAW/PLLMS functions, Section 3.5.1.2, EMIFA Address Width (AEAW) Fast Boot Multiplier Select (PLLMS). These pins multiplexed between VPBE (VENC), EMIFA, GPIO. When RESET asserted, these pins function EMIFA configuration pins. reset, input states AEM[2:0] sampled EMIFA Pinout Mode. more details, Section 3.5.1, Configurations Reset. After reset, these pins function VPBE (VENC), EMIFA, GPIO functions based selection. more details functions, Section 3.5.1.1, EMIFA Pinout Mode (AEM[2:0]). DESCRIPTION
I/O/Z
I/O/Z I/O/Z I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 001)
SIGNAL NAME TYPE OTHER DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit ASYNC/NOR (EMIFA Pinout Mode AEM[2:0] 001) Actual functions determined PINMUX0 PINMUX1 register settings (e.g., PCIEN, AEAW[2:0], AEM[2:0], etc.). more details, Section 3.7, Multiplexed Configurations. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, this Chip Select output EM_CS2 with asynchronous memories (i.e., flash). This chip select default boot boot modes. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, this Chip Select output EM_CS3 with asynchronous memories (i.e., flash). Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, Chip Select output EM_CS4 with asynchronous memories (i.e., flash). Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, Chip Select output EM_CS5 with asynchronous memories (i.e., flash). Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPFE (CCDC), EMIFA, GPIO. EMIFA, read/write output EM_R/W. EMIFA (ASYNC/NOR), this wait state extension input EM_WAIT. EMIFA, output enable output EM_OE. EMIFA, write enable output EM_WE. This multiplexed between VPBE (VENC), EMIFA, GPIO. R2/EM_BA[0]/ GP[6]/(AEM1) I/O/Z DVDD33 EMIFA, this Bank Address output (EM_BA[0]). When connected 8-bit asynchronous memory, this lowest order byte address. This multiplexed between VPBE (VENC), EMIFA, GPIO. B2/EM_BA[1]/ GP[5]/(AEM0) I/O/Z DVDD33 EMIFA, this Bank Address output EM_BA[1]. When connected 8-bit asynchronous memory, this address.
G0/EM_CS2/ GP[12]
I/O/Z
DVDD33
LCD_OE/EM_CS3/ GP[13]
I/O/Z
DVDD33
VSYNC/EM_CS4/ GP[32]
I/O/Z
DVDD33
HSYNC/EM_CS5/ GP[33]
I/O/Z
DVDD33
C_WE/EM_R/W/ GP[35] EM_WAIT/ (RDY/BSY) EM_OE EM_WE
I/O/Z I/O/Z I/O/Z I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
TMS320DM6437 Digital Media Processor
Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 001) (continued)
SIGNAL NAME C_FIELD/ EM_A[21]/GP[34] CI0(CCD8)/ EM_A[20]/ PINTA/ EM_D[7]/GP[44] CI1(CCD9)/ EM_A[19]/ PREQ/ EM_D[6]/GP[45] CI2(CCD10)/ EM_A[18]/ PRST/ EM_D[5]/GP[46] CI3(CCD11)/ EM_A[17]/ AD31/ EM_D[4]/GP[47] CI4(CCD12)/ EM_A[16]/ PGNT/ EM_D[3]/GP[48] CI5(CCD13)/ EM_A[15]/ AD29/ EM_D[2]/GP[49] CI6(CCD14)/ EM_A[14]/ AD27/ EM_D[1]/GP[50] CI7(CCD15)/ EM_A[13]/ AD25/ EM_D[0]/GP[51] EM_A[12]/PCBE3/ GP[89] EM_A[11]/AD24/ GP[90] EM_A[10]/AD23/ GP[91] EM_A[9]/PIDSEL/ GP[92] EM_A[8]/AD21/ GP[93] EM_A[7]/AD22/ GP[94] EM_A[6]/AD20/ GP[95] TYPE OTHER DVDD33 DVDD33 DESCRIPTION This multiplexed between VPFE (CCDC), EMIFA, GPIO. EMIFA, address output EM_A[21]. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. EMIFA (AEM[2:0] 001), this address output EM_A[20] AEAW[2:0] 100b. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. EMIFA (AEM[2:0] 001), this address output EM_A[19] AEAW[2:0] 100b. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. EMIFA (AEM[2:0] 001), this address output EM_A[18] AEAW[2:0] 011/100b. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. EMIFA (AEM[2:0] 001), this address output EM_A[17] AEAW[2:0] 011/100b. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. EMIFA (AEM[2:0] 001), this address output EM_A[16] AEAW[2:0] 010/011/100b. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. EMIFA (AEM[2:0] 001), this address output EM_A[15] AEAW[2:0] 010/011/100b. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. EMIFA (AEM[2:0] 001), this address output EM_A[14] AEAW[2:0] 001/010/011/100b. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. EMIFA (AEM[2:0] 001), this address output EM_A[13] AEAW[2:0] 001/010/011/100b. This multiplexed between EMIFA, PCI, GPIO. EMIFA, this address output EM_A[12]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, this address output EM_A[11]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, this address output EM_A[10]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, this address output EM_A[9]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, this address output EM_A[8]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, this address output EM_A[7]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, this address output EM_A[6].
I/O/Z
I/O/Z
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 001) (continued)
SIGNAL NAME EM_A[5]/AD19/ GP[96] R0/EM_A[4]/ GP[10]/ (AEAW2/PLLMS2) B0/LCD_FIELD/ EM_A[3]/GP[11] B1/EM_A[2]/ (CLE)/GP[8]/ (AEAW0/PLLMS0) G1/EM_A[1]/ (ALE)/GP[9]/ (AEAW1/PLLMS1) TYPE OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DESCRIPTION This multiplexed between EMIFA, PCI, GPIO. EMIFA, this address output EM_A[5]. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, this address output EM_A[4]. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, this address output EM_A[3]. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, this address output EM_A[2]. This multiplexed between VPBE (VENC), EMIFA, GPIO. When used EMIFA, this address output EM_A[1]. This multiplexed between VPBE (VENC), EMIFA, GPIO. EM_A[0]/ GP[7]/(AEM2) I/O/Z DVDD33 EMIFA, this Address output EM_A[0], which least significant 32-bit word address. 8-bit asynchronous memory, this address.
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
COUT0/EM_D0/ GP[14] COUT1/EM_D1/ GP[15] COUT2/EM_D2/ GP[16] COUT3/EM_D3/ GP[17] COUT4/EM_D4/ GP[18] COUT5/EM_D5/ GP[19] COUT6/EM_D6/ GP[20] COUT7/EM_D7/ GP[21]
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. When used EMIFA (NAND) this Address Latch Enable output (ALE). This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. When used EMIFA (NAND), this Command Latch Enable output (CLE). When used EMIFA (NAND), this ready/busy input (RDY/BSY). When used EMIFA (NAND), this read enable output (RE). When used EMIFA (NAND), this write enable output (WE). These pins multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA (AEM[2:0] 001), these pins 8-bit bi-directional data (EM_D[7:0]).
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode AEM[2:0] 001) G1/EM_A[1]/ (ALE)/GP[9]/ (AEAW1/PLLMS1) DVDD33
I/O/Z
B1/EM_A[2]/ (CLE)/GP[8]/ (AEAW0/PLLMS0) EM_WAIT/ (RDY/BSY) EM_OE EM_WE
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33
I/O/Z I/O/Z I/O/Z
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TMS320DM6437 Digital Media Processor
Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 001) (continued)
SIGNAL NAME TYPE OTHER DESCRIPTION This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. EMIFA (NAND), this Chip Select output EM_CS2 with NAND flash. This chip select default boot boot modes. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. LCD_OE/EM_CS3/ GP[13] DVDD33 EMIFA (NAND), this Chip Select output EM_CS3 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. VSYNC/EM_CS4/ GP[32] DVDD33 EMIFA (NAND), Chip Select output EM_CS4 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. HSYNC/EM_CS5/ GP[33] DVDD33 EMIFA (NAND), Chip Select output EM_CS5 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state.
G0/EM_CS2/ GP[12]
I/O/Z
DVDD33
I/O/Z
I/O/Z
I/O/Z
COUT0/EM_D0/ GP[14] COUT1/EM_D1/ GP[15] COUT2/EM_D2/ GP[16] COUT3/EM_D3/ GP[17] COUT4/EM_D4/ GP[18] COUT5/EM_D5/ GP[19] COUT6/EM_D6/ GP[20] COUT7/EM_D7/ GP[21]
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 These pins multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. EMIFA (NAND) AEM[2:0] 001, these 8-bit bi-directional data (EM_D[7:0]).
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 011)
SIGNAL NAME TYPE OTHER DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit ASYNC/NOR with Reduced Address Reach (EMIFA Pinout Mode AEM[2:0] 011) Actual functions determined PINMUX0 PINMUX1 register settings (e.g., PCIEN, AEAW[2:0], AEM[2:0], etc.). more details, Section 3.7, Multiplexed Configurations. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, this Chip Select output EM_CS2 with asynchronous memories (i.e., flash). This chip select default boot boot modes. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, this Chip Select output EM_CS3 with asynchronous memories (i.e., flash). Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, Chip Select output EM_CS4 with asynchronous memories (i.e., flash). Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA, GPIOD. EMIFA, Chip Select output EM_CS5 with asynchronous memories (i.e., flash). Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPFE (CCDC), EMIFA, GPIO. EMIFA, read/write output EM_R/W. EMIFA (ASYNC/NOR), this wait state extension input EM_WAIT. EMIFA, output enable output EM_OE. EMIFA, write enable output EM_WE. This multiplexed between VPBE (VENC), EMIFA, GPIO. R2/EM_BA[0]/ GP[6]/(AEM1) I/O/Z DVDD33 EMIFA, this Bank Address output (EM_BA[0]). When connected 8-bit asynchronous memory, this lowest order byte address. This multiplexed between VPBE (VENC), EMIFA, GPIO. B2/EM_BA[1]/ GP[5]/(AEM0) I/O/Z DVDD33 EMIFA, this Bank Address output EM_BA[1]. When connected 8-bit asynchronous memory, this address.
G0/EM_CS2/ GP[12]
I/O/Z
DVDD33
LCD_OE/EM_CS3/ GP[13]
I/O/Z
DVDD33
VSYNC/EM_CS4/ GP[32]
I/O/Z
DVDD33
HSYNC/EM_CS5/ GP[33]
I/O/Z
DVDD33
C_WE/EM_R/W/ GP[35] EM_WAIT/ (RDY/BSY) EM_OE EM_WE
I/O/Z I/O/Z I/O/Z I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
TMS320DM6437 Digital Media Processor
Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 011) (continued)
SIGNAL NAME CI0(CCD8)/ EM_A[20]/ PINTA/ EM_D[7]/GP[44] CI1(CCD9)/ EM_A[19]/ PREQ/ EM_D[6]/GP[45] CI2(CCD10)/ EM_A[18]/ PRST/ EM_D[5]/GP[46] CI3(CCD11)/ EM_A[17]/ AD31/ EM_D[4]/GP[47] CI4(CCD12)/ EM_A[16]/ PGNT/ EM_D[3]/GP[48] CI5(CCD13)/ EM_A[15]/ AD29/ EM_D[2]/GP[49] CI6(CCD14)/ EM_A[14]/ AD27/ EM_D[1]/GP[50] CI7(CCD15)/ EM_A[13]/ AD25/ EM_D[0]/GP[51] EM_A[12]/PCBE3/ GP[89] EM_A[11]/AD24/ GP[90] EM_A[10]/AD23/ GP[91] EM_A[9]/PIDSEL/ GP[92] EM_A[8]/AD21/ GP[93] EM_A[7]/AD22/ GP[94] EM_A[6]/AD20/ GP[95] EM_A[5]/AD19/ GP[96] R0/EM_A[4]/ GP[10]/ (AEAW2/PLLMS2) TYPE OTHER DESCRIPTION
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. EMIFA (AEM[2:0] 011], these pins 8-bit bi-directional data (EM_D[7:0]).
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between EMIFA, PCI, GPIO. EMIFA, address output EM_A[12]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, address output EM_A[11]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, address output EM_A[10]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, address output EM_A[9]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, address output EM_A[8]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, address output EM_A[7]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, address output EM_A[6]. This multiplexed between EMIFA, PCI, GPIO. EMIFA, address output EM_A[5]. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, address output EM_A[4].
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 011) (continued)
SIGNAL NAME B0/LCD_FIELD/ EM_A[3]/GP[11] B1/EM_A[2]/ (CLE)/GP[8]/ (AEAW0/PLLMS0) G1/EM_A[1]/ (ALE)/GP[9]/ (AEAW1/PLLMS1) EM_A[0]/ GP[7]/(AEM2) TYPE OTHER DVDD33 DVDD33 DVDD33 DESCRIPTION This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, address output EM_A[3]. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, address output EM_A[2]. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, address output EM_A[1]. This multiplexed between VPBE (VENC), EMIFA, GPIO. EMIFA, this Address output EM_A[0], which least significant 32-bit word address. 8-bit asynchronous memory, this address. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. When used EMIFA (NAND) this Address Latch Enable output (ALE). This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. When used EMIFA (NAND) this Command Latch Enable output (CLE). When used EMIFA (NAND), ready/busy input (RDY/BSY). When used EMIFA (NAND), this read enable output (RE). When used EMIFA (NAND), this write enable output (WE). This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. EMIFA, this Chip Select output EM_CS2 with NAND flash. This chip select default boot boot modes. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. LCD_OE/EM_CS3/ GP[13] DVDD33 EMIFA, this Chip Select output EM_CS3 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. VSYNC/EM_CS4/ GP[32] DVDD33 EMIFA, Chip Select output EM_CS4 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state.
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD33
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode AEM[2:0] 011) G1/EM_A[1]/ (ALE)/GP[9]/ (AEAW1/PLLMS1) DVDD33
I/O/Z
B1/EM_A[2]/ (CLE)/GP[8]/ (AEAW0/PLLMS0) EM_WAIT/ (RDY/BSY) EM_OE EM_WE
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33
I/O/Z I/O/Z I/O/Z
G0/EM_CS2/ GP[12]
I/O/Z
DVDD33
I/O/Z
I/O/Z
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TMS320DM6437 Digital Media Processor
Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 011) (continued)
SIGNAL NAME TYPE OTHER DESCRIPTION This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. HSYNC/EM_CS5/ GP[33] DVDD33 EMIFA, Chip Select output EM_CS5 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state.
I/O/Z
CI7(CCD15) EM_A[13]/ AD25/ EM_D[0]/GP[51] CI6(CCD14) EM_A[14]/ AD27/ EM_D[1]/GP[50] CI5(CCD13) EM_A[15]/ AD29/ EM_D[2]/GP[49] CI4(CCD12) EM_A[16]/ PGNT/ EM_D[3]/GP[48] CI3(CCD11)/ EM_A[17]/ AD31/ EM_D[4]/GP[47] CI2(CCD10)/ EM_A[18]/ PRST/ EM_D[5]/GP[46] CI1(CCD9)/ EM_A[19]/ PREQ/ EM_D[6]/GP[45] CI0(CCD8)/ EM_A[20]/ PINTA/ EM_D[7]/GP[44]
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
These pins multiplexed between VPFE (CCDC), EMIFA (NAND), PCI, GPIO. EMIFA (NAND) AEM[2:0] 011, these pins 8-bit bi-directional data (EM_D[7:0]).
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 100)
SIGNAL NAME TYPE OTHER DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode AEM[2:0] 100) Actual functions determined PINMUX0 PINMUX1 register settings (e.g., PCIEN, AEAW[2:0], AEM[2:0], etc.). more details, Section 3.7, Multiplexed Configurations. G1/EM_A[1]/ (ALE)/GP[9]/ (AEAW1/PLLMS1) DVDD33 This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. When used EMIFA (NAND) this Address Latch Enable output (ALE). This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. When used EMIFA (NAND) this Command Latch Enable output (CLE). When used EMIFA (NAND), ready/busy input (RDY/BSY). When used EMIFA (NAND), this read enable output (RE). When used EMIFA (NAND), this write enable output (WE). This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. EMIFA, this Chip Select output EM_CS2 with NAND flash. This chip select default boot boot modes. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. LCD_OE/EM_CS3/ GP[13] DVDD33 EMIFA, this Chip Select output EM_CS3 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. VSYNC/EM_CS4/ GP[32] DVDD33 EMIFA, Chip Select output EM_CS4 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. HSYNC/EM_CS5/ GP[33] DVDD33 EMIFA, Chip Select output EM_CS5 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state.
I/O/Z
B1/EM_A[2]/ (CLE)/GP[8]/ (AEAW0/PLLMS0) EM_WAIT/ (RDY/BSY) EM_OE EM_WE
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33
I/O/Z I/O/Z I/O/Z
G0/EM_CS2/ GP[12]
I/O/Z
DVDD33
I/O/Z
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
TMS320DM6437 Digital Media Processor
Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 100) (continued)
SIGNAL NAME CI7(CCD15) EM_A[13]/ AD25/ EM_D[0]/GP[51] CI6(CCD14) EM_A[14]/ AD27/ EM_D[1]/GP[50] CI5(CCD13) EM_A[15]/ AD29/ EM_D[2]/GP[49] CI4(CCD12) EM_A[16]/ PGNT/ EM_D[3]/GP[48] CI3(CCD11)/ EM_A[17]/ AD31/ EM_D[4]/GP[47] CI2(CCD10)/ EM_A[18]/ PRST/ EM_D[5]/GP[46] CI1(CCD9)/ EM_A[19]/ PREQ/ EM_D[6]/GP[45] CI0(CCD8)/ EM_A[20]/ PINTA/ EM_D[7]/GP[44] TYPE OTHER DESCRIPTION
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
These pins multiplexed between VPFE (CCDC), EMIFA (NAND), PCI, GPIO. EMIFA (NAND) AEM[2:0] 100, these pins 8-bit bi-directional data (EM_D[7:0]).
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-13. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 101)
SIGNAL NAME TYPE OTHER DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode AEM[2:0] 101) Actual functions determined PINMUX0 PINMUX1 register settings (e.g., PCIEN, AEAW[2:0], AEM[2:0], etc.). more details, Section 3.7, Multiplexed Configurations. G1/EM_A[1]/ (ALE)/GP[9]/ (AEAW1/PLLMS1) DVDD33 This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. When used EMIFA (NAND) this Address Latch Enable output (ALE). This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. When used EMIFA (NAND) this Command Latch Enable output (CLE). When used EMIFA (NAND), ready/busy input (RDY/BSY). When used EMIFA (NAND), this read enable output (RE). When used EMIFA (NAND), this write enable output (WE). This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. EMIFA, this Chip Select output EM_CS2 with NAND flash. This chip select default boot boot modes. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. LCD_OE/EM_CS3/ GP[13] DVDD33 EMIFA, this Chip Select output EM_CS3 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. VSYNC/EM_CS4/ GP[32] DVDD33 EMIFA, Chip Select output EM_CS4 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. HSYNC/EM_CS5/ GP[33] DVDD33 EMIFA, Chip Select output EM_CS5 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state.
I/O/Z
B1/EM_A[2]/ (CLE)/GP[8]/ (AEAW0/PLLMS0) EM_WAIT/ (RDY/BSY) EM_OE EM_WE
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33
I/O/Z I/O/Z I/O/Z
G0/EM_CS2/ GP[12]
I/O/Z
DVDD33
I/O/Z
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
TMS320DM6437 Digital Media Processor
Table 2-13. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 101) (continued)
SIGNAL NAME COUT0/EM_D0/ GP[14] COUT1/EM_D1/ GP[15] COUT2/EM_D2/ GP[16] COUT3/EM_D3/ GP[17] COUT4/EM_D4/ GP[18] COUT5/EM_D5/ GP[19] COUT6/EM_D6/ GP[20] COUT7/EM_D7/ GP[21] TYPE OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 These pins multiplexed between VPBE (VENC), EMIFA (NAND), GPIO. EMIFA (NAND) AEM[2:0] 101, these 8-bit bi-directional data (EM_D[7:0]). DESCRIPTION
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-14. DDR2 Memory Controller Terminal Functions
SIGNAL NAME AA15 AA18 AB10 AA10 AA11 AB11 AA12 AB12 AA13 AB13 AA14 AB14 AB15 I/O/Z DVDDR2 DDR2 Address Output I/O/Z DVDDR2 Bank Select Outputs (BA[2:0]). required support DDR2 memories. TYPE OTHER DDR2 Memory Controller DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_DQM[3] DDR_DQM[2] DDR_DQM[1] DDR_DQM[0] DDR_RAS DDR_CAS DDR_DQS[0] DDR_DQS[1] DDR_DQS[2] DDR_DQS[3] DDR_BA[0] DDR_BA[1] DDR_BA[2] DDR_A[12] DDR_A[11] DDR_A[10] DDR_A[9] DDR_A[8] DDR_A[7] DDR_A[6] DDR_A[5] DDR_A[4] DDR_A[3] DDR_A[2] DDR_A[1] DDR_A[0] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DDR2 Clock Output DDR2 Differential Clock Output DDR2 Clock Enable Output DDR2 Active Chip Select Output DDR2 Active Write Enable Output DDR2 Data Mask Outputs DQM3: upper byte data DDR_D[31:24] DQM2: DDR_D[23:16] DQM1: DDR_D[15:8] DQM0: lower byte DDR_D[7:0] DDR2 Access Signal Output DDR2 Column Access Signal Output Data Strobe Input/Outputs each byte 32-bit data bus. They outputs DDR2 memory when writing inputs when reading. They used synchronize data transfers. DQS3 upper byte DDR_D[31:24] DQS2: DDR_D[23:16] DQS1: DDR_D[15:8] DQS0: bottom byte DDR_D[7:0] DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Fore more information, Recommended Operating Conditions table
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Table 2-14. DDR2 Memory Controller Terminal Functions (continued)
SIGNAL NAME DDR_D[31] DDR_D[30] DDR_D[29] DDR_D[28] DDR_D[27] DDR_D[26] DDR_D[25] DDR_D[24] DDR_D[23] DDR_D[22] DDR_D[21] DDR_D[20] DDR_D[19] DDR_D[18] DDR_D[17] DDR_D[16] DDR_D[15] DDR_D[14] DDR_D[13] DDR_D[12] DDR_D[11] DDR_D[10] DDR_D[9] DDR_D[8] DDR_D[7] DDR_D[6] DDR_D[5] DDR_D[4] DDR_D[3] DDR_D[2] DDR_D[1] DDR_D[0] DDR_VREF DDR_VSSDLL DDR_VDDDLL DDR_ZN DDR_ZP AA21 AB20 AA20 AB19 AA19 AB18 AB17 AA17 AB16 AA16
TYPE
OTHER
DESCRIPTION
I/O/Z
DVDDR2
DDR2 bi-directional data configured 32-bits wide 16-bits wide.
Reference voltage input SSTL_18 buffers Ground DDR2 Power (1.8 Volts) DDR2 Digital Locked Loop Impedance control DDR2 outputs. This must connected 200- resistor DVDDR2. Impedance control DDR2 outputs. This must connected 200- resistor VSS.
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-15. Peripheral Component Interconnect (PCI) Terminal Functions
SIGNAL NAME TYPE OTHER CI4(CCD12)/ EM_A[16]/ PGNT/ EM_D[3]/GP[48] CI2(CCD10)/ EM_A[18]/ PRST/ EM_D[5]/GP[46] CI1(CCD9)/ EM_A[19]/ PREQ/ EM_D[6]/GP[45] CI0(CCD8)/ EM_A[20]/ PINTA/ EM_D[7]/GP[44] EM_A[12]/PCBE3/ GP[89] HD3/VLYNQ_RXD2/ PCBE2 /GP[61] HD11/MTXD3/ PCBE1/GP[69] HRDY/MRXD2/ PCBE0/GP[80] EM_A[9]/PIDSEL/ GP[92] VLYNQ_CLOCK/ PCICLK/GP[57] HD4/VLYNQ_RXD3/ PFRAME/GP[62] HD5/VLYNQ_TXD0/ PIRDY/GP[63] HD6/VLYNQ_TXD1/ PTRDY/GP[64] HD7/VLYNQ_TXD2/ PDEVSEL/GP[65] HD8/VLYNQ_TXD3/ PPERR/GP[66] HD9/MCOL/ PSTOP/GP[67] HD10/MCRS/ PSERR/GP[68] HD12/MTXD2/ PPAR/GP[70] I/O/Z DVDD33 This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. mode, this grant This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. mode, this reset This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. mode, this request (O/Z) This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. mode, this interrupt (O/Z) This multiplexed between EMIFA, PCI, GPIO. mode, this command/byte enable (I/O/Z). This multiplexed between HPI, VLYNQ, PCI, GPIO. mode, this command/byte enable (I/O/Z) This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. mode, this command/byte enable (I/O/Z) This multiplexed between HPI, EMAC, PCI, GPIO. mode, this command/byte enable (I/O/Z) This multiplexed between EMIFA, PCI, GPIO. mode, this initialization device select This multiplexed between VLYNQ, PCI, GPIO. mode, this clock This multiplexed between HPI, VLYNQ, PCI, GPIO. mode, this frame (I/O/Z) This multiplexed between HPI, VLYNQ, PCI, GPIO. mode, this initiator ready (I/O/Z) This multiplexed between HPI, VLYNQ, PCI, GPIO. mode, this target ready (I/O/Z) This multiplexed between HPI, VLYNQ, PCI, GPIO. mode, this device select (I/O/Z) This multiplexed between HPI, VLYNQ, PCI, GPIO. mode, this parity error (I/O/Z) This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. mode, this stop (I/O/Z) This multiplexed between HPI, EMAC, PCI, GPIO. mode, this system error (I/O/Z) This multiplexed between HPI, EMAC, PCI, GPIO. mode, this parity (I/O/Z) DESCRIPTION
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-15. Peripheral Component Interconnect (PCI) Terminal Functions (continued)
SIGNAL NAME CI3(CCD11)/ EM_A[17]/ AD31/ EM_D[4]/GP[47] AD30 CI5(CCD13)/ EM_A[15]/ AD29/ EM_D[2]/GP[49] AD28 CI6(CCD14)/ EM_A[14]/ AD27/ EM_D[1]/GP[50] AD26 CI7(CCD15)/ EM_A[13]/ AD25/ EM_D[0]/GP[51] EM_A[11]/AD24/GP[90] EM_A[10]/AD23/GP[91] EM_A[7]/AD22/GP[94] EM_A[8]/AD21/GP[93] EM_A[6]/AD20/GP[95] EM_A[5]/AD19/GP[96] HD0/VLYNQ_SCRUN/ AD18/GP[58] HD2/VLYNQ_RXD1/ AD17/GP[60] HD1/VLYNQ_RXD0/ AD16/GP[59] HD14/MTXD0/ AD15/GP[72] HD13/MTXD1/ AD14/GP[71] HHWIL/MRXDV/ AD13/GP[74] HD15/MTXCLK/ AD12/GP[73] HCNTL1/MTXEN/ AD11/GP[75] TYPE OTHER DESCRIPTION
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 These pins multiplexed between VPFE (CCDC), PCI, EMIFA, HPI, VLYNQ, EMAC (MII), GPIO. PCI, these pins data-address [31:0] (I/O/Z)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-15. Peripheral Component Interconnect (PCI) Terminal Functions (continued)
SIGNAL NAME HCNTL0/MRXER/ AD10/GP[76] HDS2/MRXD0/ AD9/GP[78] HR/W/MRXCLK/ AD8/GP[77] HDS1/MRXD1/ AD7/GP[79] HINT/MRXD3/ AD6/GP[82] HCS/MDCLK/ AD5/GP[81] AD4/GP[3] HAS/MDIO/ AD3/GP[83] AD2/GP[2] AD1/GP[1] AD0/GP[0] TYPE OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 These pins multiplexed between VPFE (CCDC), PCI, EMIFA, HPI, VLYNQ, EMAC (MII), GPIO. PCI, these pins data-address [31:0] (I/O/Z) DESCRIPTION
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
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Table 2-16. EMAC MDIO Terminal Functions
SIGNAL NAME TYPE OTHER EMAC HCNTL1/MTXEN/ AD11/GP[75] HD15/MTXCLK/ AD12/GP[73] HD9/MCOL/ PSTOP/GP[67] HD11/MTXD3/ PCBE1/GP[69] HD12/MTXD2/ PPAR/GP[70] HD13/MTXD1/ AD14/GP[71] HD14/MTXD0/ AD15/GP[72] HR/W/MRXCLK/ AD8/GP[77] HHWIL/MRXDV/ AD13/GP[74] HCNTL0/MRXER/ AD10/GP[76] HD10/MCRS/ PSERR/GP[68] HINT/MRXD3/ AD6/GP[82] HRDY/MRXD2/ PCBE0/GP[80] HDS1/MRXD1/ AD7/GP[79] HDS2/MRXD0/ AD9/GP[78] I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Transmit Enable output MTXEN. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Transmit Clock input MTXCLK. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Collision Detect input MCOL. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Transmit Data output MTXD3. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Transmit Data output MTXD2. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Transmit Data output MTXD1. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Transmit Data output MTXD0. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Receive Clock input MRXCLK. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Receive Data Valid input MRXDV. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Receive Error input MRXER. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Carrier Sense input MCRS. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Receive Data input MRXD3. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Receive Data input MRXD2. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Receive data input MRXD1. This multiplexed between HPI, Ethernet (EMAC), PCI, GPIO. Ethernet mode, Receive Data input MRXD0. MDIO HCS/MDCLK/ AD5/GP[81] HAS/MDIO/ AD3/GP[83] I/O/Z I/O/Z DVDD33 DVDD33 This multiplexed between HPI, MDIO, PCI, GPIO. Ethernet mode, Management Data Clock output MDCLK. This multiplexed between HPI, MDIO, PCI, GPIO. Ethernet mode, Management Data MDIO (I/O/Z). DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-17. VLYNQ Terminal Functions
SIGNAL NAME TYPE OTHER VLYNQ VLYNQ_CLOCK/ PCICLK/GP[57] HD0/VLYNQ_SCRUN/ AD18/GP[58] HD8/VLYNQ_TXD3/ PPERR/GP[66] HD7/VLYNQ_TXD2/ PDEVSEL/GP[65] HD6/VLYNQ_TXD1/ PTRDY/GP[64] HD5/VLYNQ_TXD0/ PIRDY/GP[63] HD4/VLYNQ_RXD3/ PFRAME/GP[62] HD3/VLYNQ_RXD2/ PCBE2/GP[61] HD2/VLYNQ_RXD1/ AD17/GP[60] HD1/VLYNQ_RXD0/ AD16/GP[59] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between VLYNQ, PCI, GPIO. VLYNQ, clock VLYNQ_CLOCK (I/O/Z). This multiplexed between HPI, VLYNQ, PCI, GPIO. VLYNQ, Serial Clock request VLYNQ_SCRUN (I/O/Z). This multiplexed between HPI, VLYNQ, PCI, GPIO. VLYNQ, transmit output VLYNQ_TXD3. This multiplexed between HPI, VLYNQ, PCI, GPIO. VLYNQ, transmit output VLYNQ_TXD2. This multiplexed between HPI, VLYNQ, PCI, GPIO. VLYNQ, transmit output VLYNQ_TXD1. This multiplexed between HPI, VLYNQ, PCI, GPIO. VLYNQ, transmit output VLYNQ_TXD0. This multiplexed between HPI, VLYNQ, PCI, GPIO. VLYNQ, receive input VLYNQ_RXD3. This multiplexed between HPI, VLYNQ, PCI, GPIO. VLYNQ, receive input VLYNQ_RXD2. This multiplexed between HPI, VLYNQ, PCI, GPIO. VLYNQ, receive input VLYNQ_RXD1. This multiplexed between HPI, VLYNQ, PCI, GPIO. VLYNQ, receive input VLYNQ_RXD0. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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TMS320DM6437 Digital Media Processor
Table 2-18. Host-Port Interface Terminal Functions
SIGNAL NAME TYPE OTHER Host-Port Interface (HPI) HD0/VLYNQ_SCRUN/ AD18/GP[58] HD1/VLYNQ_RXD0/ AD16/GP[59] HD2/VLYNQ_RXD1/ AD17/GP[60] HD3/VLYNQ_RXD2/ PCBE2/GP[61] HD4/VLYNQ_RXD3/ PFRAME/GP[62] HD5/VLYNQ_TXD0/ PIRDY/GP[63] HD6/VLYNQ_TXD1/ PTRDY/GP[64] HD7/VLYNQ_TXD2/ PDEVSEL/GP[65] HD8/VLYNQ_TXD3/ PPERR/GP[66] HD9/MCOL/ PSTOP/GP[67] HD10/MCRS/ PSERR/GP[68] HD11/MTXD3/ PCBE1/GP[69] HD12/MTXD2/ PPAR/GP[70] HD13/MTXD1/ AD14/GP[71] HD14/MTXD0/ AD15/GP[72] HD15/MTXCLK/ AD12/GP[73] HHWIL/MRXDV/ AD13/GP[74] I/O/Z I/O/Z DVDD33 This multiplexed between HPI, EMAC, PCI, GPIO. mode, this half-word identification input HHWIL (I). This multiplexed between HPI, EMAC, PCI, GPIO. mode, this control input HCNTL1 (I). state HCNTL1 HCNTL0 determines address, data, control information being transmitted between external host DM6437. This multiplexed between HPI, EMAC, PCI, GPIO. mode, this control input HCNTL0 (I). state HCNTL1 HCNTL0 determines address, data, control information being transmitted between external host DM6437. This multiplexed between HPI, EMAC, PCI, GPIO. mode, this host read write select input HR/W(I). This multiplexed between HPI, EMAC, PCI, GPIO. mode, this host data strobe input HDS2 (I). DVDD33 This multiplexed between HPI, VLYNQ EMAC, PCI, GPIO. mode, these pins host-port data pins HD[15:0] (I/O/Z) multiplexed internally with address lines. DVDD33 DESCRIPTION
HCNTL1/MTXEN/ AD11/GP[75]
I/O/Z
DVDD33
HCNTL0/MRXER/ AD10/GP[76]
I/O/Z
DVDD33
HR/W/MRXCLK/ AD8/GP[77] HDS2/MRXD0/ AD9/GP[78]
I/O/Z I/O/Z
DVDD33 DVDD33
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-18. Host-Port Interface Terminal Functions (continued)
SIGNAL NAME HDS1/MRXD1/ AD7/GP[79] HRDY/MRXD2/ PCBE0/GP[80] HCS/MDCLK/ AD5/GP[81] HINT/RXD3/ AD6/GP[82] HAS/MDIO/ AD3/GP[83] TYPE OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DESCRIPTION This multiplexed between HPI, EMAC, PCI, GPIO. mode, this host data strobe input HDS1 (I). This multiplexed between HPI, EMAC, PCI, GPIO. mode, this host ready output from host (O/Z). This multiplexed between HPI, MDIO, PCI, GPIO. mode, this active chip select input (I). This multiplexed between HPI, EMAC, PCI, GPIO. mode, this host interrupt output HINT (O/Z). This multiplexed between HPI, MDIO, PCI, GPIO. mode, this host address strobe (I). proper operation, this routed out, must pulled external resistor.
I/O/Z I/O/Z
I/O/Z I/O/Z
I/O/Z
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TMS320DM6437 Digital Media Processor
Table 2-19. VPFE Terminal Functions
SIGNAL NAME TYPE OTHER VIDEO/IMAGE (VPFE) PCLK/GP[54] I/O/Z DVDD33 This multiplexed between VPFE (CCDC) GPIO. VPFE mode, this pixel clock input (PCLK) used load image data into Controller (CCDC) pins CI[7:0] YI[7:0]. This multiplexed between VPFE (CCDC) GPIO. VPFE mode, this vertical synchronization signal (VD) that either input (slave mode) output (master mode), which signals start frame CCDC. This multiplexed between VPFE (CCDC) GPIO. VPFE mode, this horizontal synchronization signal (HD) that either input (slave mode) output (master mode), which signals start line CCDC. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. CI7(CCD15)/ EM_A[13]/ AD25/ EM_D[0]/GP[51] I/O/Z DVDD33 When used CCDC input CI7, supports several modes: 16-bit mode, input CCD15. 16-bit YCbCr mode, time multiplexed between inputs. 8-bit YCbCr mode, time multiplexed between CB7, upper 8-bit channel. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. CI6(CCD14)/ EM_A[14]/ AD27/ EM_D[1]/GP[50] I/O/Z DVDD33 When used CCDC input CI6, supports several modes: 16-bit mode, input CCD14. 16-bit YCbCr mode, time multiplexed between inputs. 8-bit YCbCr mode, time multiplexed between CB6, upper 8-bit channel. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. CI5(CCD13)/ EM_A[15]/ AD29/ EM_D[2]/GP[49] I/O/Z DVDD33 When used CCDC input CI5, supports several modes: 16-bit mode, input CCD13. 16-bit YCbCr mode, time multiplexed between CB5, inputs. 8-bit YCbCr mode, time multiplexed between CB5, upper 8-bit channel. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. CI4(CCD12)/ EM_A[16]/ PGNT/ EM_D[3]/GP[48] When used CCDC input CI4, supports several modes: I/O/Z DVDD33 16-bit mode, input CCD12. 16-bit YCbCr mode, time multiplexed between CB4, inputs. 8-bit YCbCr mode, time multiplexed between CB4, upper 8-bit channel. DESCRIPTION
VD/GP[53]
I/O/Z
DVDD33
HD/GP[52]
I/O/Z
DVDD33
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal addition these default functions, YCbCr mode, VPFE Configuration register CCDCFG.YCINSWP field allows user swap function YI[7:0] CI[7:0] pins.
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-19. VPFE Terminal Functions (continued)
SIGNAL NAME TYPE OTHER DESCRIPTION This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. CI3(CCD11)/ EM_A[17]/ AD31/ EM_D[4]/GP[47] When used CCDC input CI3, supports several modes: I/O/Z DVDD33 16-bit mode, input CCD11. 16-bit YCbCr mode, time multiplexed between CB3, inputs. 8-bit YCbCr mode, time multiplexed between CB3, upper 8-bit channel. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. CI2(CCD10)/ EM_A[18]/ PRST/ EM_D[5]/GP[46] This CCDC input supports several modes: I/O/Z DVDD33 16-bit mode, input CCD10. 16-bit YCbCr mode, time multiplexed between CB2, inputs. 8-bit YCbCr mode, time multiplexed between CB2, upper 8-bit channel. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. CI1(CCD9)/ EM_A[19]/ PREQ/ EM_D[6]/GP[45] This CCDC input supports several modes: I/O/Z DVDD33 16-bit mode, input CCD9. 16-bit YCbCr mode, time multiplexed between CB1, inputs. 8-bit YCbCr mode, time multiplexed between CB1, upper 8-bit channel. This multiplexed between VPFE (CCDC), EMIFA, PCI, GPIO. CI0(CCD8)/ EM_A[20]/ PINTA/ EM_D[7]/GP[44] This CCDC input supports several modes: I/O/Z DVDD33 16-bit mode, input CCD8. 16-bit YCbCr mode, time multiplexed between CB0, inputs. 8-bit YCbCr mode, time multiplexed between CB0, upper 8-bit channel. This multiplexed between VPFE (CCDC) GPIO. This CCDC input supports several modes: YI7(CCD7)/ GP[43] I/O/Z DVDD33 16-bit mode, input CCD7. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB7, lower 8-bit channel. This multiplexed between VPFE (CCDC) GPIO. This CCDC input supports several modes: YI6(CCD6)/ GP[42] I/O/Z DVDD33 16-bit mode, input CCD6. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB6, lower 8-bit channel. This multiplexed between VPFE (CCDC) GPIO. This CCDC input supports several modes: YI5(CCD5)/ GP[41] I/O/Z DVDD33 16-bit mode, input CCD5. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB5, lower 8-bit channel.
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TMS320DM6437 Digital Media Processor
Table 2-19. VPFE Terminal Functions (continued)
SIGNAL NAME TYPE OTHER DESCRIPTION This multiplexed between VPFE(CCDC) GPIO. YI4(CCD4)/ GP[40] I/O/Z DVDD33 This CCDC input supports several modes: 16-bit mode, input CCD4. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB4, lower 8-bit channel. This multiplexed between VPFE (CCDC) GPIO. YI3(CCD3)/ GP[39] I/O/Z DVDD33 This CCDC input supports several modes: 16-bit mode, input CCD3. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB3, lower 8-bit channel. This multiplexed between VPFE (CCDC) GPIO. YI2(CCD2)/ GP[38] I/O/Z DVDD33 This CCDC input supports several modes: 16-bit mode, input CCD2. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB2, lower 8-bit channel. This multiplexed between VPFE (CCDC) GPIO. YI1(CCD1)/ GP[37] I/O/Z DVDD33 This CCDC input supports several modes: 16-bit mode, input CCD1. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB1, lower 8-bit channel. This multiplexed between VPFE (CCDC) GPIO. YI0(CCD0)/ GP[36] I/O/Z DVDD3 This CCDC input supports several modes: 16-bit mode, input CCD0. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB0, lower 8-bit channel. This multiplexed between VPFE (CCDC), EMIFA, GPIO. VPFE mode, Controller write enable input C_WE. This multiplexed between VPFE (CCDC), EMIFA, GPIO. VPFE mode, CCDC field identification bidirectional signal C_FIELD.
C_WE/EM_R/W/ GP[35] C_FIELD/EM_A[21]/ GP[34]
I/O/Z I/O/Z
DVDD33 DVDD33
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-20. VPBE Terminal Functions
SIGNAL NAME TYPE OTHER VIDEO (VPBE) HSYNC/EM_CS5/ GP[33] VSYNC/EM_CS4/ GP[32] VCLK/GP[31] VPBECLK/GP[30] COUT0/EM_D[0]/ GP[14] COUT1/EM_D[1]/ GP[15] COUT2/EM_D[2]/ GP[16] COUT3/EM_D[3]/ GP[17] COUT4/EM_D[4]/ GP[18] COUT5/EM_D[5]/ GP[19] COUT6/EM_D[6]/ GP[20] COUT7/EM_D[7]/ GP[21] YOUT0/GP[22]/ (BOOTMODE0) YOUT1/GP[23]/ (BOOTMODE1) YOUT2/GP[24]/ (BOOTMODE2) YOUT3/GP[25]/ (BOOTMODE3) YOUT4/GP[26]/ (FASTBOOT) YOUT5/GP[27] YOUT6/ GP[28] YOUT7/ GP[29] LCD_OE/EM_CS3/ GP[13] G0/EM_CS2/ GP[12] B0/LCD_FIELD/ EM_A[3]/GP[11] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between VPBE (VENC) GPIO. VPBE mode, this VENC output YOUT7. This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, output enable LCD_OE (O/Z). This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, this RGB666/888 Green output data This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, this RGB666/888 Blue output data interlaced LCD_FIELD (I/O/Z). These pins multiplexed between VPBE (VENC) GPIO. After reset, these video encoder (VENC) outputs 6:0, YOUT[6:0]. proper DM6437 device operation, YOUT6 must pulled down external resistor. proper DM6437 device operation, YOUT5 must pulled external resistor. This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, this VPBE Horizontal Sync (I/O/Z). This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, this VPBE Vertical Sync (I/O/Z). This multiplexed between VPBE GPIO. VPBE mode, this VPBE Clock Output. This multiplexed between VPBE GPIO. VPBE mode, this VPBE Clock Input. This multiplexed between VPBE (VENC), EMIFA, GPIO. VPBE mode, this video encoder (VENC) output COUT0. This multiplexed between VPBE(VENC), EMIFA, GPIO. VPBE mode, this video encoder (VENC) output COUT1. This multiplexed between VPBE(VENC), EMIFA, GPIO. VPBE mode, this video encoder (VENC) output COUT2. This multiplexed between VPBE(VENC), EMIFA, GPIO. VPBE mode, this video encoder (VENC) output COUT3. This multiplexed between VPBE(VENC), EMIFA, GPIO. VPBE mode, this video encoder (VENC) output COUT4. This multiplexed between VPBE(VENC), EMIFA, GPIO. VPBE mode, this video encoder (VENC) output COUT5. This multiplexed between VPBE(VENC), EMIFA, GPIO. VPBE mode, this video encoder (VENC) output COUT6. This multiplexed between VPBE (VENC), EMIFA, GPIO. VPBE mode, this video encoder (VENC) output COUT7. DESCRIPTION
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
TMS320DM6437 Digital Media Processor
Table 2-20. VPBE Terminal Functions (continued)
SIGNAL NAME R0/EM_A[4]/ GP[10]/ (AEAW2/PLLMS2) G1/EM_A[1]/ (ALE)/GP[9]/ (AEAW1/PLLMS1) B1/EM_A[2]/ (CLE)/GP[8]/ (AEAW0/PLLMS0) R1/EM_A[0]/ GP[7]/(AEM2) R2/EM_BA[0]/ GP[6]/(AEM1) B2/EM_BA[1]/ GP[5]/(AEM0) TYPE OTHER DESCRIPTION
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33
This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, this RGB666/888 output data This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, this RGB666/888 Green output data This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, this RGB666/888 Blue output data This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, this RGB666/888 output data This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, this RGB666/888 output data This multiplexed between VPBE, EMIFA, GPIO. VPBE mode, this RGB666/888 Blue output data
I/O/Z
I/O/Z I/O/Z I/O/Z I/O/Z
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-21. [Part VPBE] Terminal Functions
SIGNAL NAME TYPE OTHER DAC[A:D] Reference voltage input (0.5 DAC_VREF
DESCRIPTION
Note: peripheral being used, proper device operation, this must tied directly VSS. Output
DAC_IOUT_A
Note: peripheral being used, proper device operation, this must left unconnected. Output
DAC_IOUT_B
Note: peripheral being used, proper device operation, this must left unconnected. Output
DAC_IOUT_C
Note: peripheral being used, proper device operation, this must left unconnected. Output
DAC_IOUT_D
Note: peripheral being used, proper device operation, this must left unconnected. Analog power
VDDA_1P8V
Note: peripheral being used, proper device operation, this must tied directly VSS. Analog ground
VSSA_1P8V
Note: peripheral being used, proper device operation, this must tied directly VSS. 1.20 Analog core supply voltage (-7/-6/-5/-4/-L/-Q6/-Q5/-Q4 devices)
VDDA_1P1V
1.05 Analog core supply voltage (-7/-6/-5/-4/-L/-Q5 devices) Note: peripheral being used, proper device operation, this must tied directly VSS. Analog core ground
VSSA_1P1V
Note: peripheral being used, proper device operation, this must tied directly VSS. External resistor connection current bias configuration. This must connected resistor VSSA_1P8V.
DAC_RBIAS
Note: peripheral being used, proper device operation, this must tied directly VSS. Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table
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TMS320DM6437 Digital Media Processor
Table 2-22. Terminal Functions
SIGNAL NAME TYPE OTHER I/O/Z DVDD33 I2C, this clock. master mode, this output. slave mode, this input. When module used, proper device operation, this must pulled external resistor. I2C, this bi-directional data signal. When module used, proper device operation, this must pulled external resistor. DESCRIPTION
I/O/Z
DVDD33
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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TMS320DM6437 Digital Media Processor
SPRS345D NOVEMBER 2006 REVISED JUNE 2008 www.ti.com
Table 2-23. Multichannel Buffered Serial Port Multichannel Buffered Serial Port (McBSP0 McBSP1) Terminal Functions
SIGNAL NAME TYPE OTHER DESCRIPTION
Multichannel Buffered Serial Port (McBSP0) more details multiplexing, Section 3.7, Multiplexed Configurations. CLKS0/TOUT0L/ GP[97] ACLKR0/CLKX0/ GP[99] AHCLKR0/CLKR0/ GP[101] AXR0[2]/FSX0/ GP[103] AXR0[3]/FSR0/ GP[102] AXR0[1]/DX0/ GP[104] AFSR0/DR0/ GP[100] I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between McBSP0, Timer0, GPIO. McBSP0, McBSP0 external clock source (I). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 transmit clock CLKX0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 receive clock CLKR0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 transmit frame synchronization FSX0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 receive frame synchronization FSR0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 data transmi
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