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TMS320DM357 Digital Media System-on-Chip
Digital Media System-on-Chip (DMSoC)
High-Performance Digital Media 270-MHz ARM926EJ-SCore Fully Software-Compatible With ARM9ARM926EJ-S Core Support 32-Bit 16-Bit (Thumb® Mode) Instruction Sets ARM® Jazelle® Technology EmbeddedICE-RTLogic Real-Time Debug ARM9 Memory Architecture 16K-Byte Instruction Cache 8K-Byte Data Cache 16K-Byte 8K-Byte H.264/MPEG4/JPEG Coprocessor Fixed Function Coprocessor Supports: H.264 Codec VGA, MPEG4 Codec VGA, JPEG Codec Embedded Trace Buffer(ETB11TM) With Memory ARM9 Debug Endianness: Little Endian Video Processing Subsystem Front Provides: CMOS Imager Interface BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface Preview Engine Real-Time Image Processing Glueless Interface Common Video Decoders Histogram Module Auto-Exposure, Auto-White Balance Auto-Focus Module Resize Engine Resize Images From 1/4x Separate Horizontal/Vertical Control Back Provides: Hardware On-Screen Display (OSD) 54-MHz DACs Combination Composite NTSC/PAL Video Luma/Chroma Separate Video (S-video) Component (YPbPr RGB) Video (Progressive/Interlaced) Digital Output 8-/16-bit 24-Bit Video Windows External Memory Interfaces (EMIFs) 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O) Asynchronous 16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach Flash Memory Interfaces (8-/16-Bit-Wide Data) NAND (8-/16-Bit-Wide Data) Flash Card Interfaces Multimedia Card (MMC)/Secure Digital (SD) with Secure Data (SDIO) SmartMedia Enhanced Direct-Memory-Access (EDMA) Controller Independent Channels) 64-Bit General-Purpose Timers (Each Configurable 32-Bit Timers) 64-Bit Watch Timer Three UARTs (One with Flow Control) Serial Peripheral Interface (SPI) With Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Audio Serial Port (ASP) AC97 Audio Codec Interface Standard Voice Codec Interface (AIC12) 10/100 Mb/s Ethernet Media Access Controller (EMAC) IEEE 802.3 Compliant Media Independent Interface (MII) Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data USB2.0 Controller With Integrated High-Speed Three Pulse Width Modulator (PWM) Outputs On-Chip Bootloader (RBL) Boot From NAND Flash UART Comprehensive Power-Saving Modes Flexible Clock Generators
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PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2008, Texas Instruments Incorporated
TMS320DM357 Digital Media System-on-Chip
SPRS553 NOVEMBER 2008 www.ti.com
IEEE-1149.1 (JTAG) BoundaryScan-Compatible General-Purpose (GPIO) Pins (Multiplexed With Other Device Functions) 361-Pin Pb-Free Package (ZWT Suffix), 0.8-mm Ball Pitch
0.09-µm/6-Level Metal Process (CMOS) 3.3-V 1.8-V I/O, 1.2-V Core Applications: Digital Media Networked Media Encode/Decode Video Imaging
Description
TMS320DM357 (also referenced DM357) leverages TI's DaVincitechnology meet networked media encode decode application processing needs next-generation embedded devices. DM357 enables OEMs ODMs quickly bring market devices featuring robust operating systems support, rich user interfaces, high processing performance, long battery life through maximum flexibility fully integrated mixed processor solution. ARM926EJ-S 32-bit RISC processor core that performs 32-bit 16-bit instructions processes 32-bit, 16-bit, 8-bit data. core uses pipelining that parts processor memory system operate continuously. core incorporates: coprocessor (CP15) protection module Data program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction 8K-byte data caches. Both four-way associative with virtual index virtual (VIVT). DM357 performance enhanced H.264/MPEG4/JPEG coprocessor (HMJCP). HMJCP performs computational operations required image processing; JPEG compression MPEG4 video imaging standard. H.264/MPEG4/JPEG coprocessor supports MPEG4 Simple Profile (SP) VGA, encode/decode resolutions JPEG encode/decode. peripheral includes: configurable video ports (one input port output port); 10/100 Mb/s Ethernet (EMAC) with Management Data Input/Output (MDIO) module; inter-integrated circuit (I2C) interface; audio serial port (ASP); 64-bit general-purpose timers each configurable independent 32-bit timers; 64-bit watchdog timer; 71-pins general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; UARTs with hardware handshaking support UART; pulse width modulator (PWM) peripherals; external memory interfaces: asynchronous external memory interface (EMIFA) slower memories/peripherals, higher speed synchronous memory interface DDR2. DM357 device includes Video Processing Subsystem (VPSS) with configurable video/imaging peripherals: Video Processing Front-End (VPFE) input used video capture, Video Processing Back-End (VPBE) output displaying video images. Video Processing Front-End (VPFE) comprised Controller (CCDC), Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), Resizer. CCDC capable interfacing common video decoders, CMOS sensors, Charge Coupled Devices (CCDs). Previewer real-time image processing engine that takes imager data from CMOS sensor converts from Bayer Pattern YUV4:2:2. Histogram modules provide statistical information color data DM357. Resizer accepts image data separate horizontal vertical resizing from 1/4x increments 256/N, where between 1024.
Digital Media System-on-Chip (DMSoC)
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TMS320DM357 Digital Media System-on-Chip
Video Processing Back-End (VPBE) comprised On-Screen Display Engine (OSD) Video Encoder (VENC). engine capable handling separate video windows separate windows. Other configurations include video windows, window, attribute window allowing levels alpha blending. VENC provides three analog DACs that MHz, providing means composite NTSC/PAL video, S-Video, and/or Component video output. VENC also provides bits digital output interface RGB888 devices hi-speed triple DACs such THS8200. digital output capable 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal vertical syncs. Ethernet Media Access Controller (EMAC) provides efficient interface between DM357 network. DM357 EMAC support both 10Base-T 100Base-TX, Mbits/second (Mbps) Mbps either half- full-duplex mode, with hardware flow control quality service (QOS) support. Management Data Input/Output (MDIO) module continuously polls MDIO addresses order enumerate devices system. Once Ethernet candidate been selected ARM, MDIO module transparently monitors link state reading status register. Link change events stored MDIO module optionally interrupt ARM, allowing poll link status device without continuously performing costly MDIO accesses. HPI, I2C, SPI, USB2.0 ports allow DM357 easily control peripheral devices and/or communicate with host processors. DM357 also provides multimedia card support, MMC/SD, with SDIO support. rich peripheral provides ability control external peripheral devices communicate with external processors. details each peripherals, related sections later this document associated peripheral reference guides. DM357 complete development tools ARM926EJS. These include compilers Windowsdebugger interface visibility into source code execution.
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Digital Media System-on-Chip (DMSoC)
TMS320DM357 Digital Media System-on-Chip
SPRS553 NOVEMBER 2008 www.ti.com
Functional Block Diagram
Figure shows functional block diagram device.
BT.656, Y/C, (Bayer) JTAG Interface System Control Input Clock(s) PLLs/Clock Generator Power/Sleep Controller Multiplexing Subsystem ARM926EJ-S H.264 I-Cache D-Cache MPEG4 Resizer Controller Histogram/ Video Interface Preview On-Screen Video Display Encoder (VENC) (OSD) HMJCP Coprocessor Video Processing Subsystem (VPSS) Front Back BT.656, Y/C, NTSC/ PAL, S-Video, RGB, YPbPr
JPEG
Switched Central Resource (SCR)
Peripherals Serial Interfaces System
EDMA
Audio Serial Port
UART
GeneralPurpose Timer
Watchdog Timer
Connectivity EMAC With MDIO
Program/Data Storage DDR2 Ctlr (32b)
Async EMIF/ NAND/ SmartMedia
Figure 1-1. TMS320DM357 Functional Block Diagram
Digital Media System-on-Chip (DMSoC)
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Contents
Digital Media System-on-Chip (DMSoC)
Features Description Functional Block Diagram Device Characteristics Device Compatibility Subsystem HMJCP Coprocessor Memory Summary Assignments 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 Parameter Information Recommended Clock Control Signal Transition Behavior Power Supplies Reset External Clock Input From MXI/CLKIN Pin. Clock PLLs Interrupts General-Purpose Input/Output (GPIO). Enhanced Direct Memory Access (EDMA) Controller External Memory Interface (EMIF) MMC/SD/SDIO Video Processing Sub-System (VPSS) Overview Host-Port Interface (HPI). Universal Asynchronous Receiver/Transmitter (UART) Serial Peripheral Interface (SPI) Inter-Integrated Circuit (I2C) Audio Serial Port (ASP) Ethernet Media Access Controller (EMAC) Management Data Input/Output (MDIO) Timer Pulse Width Modulator (PWM). IEEE 1149.1 JTAG
Device Overview
Terminal Functions Device Support Device Configurations. System Module Registers Power Considerations Bootmode Configurations Reset Configurations After Reset System Interconnect System Interconnect Block Diagram Device Operating Conditions
Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) Recommended Operating Conditions Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Case Temperature (Unless Otherwise Noted)
Mechanical Packaging Orderable Information
Thermal Data 7.1.1 Packaging Information.
Peripheral Electrical Specifications.
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Contents
TMS320DM357 Digital Media System-on-Chip
SPRS553 NOVEMBER 2008 www.ti.com
Device Overview
Device Characteristics
Table provides overview TMS320DM357 SoC. table shows significant features device, including capacity on-chip RAM, peripherals, ARM9 operating frequency, package type with count, etc. Table 2-1. Characteristics Processor
HARDWARE FEATURES DDR2 Memory Controller Asynchronous EMIF (EMIFA) Flash Cards EDMA Timers UART Audio Serial Port [ASP] 10/100 Ethernet with Management Data Input/Output General-Purpose Input/Output Port Configurable Video Ports USB2.0 16KB I-cache D-cache 16KB 0x1B70 002F (Silicon Revision 2.1) 3.70 (Bypass), 361-Pin (ZWT) 0.09
DM357 DDR2 (32-bit width) Asynchronous (8/16-bit width) RAM, Flash (NOR, NAND) MMC/SD with secure data input/output (SDIO) SmartMedia/xD independent channels QDMA channels 64-Bit General Purpose (each configurable separate 32-bit timers) 64-Bit Watchdog (one with flow control) (supports slave devices) (Master/Slave) (16-bit multiplexed address/data) outputs Input (VPFE) Output (VPBE) HS/FS/LS Host HS/FS Device
Peripherals peripherals pins available same time (for more detail, Device Configurations section).
On-Chip Memory
Organization
JTAG BSDL_ID Frequency Cycle Time Voltage Options Package Process Technology Product Status
JTAGID Register (address location: 0x01C4 0028) Core CLKIN frequency multiplier reference) Product Preview (PP), Advance Information (AI), Production Data (PD)
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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Device Compatibility
ARM926EJ-S RISC compatible with other ARM9 CPUs from Holdings plc.
Subsystem
Subsystem designed give ARM926EJ-S (ARM9) master control device. general, responsible configuration control device; including Video Image Coprocessor (HMJCP), VPSS Subsystem, majority peripherals external memories. Subsystem includes following features: ARM926EJ-S RISC processor ARMv5TEJ (32/16-bit) instruction Little endian Co-Processor (CP15) 16KB Instruction cache Data cache Write Buffer 16KB Internal (32-bit wide access) Internal (ARM bootloader non-EMIFA boot options) Embedded Trace Module Embedded Trace Buffer (ETM/ETB) Interrupt controller Controller Power Sleep Controller (PSC) System Module
2.3.1
ARM926EJ-S RISC
Subsystem integrates ARM926EJ-S processor. ARM926EJ-S processor member ARM9 family general-purpose microprocessors. This processor targeted multi-tasking applications where full memory management, high performance, size, power important. ARM926EJ-S processor supports 32-bit THUMB instruction sets, enabling user trade between high performance high code density. Specifically, ARM926EJ-S processor supports ARMv5TEJ instruction set, which includes features efficient execution Java byte codes, providing Java performance similar Just Time (JIT) Java interpreter, without associated code overhead. ARM926EJ-S processor supports debug architecture includes logic assist both hardware software debug. ARM926EJ-S processor Harvard architecture provides complete high performance subsystem, including: ARM926EJ integer core CP15 system control coprocessor Memory Management Unit (MMU) Separate instruction data Caches Write buffer Separate instruction data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces Separate instruction data interfaces Embedded Trace Module Embedded Trace Buffer (ETM/ETB) more complete details ARM9, refer ARM926EJ-S Technical Reference Manual, available http://www.arm.com
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2.3.2
CP15
ARM926EJ-S system control coprocessor (CP15) used configure control instruction data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), other subsystem functions. CP15 registers programmed using instructions, when privileged mode such supervisor system mode.
2.3.3
ARM926EJ-S provides virtual memory features required operating systems such Linux®, Windows® Ultron®, ThreadX®, etc. single level page tables stored main memory used control address translation, permission checks memory region attributes both data instruction accesses. uses single unified Translation Lookaside Buffer (TLB) cache information held page tables. features are: Standard architecture mapping sizes, domains access protection scheme. Mapping sizes are: (sections) 64KB (large pages) (small pages) (tiny pages) Access permissions large pages small pages specified separately each quarter page (subpage permissions) Hardware page table walks Invalidate entire TLB, using CP15 register Invalidate entry, selected MVA, using CP15 register Lockdown entries, using CP15 register
2.3.4
Caches Write Buffer
size Instruction Cache 16KB, Data cache 8KB. Additionally, Caches have following features: Virtual index, virtual tag, addressed using Modified Virtual Address (MVA) Four-way associative, with cache line length eight words line (32-bytes line) with dirty bits Dcache Dcache supports write-through write-back copy back) cache operation, selected memory region using bits translation tables. Critical-word first cache refilling Cache lockdown registers enable control over which cache ways used allocation line fill, providing mechanism both lockdown, controlling cache corruption Dcache stores Physical Address TAG) corresponding each Dcache entry during cache line write-backs, addition Virtual Address stored RAM. This means that involved Dcache write-back operations, removing possibility misses related write-back address. Cache maintenance operations provide efficient invalidation entire Dcache Icache, regions Dcache Icache, regions virtual memory. write buffer used writes noncachable bufferable region, write-through region write misses write-back region. separate buffer incorporated Dcache holding write-back cache line evictions cleaning dirty cache lines. main write buffer 16-word data buffer four-address buffer. Dcache write-back eight data word entries single address entry.
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2.3.5
Tightly Coupled Memory (TCM)
internal provided storing real-time performance-critical code/data Interrupt Vector table. internal enables non-EMIFA boot options, such NAND UART. memories interfaced ARM926EJ-S tightly coupled memory interface that provides separate instruction data connections. Since does allow instructions D-TCM data I-TCM bus, arbiter included that both data instructions stored internal RAM/ROM. arbiter also allows accesses RAM/ROM from extra-ARM sources (e.g., EDMA other masters). ARM926EJ-S built-in support direct accesses internal memory from non-ARM master. Because time-critical nature link internal memory, accesses from non-ARM devices treated transfers. Instruction Data accesses differentiated accessing different memory regions, with instruction region from 0x0000 through 0x7FFF data from 0x8000 through 0xFFFF. instruction region 0x0000 data region 0x8000 same physical 16KB RAM. Placing instruction region 0x0000 necessary allow Interrupt Vector table placed 0x0000, required architecture. internal 16-KB split into physical banks each, which allows simultaneous instruction data accesses accomplished code data separate banks.
2.3.6
Advanced High-Performance (AHB)
Subsystem uses port ARM926EJ-S connect Config external memories. Arbiters employed arbitrate access separate D-AHB I-AHB Config external memories bus.
2.3.7
Embedded Trace Macrocell (ETM) Embedded Trace Buffer (ETB)
support real-time trace, ARM926EJ-S processor provides interface enable connection Embedded Trace Macrocell (ETM). ARM926ES-J Subsystem DM357 also includes Embedded Trace Buffer (ETB). Econsists parts: Trace Port provides real-time trace capability ARM9. Triggering facilities provide trigger resources, which include address data comparators, counter, sequencers. DM357 trace port pinned instead only connected Embedded Trace Buffer. buffer memory. enabled debug tools required read/interpret captured trace data.
2.3.8
Memory Mapping
memory shown Section 2.5, Memory Summary this document. access memories shown following sections.
2.3.8.1 Internal Memories access following internal memories: 16KB Internal interface, logically separated into pages allow simultaneous access given cycle there separate accesses code (I-TCM bus) data (D-TCM) different memory regions. Internal
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2.3.8.2 External Memories access following external memories: DDR2 Synchronous DRAM Asynchronous EMIF Flash NAND Flash Flash card devices: MMC/SD with SDIO SmartMedia
2.3.9
Peripherals
ARM9 access peripherals DM357 device.
2.3.10 Controller (PLLC)
Subsystem includes Controller. Controller contains registers configuring DM357's internal PLLs (PLL1 PLL2). Controller provides following configuration control: Bypass Mode multiplier parameters divider parameters power down Oscillator power down PLLs briefly described this document Clocking section. more detailed information PLLs Controller register descriptions, Section 2.8.3, Documentation Support, this document TMS320DM357 Subsystem Reference Guide (literature number SPRUG25).
2.3.11 Power Sleep Controller (PSC)
Subsystem includes Power Sleep Controller (PSC). Through register settings accessible ARM9, provides levels power savings: peripheral/module clock gating power domain shut-off. Brief details given Section 6.3, Power Supplies. more detailed information complete register descriptions PSC, Section 2.8.3, Documentation Support, TMS320DM357 Subsystem Reference Guide (literature number SPRUG25).
2.3.12 Interrupt Controller (AINTC)
Interrupt Controller (AINTC) accepts device interrupts maps them either ARM's (interrupt request) (fast interrupt request). Interrupt Controller briefly described this document Interrupts section. detailed information Interrupt Controller, Section 2.8.3, Documentation Support TMS320DM357 Subsystem Guide.
2.3.13 System Module
Subsystem includes System module. System module consists registers configuring controlling variety system functions. details register descriptions System module, Section Device Configurations Section 2.8.3, Documentation Support, TMS320DM357 Subsystem Reference Guide (literature number SPRUG25).
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2.3.14 Power Management
DM357 several means managing power consumption. There extensive clock gating, which reduces power used global device clocks individual peripheral clocks. Clock management utilized reduce clock frequencies order reduce switching power. more details power management techniques, Section Device Configurations, Section Peripheral Electrical Specifications, Section 2.8.3, Documentation Support, TMS320DM357 Subsystem Reference Guide (literature number SPRUG25). DM357 gives programmer full flexibility previously mentioned capabilities customize optimal power management strategy. Several typical power management scenarios described following sections.
HMJCP Coprocessor
DM357 performance enhanced H.264/MPEG4/JPEG coprocessor (HMJCP). HMJCP performs computational operations required image processing; JPEG compression MPEG4 video imaging standard. HMJCP includes following features: H.264 MPEG4 JPEG
Memory Summary
Table shows memory address ranges device. Table depicts expanded Configuration Space (0x0180 0000 through 0x0FFF FFFF). device multiple on-chip memories associated with processors various subsystems. help simplify software development unified memory used where possible maintain consistent view device resources across masters.
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SPRS553 NOVEMBER 2008 www.ti.com
Table 2-2. Memory Summary
START ADDRESS 0x0000 0000 0x0000 2000 0x0000 4000 0x0000 6000 0x0000 8000 0x0000 A000 0x0000 C000 0x0000 E000 0x0001 0000 0x0010 0000 0x0020 0000 0x0080 0000 0x0081 0000 0x00E0 8000 0x00E1 0000 0x00F0 4000 0x00F1 0000 0x00F1 8000 0x0180 0000 0x01BC 0000 0x01BC 1000 0x01BC 1800 0x01BC 1900 0x01C0 0000 0x0200 0000 0x0A00 0000 0x0C00 0000 0x1000 0000 0x1000 8000 0x1000 A000 0x1000 C000 0x1000 E000 0x1001 0000 0x1110 0000 0x1120 0000 0x1180 0000 0x1181 0000 0x11E0 8000 0x11E1 0000 0x11F0 4000 0x11F1 0000 0x11F1 8000 0x2000 0000 0x2000 8000 0x4200 0000 0x5000 0000 0x8000 0000 0x9000 0000 ADDRESS 0x0000 1FFF 0x0000 3FFF 0x0000 5FFF 0x0000 7FFF 0x0000 9FFF 0x0000 BFFF 0x0000 DFFF 0x0000 FFFF 0x000F FFFF 0x001F FFFF 0x007F FFFF 0x0080 FFFF 0x00E0 7FFF 0x00E0 FFFF 0x00F0 3FFF 0x00F0 FFFF 0x00F1 7FFF 0x017F FFFF 0x01BB FFFF 0x01BC 0FFF 0x01BC 17FF 0x01BC 18FF 0x01BF FFFF 0x01FF FFFF 0x09FF FFFF 0x0BFF FFFF 0x0FFF FFFF 0x1000 7FFF 0x1000 9FFF 0x1000 BFFF 0x1000 DFFF 0x1000 FFFF 0x110F FFFF 0x111F FFFF 0x117F FFFF 0x1180 FFFF 0x11E0 7FFF 0x11E0 FFFF 0x11F0 3FFF 0x11F0 FFFF 0x11F1 7FFF 0x1FFF FFFF 0x2000 7FFF 0x41FF FFFF 0x4FFF FFFF 0x7FFF FFFF 0x8FFF FFFF 0xFFFF FFFF SIZE (Bytes) 960K 6112K Reserved 976K Reserved 9120K 3840K 255744 128M Reserved 17344K Reserved 6112K 976K Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DDR2 Control Registers Reserved Reserved Reserved DDR2 Reserved DDR2 Reserved DDR2 Reserved Reserved DDR2 Control Registers Reserved Memory Registers IceCrusher Reserved Peripherals EMIFA (Code Data) Reserved Reserved Peripherals EMIFA (Data) Reserved Reserved Reserved RAM0 RAM1 Peripherals Reserved Reserved RAM0 (Instruction) RAM1 (Instruction) Reserved (Instruction) Reserved RAM0 (Data) RAM1 (Data) (Data) RAM0 RAM1 RAM0 RAM1 Reserved EDMA/ PERIPHERAL VPSS
241M-32K Reserved DDR2 Control Registers
544M-32k Reserved 224M 768M 256M 1792M Reserved Reserved DDR2 Reserved
HPI's access configuration peripherals limited power sleep controller registers, PLL1 PLL2 registers, configuration registers.
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Table 2-3. Configuration Memory Summary
START ADDRESS 0x0180 0000 0x0181 0000 0x0181 1000 0x0181 2000 0x0182 0000 0x0183 0000 0x0184 0000 0x0185 0000 0x0188 0000 0x01BC 0000 0x01BC 0100 0x01BC 0200 0x01BC 1000 0x01BC 1800 0x01BC 1900 0x01C0 0000 0x01C1 0000 0x01C1 0400 0x01C1 8800 0x01C1 A000 0x01C2 0000 0x01C2 0400 0x01C2 0800 0x01C2 0C00 0x01C2 1000 0x01C2 1400 0x01C2 1800 0x01C2 1C00 0x01C2 2000 0x01C2 2400 0x01C2 2800 0x01C2 2C00 0x01C4 0000 0x01C4 0800 0x01C4 0C00 0x01C4 1000 0x01C4 2000 0x01C4 2030 0x01C4 2034 0x01C4 2400 0x01C4 8000 0x01C4 8400 0x01C6 0000 0x01C6 4000 0x01C6 6000 0x01C6 6800 ADDRESS 0x0180 FFFF 0x0181 0FFF 0x0181 1FFF 0x0181 2FFF 0x0182 FFFF 0x0183 FFFF 0x0184 FFFF 0x0187 FFFF 0x01BB FFFF 0x01BC 00FF 0x01BC 01FF 0x01BC 0FFF 0x01BC 17FF 0x01BC 18FF 0x01BF FFFF 0x01C0 FFFF 0x01C1 03FF 0x01C1 07FF 0x01C1 9FFF 0x01C1 FFFF 0x01C2 03FF 0x01C2 07FF 0x01C2 0BFF 0x01C2 0FFF 0x01C2 13FF 0x01C2 17FF 0x01C2 1BFF 0x01C2 1FFF 0x01C2 23FF 0x01C2 27FF 0x01C2 2BFF 0x01C3 FFFF 0x01C4 07FF 0x01C4 0BFF 0x01C4 0FFF 0x01C4 1FFF 0x01C4 202F 0x01C4 2033 0x01C4 23FF 0x01C4 7FFF 0x01C4 83FF 0x01C5 FFFF 0x01C6 3FFF 0x01C6 5FFF 0x01C6 67FF 0x01C6 6FFF SIZE (Bytes) 192K 3328K 3.5K 255744 117K Registers Crusher Reserved EDMA EDMA EDMA Reserved UART0 UART1 UART2 Reserved Timer0 Timer1 Timer2 (Watchdog) PWM0 PWM1 PWM2 Reserved System Module Controller Controller Power Sleep Controller Reserved DDR2 Reserved Interrupt Controller Reserved USB2.0 Registers Reserved Memory Reserved ARM/EDMA
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0x01C6 7000 0x01C6 7800 0x01C6 8000 0x01C7 0000 0x01C7 4000 0x01C8 0000 0x01C8 1000 0x01C8 2000 0x01C8 4000 0x01C8 4800 0x01C8 5000 0x01CC 0000 0x01CE 0000 0x01D0 0000 0x01E0 0000 0x01E0 1000 0x01E0 2000 0x01E0 4000 0x01E1 0000 0x01E2 0000 0x01E4 0000 0x0200 0000 0x0400 0000 0x0600 0000 0x0800 0000 0x0A00 0000 0x0C00 0000
0x01C6 77FF 0x01C6 7FFF 0x01C6 FFFF 0x01C7 3FFF 0x01C7 FFFF 0x01C8 0FFF 0x01C8 1FFF 0x01C8 3FFF 0x01C8 47FF 0x01C8 4FFF 0x01CB FFFF 0x01CD FFFF 0x01CF FFFF 0x01DF FFFF 0x01E0 0FFF 0x01E0 1FFF 0x01E0 3FFF 0x01E0 FFFF 0x01E1 FFFF 0x01E3 FFFF 0x01FF FFFF 0x03FF FFFF 0x05FF FFFF 0x07FF FFFF 0x09FF FFFF 0x0BFF FFFF 0x0FFF FFFF
236K 128K 128K 128K 1792K
GPIO Reserved VPSS Registers Reserved EMAC Control Registers EMAC Control Module Registers EMAC Control Module MDIO Control Registers Reserved HMJCP Reserved EMIFA Control Reserved Reserved MMC/SD/SDIO Reserved EMIFA Data/Code (CS2) EMIFA Data/Code (CS3) EMIFA Data/Code (CS4) EMIFA Data/Code (CS5) Reserved Reserved
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Assignments
Extensive multiplexing used accommodate largest number peripheral functions smallest possible package. multiplexing controlled using combination hardware configuration device reset software programmable register settings. more information muxing, Section 3.5.2, Multiplexed Configurations, this document.
2.6.1
(Bottom View)
Figure through Figure show bottom view package assignments four quadrants
RSV3
DDR_D[4]
DDR_D[7]
DDR_D[9]
DDR_D[12]
DDR_D[14]
DDR_CLK0
DDR_CLK0
DDR_A[12]
DDR_A[11]
DDR_D[2]
DDR_D[3]
DDR_D[6]
DDR_D[8]
DDR_D[11]
DDR_D[13]
DDR_D[15]
DDR_CKE
DDR_BS[1]
DDR_A[8]
DDR_D[0]
DDR_D[1]
DDR_D[5]
DDR_DQS[0]
DDR_D[10]
DDR_DQS[1]
DDR_RAS
DDR_BS[0]
DDR_BS[2]
DDR_A[10]
EM_CS5/ GPIO8
EM_CS4/ GPIO9
EM_A[21]/ GPIO10
DDR_ DQM[0]
DVDDR2
DDR_ DQM[1]
DDR_CAS
DDR_WE
DDR_CS
DDR_VDDDLL
EM_A[12]/ GPIO19
EM_A[17]/ GPIO14
EM_A[20]/ GPIO11
EM_A[19]/ GPIO12
EM_A[16]/ GPIO15
RSV7
DVDDR2
EM_A[10]/ GPIO21
EM_A[11]/ GPIO20
EM_A[15]/ GPIO16
EM_A[14]/ GPIO17
EM_A[18]/ GPIO13
DVDDR2
DVDDR2
DVDDR2
EM_A[6]/ GPIO25
EM_A[7]/ GPIO24
EM_A[8]/ GPIO23
EM_A[13]/ GPIO18
DVDD18
DVDDR2
DVDDR2
PLLVDD18
RSV24
EM_A[9]/ GPIO22
DVDD18
CVDD
CVDD
MXI/CLKIN
MXVSS
RSV6
RESET
MXVDD
DVDD18
CVDD
CVDD
CVDD
CLK_OUT0/ GPIO48
EM_A[3]/ GPIO28
EM_A[5]/ GPIO26
EM_A[4]/ GPIO27
DVDD18
CVDD
CVDD
CVDD
Figure 2-1. [Quadrant
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DDR_A[6]
DDR_A[5]
DDR_A[0]
DDR_D[16]
DDR_D[18]
DDR_D[21]
DDR_D[27]
DDR_D[29]
RSV4
DDR_A[7]
DDR_A[4]
DDR_A[2]
DDR_D[17]
DDR_D[19]
DDR_D[22]
DDR_D[24]
DDR_D[28]
DDR_D[30]
DDR_A[9]
DDR_A[3]
DDR_A[1]
DDR_DQS[2]
DDR_D[20]
DDR_DQS[3]
DDR_D[25]
DDR_D[26]
DDR_D[31]
DDR_ VSSDLL
DDR_ZN
DDR_ZP
DDR_DQM[2]
DDR_VREF
DDR_DQM[3]
DDR_D[23]
VSSA_1P1V
RSV45
DVDDR2
DVDDR2
DVDDR2
DAC_RBIAS
DAC_VREF
VDDA_1P8V
DAC_IOUT_C
DVDDR2
DVDDR2
VDDA_1P1V
VSSA_1P8V
DAC_IOUT_B
DAC_IOUT_A
DVDDR2
DVDDR2
CI3/CCD11
CI4/CCD12/ UART_RTS2
CI5/CCD13/ UART_CTS2
CI6/CCD14/ UART_TXD2
CI7/CCD15/ UART_RXD2
CVDD
DVDD18
CI0/CCD8
CI1/CCD9
CI2/CCD10
PCLK
CVDD
DVDD18
YI4/CCD4
YI5/CCD5
YI6/CCD6
YI7/CCD7
CVDD
CVDD
DVDD18
YI0/CCD0
YI1/CCD1
YI2/CCD2
YI3/CCD3
Figure 2-2. [Quadrant
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CVDD
CVDD
DVDD18
USB_ID
USB_VBUS
USB_ VSSA3P3
USB_ VDDA3P3
CVDD
CVDD
DVDD18
USB_VSS1P8
USB_VDD1P8
USB_R1
USB_DM
DVDD18
USB_ VSSREF
USB_ VSSA1P2LD0
USB_ VDDA1P2LD0
USB_DP
DVDD33
DVDD33
DVDD33
DVDD18
CVDD
M24VDD
M24VSS
M24XI
M24XO
GPIOV33_10/ RXD3
GPIOV33_7/ RXD0
GPIO1/ C_WE
GPIO5/G1
YOUT4/R4/ AEAW4
YOUT5/R5
YOUT6/R6
YOUT7/R7
CLK_OUT1/ TIM_IN/ GPIO49
GPIOV33_12/ RXDV
GPIOV33_4/ TXD1
GPIO2/G0
GPIO38/R1
YOUT0/G5/ AEAW0
YOUT1/G6/ AEAW1
YOUT2/G7/ AEAW2
YOUT3/R3/ AEAW3
VCLK
GPIOV33_8/ RXD1
GPIOV33_6/ TXD3
GPIO0/ LCD_OE
GPIO3/B0/ LCD_FIELD
PWM0/ GPIO45
COUT7/G4
HSYNC
VSYNC
VPBECLK
GPIOV33_9/ RXD2
GPIOV33_3/ TXD0
GPIOV33_0/ TXEN
GPIO4/R0/ C_FIELD
PWM1/R2/ GPIO46
COUT1/B4/ BTSEL1
COUT3/B6
COUT5/G2
COUT6/G3
GPIOV33_5/ TXD2
GPIOV33_2/
GPIOV33_1/ TXCLK
GPIO6/B1
PWM2/ B2/GPIO47
COUT0/B3/ BTSEL0
COUT2/B5/ EM_WIDTH
COUT4/B7
RSV2
Figure 2-3. [Quadrant
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TMS320DM357 Digital Media System-on-Chip
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EM_A[2]/ (CLE)/ HCNTL0
EM_A[1]/ (ALE)/ HHWIL
EM_BA[0]/ HINT
EM_A[0]/ HCNTL1/ GPIO53
GPIO50
DVDD18
CVDD
CVDD
GPIO51
EM_BA[1]/ GPIO52
UART_TXD1
EM_OE/(RE)/ HDS1
EM_D14/ HD14
DVDD18
CVDD
CVDD
UART_RXD1
EM_WE/(WE)/ HDS2
EM_R/W/ HR/W
EM_D11/ HD11
EM_D10/ HD10
DVDD18
DVDD18
EM_WAIT/ (RDY/BSY)/ HRDY
EM_D13/ HD13
EM_D8/
EM_D6/
EM_D2/
DVDD18
DVDD18
DVDD33
EM_D15/ HD15
EM_D9/
EM_D3/
EM_D4/
EM_D0/
DVDD18
SD_DATA1
GPIOV33_15/ MDIO
EM_D12/ HD12
EM_D5/
EM_D1/
RSV5
UART_RXD0/ GPIO35
EMU0
TRST
SD_DATA0
SD_DATA2
GPIOV33_13/ RXER
EM_D7/
EM_CS2/
GPIO7
SCL/ GPIO43
UART_TXD0/ GPIO36
EMU1
FSR/ GPIO32
FSX/ GPIO31
SD_DATA3
GPIOV33_14/
EM_CS3
SPI_EN1/ GPIO42
SPI_DI/ GPIO40
SDA/GPIO44
RTCK
GPIO33
CLKX/ GPIO29
SD_CMD
GPIOV33_16/ MDCLK
RSV1
SPI_DO/ GPIO41
SPI_CLK/ GPIO39
SPI_EN0/ GPIO37
GPIO34
CLKR/ GPIO30
SD_CLK
GPIOV33_11/ RXCLK
Figure 2-4. [Quadrant
Device Overview
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Terminal Functions
terminal functions tables (Table through Table 2-27) identify external signal names, associated (ball) numbers along with mechanical package designator, type, whether internal pullup pulldown resistors, functional description. more detailed information device configuration, peripheral selection, multiplexed/shared pin, Device Configurations section this data manual. Table 2-4. BOOT Terminal Functions
SIGNAL NAME TYPE OTHER BOOT These pins multiplexed between boot mode VPBE. reset, boot mode inputs BTSEL0 BTSEL1 sampled determine boot configuration. below boot modes these inputs. Bootmode section more details. After reset, these video encoder outputs COUT0 COUT1, RGB666/888 Blue output data bits B3/B4. BTSEL1 COUT1/ BTSEL1 I/O/Z DVDD18 BTSEL0 Boot Mode Boot (NAND) [default] EMIFA Boot (NOR) Boot (HPI) Boot (UART0) DESCRIPTION
COUT0/ BTSEL0
I/O/Z
DVDD18
COUT2/ EM_WIDTH
I/O/Z
DVDD18
This multiplexed between EMIFA VPBE. reset, input state sampled EMIFA data width (EM_WIDTH). 8-bit wide EMIFA data bus, EM_WIDTH 16-bit wide EMIFA data bus, EM_WIDTH After reset, video encoder output COUT2 RGB666/888 Blue output data proper device operation, reset this must externally pulled down 10-k resistor. After reset, video encoder output COUT3 RGB666/888 Blue data output
COUT3/ YOUT0/ AEAW0 YOUT1/ AEAW1 YOUT2/ AEAW2 YOUT3/ AEAW3 YOUT4/ AEAW4
I/O/Z
DVDD18
I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 These pins multiplexed between EMIFA VPBE. reset, input states AEAW[4:0] sampled EMIFA address width. Peripheral Selection Device Reset section details. After reset, these video encoder outputs YOUT[0:4] RGB666/888 Green data outputs
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
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Table 2-5. Oscillator/PLL Terminal Functions
SIGNAL NAME TYPE OTHER OSCILLATOR, MXI/CLKIN MXVDD MXVSS M24XI DVDD18 DVDD18
DESCRIPTION
Crystal input oscillator (system oscillator, typically MHz). crystal input used, instead physical clock-in source supplied, this external oscillator clock input. Crystal output oscillator. crystal input used, instead physical clock-in source supplied, should left Connect. 1.8-V power supply oscillator. crystal input used, instead physical clock-in source supplied, MXVDD should still connected 1.8-V power supply. Ground oscillator. crystal input used, instead physical clock-in source supplied, MXVSS should still connected ground. Crystal input oscillator USB). crystal input used, instead physical clock-in source supplied, this external oscillator clock input. When peripheral used, M24XI should left Connect. Crystal output oscillator. crystal input used, instead physical clock-in source supplied, M24XO should left Connect. When peripheral used, M24XO should left Connect. 1.8-V power supply oscillator. crystal input used, instead physical clock-in source supplied, M24VDD should still connected 1.8-V power supply. When peripheral used, M24VDD should connected 1.8-V power supply. Ground oscillator. crystal input used, instead physical clock-in source supplied, M24VSS should still connected ground. When peripheral used, M24VSS should connected ground. 1.8-V power supply PLLs (system).
DVDD18
M24XO
DVDD18
M24VDD
M24VSS PLLVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table
Table 2-6. Clock Generator Terminal Functions
SIGNAL NAME TYPE OTHER CLOCK GENERATOR CLK_OUT0/ GPIO48 CLK_OUT1/ TIM_IN/ GPIO49 I/O/Z DVDD18 This multiplexed between PLL1 clock generator GPIO. PLL1 clock generator, clock output CLK_OUT0. This configurable 13.5 clock outputs. This multiplexed between clock generator, timer, GPIO. clock generator, clock output CLK_OUT1. This configurable clock outputs. DESCRIPTION
I/O/Z
DVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
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Table 2-7. RESET JTAG Terminal Functions
SIGNAL NAME TYPE OTHER RESET RESET DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 This active global reset input. JTAG RTCK TRST EMU1 EMU0 I/O/Z I/O/Z JTAG test-port mode select input JTAG test-port data output JTAG test-port data input JTAG test-port clock input JTAG test-port return clock output JTAG test-port reset. IEEE 1149.1 JTAG compatibility, IEEE 1149.1 JTAG compatibility statement portion this data manual Emulation Emulation DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
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Table 2-8. EMIFA Terminal Functions
SIGNAL NAME TYPE OTHER EMIFA BOOT CONFIGURATION COUT2/ EM_WIDTH YOUT0/ AEAW0 YOUT1/ AEAW1 YOUT2/ AEAW2 YOUT3/ AEAW3 YOUT4/ AEAW4 DVDD18 This multiplexed between EMIFA VPBE. reset, input state sampled EMIFA data width (EM_WIDTH). 8-bit wide EMIFA data bus, EM_WIDTH 16-bit wide EMIFA data bus, EM_WIDTH After reset, video encoder output COUT2 RGB666/888 Blue output data DESCRIPTION
I/O/Z
I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 EMIFA FUNCTIONAL PINS: ASYNC These pins multiplexed between EMIFA VPBE. reset, input states AEAW[4:0] sampled EMIFA address width. Peripheral Selection Device Reset section details. After reset, these video encoder outputs YOUT[0:4] RGB666/888 Green data outputs
I/O/Z
I/O/Z
I/O/Z
I/O/Z
EM_CS2/ EM_CS3 EM_CS4/ GPIO9 EM_CS5/ GPIO8 EM_R/W/ HR/W EM_WAIT/ (RDY/BSY) HRDY EM_OE/ (RE) HDS1 EM_WE (WE)/ HDS2
I/O/Z
DVDD18
This multiplexed between EMIFA HPI. EMIFA, this Chip Select output EM_CS2 with asynchronous memories (i.e., flash) NAND flash. This chip select default boot boot modes. EMIFA, this Chip Select output EM_CS3 with asynchronous memories (i.e., flash) NAND flash. This multiplexed between EMIFA GPIO. EMIFA, Chip Select output EM_CS4 with asynchronous memories (i.e., flash) NAND flash. This multiplexed between EMIFA GPIO. EMIFA, Chip Select output EM_CS5 with asynchronous memories (i.e., flash) NAND flash. This multiplexed between EMIFA HPI. EMIFA, read/write output EM_R/W. This multiplexed between EMIFA (NAND/SmartMedia/xD) HPI. EMIFA, wait state extension input EM_WAIT. This multiplexed between EMIFA (NAND/SmartMedia/xD) HPI. EMIFA, output enable output EM_OE. This multiplexed between EMIFA (NAND/SmartMedia/xD) HPI. NAND/SmartMedia/xD EMIFA, write enable output EM_WE. This multiplexed between EMIFA HPI. EMIFA, this Bank Address output (EM_BA[0]). When connected 8-bit asynchronous memory, this lowest order byte address. When connected 16-bit asynchronous memory, this same function EMIF address (EM_A[22]).
I/O/Z I/O/Z
DVDD18 DVDD18
I/O/Z I/O/Z I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18
I/O/Z
I/O/Z
DVDD18
EM_BA[0]/ HINT
I/O/Z
DVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
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Table 2-8. EMIFA Terminal Functions (continued)
SIGNAL NAME TYPE OTHER DESCRIPTION This multiplexed between EMIFA GPIO. EMIFA, this Bank Address output EM_BA[1]. When connected asynchronous memory this lowest order 16-bit word address. When connected 8-bit asynchronous memory, this address. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[21]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[20]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[19]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[18]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[17]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[16]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[15]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[14]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[13]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[12]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[11]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[10]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[9]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[8]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[7]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[6]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[5]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[4]. This multiplexed between EMIFA GPIO. EMIFA, address output EM_A[3]. This multiplexed between EMIFA HPI. EMIFA, this EM_A[2] address line. This multiplexed between EMIFA (NAND/SmartMedia.xD) HPI. This multiplexed between EMIFA, HPI, GPIO. EMIFA, this Address output EM_A[0], which least significant 32-bit word address. When connected 16-bit asynchronous memory, this address. 8-bit asynchronous memory, this address.
EM_BA[1]/ GPIO52
I/O/Z
DVDD18
EM_A[21]/ GPIO10 EM_A[20]/ GPIO11 EM_A[19]/ GPIO12 EM_A[18]/ GPIO13 EM_A[17]/ GPIO14 EM_A[16]/ GPIO15 EM_A[15]/ GPIO16 EM_A[14]/ GPIO17 EM_A[13]/ GPIO18 EM_A[12]/ GPIO19 EM_A[11]/ GPIO20 EM_A[10]/ GPIO21 EM_A[9]/ GPIO22 EM_A[8]/ GPIO23 EM_A[7]/ GPIO24 EM_A[6]/ GPIO25 EM_A[5]/ GPIO26 EM_A[4]/ GPIO27 EM_A[3]/ GPIO28 EM_A[2]/ (CLE)/ HCNTL0 EM_A[1]/ (ALE)/ HHWIL EM_A[0]/ HCNTL1/ GPIO53
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
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Table 2-8. EMIFA Terminal Functions (continued)
SIGNAL NAME EM_D0/ EM_D1/ EM_D2/ EM_D3/ EM_D4/ EM_D5/ EM_D6/ EM_D7/ EM_D8/ EM_D9/ EM_D10/ HD10 EM_D11/ HD11 EM_D12/ HD12 EM_D13/ HD13 EM_D14/ HD14 EM_D15/ HD15 TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z OTHER DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 These pins multiplexed between EMIFA (NAND) HPI. cases they used bi-directional data bus. EMIFA (NAND), these EM_D[15:0]. DESCRIPTION
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Table 2-8. EMIFA Terminal Functions (continued)
SIGNAL NAME EM_A[1]/ (ALE)/ HHWIL EM_A[2]/ (CLE)/ HCNTL0 EM_WAIT/ (RDY/BSY)/ HRDY EM_OE/ (RE)/ HDS1 EM_WE (WE)/ HDS2 EM_CS2/ EM_CS3 EM_CS4/ GPIO9 EM_CS5/ GPIO8 TYPE OTHER DESCRIPTION
EMIFA FUNCTIONAL PINS: NAND SMARTMEDIA I/O/Z DVDD18 This multiplexed between EMIFA HPI. NAND/SmartMedia/xD, Address Latch Enable output (ALE). This multiplexed between EMIFA HPI. NAND/SmartMedia/xD, this Command Latch Enable output (CLE). This multiplexed between EMIFA (NAND/SmartMedia/xD) HPI. NAND/SmartMedia/xD, ready/busy input (RDY/BSY). This multiplexed between EMIFA (NAND/SmartMedia/xD) HPI. NAND/SmartMedia/xD, read enable output (RE). This multiplexed between EMIFA (NAND/SmartMedia/xD) HPI. NAND/SmartMedia/xD, write enable output (WE). This multiplexed between EMIFA HPI. EMIFA, this Chip Select output EM_CS2 with asynchronous memories (i.e. flash) NAND flash. This chip select default boot boot modes. EMIFA, this Chip Select output EM_CS3 with asynchronous memories (i.e. flash) NAND flash. This multiplexed between EMIFA GPIO. EMIFA, Chip Select output EM_CS4 with asynchronous memories (i.e., flash) NAND flash. This multiplexed between EMIFA GPIO. EMIFA, Chip Select output EM_CS5 with asynchronous memories (i.e., flash) NAND flash.
I/O/Z
DVDD18 DVDD18 DVDD18
I/O/Z
I/O/Z
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z I/O/Z
DVDD18 DVDD18
I/O/Z
DVDD18
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Table 2-8. EMIFA Terminal Functions (continued)
SIGNAL NAME EM_D0/ EM_D1/ EM_D2/ EM_D3/ EM_D4/ EM_D5/ EM_D6/ EM_D7/ EM_D8/ EM_D9/ EM_D10/ HD10 EM_D11/ HD11 EM_D12/ HD12 EM_D13/ HD13 EM_D14/ HD14 EM_D15/ HD15 TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z OTHER DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 These pins multiplexed between EMIFA (NAND) HPI. cases they used bi-directional data bus. EMIFA (NAND), these EM_D[15:0]. DESCRIPTION
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Table 2-9. DDR2 Memory Controller Terminal Functions
SIGNAL NAME DDR_CLK0 DDR_CLK0 DDR_CKE DDR_CS DDR_WE DDR_DQM[3] DDR_DQM[2] DDR_DQM[1] DDR_DQM[0] DDR_RAS DDR_CAS DDR_DQS[0] DDR_DQS[1] DDR_DQS[2] DDR_DQS[3] DDR_BS[0] DDR_BS[1] DDR_BS[2] DDR_A[12] DDR_A[11] DDR_A[10] DDR_A[9] DDR_A[8] DDR_A[7] DDR_A[6] DDR_A[5] DDR_A[4] DDR_A[3] DDR_A[2] DDR_A[1] DDR_A[0] I/O/Z DVDDR2 DDR2 address I/O/Z DVDDR2 Bank select outputs (BS[2:0]). required support DDR2 memories. TYPE OTHER DDR2 Memory Controller I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DDR2 Clock DDR2 Differential clock DDR2 Clock Enable DDR2 Active chip select DDR2 Active Write enable DDR2 Data mask outputs DQM3: upper byte data DDR_D[31:24] DQM2: DDR_D[23:16] DQM1: DDR_D[15:8] DQM0: lower byte DDR_D[7:0] DDR2 Access Signal output DDR2 Column Access Signal output Data strobe input/outputs each byte 32-bit data bus. They outputs DDR2 memory when writing inputs when reading. They used synchronize data transfers. DQS3 upper byte DDR_D[31:24] DQS2: DDR_D[23:16] DQS1: DDR_D[15:8] DQS0: bottom byte DDR_D[7:0] DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table
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Table 2-9. DDR2 Memory Controller Terminal Functions (continued)
SIGNAL NAME DDR_D[31] DDR_D[30] DDR_D[29] DDR_D[28] DDR_D[27] DDR_D[26] DDR_D[25] DDR_D[24] DDR_D[23] DDR_D[22] DDR_D[21] DDR_D[20] DDR_D[19] DDR_D[18] DDR_D[17] DDR_D[16] DDR_D[15] DDR_D[14] DDR_D[13] DDR_D[12] DDR_D[11] DDR_D[10] DDR_D[9] DDR_D[8] DDR_D[7] DDR_D[6] DDR_D[5] DDR_D[4] DDR_D[3] DDR_D[2] DDR_D[1] DDR_D[0] DDR_VREF DDR_VSSDLL DDR_VDDDLL DDR_ZN DDR_ZP
TYPE
OTHER
DESCRIPTION
I/O/Z
DVDDR2
DDR2 data configured bits wide bits wide.
Reference voltage input SSTL_18 buffers. Ground DDR2 Digital Locked Loop. Power (1.8 Volts) DDR2 Digital Locked Loop. Impedance control DDR2 outputs. This must connected resistor DVDDR2. Impedance control DDR2 outputs. This must connected resistor VSS.
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Table 2-10. Terminal Functions
SIGNAL NAME SCL/ GPIO43 SDA/ GPIO44 TYPE OTHER I/O/Z I/O/Z DVDD18 DVDD18 This multiplexed between GPIO. I2C, clock output SCL. This multiplexed between GPIO. I2C, bi-directional data signal SDA. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
Table 2-11. Audio Serial Port (ASP) Terminal Functions
SIGNAL NAME CLKX/ GPIO29 CLKR/ GPIO30 FSX/ GPIO31 FSR/ GPIO32 GPIO33 GPIO34 TYPE OTHER Audio Serial Port (ASP) I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 This multiplexed between GPIO. ASP, Transmit clock CLKX. This multiplexed between GPIO. ASP, Receive clock CLKR. This multiplexed between GPIO. ASP, Transmit frame synchronization FSX. This multiplexed between GPIO. ASP, Receive frame synchronization FSR. This multiplexed between GPIO. ASP, Data Transmit output This multiplexed between GPIO. ASP, Data Receive input DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
Table 2-12. Terminal Functions
SIGNAL NAME SPI_EN0/ GPIO37 SPI_EN1/ GPIO42 SPI_CLK/ GPIO39 SPI_DI/ GPIO40 SPI_DO/ GPIO41 TYPE OTHER Serial Peripheral Interface (SPI) I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 This multiplexed between GPIO. When used SPI, slave device enable output SPI_EN0. This multiplexed between GPIO. When used SPI, slave device enable output SPI_EN1. This multiplexed between GPIO. SPI, clock output SPI_CLK. This multiplexed between GPIO. SPI, data input SPI_DI. This multiplexed between GPIO. data output SPI_DO. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
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Table 2-13. EMAC MDIO Terminal Functions
SIGNAL NAME GPIOV33_0/ TXEN GPIOV33_1/ TXCLK GPIOV33_2/ GPIOV33_6/ TXD3 GPIOV33_5/ TXD2 GPIOV33_4/ TXD1 GPIOV33_3/ TXD0 GPIOV33_11/ RXCLK GPIOV33_12/ RXDV GPIOV33_13/ RXER GPIOV33_14/ GPIOV33_10/ RXD3 GPIOV33_9/ RXD2 GPIOV33_8/ RXD1 GPIOV33_7/ RXD0 GPIOV33_16/ MDCLK GPIOV33_15/ MDIO TYPE OTHER EMAC I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between GPIO Ethernet MAC. Ethernet mode, Transmit Enable output TXEN. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Transmit Clock input TXCLK. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Collision Detect input COL. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Transmit Data output TXD3. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Transmit Data output TXD2. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Transmit Data output TXD1. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Transmit Data output TXD0. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Receive Clock input RXCLK. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Receive Data Valid input RXDV. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Receive Error input RXER. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Carrier Sense input CRS. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Receive Data input RXD3. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Receive Data input RXD2. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Receive data input RXD1. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Receive Data input RXD0. MDIO I/O/Z I/O/Z DVDD33 DVDD33 This multiplexed between GPIO Ethernet MAC. Ethernet mode, Management Data Clock output MDCLK. This multiplexed between GPIO Ethernet MAC. Ethernet mode, Management Data MDIO. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
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Table 2-14. GPIOV33 Terminal Functions
SIGNAL NAME GPIOV33_16/ MDCLK GPIOV33_15/ MDIO GPIOV33_14/ GPIOV33_13/ RXER GPIOV33_12/ RXDV GPIOV33_11/ RXCLK GPIOV33_10/ RXD3 GPIOV33_9/ RXD2 GPIOV33_8/ RXD1 GPIOV33_7/ RXD0 GPIOV33_6/ TXD3 GPIOV33_5/ TXD2 GPIOV33_4/ TXD1 GPIOV33_3/ TXD0 GPIOV33_2/ GPIOV33_1/ TXCLK GPIOV33_0/ TXEN TYPE OTHER GPIOV33 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_16. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_15. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_14. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_13. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_12. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_11. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_10. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_9. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_8. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_7. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_6. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_5. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_4. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_3. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_2. This multiplexed between GPIO Ethernet MAC. GPIO mode, 3.3V GPIO GPIOV33_1. This multiplexed between GPIO Ethernet MAC. GPIO mode, this 3.3V GPIO GPIOV33_0. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
Table 2-15. Standalone GPIOV18 Terminal Functions
SIGNAL NAME GPIO7 GPIO50 GPIO51 TYPE OTHER Standalone GPIOV18 I/O/Z I/O/Z I/O/Z DVDD18 DVDD18 DVDD18 This standalone functions GPIO7. This standalone functions GPIO50. This standalone functions GPIO51. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
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Table 2-16. Terminal Functions
SIGNAL NAME TYPE OTHER Crystal input oscillator USB). M24XI DVDD18 crystal input used, instead physical clock-in source supplied, this external oscillator clock input. When peripheral used, M24XI should left Connect. Crystal output oscillator. M24XO DVDD18 crystal input used, instead physical clock-in source supplied, M24XO should left Connect. When peripheral used, M24XO should left Connect. 1.8-V power supply oscillator. M24VDD
DESCRIPTION
crystal input used, instead physical clock-in source supplied, M24VDD should still connected 1.8-V power supply. When peripheral used, M24VDD should connected 1.8-V power supply. Ground oscillator.
M24VSS
crystal input used, instead physical clock-in source supplied, M24VSS should still connected ground. When peripheral used, M24VSS should connected ground. input that signifies that VBUS connected.
USB_VBUS
When peripheral used, USB_VBUS signal should either pulled down pulled 10-k resistor. operating mode identification pin. Host mode operation, pull down this ground (VSS) external 1.5-k resistor. Device mode operation, pull this DVDD33 rail external 1.5-k resistor. When peripheral used, USB_ID signal should either pulled down pulled 10-k resistor.
USB_ID
USB_DP USB_DM
bi-directional Data Differential signal pair [positive/negative]. When peripheral used, USB_DP signal should pulled high USB_DM signal should pulled down 10-k resistor. Reference current output. This must connected 10-k resistor USB_VSSREF. When peripheral used, USB_R1 signal should connected 10-k resistor USB_VSSREF.
USB_R1
Ground reference current. This must connected 10-k resistor USB_R1. When peripheral used, USB_VSSREF signal should connected VSS. Analog power supply phy.
USB_VSSREF
USB_VDDA3P3
When peripheral used, USB_VDDA3P3 signal should connected DVDD33. Analog ground phy. When peripheral used, USB_VSSA3P3 signal should connected VSS. 1.8-V power supply phy. When peripheral used, USB_VDD1P8 signal should connected DVDD18.
USB_VSSA3P3
USB_VDD1P8
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table Device Overview Submit Documentation Feedback
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Table 2-16. Terminal Functions (continued)
SIGNAL NAME USB_VSS1P8 TYPE OTHER Ground phy.
DESCRIPTION
When peripheral used, USB_VSS1P8 signal should connected VSS. Core Power supply output phy. This must connected 1-µF capacitor VSS. When peripheral used, USB_VDDA1P2LDO signal should still connected 1-µF capacitor VSS.
USB_VDDA1P2LDO
USB_VSSA1P2LDO
Core Ground phy. This ground must connected VSS. When peripheral used, USB_VSSA1P2LDO signal should still connected VSS.
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Table 2-17. VPFE Terminal Functions
SIGNAL NAME TYPE OTHER VIDEO/IMAGE (VPFE) PCLK I/O/Z I/O/Z DVDD18 DVDD18 DVDD18 Pixel clock input used load image data into Controller (CCDC) pins CI[7:0] YI[7:0]. Vertical synchronization signal that either input (slave mode) output (master mode), which signals start frame CCDC. Horizontal synchronization signal that either input (slave mode) output (master mode), which signals start line CCDC. This multiplexed between CCDC UART2. When used CCDC input CI7, supports several modes. 16-bit Analog-Front-End (AFE) mode, input CCD15. 16-bit YCbCr mode, time multiplexed between inputs. 8-bit YCbCr mode, time multiplexed between CB7, upper 8-bit channel. This multiplexed between CCDC UART2. When used CCDC input CI6, supports several modes. 16-bit mode, input CCD14. 16-bit YCbCr mode, time multiplexed between inputs. 8-bit YCbCr mode, time multiplexed between CB6, upper 8-bit channel. This multiplexed between CCDC UART2. When used CCDC input CI5, supports several modes. 16-bit mode, input CCD13. 16-bit YCbCr mode, time multiplexed between inputs. 8-bit YCbCr mode, time multiplexed between CB5, upper 8-bit channel. This multiplexed between CCDC UART2. When used CCDC input CI4, supports several modes. 16-bit mode, input CCD12. 16-bit YCbCr mode, time multiplexed between inputs. 8-bit YCbCr mode, time multiplexed between CB4, upper 8-bit channel. This CCDC input supports several modes. 16-bit mode, input CCD11. 16-bit YCbCr mode, time multiplexed between inputs. 8-bit YCbCr mode, time multiplexed between CB3, upper 8-bit channel. This CCDC input supports several modes. 16-bit mode, input CCD10. 16-bit YCbCr mode, time multiplexed between inputs. 8-bit YCbCr mode, time multiplexed between CB2, upper 8-bit channel. This CCDC input supports several modes. 16-bit mode, input CCD9. 16-bit YCbCr mode, time multiplexed between inputs. 8-bit YCbCr mode, time multiplexed between CB1, upper 8-bit channel. This CCDC input supports several modes. 16-bit mode, input CCD8. 16-bit YCbCr mode, time multiplexed between inputs. 8-bit YCbCr mode, time multiplexed between CB0, upper 8-bit channel. This CCDC input supports several modes. 16-bit mode, input CCD7. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB7, lower 8-bit channel. DESCRIPTION
CI7/ CCD15/ UART_RXD2
I/O/Z
DVDD18
CI6/ CCD14/ UART_TXD2
I/O/Z
DVDD18
CI5/ CCD13/ UART_CTS2
I/O/Z
DVDD18
CI4/ CCD12/ UART_RTS2
I/O/Z
DVDD18
CI3/ CCD11
DVDD18
CI2/ CCD10
DVDD18
CI1/ CCD9
DVDD18
CI0/ CCD8
DVDD18
YI7/ CCD7
DVDD18
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
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Table 2-17. VPFE Terminal Functions (continued)
SIGNAL NAME YI6/ CCD6 TYPE OTHER DESCRIPTION This CCDC input supports several modes. 16-bit mode, input CCD6. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB6, lower 8-bit channel. This CCDC input supports several modes. 16-bit mode, input CCD5. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB5, lower 8-bit channel. This CCDC input supports several modes. 16-bit Analog-Front-End (AFE) mode, input CCD4. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB4, lower 8-bit channel. This CCDC input supports several modes. 16-bit mode, input CCD3. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB3, lower 8-bit channel. This CCDC input supports several modes. 16-bit mode, input CCD2. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB2, lower 8-bit channel. This CCDC input supports several modes. 16-bit mode, input CCD1. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB1, lower 8-bit channel. This CCDC input supports several modes. 16-bit mode, input CCD0. 16-bit YCbCr mode, input 8-bit YCbCr mode, time multiplexed between CB0, lower 8-bit channel. This multiplexed between GPIO VPFE. VPFE mode, Controller write enable input C_WE. This multiplexed between GPIO, VPFE, VPBE. VPFE mode, CCDC field identification bidirectional signal C_FIELD.
DVDD18
YI5/ CCD5
DVDD18
YI4/ CCD4
DVDD18
YI3/ CCD3
DVDD18
YI2/ CCD2
DVDD18
YI1/ CCD1
DVDD18
YI0/ CCD0 GPIO1/ C_WE GPIO4/ C_FIELD
DVDD18
I/O/Z I/O/Z
DVDD18 DVDD18
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Table 2-18. VPBE Terminal Functions
SIGNAL NAME TYPE OTHER VIDEO (VPBE) HSYNC VSYNC VCLK VPBECLK COUT0/ BTSEL0 COUT1/ BTSEL1 COUT2/ EM_WIDTH COUT3/ COUT4/ COUT5/ COUT6/ COUT7/ YOUT0/ AEAW0 YOUT1/ AEAW1 YOUT2/ AEAW2 YOUT3/ AEAW3 YOUT4/ AEAW4 YOUT5/ YOUT6/ YOUT7/ GPIO0/ LCD_OE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 VPBE Horizontal Sync signal that either input output. VPBE Vertical Sync signal that either input output. VPBE Clock Output VPBE Clock Input This multiplexed between boot mode VPBE. After reset, this either video encoder outputs COUT0, RGB666/888 Blue output data bits This multiplexed between boot mode VPBE. After reset, this either video encoder outputs COUT1, RGB666/888 Blue output data bits This multiplexed between EMIFA VPBE. After reset, video encoder output COUT2 RGB666/888 Blue output data proper device operation, reset this must externally pulled down 10-k resistor. After reset, video encoder output COUT3 RGB666/888 Blue data output Video encoder output COUT4 RGB666/888 Blue data output Video encoder output COUT5 RGB666/888 Green data output Video encoder output COUT6 RGB666/888 Green data output Video encoder output COUT7 RGB666/888 Green data output DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
DVDD18
I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18
I/O/Z
I/O/Z
These pins multiplexed between EMIFA VPBE. After reset, these video encoder outputs YOUT[0:4] RGB666/888 Green data outputs
I/O/Z
I/O/Z I/O/Z
Video encoder output YOUT5 RGB666/888 data output Video encoder output YOUT6 RGB666/888 data output Video encoder output YOUT7 RGB666/888 data output This multiplexed between GPIO VPBE. VPBE mode, output enable LCD_OE.
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
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Table 2-18. VPBE Terminal Functions (continued)
SIGNAL NAME GPIO2/ GPIO3/ LCD_FIELD GPIO4/ C_FIELD GPIO5/ GPIO6/ GPIO38/ PWM1/ GPIO46 PWM2/ GPIO47 TYPE I/O/Z I/O/Z OTHER DVDD18 DVDD18 DESCRIPTION This multiplexed between GPIO VPBE. VPBE mode, RGB888 Green data output This multiplexed between GPIO, VPBE. VPBE mode, RGB888 Blue data output interlaced bidirectional LCD_FIELD. This multiplexed between GPIO, VPFE, VPBE. VPBE mode, RGB888 data output This multiplexed between GPIO VPBE. VPBE mode, RGB888 Green data output This multiplexed between GPIO VPBE. VPBE mode, RGB888 Blue data output This multiplexed between VPBE GPIO. VPBE mode, RGB888 output data This multiplexed between PWM1, VPBE, GPIO. VPBE mode, RGB888 output (R2). This multiplexed between PWM2, VPBE, GPIO. VPBE mode, RGB888 Blue output (B2).
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18
I/O/Z
DVDD18
Table 2-19. [Part VPBE] Terminal Functions
SIGNAL NAME TYPE OTHER DAC[A:D] DAC_VREF DAC_IOUT_A DAC_IOUT_B DAC_IOUT_C VDDA_1P8V VSSA_1P8V VDDA_1P1V VSSA_1P1V DAC_RBIAS
DESCRIPTION
Reference voltage input (0.5 When used, DAC_VREF signal should connected VSS. Output When used, DAC_IOUT_A signal should left Connect. Output When used, DAC_IOUT_B signal should left Connect. Output When used, DAC_IOUT_C signal should left Connect. 1.8-V analog power. When used, VDDA_1P8V signal should connected VSS. Analog ground. When used, VSSA_1P8V signal should connected VSS. 1.20-V analog core supply voltage. When used, VDDA_1P1V signal should connected VSS. Analog core ground. When used, VSSA_1P1V signal should connected VSS. External resistor connection current bias configuration. This must connected resistor VSSA_1P8V. When used, DAC_RBIAS signal should connected VSS.
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table
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Table 2-20. UART0, UART1, UART2 Terminal Functions
SIGNAL NAME CI7/ CCD15/ UART_RXD2 CI6/ CCD14/ UART_TXD2 CI5/ CCD13/ UART_CTS2 CI4/ CCD12/ UART_RTS2 UART_TXD1 UART_RXD1 TYPE OTHER UART2 I/O/Z DVDD18 DVDD18 DVDD18 DVDD18 This multiplexed between CCDC UART2. When used UART2 receive data input UART_RXD2. This multiplexed between CCDC UART2. UART2 mode, transmit data output UART_TXD2. This multiplexed between CCDC UART2. UART2 mode, clear send input UART_CTS2. This multiplexed between CCDC UART2. UART2 mode, ready send output UART_RTS2. UART1 I/O/Z I/O/Z DVDD18 DVDD18 This transmit data output UART_TXD1. This receive data input UART_RXD1. UART0 UART_RXD0/ GPIO35 UART_TXD0/ GPIO36 I/O/Z I/O/Z DVDD18 DVDD18 This multiplexed between UART0 GPIO. UART0, receive data input UART_RXD0. This multiplexed between UART0 GPIO. UART0, transmit data output UART_TXD0. DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
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Table 2-21. PWM0, PWM1, PWM2 Terminal Functions
SIGNAL NAME PWM2/ GPIO47 PWM1/ GPIO46 PWM0/ GPIO45 TYPE OTHER PWM2 I/O/Z DVDD18 This multiplexed between PWM2, VPBE, GPIO. PWM2, output PWM2. PWM1 I/O/Z DVDD18 This multiplexed between PWM1, VPBE, GPIO. PWM1, output PWM1. PWM0 I/O/Z DVDD18 This multiplexed between PWM0 GPIO. PWM0, output PWM0. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
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Table 2-22. MMC/S-D/SDIO Terminal Functions
SIGNAL NAME SD_CLK SD_CMD SD_DATA3 SD_DATA2 SD_DATA1 SD_DATA0 TYPE OTHER MMC/SD/SDIO I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 These pins nibble wide bi-directional data SD_DATA[3:0]. DVDD33 DVDD33 Data clock output SD_CLK Bi-directional command SD_CMD DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
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Table 2-23. Terminal Functions
SIGNAL NAME TYPE OTHER Host-Port Interface (HPI) EM_CS3 EM_BA[0]/ HINT EM_A[0]/ HCNTL1/ GPIO53 EM_A[2]/ (CLE)/ HCNTL0 EM_A[1]/ (ALE)/ HHWIL EM_R/W/ HR/W EM_CS2/ EM_WE (WE) HDS2 EM_OE/ (RE)/ HDS1 EM_WAIT/ (RDY/BSY)/ HRDY I/O/Z I/O/Z DVDD18 DVDD18 EMIFA, this Chip Select output. mode this must pulled high external 10-k resistor. This multiplexed between EMIFA HPI. mode, host interrupt output HINT. This multiplexed between EMIFA, HPI, GPIO. HPI, control input HCNTL1. state HCNTL1 HCNTL0 determine address, data, control information being transmitted between external host DM357. This multiplexed between EMIFA (NAND/SmartMedia/xD), HPI. mode, control input HCNTL0. state HCNTL1 HCNTL0 determine address, data, control information being transmitted between external host DM357. This multiplexed between EMIFA (NAND/SmartMedia/xD), HPI. mode, Half-word identification input HHWIL. This multiplexed between EMIFA HPI. HPI, Host Read Write input HR/W. This signal active high reads writes. This multiplexed between EMIFA HPI. mode, this Active Chip Select input HCS. This multiplexed between EMIFA (NAND/SmartMedia/xD) HPI. HPI, data strobe input HDS2. This multiplexed between EMIFA (NAND/SmartMedia/xD) HPI. HPI, data strobe input HDS1. This multiplexed between EMIFA (NAND/SmartMedia/xD) HPI. HPI, ready output HRDY. DESCRIPTION
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z
DVDD18
I/O/Z I/O/Z I/O/Z
DVDD18 DVDD18 DVDD18
I/O/Z
DVDD18 DVDD18
I/O/Z
Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
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Table 2-23. Terminal Functions (continued)
SIGNAL NAME EM_D15/ HD15 EM_D14/ HD14 EM_D13/ HD13 EM_D12/ HD12 EM_D11/ HD11 EM_D10/ HD10 EM_D9/ EM_D8/ EM_D7/ EM_D6/ EM_D5/ EM_D4/ EM_D3/ EM_D2/ EM_D1/ EM_D0/ I/O/Z DVDD18 These pins multiplexed between EMIFA (NAND) HPI. mode, these HD[15:0] multiplexed internally with address lines. TYPE OTHER DESCRIPTION
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Table 2-24. Timer Timer Timer Terminal Functions
SIGNAL NAME TYPE OTHER Timer Timer external pins. Timer Timer peripheral pins pinned external pins. Timer CLK_OUT1/ TIM_IN/ GPIO49 I/O/Z DVDD18 This multiplexed between clock generator, timer, GPIO. Timer0, timer event capture input TIM_IN. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
Table 2-25. Reserved Terminal Functions
SIGNAL NAME RSV1 RSV2 RSV3 RSV4 RSV5 RSV6 RSV7 RSV24 RSV45 TYPE OTHER RESERVED Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. This must tied directly normal device operation. Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. pull signal opposite supply rail, resistor should used.) Specifies operating supply voltage each signal
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Table 2-26. Supply Terminal Functions
SIGNAL NAME DVDD33 DVDD18 DVDDR2 Input, Output, High impedance, Supply voltage, Ground, Analog signal DDR2 supply voltage (see Power-Supply Decoupling section this data manual) supply voltage (see Power-Supply Decoupling section this data manual) supply voltage (see Power-Supply Decoupling section this data manual) TYPE OTHER SUPPLY VOLTAGE PINS DESCRIPTION
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Table 2-26. Supply Terminal Functions (continued)
SIGNAL NAME CVDD 1.20 core supply voltage (-270 devices) (see Power-Supply Decoupling section this data manual) TYPE OTHER DESCRIPTION
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Table 2-27. Ground Terminal Functions
SIGNAL NAME Input, Output, High impedance, Supply voltage, Ground, Analog signal Ground pins TYPE OTHER GROUND PINS DESCRIPTION
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Table 2-27. Ground Terminal Functions (continued)
SIGNAL NAME Ground pins TYPE OTHER DESCRIPTION
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Device Support 2.8.1 Development Support
offers extensive line development tools TMS320DM357 platform, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules. tool's support documentation electronically available within Code Composer StudioIntegrated Development Environment (IDE). following products support development TMS320DM357 SoC-based applications: Software Development Tools: Code Composer StudioIntegrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, Debug plus additional development tools Hardware Development Tools: Extended Development System (XDSTM) Emulator complete listing development-support tools TMS320DM357 platform, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL). information pricing availability, contact nearest field sales office authorized distributor.
2.8.2
Device Development-Support Tool Nomenclature
designate stages product development cycle, assigns prefixes part numbers devices support tools. Each DM357 commercial family member three prefixes: TMX, TMP, (e.g., TMS320DM357ZWT). Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: Experimental device that necessarily representative final device's electrical specifications. Final silicon that conforms device's electrical specifications completed quality reliability verification. Fully-qualified production device.
Support tool development evolutionary flow: TMDX TMDS Development-support product that completed Texas Instruments internal qualification testing. Fully qualified development-support product.
devices TMDX development-support tools shipped against following disclaimer: "Developmental product intended internal evaluation purposes." devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX TMP) have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used.
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device nomenclature also includes suffix with device family name. This suffix indicates package type (for example, ZWT), temperature range (for example, "Blank" commercial temperature range), device speed range megahertz (for example, "Blank" default [270-MHz ARM9]). Figure provides legend reading complete device name TMS320DM357 platform member.
PREFIX Experimental device Qualified device DEVICE FAMILY TMS320DSP Family DEVICE(B) DM35x DMSoC: DM357 PACKAGE TYPE 361-pin plastic BGA, with Pb-Free soldered balls SILICON REVISION: =Silicon Ball Grid Array actual part numbers (P/Ns) ordering information, websitr (http://www.ti.com)
DM357
DEVICE SPEED RANGE Blank 270-MHz ARM9 TEMPERATURE RANGE (DEFAULT: 85°C) Blank commercial temperature
Figure 2-5. Device Nomenclature
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2.8.3
Documentation Support
2.8.3.1 Related Documentation From Texas Instruments following documents describe TMS320DM357 Digital Media System-on-Chip (DMSoC). Copies these documents available Internet www.ti.com. Tip: Enter literature number search provided www.ti.com. SPRUG06 TMS320DM357 DMSoC Video Processing Back (VPBE) User's Guide. Describes video processing back (VPBE) TMS320DM357 Digital Media System-on-Chip (DMSoC) video processing subsystem. Included VPBE video encoder, on-screen display, digital controller. TMS320DM357 DMSoC Subsystem Reference Guide. Describes subsystem TMS320DM357 Digital Media System-on-Chip (DMSoC). subsystem designed give ARM926EJ-S (ARM9) master control device. general, responsible configuration control device; including video processing subsystem, majority peripherals external memories. TMS320DM357 DMSoC Universal Asynchronous Receiver/Transmitter (UART) User's Guide. This document describes universal asynchronous receiver/transmitter (UART) peripheral TMS320DM357 Digital Media System-on-Chip (DMSoC). UART peripheral performs serial-to-parallel conversion data received from peripheral device, parallel-to-serial conversion data received from CPU. TMS320DM357 DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide. Describes inter-integrated circuit (I2C) peripheral TMS320DM357 Digital Media System-on-Chip (DMSoC). peripheral provides interface between DMSoC other devices compliant with I2C-bus specification connected I2C-bus. External components attached this 2-wire serial transmit receive 8-bit wide data from DMSoC through peripheral. This document assumes reader familiar with I2C-bus specification. TMS320DM357 DMSoC 64-Bit Timer User's Guide. Describes operation software-programmable 64-bit timer TMS320DM357 Digital Media System-on-Chip (DMSoC). Timer Timer used general-purpose (GP) timers programmed 64-bit mode, dual 32-bit unchained mode, dual 32-bit chained mode; Timer used only watchdog timer. timer modes used generate periodic interrupts enhanced direct memory access (EDMA) synchronization events. watchdog timer mode used provide recovery mechanism device event fault condition, such non-exiting code loop. TMS320DM357 DMSoC Serial Peripheral Interface (SPI) User's Guide. Describes serial peripheral interface (SPI) TMS320DM357 Digital Media System-on-Chip (DMSoC). high-speed synchronous serial input/output port that allows serial stream programmed length bits) shifted into device programmed bit-transfer rate. normally used communication between DMSoC external peripherals. Typical applications include interface external peripheral expansion devices such shift registers, display drivers, EPROMs analog-to-digital converters. TMS320DM357 DMSoC Host Port Interface (HPI) Reference Guide. This document describes host port interface TMS320DM357 Digital Media System-on-Chip (DMSoC). provides parallel port interface through which external host processor directly access TMS320DM357 DMSoC processor's resources (configuration program/data memories). TMS320DM357 DMSoC General-Purpose Input/Output (GPIO) User's Guide. Describes general-purpose input/output (GPIO) peripheral TMS320DM357 Digital Media
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Device Overview
TMS320DM357 Digital Media System-on-Chip
System-on-Chip (DMSoC). GPIO peripheral provides dedicated general-purpose pins that configured either inputs outputs. When configured input, detect state input reading state internal register. When configured output, write internal register control state driven output pin. SPRUG32 TMS320DM357 DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller User's Guide. Describes multimedia card (MMC)/secure digital (SD) card controller TMS320DM357 Digital Media System-on-Chip (DMSoC). MMC/SD card used number applications provide removable data storage. MMC/SD controller provides interface external cards. communication between MMC/SD controller MMC/SD card(s) performed MMC/SD protocol. TMS320DM357 DMSoC Asynchronous External Memory Interface (EMIF) User's Guide. Describes asynchronous external memory interface (EMIF) TMS320DM357 Digital Media System-on-Chip (DMSoC). EMIF supports glueless interface variety external devices. TMS320DM357 DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide. Describes operation enhanced direct memory access (EDMA3) controller TMS320DM357 Digital Media System-on-Chip (DMSoC). EDMA3 controller's primary purpose service user-programmed data transfers between memory-mapped slave endpoints DMSoC. TMS320DM357 DMSoC Audio Serial Port (ASP) User's Guide. Describes operation audio serial port (ASP) audio interface TMS320DM357 Digital Media System-on-Chip (DMSoC). primary audio modes that supported AC97 modes. addition primary audio modes, supports general serial port receive transmit operation, intended used high-speed interface. TMS320DM357 DMSoC Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module User's Guide. Discusses ethernet media access controller (EMAC) physical layer (PHY) device management data input/output (MDIO) module TMS320DM357 Digital Media System-on-Chip (DMSoC). EMAC controls flow packet data from DMSoC PHY. MDIO module controls configuration status monitoring. TMS320DM357 DMSoC Pulse-Width Modulator (PWM) Peripheral User's Guide. Describes pulse-width modulator (PWM) peripheral TMS320DM357 Digital Media System-on-Chip (DMSoC). TMS320DM357 DMSoC DDR2 Memory Controller User's Guide. Describes DDR2 memory controller TMS320DM357 Digital Media System-on-Chip (DMSoC). DDR2 memory controller used interface with JESD79D-2A standard compliant DDR2 SDRAM devices. TMS320DM357 DMSoC Video Processing Front (VPFE) User's Guide. Describes video processing front (VPFE) TMS320DM357 Digital Media System-on-Chip (DMSoC) video processing subsystem. Included VPFE preview engine, controller, resizer, histogram, hardware (H3A) statistic generator. TMS320DM357 DMSoC Peripherals Overview Reference Guide. This document provides overview peripherals TMS320DM357 Digital Media System-on-Chip (DMSoC). TMS320DM357 DMSoC Universal Serial Controller User's Guide. This document describes universal serial (USB) controller TMS320DM357 Digital Media System-on-Chip (DMSoC). controller supports data throughput rates Mbps. provides mechanism data transfer between devices also supports
Device Overview
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host negotiation.
Device Overview
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Device Configurations
System Module Registers
system module includes status control registers required configuration device. Brief descriptions various registers shown Table 3-1. System Module registers required device configurations discussed following sections. Table 3-1. System Module Register Memory
ADDRESS RANGE 0x01C4 0000 0x01C4 0004 0x01C4 0008 0x01C4 000C 0x01C4 0010 0x01C4 0014 0x01C4 0018 0x01C4 0027 0x01C4 0028 0x01C4 002C 0x01C4 0030 0x01C4 0034 0x01C4 0038 0x01C4 003C 0x01C4 0040 0x01C4 0044 0x01C4 0048 0x01C4 004C 0x01C4 0050 0x01C4 006F REGISTER ACRONYM PINMUX0 PINMUX1 BOOTCFG JTAGID HPI_CTL USBPHY_CTL MSTPRI0 MSTPRI1 VPSS_CLKCTL VDD3P3V_PWDN DRRVTPER DESCRIPTION multiplexing control details, Section 3.5.4, PINMUX0 Register Description. multiplexing control details, Section 3.5.5, PINMUX1 Register Description. Reserved. Reserved Reserved. Device boot configuration. details, Section 3.3.1.1, BOOTCFG Register Description. Reserved. JTAGID/Device number. details, Section 6.23.1, JTAG Register Description. Reserved. control. details, Section 3.5.6.10, EMIFA Multiplexing. control. details, Section 6.14.1, USBPHY_CTL Register Description. Reserved. master priority control details, Section 3.5.1, Switched Central Resource (SCR) Priorities. master priority control details, Section 3.5.1, Switched Central Resource (SCR) Priorities. VPSS clock control. 3.3V powerdown control. details, Section 3.2.1, Power Configurations after Reset. Enables access DDR2 Register. Reserved.
Power Considerations
Global device power domains controlled Power Sleep Controller, except shown following sections.
3.2.1
Power Configurations after Reset
VDD3P3V_PWDN register controls power 3.3V buffers MMC/SD/SDIO GPIOV33. 3.3V I/Os separated into groups independent control shown Figure described Table 3-2. default, these pins disabled reset. Figure 3-1. VDD3P3V_PWDN Register
RESERVED R-0000 0000 0000 0000 0000 0000 0000
IOPWDN1 R/W-1
IOPWDN0 R/W-1
LEGEND: Read, Write, value reset
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Table 3-2. VDD3P3V_PWDN Register Description
NAME IOPWDN0 DESCRIPTION GIOV33 Powerdown controls GIOV33[16:0] pins. buffers powered buffers powered down MMC/SD/SDIO Powerdown controls SD_CLK, SD_CMD, SD_DATA[3:0] pins. buffers powered buffers powered down
IOPWDN1
Bootmode
device booted through multiple means: states captured reset, primary bootloaders within internal EMIFA, secondary user bootloaders from peripherals external memories. Boot modes, configurations, register configurations required booting device, described following sections.
3.3.1
Bootmode Registers
BOOTCFG register described following sections. reset, status various pins required proper boot stored within this register.
3.3.1.1 BOOTCFG Register Description BOOTCFG register (located address 0x01C4 000A) contains status values BTSEL1, BTSEL0, EM_WIDTH, AEAW[4:0] pins captured rising edge RESET. register format shown Figure field descriptions shown Table 3-3. captured bits software readable after reset. Figure 3-2. BOOTCFG Register
RESERVED
BTSEL
EM_WIDTH
DAEAW
R-0000 0000 0000 0000 0000 0000
R-LL
R-LLLLL
LEGEND: Read; Write; state latched reset rising; value after reset
Table 3-3. BOOTCFG Register Description
NAME BTSEL DESCRIPTION Boot mode selection states (BTSEL1, BTSEL0) captured rising edge RESET. `00' indicates boots from (NAND Flash). `01' indicates that boots from EMIFA (NOR Flash). `10' indicates that boots from (HPI). `11' indicates that boots from (UART0). EM_WIDTH proprer device operation, this should always "0". EMIFA data width selection state captured rising edge RESET. sets EMIFA data width sets EMIFA data width. DAEAW EMIFA address width selection states (AEAW[4:0]) captured rising edge RESET. This configures EMIFA address pins multiplexed with GPIO. Table 3-6,Table 3-7, Table
3.3.2
Boot
DM357 boot from EMIFA, internal (NAND), UART0, HPI, determined setting BTSEL[1:0] pins. BTSEL[1:0] pins read Boot Loader (RBL) further define boot mode. boot modes summarized Table 3-4.
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Table 3-4. Boot Modes
BTSEL1 BTSEL0 BOOT MODE NAND EMIFA External Boot UART RESET VECTOR 0x0000 4000 0x0200 0000 0x0000 4000 0x0000 4000 BRIEF DESCRIPTION K-bytes secondary boot loader through NAND with K-bytes page sizes. EMIFA EM_CS2 external memory space. K-btyes secondary boot loader through external host. K-bytes secondary boot loader through UART0.
When BTSEL[1:0] pins EMIFA External Boot ("01"), immediately begins executing code from EMIFA EM_CS2 memory space (0x0200 0000). When BTSEL[1:0] pins indicate condition other than EMIFA External Boot (!01), begins execution. NAND Boot mode following features: Loads secondary User Boot Loader (UBL) from NAND flash Internal (AIM) transfers control user software. Support NAND with page sizes 2048 bytes. Support error correction when loading Support 14KB Optional, user selectable, support DMA, I-cache, enable while loading UART Boot mode following features: Loads secondary UART0 transfers control user software. Support 14KB Boot Mode following features: support full firmware boot. Instead, waits external host load secondary transfers control user software. Support 14KB UBL. further details Bootloader, refer Subsystem Users Guide.
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Device Configurations
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Configurations Reset
following sections give information configuration settings device reset.
3.4.1
Device Configuration Device Reset
Table shows summary device inputs required booting configuring EMIFA data address widths proper operation device rising edge RESET input. Table 3-5. Device Configurations (Input Pins Sampled Reset)
DEVICE SIGNALS SAMPLED RESET BTSEL[1:0]
DEVICE SIGNAL NAME AFTER RESET COUT[1:0] Boot mode selection pins. `00' indicates `01' indicates `10' indicates `11' indicates
DESCRIPTION
boots from (NAND Flash). that boots from EMIFA (NOR Flash). that boots from (ROM) that boots from (UART0).
COUT3 EM_WIDTH
COUT3 COUT2
proper device operation, this must pulled down external 10-k resistor. EMIFA data width selection pin. sets EMIFA 8-bit data width sets EMIFA 16-bit data width.
AEAW[4:0]
YOUT[4:0]
EMIFA address width selection pins EMIFA address pins multiplexed with GPIO. Table 3-6, Table 3-7, Table details.
3.4.2
Peripheral Selection Device Reset
briefly mentioned Table 3-5, state AEAW[4:0] pins captured reset configures number EMIFA address pins required device boot. These values stored AEAW field PINMUX0 register. reset, this provides proper addressing external boot. Unused address pins available GPIO. register settings software programmable after reset. Table 3-6, Table 3-7, Table show AEAW[4:0] settings corresponding multiplexing EMIFA address GPIO pins. number EMIFA address bits enabled configurable from EM_BA[1] EM_A[21:0] pins that assigned another peripheral enabled address signals become GPIO pins. enabled address pins always contiguous from EM_BA[1] upwards address bits cannot skipped. exception this EM_A[2:1] pins. EM_A[2:1] usable signals NAND Flash mode EMIFA always enabled EMIFA pins. address width selected, this still allows NAND Flash accessed. Also, selecting address width (AEAW[4:0] 00010, 00011, 00100) always results address outputs. these other address enable settings, Table 3-6, Table 3-7, Table 3-8.
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Table 3-6. GPIO EMIFA Multiplexing (Part
Register AEAW[4:0] Settings 00000 (default) GPIO[52] GPIO[53] EM_A[1] EM_A[2] GPIO[28] GPIO[27] GPIO[26] GPIO[25] GPIO[24] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 00001 EM_BA[1] GPIO[53] EM_A[1] EM_A[2] GPIO[28] GPIO[27] GPIO[26] GPIO[25] GPIO[24] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 00010 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] GPIO[28] GPIO[27] GPIO[26] GPIO[25] GPIO[24] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 00011 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] GPIO[28] GPIO[27] GPIO[26] GPIO[25] GPIO[24] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 00100 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] GPIO[28] GPIO[27] GPIO[26] GPIO[25] GPIO[24] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 00101 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] GPIO[27] GPIO[26] GPIO[25] GPIO[24] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 00110 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] GPIO[26] GPIO[25] GPIO[24] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 00111 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] GPIO[25] GPIO[24] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10]
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Table 3-7. GPIO EMIFA Multiplexing (Part
Register AEAW[4:0] Settings 01000 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] GPIO[24] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 01001 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 01010 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 01011 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] GPIO[21] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 01100 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] GPIO[20] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 01101 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] GPIO[19] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 01110 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] EM_A[12] GPIO[18] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 01111 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] EM_A[12] EM_A[13] GPIO[17] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10]
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Table 3-8. GPIO EMIFA Multiplexing (Part
Register AEAW[4:0] Settings 10000 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] EM_A[12] EM_A[13] EM_A[14] GPIO[16] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 10001 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] EM_A[12] EM_A[13] EM_A[14] EM_A[15] GPIO[15] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 10010 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] EM_A[12] EM_A[13] EM_A[14] EM_A[15] EM_A[16] GPIO[14] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 10011 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] EM_A[12] EM_A[13] EM_A[14] EM_A[15] EM_A[16] EM_A[17] GPIO[13] GPIO[12] GPIO[11] GPIO[10] 10100 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] EM_A[12] EM_A[13] EM_A[14] EM_A[15] EM_A[16] EM_A[17] EM_A[18] GPIO[12] GPIO[11] GPIO[10] 10101 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] EM_A[12] EM_A[13] EM_A[14] EM_A[15] EM_A[16] EM_A[17] EM_A[18] EM_A[19] GPIO[11] GPIO[10] 10110 EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] EM_A[12] EM_A[13] EM_A[14] EM_A[15] EM_A[16] EM_A[17] EM_A[18] EM_A[19] EM_A[20] GPIO[10] Others EM_BA[1] EM_A[0] EM_A[1] EM_A[2] EM_A[3] EM_A[4] EM_A[5] EM_A[6] EM_A[7] EM_A[8] EM_A[9] EM_A[10] EM_A[11] EM_A[12] EM_A[13] EM_A[14] EM_A[15] EM_A[16] EM_A[17] EM_A[18] EM_A[19] EM_A[20] EM_A[21]
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Configurations After Reset
following sections give details configuring device after reset.
3.5.1
Switched Central Resource (SCR) Priorities
Prioritization within switched central resource (SCR) programmable each master. register fields default priority levels DM357 masters shown Table 3-9. priority levels should tuned obtain best system performance particular application. Lower values indicate higher priority. most masters, their priority values programmed system level configuring MSTPRI0 MSTPRI1 registers. Details MSTPRI0/1 registers shown Figure Figure 3-4. VPSS EDMA masters contain registers that control their priority values. Table 3-9. DM357 Default Master Priorities
PRIORITY FIELD VPSSP EDMATC0P EDMATC1P ARM_DMAP ARM_CFGP EMACP USBP HPIP MASTER VPSS EDMATC0 EDMATC1 DEFAULT PRIORITY LEVEL (VPSS Register) (EDMACC QUEPRI Register) (EDMACC QUEPRI Register)
(DMA) (MSTPRI0 Register) (CFG) (MSTPRI0 Register) EMAC (MSTPRI1 Register) (MSTPRI1 Register) (MSTPRI1 Register)
Figure 3-3. MSTPRI0 Register
RESERVED R-0000 0000 0000 RESERVED R-0000 RESERVED R/W-001 ARM_CFGP R/W-001 ARM_DMAP R/W-001 RESERVED R/W-101
LEGEND: Read; Write; value after reset
Figure 3-4. MSTPRI1 Register
RESERVED R-0000 0000 RESERVED R/W-100 USBP R/W-100 RESERVED R-100 HPIP R-100 EMACP R/W-100 RESERVED R/W-100
LEGEND: Read; Write; value after reset
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3.5.2
Multiplexed Configurations
There numerous multiplexed pins that shared more than peripheral. Some these pins configured external pullup/pulldown resistors only reset, others configured software. described detail Section 3.4.1 Section 3.4.2, hardware configurable multiplexed pins programmed external pullup/pulldown resistors reset initial functionality pins single peripheral. After reset, software configurable multiplexed pins programmable through Memory Mapped Registers (MMR) allow switching functionalities during run-time. Section 3.5.3 more details register settings. summary multiplexing shown Table 3-10. EMAC peripheral shares pins with 3.3V GPIO pins. ASP, UART0/1/2, SPI, I2C, PWM0/1/2 default GPIO pins when enabled. VPBE function VPSS requires additional pins implement RGB888 mode. These multiplexed with GPIOs. Table 3-10. DM357 Multiplexed Peripheral Pins Multiplexing Controls
MULTIPLEXED PERIPHERALS
PRIMARY (DEFAULT) FUNCTION
SECONDARY FUNCTION
TERTIARY FUNCTION
SECONDARY REGISTER/PIN CONTROL PinMux0:HPIEN, Pins:BTSEL[1:0]
TERTIARY REGISTER/PIN CONTROL
EMIFA (NAND), EMIFA (NAND): HPI: EM_A[1] (ALE), HHWIL, HCNTL0, EM_A[2] (CLE), EM_CS2, EM_CS3 EMIFA, EMIFA: EM_D[0:15], EM_BA[0] HPI: HD[0:15], HINT HPI: HR/W, HRDY, HDS1, HDS2
PinMux0:HPIEN, Pins:BTSEL[1:0] PinMux0:HPIEN, Pins:BTSEL[1:0]
EMIFA (NAND), EMIFA (NAND): R/W, EM_WAIT (RDY/BSY), EM_OE (RE), EM_WE (WE) VPBE LCD, GPIO VPFE CCD, GPIO VPBE RGB888, GPIO GPIO:GPIO[0] GPIO:GPIO[1] GPIO:GPIO[2]
VPBE: LCD_OE VPFE: C_WE VPBE: RGB888 VPBE: RGB888 VPBE: RGB888 VPBE: RGB888 EMIFA: EM_CS5 EMIFA: EM_CS4 EMIFA: EM_A[21:14] EMIFA: EM_A[13:3] ASP: (all pins) UART0: RXD, VPBE: LCD_FIELD VPFE: CCD_FIELD
PinMux0:LOEEN PinMux0:CWE PinMux0:RGB888 PinMux0:RGB888 PinMux0:RGB888 PinMux0:RGB888 PinMux0:LFLDEN PinMux0:CFLDEN
VPBE GPIO:GPIO[3] LCD/RGB888, GPIO VPFE CCD, VPBE RGB888, GPIO VPBE RGB888, GPIO EMIFA, GPIO EMIFA, GPIO EMIFA, GPIO EMIFA, GPIO ASP, GPIO UART0, GPIO GPIO:GPIO[4] GPIO: GPIO[5:6, GPIO:GPIO[8] GPIO:GPIO[9] GPIO: GPIO[10:17] GPIO: GPIO[18:28] GPIO: GPIO[29:34] GPIO: GPIO[35:36]
PinMux0:AECS5 PinMux0:AECS4 PinMux0:AEAW, Pins:DAEAW[4:0] PinMux0:AEAW, Pins:DAEAW[4:0] PinMux1:ASP PinMux1:UART0
When Secondary function enabled, avoid potential contention, ensure that Primary GPIO) Tertiary functions disabled. When Tertiary function enabled, avoid potential contention, ensure that Primary GPIO), Secondary, other Tertiary functions disabled. states sampled power reset written into register fields. Terminal Functions section details. Device Configurations
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TMS320DM357 Digital Media System-on-Chip
SPRS553 NOVEMBER 2008 www.ti.com
Table 3-10. DM357 Multiplexed Peripheral Pins Multiplexing Controls (continued)
MULTIPLEXED PERIPHERALS SPI, GPIO PRIMARY (DEFAULT) FUNCTION GPIO: GPIO[37, 39:42] SECONDARY FUNCTION SPI: SPI_EN0, SPI_CLK, SPI_DI, SPI_DO, SPI_EN1 I2C: SCL, PWM0 VPBE: PWM1: RGB666/RGB888 PWM1 VPBE: PWM2: RGB666/RGB888 PWM2 CLK_OUT0 CLK_OUT1 EMIFA: EM_BA[1] EMIFA: EM_A[0] EMAC: (all pins, except CRS) EMAC: CRS, MDIO: MDIO, MDCLK TIMER0: TIM_IN HPI: HCNTL1 TERTIARY FUNCTION SECONDARY REGISTER/PIN CONTROL PinMux1:SPI TERTIARY REGISTER/PIN CONTROL
I2C, GPIO PWM0, GPIO PWM1, VPBE (RGB666/RGB888), GPIO PWM2, VPBE (RGB666/RGB888), GPIO ClockOut0, GPIO
GPIO: GPIO[43:44] GPIO:GPIO[45] GPIO:GPIO[46]
PinMux1:I2C PinMux1:PWM0 PinMux0:RGB666/ PinMux0:RGB888 PinMux0:RGB666/ PinMux0:RGB888 PinMux1:CLK0 PinMux1:CLK1 PinMux0:AEAW[4:0], Pins:DAEAW[4:0] PinMux0:AEAW[4:0], Pins:DAEAW[4:0] PinMux0:EMACEN PinMux1:TIM_IN PinMux0:HPIEN, Pins:BTSEL[1:0] PinMux1:PWM1
GPIO:GPIO[47]
PinMux1:PWM2
GPIO:GPIO[48]
ClockOut1, TIMER0, GPIO:GPIO[49] GPIO EMIFA, GPIO EMIFA, HPI, GPIO EMAC, GPIO3V GPIO:GPIO[52] GPIO:GPIO[53] GPIO: GPIO3V[0:13] GPIO: GPIO3V[14:16]
EMAC, MDIO, GPIO3V
PinMux0:EMACEN
UART2, VPFE
VPFE: UART2: CI[7:6]/ UART_RXD2, CCD_DATA[15:14] UART_TXD2 VPFE: UART2: CI[5:4]/ UART_CTS2, CCD_DATA[13:12] UART_RTS2
PinMux1:UART2
UART2, VPFE
PinMux1:UART2, PinMux1:U2FLO
3.5.3
Peripheral Selection After Device Reset
After device reset, PINMUX0 PINMUX1 registers software programmable allow multiplexing shared device pins between peripherals, given Terminal Functions section. Section 3.5.4, Section 3.5.5, Section 3.5.6 identify register settings necessary configure specific multiplexed functions show primary (default) function after reset.
3.5.4
PINMUX0 Register Description
PINMUX0 multiplexing register controls which peripheral given ownership over shared pins among EMAC, CCD, LCD, RGB888, RGB666, EMIFA, HPI, GPIO peripherals. register format shown Figure field descriptions given Table 3-11. More details PINMUX0 muxing fields given Section 3.5.6. value enables secondary tertiary function.
Device Configurations
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TMS320DM357 Digital Media System-on-Chip
Figure 3-5. PINMUX0 Register
EMACEN HPIEN CFLDEN LFLDEN LOEEN RGB888 RGB666 Reserved
R/W-0
R/W-0
R/W-D
R/W-0
AECS5
R/W-0
AECS4
R/W-0
R/W-0
R/W-0
R/W-0
R-0000
R/W-0
R/W-0
Reserved
AEAW
R/W-0
R/W-0
R/W-00
R/W-0
R/W-0
R-00000
R/W-LLLL
LEGEND: Read; Write; state latched reset rising edge; derived from states; value after reset proper DM357 device operation, always write value bits through
Table 3-11. PINMUX0 Register Description
Name EMACEN HPIEN Description Enable EMAC MDIO function default GPIO3V[0:16] pins. Enable module pins. Default value derived from BTSEL[1:0] configuration inputs. HPIEN when BTSEL[1:0] non-secure devices only. HPIEN default state always secure divices. Enable C_FIELD function default GPIO[4] Enable C_WE function default GPIO[1] Enable LCD_FIELD function default GPIO[3] Enable LCD_OE function default GPIO[0] Enable VPBE RGB888 function default GPIO[2:6, 46:47] pins Enable VPBE RGB666 function default GPIO[46:47] pins Enable EMIFA EM_CS5 function GPIO[8] Enable EMIFA EM_CS4 function GPIO[9] EMIFA address width selection. Default value latched reset from AEAW[4:0] configuration input pins. This enables EMIF address function default GPIO[10:28] pins.
CFLDEN LFLDEN LOEEN RGB888 RGB666 AECS5 AECS4 AEAW
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Device Configurations
TMS320DM357 Digital Media System-on-Chip
SPRS553 NOVEMBER 2008 www.ti.com
3.5.5
PINMUX1 Register Description
PINMUX1 multiplexing register controls which peripheral given ownership over shared pins among Timer, PLL, ASP, SPI, I2C, PWM, UART peripherals. register format shown Figure field descriptions given Table 3-12. More details PINMUX1 muxing fields given Section 3.5.6. value enables secondary tertiary function. Figure 3-6. PINMUX1 Register
Reserved
TIMIN
CLK1
CLK0
R-0000 0000 0000
Reserved
R/W-0
R/W-0
UART1
R/W-0
UART0
PWM2
PWM1
PWM0
U2FLO
UART2
R-0000
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: Read/Write; Read only; value after reset proper DM357 device operation, always write value
Table 3-12. PINMUX1 Register Description
Name TIMIN CLK1 CLK0 PWM2 PWM1 PWM0 U2FLO UART2 UART1 UART0 Description Enable TIM_IN function default GPIO[49] Enable CLK_OUT1 function default GPIO[49] Enable CLK_OUT0 function default GPIO[48] Enable function default GPIO[29:34] pins Enable function default GPIO[37,39:42] pins Enable function default GPIO[43:44] pins Enable PWM2 function default GPIO[47] Enable PWM1 function default GPIO[46] Enable PWM0 function default GPIO[45] Enable UART2 flow control function default VPFE CI[5:4]/CCD_DATA[13:12] pins Enable UART2 function default VPFE CI[7:6]/CCD_DATA[15:14] pins Enable UART1 function Enable UART0 function default GPIO[35:36] pins
Device Configurations
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TMS320DM357 Digital Media System-on-Chip
3.5.6
Multiplexing Register Field Details
fields various multiplexing options within PINMUX0 PINMUX1 registers described following sections.
3.5.6.1 EMAC GPIO3V Multiplexing EMAC functions selected shown Table 3-13. functionality each individual pins affec
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