TMS320C6421 Fixed-Point Digital Signal Processor High-Performance

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TMS320C6421 Fixed-Point Digital Signal Processor
TMS320C6421 Fixed-Point Digital Signal Processor
High-Performance Digital Signal Processor (C6421) 2.5-, 2.-, 1.67-,1.43- Instruction Cycle Time 400-, 500-, 600-, 700-MHz C64x+Clock Rate Eight 32-Bit C64x+ Instructions/Cycle 3200, 4000, 4800, 5600 MIPS Fully Software-Compatible With C64x Commercial Automotive suffix) Grades Low-Power Device suffix) VelociTI.2Extensions VelociTIAdvanced Very-Long-Instruction-Word (VLIW) TMS320C64x+DSP Core Eight Highly Independent Functional Units With VelociTI.2 Extensions: ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, Quad 8-Bit Arithmetic Clock Cycle Multipliers Support Four 16-Bit Multiplies (32-Bit Results) Clock Cycle Eight 8-Bit Multiplies (16-Bit Results) Clock Cycle Load-Store Architecture With Non-Aligned Support 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size Instructions Conditional Additional C64x+Enhancements Protected Mode Operation Exceptions Support Error Detection Program Redirection Hardware Support Modulo Loop Auto-Focus Module Operation C64x+ Instruction Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation, Bit-Counting VelociTI.2 Increased Orthogonality C64x+ Extensions Compact 16-bit Instructions Additional Instructions Support Complex Multiplies
C64x+ L1/L2 Memory Architecture 128K-Bit (16K-Byte) Program RAM/Cache [Flexible Allocation] 384K-Bit (48K-Byte) Data RAM/Cache [Flexible Allocation] 512K-Bit (64K-Byte) Unified Mapped RAM/Cache [Flexible Allocation] Endianess: Supports Both Little Endian Endian External Memory Interfaces (EMIFs) 16-Bit DDR2 SDRAM Memory Controller With 128M-Byte Address Space (1.8-V I/O) Supports 266-MHz (data rate) interfaces DDR2-400 SDRAM Asynchronous 8-Bit-Wide EMIF (EMIFA) With 64M-Byte Address Reach Flash Memory Interfaces (8-Bit-Wide Data) NAND (8-Bit-Wide Data) Enhanced Direct-Memory-Access (EDMA) Controller Independent Channels) 64-Bit General-Purpose Timers (Each Configurable 32-Bit Timers) 64-Bit Watch Timer UART With Flow Control Master/Slave Inter-Integrated Circuit (I2C BusTM) Multichannel Buffered Serial Port (McBSP0) AC97 Audio Codec Interface Standard Voice Codec Interface (AIC12) Telecom Interfaces ST-Bus, H-100 Channel Mode Multichannel Audio Serial Port (McASP0) Four Serializers SPDIF (DIT) Mode 16-Bit Host-Port Interface (HPI) 10/100 Mb/s Ethernet (EMAC) IEEE 802.3 Compliant Supports Multiple Media Independent Interfaces (MII, RMII) Management Data (MDIO) Module
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this document. trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2007-2008, Texas Instruments Incorporated
TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
VLYNQInterface (FPGA Interface) Three Pulse Width Modulator (PWM) Outputs On-Chip Bootloader Individual Power-Savings Modes Flexible Clock Generators IEEE-1149.1 (JTAGTM) Boundary-Scan-Compatible General-Purpose (GPIO) Pins (Multiplexed With Other Device Functions)
Packages: 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch 376-Pin Plastic Package (ZDU Suffix), 1.0-mm Ball Pitch 0.09-µm/6-Level Metal Process (CMOS) 3.3-V 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-Q6/-Q5/-Q4) 3.3-V 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5) Applications: Telecom Audio Industrial Applications
Description
TMS320C64x+DSPs (including TMS320C6421 device) highest-performance fixed-point generation TMS320C6000DSP platform. C6421 device based third-generation high-performance, advanced (VLIW) architecture developed Texas Instruments (TI), making these DSPs excellent choice digital signal processor applications. C64x+devices upward code-compatible from previous devices that part C6000DSP platform. C64xDSPs support added functionality have expanded instruction from previous devices. reference C64x C64x also applies, unless otherwise noted, C64x+ C64x+ CPU, respectively. With performance 5600 million instructions second (MIPS) clock rate MHz, C64x+ core offers solutions high-performance programming challenges. core possesses operational flexibility high-speed controllers numerical capability array processors. C64x+ core processor general-purpose registers 32-bit word length eight highly independent functional units-two multipliers 32-bit result arithmetic logic units (ALUs). eight functional units include instructions accelerate performance telecom, audio, industrial applications. core produce four 16-bit multiply-accumulates (MACs) cycle total 2800 million MACs second (MMACS), eight 8-bit MACs cycle total 5600 MMACS. more details C64x+ DSP, TMS320C64x/C64x+ Instruction Reference Guide (literature number SPRU732). C6421 also application-specific hardware logic, on-chip memory, additional on-chip peripherals similar other C6000 platform devices. C6421 core uses two-level cache-based architecture. Level program memory/cache (L1P) consists 128K-bit memory space that configured mapped memory direct mapped cache, Level data (L1D) consists 384K-bit memory space that configured mapped memory 2-way set-associative cache. Level memory/cache (L2) consists 512K-bit memory space that shared between program data space. memory configured mapped memory, cache, combinations two.
TMS320C6421 Fixed-Point Digital Signal Processor
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TMS320C6421 Fixed-Point Digital Signal Processor
peripheral includes: 10/100 Mb/s Ethernet (EMAC) with management data input/output (MDIO) module; 4-bit transmit, 4-bit receive VLYNQ interface; inter-integrated circuit (I2C) interface; multichannel buffered serial port (McBSP0); multichannel audio serial port (McASP0) with serializers; 64-bit general-purpose timers each configurable independent 32-bit timers; 64-bit watchdog timer; user-configurable 16-bit host-port interface (HPI); 111-pins general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; UART with hardware handshaking support; pulse width modulator (PWM) peripherals; glueless external memory interfaces: asynchronous external memory interface (EMIFA) slower memories/peripherals, higher speed synchronous memory interface DDR2. Ethernet Media Access Controller (EMAC) provides efficient interface between C6421 network. C6421 EMAC supports 10Base-T 100Base-TX Mbits/second (Mbps) Mbps either half- full-duplex mode, with hardware flow control quality service (QOS) support. Management Data Input/Output (MDIO) module continuously polls MDIO addresses order enumerate devices system. VLYNQ ports allow C6421 easily control peripheral devices and/or communicate with host processors. rich peripheral provides ability control external peripheral devices communicate with external processors. details each peripherals, related sections later this document associated peripheral reference guides. C6421 complete development tools. These include compilers, assembly optimizer simplify programming scheduling, Windowsdebugger interface visibility into source code execution.
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TMS320C6421 Fixed-Point Digital Signal Processor
TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
Functional Block Diagram
Figure shows functional block diagram C6421 device.
JTAG Interface System Control Input Clock(s) C64x+DSP PLLs/Clock Generator Power/Sleep Controller Multiplexing Data
Boot
Switched Central Resource (SCR)
Peripherals Serial Interfaces System
McASP
McBSP
UART
GeneralPurpose Timer
Watchdog Timer
GPIO
EDMA Program/Data Storage
Connectivity EMAC With MDIO
VLYNQ
DDR2 Ctlr (16b)
Async EMIF/ NAND/ (8b)
Figure 1-1. TMS320C6421 Functional Block Diagram
TMS320C6421 Fixed-Point Digital Signal Processor
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TMS320C6421 Fixed-Point Digital Signal Processor
Contents
TMS320C6421 Fixed-Point Digital Signal Processor.
Features Description Functional Block Diagram Ranges Supply Voltage Operating Temperature (Unless Otherwise Noted)
Peripheral Information Electrical Specifications
6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 Parameter Information Recommended Clock Control Signal Transition Behavior. Power Supplies Enhanced Direct Memory Access (EDMA3) Controller Reset External Clock Input From MXI/CLKIN
Revision History Device Overview
Device Characteristics C64x+ Megamodule
Terminal Functions Device Support
Memory Summary Assignments
Clock PLLs Interrupts External Memory Interface (EMIF) Universal Asynchronous Receiver/Transmitter (UART) Inter-Integrated Circuit (I2C) Host-Port Interface (HPI) Peripheral Multichannel Buffered Serial Port (McBSP). Multichannel Audio Serial Port (McASP0) Peripheral Ethernet Media Access Controller (EMAC) Management Data Input/Output (MDIO)
Device Development-Support Tool Nomenclature Documentation Support System Module Registers Power Considerations Clock Considerations Boot Sequence Configurations Reset Configurations After Reset Multiplexed Configurations Device Initialization Sequence After Reset Debugging Considerations System Interconnect Block Diagram
Device Configurations.
Timers Pulse Width Modulator (PWM). VLYNQ General-Purpose Input/Output (GPIO). IEEE 1149.1 JTAG Thermal Data
System Interconnect
Device Operating Conditions.
Absolute Maximum Ratings Over Operating Temperature Range (Unless Otherwise Noted) Recommended Operating Conditions Electrical Characteristics Over Recommended
Mechanical Data.
7.1.1 Thermal Data 7.1.2 Packaging Information.
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Contents
TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
Revision History
NOTE: Page numbers previous revisions differ from page numbers current version.
This data manual revision history highlights technical changes made SPRS346C device-specific data manual make SPRS346D revision. Scope: Applicable updates TMS320C642x, specifically relating TMS320C6421 device, have been incorporated. Added 700-MHz C64x+device speed. Added designators low-power (-L) devices.
Section Section
Added "5600 MIPS" "High-Performance Digital Signal Processor (C6421)" bullet first paragraph, updated/changed following: First sentence from "With performance 4800 million instructions second (MIPS) clock rate MHz." "With performance 5600 million instructions second (MIPS) with clock rate MHz." Fifth sentence from "The core produce.for total 2400 million MACs second.or total 4800 MMACS."to "The core produce.for total 2800 million MACs second.or total 5600 MMACS."
Section Section
Updated/Changed Figure 2-12, Device Nomenclature, reflect device speeds low-power designator suffix). Table 2-20, Multichannel Audio Serial Port (McASP0) Terminal Functions: Updated/Changed AFSR0/DR0/GP[100] description from frame synchronization AFSX0." ".frame synchronization AFSR0." Updated/Changed AFSX0/DX1/GP[107] description from ".frame synchronization AFSR0." ".frame synchronization AFSX0." Table 2-25, Standalone GPIO Terminal Functions: Added "Note: GP[xx] only available when GP[36] through GP[43]. Table 3-19, Multiplexed Pins C6421: Added "Note: GP[43:36] only available when GP[36] through GP[43]. Updated/Changed ICDD IDDD test conditions footnote Section 5.3, Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Temperature (Unless Otherwise Noted). Deleted "Future variants." footnote from table Table 6-15, PLLC1 Clock Frequency Ranges: Updated/Changed PLLOUT 1.2V-CVDD value from "700 MHz" "600 MHz" -6/-5/-4/-Q6/-Q5/-Q4 devices. Updated/Changed SYSCLK1 1.05V-CVDD value from "560 MHz" "520 MHz" devices. Updated/Changed sentence from requires filter manufacturer Murata." recommends filter manufacturer Murata." Deleted "(-4, -4Q, -4S, -5Q, -5S, -6)" from Table 6-19 title, Timing Requirements MXI/CLKIN.
Section Section 3.7.3.1 Section Section Section 6.7.1
Section 6.7.1 Section 6.7.4
Revision History
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TMS320C6421 Fixed-Point Digital Signal Processor
Device Overview
Device Characteristics
Table 2-1, provides overview TMS320C6421 DSP. tables show significant features C6421 device, including capacity on-chip RAM, peripherals, frequency, package type with count. Table 2-1. Characteristics C6421 Processor
HARDWARE FEATURES DDR2 Memory Controller Asynchronous EMIF [EMIFA] EDMA3 Timers Peripherals peripherals pins available same time (For more detail, Device Configuration section). UART McBSP McASP 10/100 Ethernet (EMAC) with Management Data Input/Output (MDIO) VLYNQ General-Purpose Input/Output Port (GPIO) (16-bit) Size (Bytes) On-Chip Memory Organization Revision Register (MM_REVID.[15:0]) (address location: 0x0181 2000) Control Status Register (CSR.[31:16]) JTAGID register (address location: 0x01C4 0028) C6421 (16-bit width) [1.8 I/O] Asynchronous (8-bit width), RAM, Flash, (8-bit 8-bit NAND) independent channels, QDMA channels) 64-bit General Purpose (configurable 64-bit 32-bit) 64-bit Watch with flow control (Master/Slave) serailizers) pins outputs 96KB RAM, 64KB 16K-Byte (16KB) Program (L1P) RAM/Cache 48KB Data (L1D) RAM/Cache 64KB Unified Mapped RAM/Cache (L2) 64KB Boot theTMS320C6424/21 Digital Signal Processor (DSP) [Silicon Revisions 1.0] Silicon Errata (literature number SPRZ252). Section 6.21.1, JTAG Peripheral Register Description(s) JTAG Register (-7, CVDD 1.2V) (-6/-Q6, CVDD 1.2V) (-5/-Q5, CVDD 1.2V) (-4/-Q4, CVDD 1.2V) (-L, CVDD 1.05V) 1.43 (-7, CVDD 1.2V) 1.67 (-6/-Q6, CVDD 1.2V) (-5/-Q5, CVDD 1.2V) (-4/-Q4, CVDD 1.2V) (-L, CVDD 1.05V) (-7/ -6/-5/ -4/-Q6/-Q5/-Q4) 1.05 (-7/-6/-5/-4/-L/-Q5) (Bypass),
Megamodule JTAG BSDL_ID
Frequency
Cycle Time
Voltage
Core
Options MXI/CLKIN frequency multiplier (15-30 reference)
Applies "tape reel" part number counterparts well. more information, Section 2.7, Device Development-Support Tool Nomenclature. Device Overview
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TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
Table 2-1. Characteristics C6421 Processor (continued)
HARDWARE FEATURES Package(s) Process Technology Product Status
C6421 361-Pin (ZWT) 376-Pin (ZDU) 0.09
pitch pitch Product Preview (PP), Advance Information (AI), Production Data (PD)
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
C64x+ Megamodule 2.2.1 C64x+ Memory Architecture
C64x+ Megamodule implements two-level internal cache-based memory architecture with external memory support. Level Program memory/cache (L1P) consists memory space that configured mapped memory direct mapped cache. Level Data memory/cache (L1D) consists memory space which configured mapped memory 2-way associated cache. Level memory/cache (L2) consists memory space that shared between program data space. memory configured mapped memory, cache, combination both. Table shows memory C64x+ cache register device. Figure 2-1, shows diagram C64x+ Cache Memory Architecture. Table 2-2. C64x+ Cache Registers
ADDRESS RANGE 0x0184 0000 0x0184 0020 0x0184 0024 0x0184 0040 0x0184 0044 0x0184 0048 0x0184 0FFC 0x0184 1000 0x0184 1004 0x0184 1FFC 0x0184 2000 0x0184 2004 0x0184 2008 0x0184 200C 0x0184 2010 0x0184 3FFF 0x0184 4000 0x0184 4004 0x0184 4010 0x0184 4014 0x0184 4018 0x0184 401C 0x0184 4020 0x0184 4024 0x0184 4030 0x0184 4034 0x0184 4038 Device Overview REGISTER ACRONYM L2CFG L1PCFG L1PCC L1DCFG L1DCC EDMAWEIGHT L2ALLOC0 L2ALLOC1 L2ALLOC2 L2ALLOC3 L2WBAR L2WWC L2WIBAR L2WIWC L2IBAR L2IWC L1PIBAR L1PIWC L1DWIBAR L1DWIWC DESCRIPTION Cache configuration register Size Cache configuration register (see Section 2.2.1.1, Configuration Register (L1PCFG) Description) Freeze Mode Cache configuration register Size Cache configuration register (see Section 2.2.1.2, Configuration Register (L1DCFG) Description) Freeze Mode Cache configuration register Reserved EDMA access control register Reserved allocation register allocation register allocation register allocation register Reserved writeback base address register writeback word count register writeback invalidate base address register writeback invalidate word count register invalidate base address register invalidate word count register invalidate base address register invalidate word count register writeback invalidate base address register writeback invalidate word count register Reserved Submit Documentation Feedback
TMS320C6421 Fixed-Point Digital Signal Processor
Table 2-2. C64x+ Cache Registers (continued)
ADDRESS RANGE 0x0184 4040 0x0184 4044 0x0184 4048 0x0184 404C 0x0184 4050 0x0184 4FFF 0x0184 5000 0x0184 5004 0x0184 5008 0x0184 500C 0x0184 5027 0x0184 5028 0x0184 502C 0x0184 5039 0x0184 5040 0x0184 5044 0x0184 5048 0x0184 8000 0x0184 80BC 0x0184 8100 0x0184 8104 0x0184 8108 0x0184 8124 0x0184 8128 0x0184 812C 0x0184 8130 0x0184 813C 0x0184 8140- 0x0184 81FC 0x0184 8200 0x0184 823C 0x0184 8240 0x0184 83FC REGISTER ACRONYM L1DWBAR L1DWWC L1DIBAR L1DIWC L2WB L2WBINV L2INV L1PINV L1DWB L1DWBINV L1DINV MAR0 MAR47 MAR64 MAR65 MAR66 MAR73 MAR74 MAR75 MAR76 MAR79 MAR80 MAR127 MAR128 MAR143 MAR144 MAR255 Block Writeback Block Writeback invalidate base address register invalidate word count register Reserved writeback register writeback invalidate register Global Invalidate without writeback Reserved Global Invalidate Reserved Global Writeback Global Writeback with Invalidate Global Invalidate without writeback Reserved (corresponds byte address 0x0000 0000 0x2FFF FFFF) Reserved (corresponds byte address 0x4000 0000 0x41FF FFFF) Memory Attribute Registers EMIFA (corresponds byte address 0x4200 0000 0x49FF FFFF) Reserved (corresponds byte address 0x4A00 0000 0x4BFF FFFF) Memory Attribute Registers VLYNQ 0x4C00 0000 0x4FFF FFFF Reserved (corresponds byte address 0x5000 0000 0x7FFF FFFF) Memory Attribute Registers DDR2 (corresponds byte address 0x8000 0000 0x8FFF FFFF) Reserved (corresponds byte address 0x9000 0000 0xFFFF FFFF) DESCRIPTION
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Device Overview
TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
C64x+ Fetch Path Data Path
SRAM Program
Cache
SRAM Data
Cache
Write Buffer
SRAM
Cache
Unified Data/Program Memory
External Memory
Legend: Addressable Memory Cache Memory Data Paths Managed Cache Controller
Figure 2-1. C64x+ Cache Memory Architecture
Device Overview
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TMS320C6421 Fixed-Point Digital Signal Processor
divided into regions-denoted Region Region This architecture C6421: Region 0-KByte Memory Region 16-KByte Memory Region configured mapped memory cache wait state latency. This region shown "L1P RAM/Cache" Table 2-5, Memory Summary. C6421 does support memory protection L1P.
divided into regions-denoted Region Region This architecture C6421: Region 16-KByte Memory This region shown "L1D RAM" Table 2-5, Memory Summary. Region 32-KByte Memory Region configured mapped memory cache. This region shown "L1D RAM/Cache" Table 2-5, Memory Summary. C6421 does support memory protection L1D.
memory implements separate memory ports. This architecture C6421: Port This port shown RAM/Cache" Table 2-5, Memory Summary. Banking Scheme: 128-bit banks Latency: cycle wait state) Port This port shown "Boot ROM" Table 2-5, Memory Summary. Banking Scheme: 256-bit bank Latency: cycle wait state) C6421 does support memory protection
more detailed information about C64x+ Cache Memory Architecture, TMS320C64x+ Cache User's Guide (literature number SPRU862) TMS320C64x+ Megamodule Reference Guide (literature number SPRU871). 2.2.1.1 Configuration Register (L1PCFG) Description Configuration Register (L1PCFG) controls/defines size cache. C6421, L1PCFG register device-specific varies from what shown TMS320C64x+ Megamodule Reference Guide (literature number SPRU871). format field descriptions L1PCFG register C6421 shown Figure Table 2-3, respectively.
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Device Overview
TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008
RESERVED R-0000 0000 0000 0000
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RESERVED 0000 0000 0000
L1PMODE R/W-111 (7h)
LEGEND: Read/Write; Read only; value after reset.
Figure 2-2. L1PCFG Register
Table 2-3. L1PCFG Register Descriptions
31:3 Field Name RESERVED Reserved. Read-only, writes have effect. L1PMODE select. L1PMODE [0h] [1h] [2h] [3h] [4h] Cache Disabled 16KB [7h] Reserved. Use. Description
proper C6421 device operation, only settings [0h] through [3h] valid. intialize RAM/Cache valid cache setting, user must follow sequence outlined Section 3.8, Device Initialization Sequence After Reset. more details, TMS320C6424/21 Digital Signal Processor (DSP) Silicon Errata [Silicon Revisions 1.0] (literature number SPRZ252).
2.2.1.2 Configuration Register (L1DCFG) Description Configuration Register (L1DCFG) controls/defines size cache. format field descriptions L1DCFG register C6421 shown Figure Table 2-4, respectively.
RESERVED R-0000 0000 0000 0000
RESERVED 0000 0000 0000
L1DMODE R/W-111 (7h)
LEGEND: Read/Write; Read only; value after reset.
Figure 2-3. L1DCFG Register
Device Overview
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TMS320C6421 Fixed-Point Digital Signal Processor
Table 2-4. L1DCFG Register Descriptions
31:3 Field Name RESERVED Reserved. Read-only, writes have effect. L1DMODE select. [0h] [1h] [2h] [3h] [4h] [5h] [6h] [7h] Cache Disabled 16KB 32KB 32KB 32KB 32KB [default] Description
L1DMODE
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TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
Memory Summary
Table shows memory address ranges device. Table depicts expanded Configuration Space (0x0180 0000 through 0x0FFF FFFF). device multiple on-chip memories associated with processors various subsystems. help simplify software development unified memory used where possible maintain consistent view device resources across masters. Table 2-5. Memory Summary
START ADDRESS 0x0000 0000 0x0010 0000 0x0011 0000 0x0080 0000 0x0081 0000 0x0082 0000 0x00E0 8000 0x00E0 C000 0x00E1 0000 0x00F0 4000 0x00F0 C000 0x00F1 0000 0x00F1 8000 0x0180 0000 0x01C0 0000 0x0200 0000 0x1010 0000 0x1011 0000 0x1080 0000 0x1081 0000 0x1082 0000 0x10E0 8000 0x10E0 C000 0x10E1 0000 0x10F0 C000 0x10F1 0000 0x10F1 8000 0x2000 0000 0x2000 8000 0x4200 0000 0x4300 0000 0x4400 0000 0x4500 0000 0x4600 0000 0x4700 0000 0x4800 0000 0x4900 0000 0x4C00 0000 0x5000 0000 0x8000 0000 0x9000 0000 ADDRESS 0x000F FFFF 0x0010 FFFF 0x007F FFFF 0x0080 FFFF 0x0081 FFFF 0x00E0 7FFF 0x00E0 BFFF 0x00E0 FFFF 0x00F0 3FFF 0x00F0 BFFF 0x00F0 FFFF 0x00F1 7FFF 0x017F FFFF 0x01BF FFFF 0x01FF FFFF 0x100F FFFF 0x1010 FFFF 0x107F FFFF 0x1080 FFFF 0x1081 FFFF 0x10E0 7FFF 0x10E0 BFFF 0x10E0 FFFF 0x10F0 BFFF 0x10F0 FFFF 0x10F1 7FFF 0x1FFF FFFF 0x2000 7FFF 0x41FF FFFF 0x42FF FFFF 0x43FF FFFF 0x44FF FFFF 0x45FF FFFF 0x46FF FFFF 0x47FF FFFF 0x48FF FFFF 0x4BFF FFFF 0x4FFF FFFF 0x7FFF FFFF 0x8FFF FFFF 0xFFFF FFFF 7M-64K 6048K 976K 9120K 225M 7M-48K 6048K 1M-16K 241M-96K 544M-32K 768M 256M 1792M SIZE (Bytes) Reserved Boot Reserved Reserved RAM/Cache Reserved Reserved RAM/Cache Reserved Reserved RAM/Cache Reserved Space Peripherals Reserved Boot Reserved Reserved RAM/Cache Reserved Reserved RAM/Cache Reserved RAM/Cache Reserved DDR2 Control Regs Reserved EMIFA Data (CS2) Reserved EMIFA Data (CS3) Reserved EMIFA Data (CS4) Reserved EMIFA Data (CS5) Reserved VLYNQ (Remote Data) Reserved DDR2 Memory Controller Reserved Reserved RAM/Cache Reserved Reserved RAM/Cache Reserved RAM/Cache Reserved DDR2 Control Regs Reserved EMIFA Data (CS2) Reserved EMIFA Data (CS3) Reserved EMIFA Data (CS4) Reserved EMIFA Data (CS5) Reserved VLYNQ (Remote Data) Reserved DDR2 Memory Controller Reserved Reserved Peripherals Reserved C64x+ MEMORY EDMA PERIPHERAL MEMORY
C6421, RAM/Cache defaults (L2CFG.L2MODE intialize RAM/Cache valid cache setting, user must follow sequence outlined Section 3.8, Device Initialization Sequence After Reset. EMIFA functionally supported C6421 device, therefore, pinned out.
Device Overview
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Table 2-6. Configuration Memory Summary
START ADDRESS 0x0180 0000 0x0181 0000 0x0181 1000 0x0181 2000 0x0182 0000 0x0183 0000 0x0184 0000 0x0185 0000 0x0188 0000 0x01BC 0000 0x01BC 0100 0x01BC 0400 0x01C0 0000 0x01C1 0000 0x01C1 0400 0x01C1 0800 0x01C1 0C00 0x01C2 0000 0x01C2 0400 0x01C2 1000 0x01C2 1400 0x01C2 1800 0x01C2 1C00 0x01C2 2000 0x01C2 2400 0x01C2 2800 0x01C2 2C00 0x01C4 0000 0x01C4 0800 0x01C4 0C00 0x01C4 1000 0x01C4 2000 0x01C6 7000 0x01C6 7800 0x01C6 8000 0x01C8 0000 0x01C8 1000 0x01C8 2000 0x01C8 4000 0x01C8 4800 0x01D0 0000 0x01D0 0800 0x01D0 1000 0x01D0 1400 0x01D0 1800 0x01E0 0000 0x01E0 1000 0x01E0 2000 ADDRESS 0x0180 FFFF 0x0181 0FFF 0x0181 1FFF 0x0181 2FFF 0x0182 FFFF 0x0183 FFFF 0x0184 FFFF 0x0187 FFFF 0x01BB FFFF 0x01BC 00FF 0x01BC 01FF 0x01BF FFFF 0x01C0 FFFF 0x01C1 03FF 0x01C1 07FF 0x01C1 0BFF 0x01C1 FFFF 0x01C2 03FF 0x01C2 0FFF 0x01C2 13FF 0x01C2 17FF 0x01C2 1BFF 0x01C2 1FFF 0x01C2 23FF 0x01C2 27FF 0x01C2 2BFF 0x01C3 FFFF 0x01C4 07FF 0x01C4 0BFF 0x01C4 0FFF 0x01C4 1FFF 0x01C6 6FFF 0x01C6 77FF 0x01C6 7FFF 0x01C7 FFFF 0x01C8 0FFF 0x01C8 1FFF 0x01C8 3FFF 0x01C8 47FF 0x01CF FFFF 0x01D0 07FF 0x01D0 0FFF 0x01D0 13FF 0x01D0 17FF 0x01DF FFFF 0x01E0 0FFF 0x01E0 1FFF 0x0FFF FFFF SIZE (Bytes) 192K 3328K 255K 117K 148K 494K 1018K 226M-8K C64x+ C64x+ Interrupt Controller C64x+ Powerdown Controller C64x+ Security C64x+ Revision C64x+ Reserved C64x+ Memory System Reserved Reserved Reserved Manager Trace Reserved EDMA EDMA EDMA EDMA Reserved UART0 Reserved Timer0 Timer1 Timer2 (Watchdog) PWM0 PWM1 PWM2 Reserved System Module Controller Controller Power Sleep Controller Reserved GPIO Reserved EMAC Control Registers EMAC Control Module Registers EMAC Control Module MDIO Control Registers Reserved McBSP0 Reserved McASP0 Control McASP0 Data Reserved EMIFA Control VLYNQ Control Registers Reserved
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TMS320C6421 Fixed-Point Digital Signal Processor
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Assignments
Extensive multiplexing used accommodate largest number peripheral functions smallest possible package. multiplexing controlled using combination hardware configuration device reset software programmable register settings. more information muxing, Section 3.7, Multiplexed Configurations.
2.4.1
(Bottom View)
Figure through Figure show bottom view package assignments four quadrants Figure through Figure 2-11 show bottom view package assignments four quadrants
DDR_D[7]
DDR_D[9]
DDR_D[12]
DDR_D[14]
DDR_CLK
DDR_CLK
DDR_A[12]
DDR_A[11]
DVDDR2
DDR_D[4]
DDR_D[6]
DDR_D[8]
DDR_D[11]
DDR_D[13]
DDR_D[15]
DDR_CKE
DDR_BA[1]
DDR_A[8]
DDR_D[2]
DDR_D[3]
DDR_D[5]
DDR_DQS[0]
DDR_D[10]
DDR_DQS[1]
DDR_RAS
DDR_BA[0]
DDR_BA[2]
DDR_A[10]
DDR_D[0]
DDR_D[1]
RSV16
DDR_DQM[0]
DVDDR2
DDR_DQM[1]
DDR_CAS
DDR_WE
DDR_CS
DDR_ZN
TRST
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDD33
EMU0
DVDDR2
DVDDR2
DVDDR2
EMU1
RESETOUT
DVDD33
CVDD
CVDD
CLKOUT0/ PWM2/ GP[84]
RESET
DVDD33
CVDD
CVDD
UCTS0/ GP[87]
URXD0/ GP[85]
URTS0/ PWM0/ GP[88]
TINP1L/ GP[56]
RSV3
DVDD33
CVDD
CVDD
TINP0L/ GP[98]
UTXD0/ GP[86]
TOUT1L/ GP[55]
RSV2
CVDD
CVDD
Figure 2-4. [Quadrant
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TMS320C6421 Fixed-Point Digital Signal Processor
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DDR_A[6]
DDR_A[5]
DDR_A[0]
RSV24
RSV26
RSV29
RSV35
DVDDR2
DVDDR2
DDR_A[7]
DDR_A[4]
DDR_A[2]
RSV25
RSV27
RSV30
RSV32
RSV37
DDR_A[9]
DDR_A[3]
DDR_A[1]
RSV22
RSV28
RSV23
RSV33
RSV36
RSV38
DDR_ZP
DDR_VDDDLL DDR_VSSDLL
RSV20
DDR_VREF
RSV21
RSV31
RSV34
RSV39
DVDDR2
RSV5
DVDDR2
DVDDR2
DVDDR2
DVDDR2
RSV14
RSV11
RSV12
RSV8
RSV7
CVDD
RSV13
RSV15
RSV10
RSV9
RSV6
CVDD
CVDD
DVDD33
CVDD
DVDDR2
RSV4
PLLPWR18
CVDD
CVDD
DVDD33
DVDD33
MXI/ CLKIN
Figure 2-5. [Quadrant
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TMS320C6421 Fixed-Point Digital Signal Processor
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CVDD
DVDD33
DVDD33
CVDD
CVDD
RMTXEN/ GP[29]
RMTXD0/ GP[28]
RMTXD1/ GP[27]/ (LENDIAN)
DVDD33
DVDD33
DVDD33
GP[24]/ GP[25]/ GP[26]/ (BOOTMODE2) (BOOTMODE3) (FASTBOOT)
RMCRSDV/ GP[30]
DVDD33
DVDD33
GP[23]/ (BOOTMODE1)
EM_D[6]/ GP[20]
EM_D[7]/ GP[21]
GP[22]/ (BOOTMODE0)
RMRXD1/ EM_CS5/ GP[33]
RSV18
RSV19
EM_WE
EM_WAIT/ (RDY/BSY)
EM_D[3]/ GP[17]
EM_D[5]/ GP[19]
EM_D[4]/ GP[18]
RMRXD0/ EM_CS4/ GP[32]
EM_A[18]/ GP[46]
EM_A[21]/ GP[34]
EM_R/W/ GP[35]
GP[40]
EM_OE
EM_D[0]/ GP[14]
EM_D[2]/ GP[16]
EM_D[1]/ GP[15]
RMREFCLK/ GP[31]
EM_A[16]/ GP[48]
EM_A[20]/ GP[44]
GP[41]
GP[38]
GP[36]
EM_BA[1]/ GP[5]/ (AEM0)
EM_BA[0]/ GP[6]/ (AEM1)
EM_CS3/ GP[13]
EM_CS2/ GP[12]
EM_A[15]/ GP[49]
EM_A[19]/ GP[45]
GP[42]
GP[39]
GP[37]
EM_A[2]/ (CLE)/GP[8]/ (PLLMS0)
EM_A[0]/ GP[7]/ (AEM2)
EM_A[3]/ GP[11]
EM_A[17]/ GP[47]
GP[43]
GP[53]
GP[54]
RMRXER/ GP[52]
EM_A[1]/ (ALE)/GP[9]/ (PLLMS1)
EM_A[4]/ GP[10]/ (PLLMS2)
DVDD33
Figure 2-6. [Quadrant
Device Overview
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DVDD33
AHCLKR0/ CLKR0/ GP[101]
AXR0[1]/ DX0/ GP[104]
CLKS0/ TOUT0L/ GP[97]
DVDD33
CVDD
CVDD
ACLKR0/ CLKX0/ GP[99]
AXR0[0]/ GP[105]
AXR0[2]/ FSX0/ GP[103]
AFSR0/ DR0/ GP[100]
DVDD33
CVDD
CVDD
AHCLKX0/ GP[108]
AFSX0/ GP[107]
AMUTE0/ GP[110]
AXR0[3]/ FSR0/ GP[102]
DVDD33
DVDD33
DVDD33
ACLKX0/ GP[106]
AMUTEIN0/ GP[109]
GP[4]/ PWM1
DVDD33
DVDD33
DVDD33
GP[0]
GP[1]
GP[2]
GP[3]
RSV1
DVDD33
DVDD33
RSV17
HAS/ MDIO/ GP[83]
HRDY/ MRXD2/ GP[80]
HCNTL1/ MTXEN/ GP[75]
HD14/ MTXD0/ GP[72]
HD12/ MTXD2/ GP[70]
HD6/ HD1/ VLYNQ_TXD1/ VLYNQ_RXD0/ GP[64] GP[59]
EM_A[6]/ GP[95]
EM_A[9]/ GP[92]
EM_A[12]/ GP[89]
HCS/ MDCLK/ GP[81]
HINT/ MRXD3/ GP[82]
HDS2/ MRXD0/ GP[78]
HHWIL/ MRXDV/ GP[74]
HD11/ MTXD3/ GP[69]
HD9/ MCOL/ GP[67]
HD4/ VLYNQ_RXD3/ GP[62]
HD0/ VLYNQ_ SCRUN/ GP[58]
EM_A[7]/ GP[94]
EM_A[11]/ GP[90]
HDS1/ MRXD1/ GP[79]
HCNTL0/ MRXER/ GP[76]
HD13/ MTXD1/ GP[71]
HD10/ MCRS/ GP[68]
HD7/ HD3/ VLYNQ_TXD2/ VLYNQ_RXD2/ GP[65] GP[61]
EM_A[5]/ GP[96]
EM_A[8]/ GP[93]
EM_A[13]/ GP[51]
DVDD33
DVDD33
HR/W/ MRXCLK/ GP[77]
HD15/ MTXCLK/ GP[73]
HD8/ HD5/ VLYNQ_TXD3/ VLYNQ_TXD0/ GP[66] GP[63]
VLYNQ_ CLOCK/ GP[57]
HD2/ VLYNQ_RXD1/ GP[60]
EM_A[10]/ GP[91]
EM_A[14]/ GP[50]
Figure 2-7. [Quadrant
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TMS320C6421 Fixed-Point Digital Signal Processor
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DDR_D[6]
DDR_D[8]
DDR_D[12]
DDR_D[15]
DDR_CLK0
DDR_CLK0
DDR_BS[1]
DDR_BS[2]
DDR_A[10]
DVDDR2
DDR_D[3]
DDR_D[4]
DDR_DQS[0]
DDR_D[10]
DDR_D[13]
DDR_DQS[1]
DDR_CKE
DDR_BS[0]
DDR_A[12]
DDR_A[11]
DDR_D[0]
DDR_D[1]
DDR_D[5]
DDR_DQM[0]
DDR_D[11]
DDR_D[14]
DDR_DQM[1]
DDR_RAS
DDR_CAS
DDR_WE
DDR_CS
DDR_D[2]
RSV16
DDR_D[7]
DDR_D[9]
DVDDR2
DVDDR2
DVDDR2
DVDDR2
TRST
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
EMU0
EMU1
RESETOUT
DVDD33
CLKOUT0/ PWM2/ GP[84]
RESET
DVDD33
UCTS0/ GP[87]
TINP1L/ GP[56]
DVDD33
CVDD
CVDD
UTXD0/ GP[86]
TOUT1L/ GP[55]
DVDD33
CVDD
URXD0/ GP[85]
URTS0/ PWM0/ GP[88]
RSV3
CVDD
CVDD
Figure 2-8. [Quadrant
Device Overview
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DDR_A[7]
DDR_A[4]
DDR_A[1]
DDR_A[0]
RSV26
RSV29
RSV30
RSV33
RSV36
DVDDR2
DVDDR2
DDR_A[9]
DDR_A[6]
DDR_A[3]
RSV22
RSV24
RSV27
RSV23
RSV31
RSV34
RSV38
DDR_A[8]
DDR_A[5]
DDR_A[2]
RSV20
RSV25
RSV28
RSV21
RSV32
RSV35
RSV37
RSV39
DDR_ZN
DDR_ZP
DDR_VDDDLL
DDR_VSSDLL
RSV5
DVDDR2
DDR_VREF
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
RSV12
RSV7
RSV6
RSV11 RSV15 RSV8
RSV14
RSV13
RSV9
RSV10
CVDD
CVDD
DVDD33
RSV4
DVDD33
DVDD33
CVDD
DVDD33
PLLPWR18
MXI/ CLKIN
CVDD
DVDD33
DVDD33
Figure 2-9. [Quadrant
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TMS320C6421 Fixed-Point Digital Signal Processor
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RMTXD1/ GP[27]/ (LENDIAN)
CVDD
CVDD
GP[24]/
(BOOTMODE2)
DVDD33
CVDD
DVDD33
GP[26]/ GP[23]/ (FASTBOOT) (BOOTMODE1)
RMTXEN/ GP[29]
RMCRSDV/ GP[30]
CVDD
CVDD
DVDD33
GP[22]/
(BOOTMODE0)
RMTXD0/ GP[28]
RMRXD1/ EM_CS5/ GP[33]
DVDD33
EM_D[7]/ GP[21]
GP[25]/
(BOOTMODE3)
RMRXD0/ EM_CS4/ GP[32]
DVDD33
EM_D[1]/ GP[15]
EM_D[4]/ GP[18]
RMREFCLK/ GP[31]
DVDD33
EM_D[3]/ GP[17]
EM_D[6]/ GP[20]
EM_D[5]/ GP[19]
DVDD33
DVDD33
DVDD33
DVDD33
EM_BA[0]/ GP[6]/ (AEM1)
EM_D[0]/ GP[14]
EM_D[2]/ GP[16]
RSV17
RSV18
RSV19
DVDD33
DVDD33
EM_OE
EM_WAIT/ (RDY/BSY)
EM_A[3]/ GP[11]
EM_CS3/ GP[13]
EM_A[11]/ GP[90]
EM_A[15]/ GP[49]
EM_A[19]/ GP[45]
EM_A[20]/ GP[44]
EM_A[21]/ GP[34]
EM_R/W/ GP[35]
GP[40]
EM_WE
EM_BA[1]/ GP[5]/ (AEM0)
EM_A[0]/ GP[7]/ (AEM2)
EM_CS2/ GP[12]
EM_A[12]/ GP[89]
EM_A[16]/ GP[48]
EM_A[17]/ GP[47]
GP[42]
GP[41]
GP[38]
GP[37]
GP[36]
EM_A[1]/ (ALE)/GP[9]/ (PLLMS1)
EM_A[4]/ GP[10]/ (PLLMS2)
EM_A[13]/ GP[51]
EM_A[14]/ GP[50]
EM_A[18]/ GP[46]
GP[43]
GP[39]
GP[53]
GP[54]
RMRXER/ GP[52]
EM_A[2]/ (CLE)/GP[8]/ (PLLMS0)
DVDD33
Figure 2-10. [Quadrant
Device Overview
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TMS320C6421 Fixed-Point Digital Signal Processor
DVDD33
TINP0L/ GP[98]
CLKS0/ TOUT0L/ GP[97]
RSV2
DVDD33
CVDD
AHCLKR0/ CLKR0/ GP[101]
AXR0[1]/ DX0/ GP[104]
AFSR0/ DR0/ GP[100]
DVDD33
CVDD
ACLKR0/ CLKX0/ GP[99]
AXR0[2]/ FSX0/ GP[103]
AXR0[3]/ FSR0/ GP[102]
DVDD33
CVDD
CVDD
AHCLKX0/ GP[108]
AXR0[0]/ GP[105]
AMUTE0/ GP[110]
DVDD33
ACLKX0/ GP[106]
AFSX0/ GP[107]
AMUTEIN0/ GP[109]
DVDD33
GP[2]
GP[3]
GP[4]/ PWM1
DVDD33
GP[0]
GP[1]
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
HCS/ MDCLK/ GP[81]
HINT/ MRXD3/ GP[82]
HHWIL/ MRXDV/ GP[74]
RSV1
DVDD33
DVDD33
DVDD33
HAS/ MDIO/ GP[83]
HDS2/ MRXD0/ GP[78]
HRDY/ MRXD2/ GP[80]
HCNTL1/ MTXEN/ GP[75]
HD12/ MTXD2/ GP[70]
HD9/ MCOL/ GP[67]
HD6/
VLYNQ_TXD1/
HD4/
VLYNQ_RXD3
HD1/
VLYNQ_RXD0
GP[64]
GP[62]
GP[59]
EM_A[7]/ GP[94]
EM_A[9]/ GP[92]
DVDD33
HCNTL0/ MRXER/ GP[76]
HDS1/ MRXD1/ GP[79]
HD13/ MTXD1/ GP[71]
HD14/ MTXD0/ GP[72]
HD10/ MCRS/ GP[68]
HD7/
VLYNQ_TXD2/
HD3/
VLYNQ_RXD2/
GP[65]
GP[61]
HD0/ VLYNQ_ SCRUN/ GP[58]
EM_A[6]/ GP[95]
EM_A[10]/ GP[91]
DVDD33
HR/W/ MRXCLK/ GP[77]
HD15/ MTXCLK/ GP[73]
HD11/ MTXD3/ GP[69]
HD8/
VLYNQ_TXD3/
HD5/
VLYNQ_TXD0
GP[66]
GP[63]
VLYNQ_ CLOCK/ GP[57]
HD2/
VLYNQ_RXD1/
GP[60]
EM_A[5]/ GP[96]
EM_A[8]/ GP[93]
Figure 2-11. [Quadrant
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Terminal Functions
terminal functions tables (Table through Table 2-28) identify external signal names, associated (ball) numbers along with mechanical package designator, type, whether internal pullup pulldown resistors, functional description. more detailed information device configuration, peripheral selection, multiplexed/shared pin, debugging considerations, Device Configurations section this data manual. device boot configuration pins multiplexed configuration pins- meaning they multiplexed with functional pins. These pins function device boot configuration pins only during device reset. input states these pins sampled latched into BOOTCFG register when device reset deasserted (see Note below). After device reset deasserted, values these multiplexed pins longer have hold configuration. proper device operation, external pullup/pulldown resistors required these device boot configuration pins. Section 3.9.1, Pullup/Pulldown Resistors discusses situations where external pullup/pulldown resistors required. Note: Internal chip, device reset pins RESET logically AND'd together purpose latching device boot configuration pins. values device boot configuration pins latched into BOOTCFG register when logical RESET transitions from low-to-high. Table 2-7. BOOT Terminal Functions
SIGNAL NAME TYPE OTHER BOOT GP[25]/ (BOOTMODE3) GP[24]/ (BOOTMODE2) GP[23]/ (BOOTMODE1) GP[22]/ (BOOTMODE0) GP[26]/ (FASTBOOT) EM_A[4]/ GP[10]/ (PLLMS2) EM_A[1]/(ALE)/ GP[9]/ (PLLMS1) EM_A[2]/(CLE)/ GP[8]/ (PLLMS0) I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 Fast Boot Fast Boot Fast Boot I/O/Z DVDD33 Bootmode configuration bits. These bootmode functions along with FASTBOOT function determine what device bootmode configuration selected. C6421 device supports several types bootmodes along with FASTBOOT option; more details types/options, Section 3.4.1, Boot Modes. DESCRIPTION
I/O/Z
Fast Boot Multiplier Select (PLLMS) These pins select multiplier Fast Boot. more details, Section 3.5.1.2, Fast Boot Multiplier Select (PLLMS).
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-7. BOOT Terminal Functions (continued)
SIGNAL NAME EM_A[0]/ GP[7]/(AEM2) EM_BA[0]/ GP[6]/(AEM1) EM_BA[1]/ GP[5]/(AEM0) TYPE OTHER DVDD33 DVDD33 DVDD33 DESCRIPTION Selects EMIFA Pinout Mode C6421 supports following EMIFA Pinout Modes: AEM[2:0] 000, EMIFA AEM[2:0] 010, EMIFA (Async) Pinout Mode AEM[2:0] 101, EMIFA (NAND) Pinout Mode This signal doesn't actually affect EMIFA module. only affects EMIFA pinned out. proper C6421 device operation, this both routed 3-stated (not driven) during device reset, must pulled down external resistor. more detailed information pullup/pulldown resistors, Section 3.9.1, Pullup/Pulldown Resistors. Endian selection Endian Little Endian
I/O/Z I/O/Z
I/O/Z
RMTXD0/GP[28]
I/O/Z
DVDD33
RMTXD1/GP[27]/ (LENDIAN)
I/O/Z
DVDD33
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Table 2-8. Oscillator/PLL Terminal Functions
SIGNAL NAME TYPE OTHER OSCILLATOR, MXI/ CLKIN MXVDD MXVSS PLLPWR18 MXVDD MXVDD
DESCRIPTION
Crystal input oscillator (system oscillator, typically MHz). internal oscillator bypassed, this external oscillator clock input. Crystal output oscillator power supply oscillator. board, this connected same power supply DVDDR2. Ground oscillator power supply PLLs
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information external board connections, External Clock Input From MXI/CLKIN Pin. more information, Recommended Operating Conditions table.
Table 2-9. Clock Generator Terminal Functions
SIGNAL NAME TYPE OTHER CLOCK GENERATOR CLKOUT0/ PWM2/GP[84] DVDD33 This multiplexed between System Clock generator (PLL1), PWM2, GPIO. System Clock generator (PLL1), clock output CLKOUT0. This configurable toggling device input clock frequency (MXI/CLKIN frequency) other divided-down /32) clock outputs. DESCRIPTION
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-10. RESET JTAG Terminal Functions
SIGNAL NAME TYPE OTHER RESET RESET RESETOUT DVDD33 DVDD33 DVDD33 JTAG TRST EMU1 EMU0 I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 JTAG test-port mode select input proper device operation, oppose this pin. JTAG test-port data output JTAG test-port data input JTAG test-port clock input JTAG test-port reset. IEEE 1149.1 JTAG compatibility, IEEE 1149.1 JTAG compatibility statement portion this data sheet Emulation Emulation Device reset Reset output status pin. RESETOUT indicates when device reset. Power-on reset. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-11. EMIFA Terminal Functions (Boot Configuration)
SIGNAL NAME TYPE OTHER EMIFA: BOOT CONFIGURATION EM_BA[1]/ GP[5]/(AEM0) EM_BA[0]/ GP[6]/(AEM1) EM_A[0]/ GP[7]/(AEM2) I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 These pins multiplexed between EMIFA, GPIO. When RESET asserted, these pins function EMIFA configuration pins. reset, input states AEM[2:0] sampled EMIFA Pinout Mode. more details, Section 3.5.1, Configurations Reset. After reset, these pins function EMIFA GPIO functions based selection. more details functions, Section 3.5.1.1, EMIFA Pinout Mode (AEM[2:0]). DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal.
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Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 010)
SIGNAL NAME TYPE OTHER DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit ASYNC/NOR (EMIFA Pinout Mode AEM[2:0] 010) Actual functions determined PINMUX0 PINMUX1 register settings (e.g., AEM[2:0], etc.). more details, Section 3.7, Multiplexed Configurations. This multiplexed between EMIFA, GPIO. EMIFA, this Chip Select output EM_CS2 with asynchronous memories (i.e., flash). This chip select default boot boot modes. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between EMIFA, GPIO. EMIFA, this Chip Select output EM_CS3 with asynchronous memories (i.e., flash). Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between EMAC (RMII), EMIFA, GPIO. RMRXD0/ EM_CS4/ GP[32] EMIFA, Chip Select output EM_CS4 with asynchronous memories (i.e., flash). Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between EMAC (RMII), EMIFA, GPIO. RMRXD1/ EM_CS5/ GP[33] EMIFA, Chip Select output EM_CS5 with asynchronous memories (i.e., flash). Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between EMIFA GPIO. EMIFA, read/write output EM_R/W. EMIFA (ASYNC/NOR), this wait state extension input EM_WAIT. EMIFA, output enable output EM_OE. EMIFA, write enable output EM_WE. This multiplexed between EMIFA GPIO. EM_BA[0]/ GP[6]/(AEM1) I/O/Z DVDD33 EMIFA, this Bank Address output (EM_BA[0]). When connected 8-bit asynchronous memory, this lowest order byte address. This multiplexed between EMIFA GPIO. EM_BA[1]/ GP[5]/(AEM0) I/O/Z DVDD33 EMIFA, this Bank Address output EM_BA[1]. When connected 8-bit asynchronous memory, this address.
EM_CS2/ GP[12]
I/O/Z
DVDD33
EM_CS3/ GP[13]
I/O/Z
DVDD33
I/O/Z
DVDD33
I/O/Z
DVDD33
EM_R/W/ GP[35] EM_WAIT/ (RDY/BSY) EM_OE EM_WE
I/O/Z I/O/Z I/O/Z I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview
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Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 010) (continued)
SIGNAL NAME TYPE OTHER DESCRIPTION This multiplexed between EMIFA GPIO. EM_A[21]/GP[34] I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 EMIFA (AEM[2:0] 010), this address output EM_A[21]. This multiplexed between EMIFA GPIO. EM_A[20]/GP[44] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[20]. This multiplexed between EMIFA GPIO. EM_A[19]/GP[45] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[19]. This multiplexed between EMIFA GPIO. EM_A[18]/GP[46] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[18]. This multiplexed between EMIFA GPIO. EM_A[17]/GP[47] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[17]. This multiplexed between EMIFA GPIO. EM_A[16]/GP[48] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[16]. This multiplexed between EMIFA GPIO. EM_A[15]/GP[49] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[15]. This multiplexed between EMIFA GPIO. EM_A[14]/GP[50] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[14]. This multiplexed between EMIFA GPIO. EM_A[13]/GP[51] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[13]. This multiplexed between EMIFA GPIO. EM_A[12]/GP[89] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[12]. This multiplexed between EMIFA GPIO. EM_A[11]/GP[90] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[11]. This multiplexed between EMIFA GPIO. EM_A[10]/GP[91] I/O/Z EMIFA (AEM[2:0] 010), this address output EM_A[10]. This multiplexed between EMIFA GPIO. EMIFA (AEM[2:0] 010), this address output EM_A[9]. This multiplexed between EMIFA GPIO. EMIFA (AEM[2:0] 010), this address output EM_A[8]. This multiplexed between EMIFA GPIO. EMIFA (AEM[2:0] 010), this address output EM_A[7]. This multiplexed between EMIFA GPIO. EMIFA (AEM[2:0] 010), this address output EM_A[6]. This multiplexed between EMIFA GPIO. EMIFA (AEM[2:0] 010), this address output EM_A[5].
EM_A[9]/GP[92]
I/O/Z
EM_A[8]/GP[93]
I/O/Z
EM_A[7]/GP[94]
I/O/Z
EM_A[6]/GP[95]
I/O/Z
EM_A[5]/GP[96]
I/O/Z
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Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 010) (continued)
SIGNAL NAME EM_A[4]/ GP[10]/(PLLMS2) EM_A[3]/ GP[11] EM_A[2]/(CLE)/ GP[8]/(PLLMS0) EM_A[1]/(ALE)/ GP[9]/(PLLMS1) TYPE OTHER DVDD33 DVDD33 DVDD33 DVDD33 DESCRIPTION This multiplexed between EMIFA GPIO. EMIFA (AEM[2:0] 010), this address output EM_A[4]. This multiplexed between EMIFA GPIO. EMIFA (AEM[2:0] 010), this address output EM_A[3]. This multiplexed between EMIFA GPIO. EMIFA (AEM[2:0] 010), this address output EM_A[2]. This multiplexed between EMIFA GPIO. EMIFA (AEM[2:0] 010), this address output EM_A[1]. This multiplexed between EMIFA GPIO. EM_A[0]/ GP[7]/(AEM2) I/O/Z DVDD33 EMIFA (AEM[2:0] 010), this Address output EM_A[0], which least significant 32-bit word address. 8-bit asynchronous memory, this address.
I/O/Z
I/O/Z
I/O/Z
I/O/Z
EM_D0/ GP[14] EM_D1/ GP[15] EM_D2/ GP[16] EM_D3/ GP[17] EM_D4/ GP[18] EM_D5/ GP[19] EM_D6/ GP[20] EM_D7/ GP[21]
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between EMIFA (NAND) GPIO. These pins multiplexed between EMIFA GPIO. EMIFA (AEM[2:0] 010), these pins 8-bit bi-directional data (EM_D[7:0]).
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode AEM[2:0] 010) EM_A[1]/(ALE)/ GP[9]/(PLLMS1) I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33
When used EMIFA (NAND) this Address Latch Enable output (ALE). This multiplexed between EMIFA (NAND) GPIO.
EM_A[2]/(CLE)/ GP[8]/(PLLMS0) EM_WAIT/ (RDY/BSY) EM_OE EM_WE
I/O/Z
When used EMIFA (NAND) this Command Latch Enable output (CLE). When used EMIFA (NAND), ready/busy input (RDY/BSY). When used EMIFA (NAND), this read enable output (RE). When used EMIFA (NAND), this write enable output (WE). This multiplexed between EMIFA (NAND) GPIO. EMIFA (NAND), this Chip Select output EM_CS2 with NAND flash. This chip select default boot boot modes. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state.
I/O/Z I/O/Z I/O/Z
EM_CS2/ GP[12]
I/O/Z
DVDD33
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TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 010) (continued)
SIGNAL NAME TYPE OTHER DESCRIPTION This multiplexed between EMIFA (NAND) GPIO. EMIFA (NAND), this Chip Select output EM_CS3 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between EMAC (RMII), EMIFA (NAND), GPIO. RMRXD0/ EM_CS4/ GP[32] DVDD33 EMIFA (NAND), Chip Select output EM_CS4 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between EMAC (RMII), EMIFA (NAND), GPIO. RMRXD1/ EM_CS5/ GP[33] DVDD33 EMIFA (NAND), Chip Select output EM_CS5 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state.
EM_CS3/ GP[13]
I/O/Z
DVDD33
I/O/Z
I/O/Z
EM_D0/ GP[14] EM_D1/ GP[15] EM_D2/ GP[16] EM_D3/ GP[17] EM_D4/ GP[18] EM_D5/ GP[19] EM_D6/ GP[20] EM_D7/ GP[21]
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 These pins multiplexed between EMIFA (NAND) GPIO. EMIFA (NAND) (AEM[2:0] 010), these pins 8-bit bi-directional data (EM_D[7:0]).
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Table 2-13. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 101)
SIGNAL NAME TYPE OTHER DESCRIPTION
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode AEM[2:0] 101) Actual functions determined PINMUX0 PINMUX1 register settings (e.g., AEM[2:0], etc.). more details, Section 3.7, Multiplexed Configurations. This multiplexed between EMIFA (NAND) GPIO. EM_A[1]/(ALE)/ GP[9]/(PLLMS1) I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 When used EMIFA (NAND) this Address Latch Enable output (ALE). This multiplexed between EMIFA (NAND) GPIO. EM_A[2]/(CLE)/ GP[8]/(PLLMS0) EM_WAIT/ (RDY/BSY) EM_OE EM_WE I/O/Z When used EMIFA (NAND) this Command Latch Enable output (CLE). When used EMIFA (NAND), ready/busy input (RDY/BSY). When used EMIFA (NAND), this read enable output (RE). When used EMIFA (NAND), this write enable output (WE). This multiplexed between EMIFA (NAND) GPIO. EMIFA (NAND), this Chip Select output EM_CS2 with NAND flash. This chip select default boot boot modes. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between EMIFA (NAND) GPIO. EMIFA (NAND), this Chip Select output EM_CS3 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between EMAC (RMII), EMIFA (NAND), GPIO. RMRXD0/ EM_CS4/ GP[32] DVDD33 EMIFA (NAND), Chip Select output EM_CS4 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state. This multiplexed between EMAC (RMII), EMIFA (NAND), GPIO. RMRXD1/ EM_CS5/ GP[33] DVDD33 EMIFA (NAND), Chip Select output EM_CS5 with NAND flash. Note: This features internal pulldown (IPD). this connected used EMIFA chip select signal, proper device operation, external pullup resistor must used ensure EM_CSx function defaults inactive (high) state.
I/O/Z I/O/Z I/O/Z
EM_CS2/ GP[12]
I/O/Z
DVDD33
EM_CS3/ GP[13]
I/O/Z
DVDD33
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview
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Table 2-13. EMIFA Terminal Functions (EMIFA Pinout Mode AEM[2:0] 101) (continued)
SIGNAL NAME EM_D0/ GP[14] EM_D1/ GP[15] EM_D2/ GP[16] EM_D3/ GP[17] EM_D4/ GP[18] EM_D5/ GP[19] EM_D6/ GP[20] EM_D7/ GP[21] TYPE OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 These pins multiplexed between EMIFA (NAND) GPIO. EMIFA (NAND) AEM[2:0] 101, these pins 8-bit bi-directional data (EM_D[7:0]). DESCRIPTION
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
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Table 2-14. DDR2 Memory Controller Terminal Functions
SIGNAL NAME AB10 AA10 AA11 AB11 AA12 AB12 AA13 AB13 AA14 AB14 AB15 I/O/Z DVDDR2 DDR2 Address Output I/O/Z DVDDR2 Bank Select Outputs (BS[2:0]). required support DDR2 memories. TYPE OTHER DDR2 Memory Controller DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_DQM[1] DDR_DQM[0] DDR_RAS DDR_CAS DDR_DQS[0] DDR_DQS[1] DDR_BA[0] DDR_BA[1] DDR_BA[2] DDR_A[12] DDR_A[11] DDR_A[10] DDR_A[9] DDR_A[8] DDR_A[7] DDR_A[6] DDR_A[5] DDR_A[4] DDR_A[3] DDR_A[2] DDR_A[1] DDR_A[0] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DDR2 Clock Output DDR2 Differential Clock Output DDR2 Clock Enable Output DDR2 Active Chip Select Output DDR2 Active Write Enable Output DDR2 Data Mask Outputs DQM1: DDR_D[15:8] DQM0: lower byte DDR_D[7:0] DDR2 Access Signal Output DDR2 Column Access Signal Output Data Strobe Input/Outputs each byte 16-bit data bus. They outputs DDR2 memory when writing inputs when reading. They used synchronize data transfers. DQS1: DDR_D[15:8] DQS0: bottom byte DDR_D[7:0] DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Fore more information, Recommended Operating Conditions table
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TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
Table 2-14. DDR2 Memory Controller Terminal Functions (continued)
SIGNAL NAME DDR_D[15] DDR_D[14] DDR_D[13] DDR_D[12] DDR_D[11] DDR_D[10] DDR_D[9] DDR_D[8] DDR_D[7] DDR_D[6] DDR_D[5] DDR_D[4] DDR_D[3] DDR_D[2] DDR_D[1] DDR_D[0] DDR_VREF DDR_VSSDLL DDR_VDDDLL DDR_ZN DDR_ZP
TYPE
OTHER
DESCRIPTION
I/O/Z
DVDDR2
DDR2 bi-directional data configured 16-bits wide.
Reference voltage input SSTL_18 buffers Ground DDR2 Power (1.8 Volts) DDR2 Digital Locked Loop Impedance control DDR2 outputs. This must connected 200- resistor DVDDR2. Impedance control DDR2 outputs. This must connected 200- resistor VSS.
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Table 2-15. EMAC (MII/RMII) MDIO Terminal Functions
SIGNAL NAME TYPE OTHER EMAC (MII) HCNTL1/MTXEN/ GP[75] HD15/MTXCLK/ GP[73] HD9/MCOL/ GP[67] HD11/MTXD3/ GP[69] HD12/MTXD2/ GP[70] HD13/MTXD1/ GP[71] HD14/MTXD0/ GP[72] HR/W/MRXCLK/ GP[77] HHWIL/MRXDV/ GP[74] HCNTL0/MRXER/ GP[76] HD10/MCRS/ GP[68] HINT/MRXD3/ GP[82] HRDY/MRXD2/ GP[80] HDS1/MRXD1/ GP[79] HDS2/MRXD0/ GP[78] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Transmit Enable output MTXEN. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Transmit Clock input MTXCLK. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Collision Detect input MCOL. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Transmit Data output MTXD3. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Transmit Data output MTXD2. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Transmit Data output MTXD1. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Transmit Data output MTXD0. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Receive Clock input MRXCLK. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Receive Data Valid input MRXDV. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Receive Error input MRXER. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Carrier Sense input MCRS. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Receive Data input MRXD3. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Receive Data input MRXD2. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Receive data input MRXD1. This multiplexed between HPI, EMAC (MII), GPIO. Ethernet (MII) mode, Receive Data input MRXD0. This multiplexed between EMAC (RMII) GPIO. Ethernet MAC(RMII) mode, EMAC carrier sense/receive data valid (RMCRSDV) [I]. This multiplexed between EMAC (RMII) GPIO. Ethernet MAC(RMII) mode, EMAC receive error (RMRXER) [I]. This multiplexed between EMAC (RMII) GPIO. Ethernet MAC(RMII) mode, EMAC transmit data (RMTXD1) [O/Z]. This multiplexed between EMAC (RMII) GPIO. Ethernet MAC(RMII) mode, EMAC transmit data (RMTXD0) [O/Z]. This multiplexed between EMAC (RMII) GPIO. Ethernet MAC(RMII) mode, EMAC RMII reference clock (RMREFCLK) [I]. This multiplexed between EMAC (RMII) GPIO. Ethernet MAC(RMII) mode, EMAC transmit enable (RMTXEN) [O/Z]. DESCRIPTION
EMAC (RMII) RMCRSDV/GP[30] I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33
RMRXER/GP[52] RMTXD1/GP[27]/ (LENDIAN) RMTXD0/GP[28]
I/O/Z
I/O/Z
I/O/Z
RMREFCLK/GP[31]
I/O/Z
RMTXEN/GP[29]
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview
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Table 2-15. EMAC (MII/RMII) MDIO Terminal Functions (continued)
SIGNAL NAME RMRXD1/EM_CS5/ GP[33] RMRXD0/EM_CS4/ GP[32] TYPE OTHER DESCRIPTION This multiplexed between EMAC (RMII), EMIFA, GPIO. Ethernet MAC(RMII) mode, EMAC receive data (RMRXD1) [I]. This multiplexed between EMAC (RMII), EMIFA, GPIO. Ethernet MAC(RMII) mode, EMAC receive data (RMRXD0) [I]. MDIO HCS/MDCLK/ GP[81] HAS/MDIO/ GP[83] I/O/Z I/O/Z DVDD33 DVDD33 This multiplexed between HPI, MDIO, GPIO. Ethernet mode, Management Data Clock output MDCLK. This multiplexed between HPI, MDIO, GPIO. Ethernet mode, Management Data MDIO (I/O/Z).
I/O/Z
DVDD33 DVDD33
I/O/Z
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Table 2-16. VLYNQ Terminal Functions
SIGNAL NAME TYPE OTHER VLYNQ VLYNQ_CLOCK/ GP[57] HD0/VLYNQ_SCRUN/ GP[58] HD8/VLYNQ_TXD3/ GP[66] HD7/VLYNQ_TXD2/ GP[65] HD6/VLYNQ_TXD1/ GP[64] HD5/VLYNQ_TXD0/ GP[63] HD4/VLYNQ_RXD3/ GP[62] HD3/VLYNQ_RXD2/ GP[61] HD2/VLYNQ_RXD1/ GP[60] HD1/VLYNQ_RXD0/ GP[59] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between VLYNQ GPIO. VLYNQ, clock VLYNQ_CLOCK (I/O/Z). This multiplexed between HPI, VLYNQ, GPIO. VLYNQ, Serial Clock request VLYNQ_SCRUN (I/O/Z). This multiplexed between HPI, VLYNQ, GPIO. VLYNQ, transmit output VLYNQ_TXD3. This multiplexed between HPI, VLYNQ, GPIO. VLYNQ, transmit output VLYNQ_TXD2. This multiplexed between HPI, VLYNQ, GPIO. VLYNQ, transmit output VLYNQ_TXD1. This multiplexed between HPI, VLYNQ, GPIO. VLYNQ, transmit output VLYNQ_TXD0. This multiplexed between HPI, VLYNQ, GPIO. VLYNQ, receive input VLYNQ_RXD3. This multiplexed between HPI, VLYNQ, GPIO. VLYNQ, receive input VLYNQ_RXD2. This multiplexed between HPI, VLYNQ, GPIO. VLYNQ, receive input VLYNQ_RXD1. This multiplexed between HPI, VLYNQ, GPIO. VLYNQ, receive input VLYNQ_RXD0. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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TMS320C6421 Fixed-Point Digital Signal Processor
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Table 2-17. Host-Port Interface Terminal Functions
SIGNAL NAME TYPE OTHER Host-Port Interface (HPI) HD0/VLYNQ_SCRUN/ GP[58] HD1/VLYNQ_RXD0/ GP[59] HD2/VLYNQ_RXD1/ GP[60] HD3/VLYNQ_RXD2/ GP[61] HD4/VLYNQ_RXD3/ GP[62] HD5/VLYNQ_TXD0/ GP[63] HD6/VLYNQ_TXD1/ GP[64] HD7/VLYNQ_TXD2/ GP[65] HD8/VLYNQ_TXD3/ GP[66] HD9/MCOL/ GP[67] HD10/MCRS/ GP[68] HD11/MTXD3/ GP[69] HD12/MTXD2/ GP[70] HD13/MTXD1/ GP[71] HD14/MTXD0/ GP[72] HD15/MTXCLK/ GP[73] HHWIL/MRXDV/ GP[74] I/O/Z I/O/Z DVDD33 This multiplexed between HPI, EMAC (MII), GPIO. mode, this half-word identification input HHWIL (I). This multiplexed between HPI, EMAC (MII), GPIO. mode, this control input HCNTL1 (I). state HCNTL1 HCNTL0 determines address, data, control information being transmitted between external host C6421. This multiplexed between HPI, EMAC (MII), GPIO. mode, this control input HCNTL0 (I). state HCNTL1 HCNTL0 determines address, data, control information being transmitted between external host C6421. This multiplexed between HPI, EMAC (MII), GPIO. mode, this host read write select input HR/W(I). This multiplexed between HPI, EMAC (MII), GPIO. mode, this host data strobe input HDS2 (I). DVDD33 This multiplexed between HPI, VLYNQ EMAC (MII), GPIO. mode, these pins host-port data pins HD[15:0] (I/O/Z) multiplexed internally with address lines. DVDD33 DESCRIPTION
HCNTL1/MTXEN/ GP[75]
I/O/Z
DVDD33
HCNTL0/MRXER/ GP[76]
I/O/Z
DVDD33
HR/W/MRXCLK/ GP[77] HDS2/MRXD0/ GP[78]
I/O/Z I/O/Z
DVDD33 DVDD33
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
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Table 2-17. Host-Port Interface Terminal Functions (continued)
SIGNAL NAME HDS1/MRXD1/ GP[79] HRDY/MRXD2/ GP[80] HCS/MDCLK/ GP[81] HINT/RXD3/ GP[82] HAS/MDIO/ GP[83] TYPE OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DESCRIPTION This multiplexed between HPI, EMAC (MII), GPIO. mode, this host data strobe input HDS1 (I). This multiplexed between HPI, EMAC (MII), GPIO. mode, this host ready output from host (O/Z). This multiplexed between HPI, MDIO, GPIO. mode, this active chip select input (I). This multiplexed between HPI, EMAC (MII), GPIO. mode, this host interrupt output HINT (O/Z). This multiplexed between HPI, MDIO, GPIO. mode, this host address strobe (I). proper operation, this routed out, must pulled external resistor.
I/O/Z I/O/Z
I/O/Z I/O/Z
I/O/Z
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TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
Table 2-18. Terminal Functions
SIGNAL NAME TYPE OTHER I/O/Z DVDD33 I2C, this clock. master mode, this output. slave mode, this input. When module used, proper device operation, this must pulled external resistor. I2C, this bi-directional data signal. When module used, proper device operation, this must pulled external resistor. DESCRIPTION
I/O/Z
DVDD33
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-19. Multichannel Buffered Serial Port (McBSP0) Terminal Functions
SIGNAL NAME TYPE OTHER DESCRIPTION
Multichannel Buffered Serial Port (McBSP0) Muxing Control: CLKS0/TOUT0L/ GP[97] ACLKR0/CLKX0/ GP[99] AHCLKR0/CLKR0/ GP[101] AXR0[2]/FSX0/ GP[103] AXR0[3]/FSR0/ GP[102] AXR0[1]/DX0/ GP[104] AFSR0/DR0/ GP[100] I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between McBSP0, Timer0, GPIO. McBSP0, McBSP0 external clock source (I). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 transmit clock CLKX0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 receive clock CLKR0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 transmit frame synchronization FSX0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 receive frame synchronization FSR0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 data transmit output (O/Z). This multiplexed between McASP0, McBSP0, GPIO. McBSP0, McBSP0 data receive input (I).
I/O/Z I/O/Z I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-20. Multichannel Audio Serial Port (McASP0) Terminal Functions
SIGNAL NAME TYPE OTHER McASP0 AMUTEIN0/ GP[109] AMUTE0/ GP[110] ACLKR0/CLKX0/ GP[99] AHCLKR0/CLKR0/ GP[101] ACLKX0/ GP[106] AHCLKX0/ GP[108] AFSR0/DR0/ GP[100] AFSX0/ GP[107] AXR0[3]/FSR0/ GP[102] AXR0[2]/FSX0/ GP[103] AXR0[1]/DX0/ GP[104] AXR0[0]/ GP[105] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between McASP0 GPIO. McASP0, McASP0 mute input AMUTEIN0 (I). This multiplexed between McASP0 GPIO. McASP0, McASP0 mute output AMUTE0 (O/Z). This multiplexed between McASP0, McBSP0, GPIO. McASP0, McASP0 receive clock ACLKR0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McASP0, McASP0 receive high-frequency master clock AHCLKR0 (I/O/Z). This multiplexed between McASP0 GPIO. McASP0, McASP0 transmit clock ACLKX0 (I/O/Z). This multiplexed between McASP0 GPIO. McASP0, McASP0 transmit high-frequency master clock AHCLKX0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McASP0, McASP0 receive frame synchronization AFSR0 (I/O/Z). This multiplexed between McASP0 GPIO. McASP0, McASP0 transmit frame synchronization AFSX0 (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McASP0, McASP0 transmit/receive (TX/RX) data AXR0[3] (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McASP0, McASP0 transmit/receive (TX/RX) data AXR0[2] (I/O/Z). This multiplexed between McASP0, McBSP0, GPIO. McASP0, McASP0 transmit/receive (TX/RX) data AXR0[1] (I/O/Z). This multiplexed between McASP0 GPIO. McASP0, McASP0 transmit/receive (TX/RX) data AXR0[0] (I/O/Z). DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-21. UART0 Terminal Functions
SIGNAL NAME TYPE OTHER UART0 URXD0/ GP[85] UTXD0/ GP[86] UCTS0/ GP[87] URTS0/ PWM0/ GP[88] I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between UART0 (Data) GPIO. When used UART0 this receive data input URXD0. This multiplexed between UART0 (Data) GPIO. UART0 mode, this transmit data output UTXD0. This multiplexed between UART0 (Flow Control) GPIO. UART0 mode, this clear send input UCTS0. This multiplexed between UART0 (Flow Control), PWM0, GPIO. UART0 mode, this ready send output URTS0. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-22. PWM0, PWM1, PWM2 Terminal Functions
SIGNAL NAME TYPE OTHER PWM2 CLKOUT0/PWM2/ GP[84] I/O/Z DVDD33 This multiplexed between System Clock generator (PLL1), PWM2, GPIO. PWM2, this output PWM2. PWM1 GP[4]/PWM1 I/O/Z DVDD33 This multiplexed between GPIO PWM1. PWM1, this output PWM1. PWM0 URTS0/PWM0/ GP[88] I/O/Z DVDD33 This multiplexed between UART0 (Flow Control), PWM0, GPIO. PWM0, this output PWM0. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-23. Timer Timer Timer Terminal Functions
SIGNAL NAME TYPE OTHER Timer external pins. Timer (watchdog) peripheral pins pinned external pins. Timer TINP1L/ GP[56] TOUT1L/ GP[55] I/O/Z DVDD33 DVDD33 This multiplexed between Timer GPIO. Timer this timer input lower 32-bit counter This multiplexed between Timer GPIO. Timer this timer output lower 32-bit counter Timer TINP0L/ GP[98] CLKS0/ TOUT0L/ GP[97] I/O/Z DVDD33 DVDD33 This multiplexed between Timer GPIO. Timer this timer input lower 32-bit counter This multiplexed between McBSP0, Timer GPIO. Timer this timer output lower 32-bit counter DESCRIPTION
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-24. GPIO Terminal Functions
SIGNAL NAME TYPE OTHER GPIO GPIO pins C6421 device multiplexed with other peripherals functions (e.g., EMAC/MDIO, McASP0, McBSP0, Timer Timer UART0, PWM0, PWM1, PWM2, EMIFA, CLKOUT0 pin), peripheral-specific Terminal Functions tables GPIO multiplexing. Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal DESCRIPTION
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Table 2-25. Standalone GPIO Terminal Functions
SIGNAL NAME TYPE OTHER Standalone GPIO GP[0] GP[1] GP[2] GP[3] GP[22]/ (BOOTMODE0) GP[23]/ (BOOTMODE1) GP[24]/ (BOOTMODE2) GP[25]/ (BOOTMODE3) GP[26]/ (FASTBOOT) GP[36] GP[37] GP[38] GP[39] GP[40] GP[41] GP[42] GP[43] GP[53] GP[54] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This functions standalone GPIO Note: GP[36] only available when This functions standalone GPIO Note: GP[37] only available when This functions standalone GPIO Note: GP[38] only available when This functions standalone GPIO Note: GP[39] only available when This functions standalone GPIO Note: GP[40] only available when This functions standalone GPIO Note: GP[41] only available when This functions standalone GPIO Note: GP[42] only available when This functions standalone GPIO Note: GP[43] only available when This functions standalone GPIO This functions standalone GPIO These pins function boot configuration pins during device reset. After device reset, these pins function standalone GPIO. This functions standalone GPIO This functions standalone GPIO This functions standalone GPIO This functions standalone GPIO DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-26. Reserved Terminal Functions
SIGNAL NAME AA15 AA18 AA16 AB16 AA17 AB17 AB18 AA19 AB19 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 TYPE OTHER RESERVED RSV1 RSV2 RSV3 RSV4 RSV5 RSV6 RSV7 RSV8 RSV9 RSV10 RSV11 RSV12 RSV13 RSV14 RSV15 RSV16 RSV17 RSV18 RSV19 RSV20 RSV21 RSV22 RSV23 RSV24 RSV25 RSV26 RSV27 RSV28 RSV29 RSV30 RSV31 RSV32 RSV33 Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. This must tied directly normal device operation. Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. This must tied directly normal device operation. Reserved. This must tied directly normal device operation. Reserved. This must tied directly normal device operation. Reserved. This must tied directly normal device operation. Reserved. This must tied directly normal device operation. Reserved. proper C6421 device operation, this must pulled down external resistor tied VSS. Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. proper C6421 device operation, this must pulled down external resistor. Reserved. proper C6421 device operation, this must pulled down external resistor. Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.9.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
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Table 2-26. Reserved Terminal Functions (continued)
SIGNAL NAME RSV34 RSV35 RSV36 RSV37 RSV38 RSV39 AA20 AB20 AA21 TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z OTHER DESCRIPTION Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground)
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Table 2-27. Supply Terminal Functions
SIGNAL NAME DVDD33 Input, Output, High impedance, Supply voltage, Ground, Analog signal supply voltage (see Section 6.3.3, Power-Supply Decoupling.) TYPE OTHER SUPPLY VOLTAGE PINS DESCRIPTION
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Table 2-27. Supply Terminal Functions (continued)
SIGNAL NAME DVDDR2 CVDD AB21 AB22 1.20 supply voltage -7/-6/-5/-4/-Q6/-Q5/-Q4 devices) 1.05 core supply voltage (-7/-6/-5/-4/-L/-Q5 devices) (see Power-Supply Decoupling section this data manual) DDR2 supply voltage (see Power-Supply Decoupling section this data manual) TYPE OTHER DESCRIPTION
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Table 2-28. Ground Terminal Functions
SIGNAL NAME Ground pins TYPE OTHER GROUND PINS DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal
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Table 2-28. Ground Terminal Functions (continued)
SIGNAL NAME AA22 Ground pins TYPE OTHER DESCRIPTION
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Device Support 2.6.1 Development Support
offers extensive line development tools TMS320C642x platform, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules. tool's support documentation electronically available within Code Composer StudioIntegrated Development Environment (IDE). following products support development TMS320C642x-based applications: Software Development Tools: Code Composer StudioIntegrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOSTM), which provides basic run-time target software needed support application. Hardware Development Tools: Extended Development System (XDSTM) Emulator (supports TMS320C642x multiprocessor system debug) (Evaluation Module) complete listing development-support tools TMS320C642x platform, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL). information pricing availability, contact nearest field sales office authorized distributor.
Device Development-Support Tool Nomenclature
designate stages product development cycle, assigns prefixes part numbers devices support tools. Each commercial family member three prefixes: TMX, TMP, (e.g., TMS320C6421ZWTQ6). Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: Experimental device that necessarily representative final device's electrical specifications. Final silicon that conforms device's electrical specifications completed quality reliability verification. Fully-qualified production device.
Support tool development evolutionary flow: TMDX TMDS Development-support product that completed Texas Instruments internal qualification testing. Fully qualified development-support product.
devices TMDX development-support tools shipped against following disclaimer: "Developmental product intended internal evaluation purposes." devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies.
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Predictions show that prototype devices (TMX TMP) have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used. device nomenclature also includes suffix with device family name. This suffix indicates package type (for example, ZWT), temperature range (for example, "Blank" commercial temperature range), device speed range megahertz (for example, "Blank" default [600-MHz]). Figure 2-12 provides legend reading complete device name TMS320C642x platform member.
PREFIX Experimental device Qualified device DEVICE FAMILY TMS320DSP Family DEVICE C64x+DSP: C6424 C6421 C6421 DEVICE SPEED RANGE Power Device TEMPERATURE RANGE (JUNCTION) Blank Commercial Grade -40°C 125°C, Automotive Grade Commercial Grade (Tape Reel) -40°C 125°C, Automotive Grade (Tape Reel) PACKAGE TYPE(A) 361-pin plastic BGA, with Pb-Free soldered balls 376-pin plastic BGA, with Pb-Free soldered balls [Green] SILICON REVISION: Blank Revision Ball Grid Array "TMX" initial devices, device number C6424. combinations available. more information, Orderable Devices table Packing Information section. device speed range symbolization indicates maximum frequency highest CVDD voltage supported. determine maximum frequency other supported CVDD voltages, refer PLL1 PLL2 section.
Figure 2-12. Device Nomenclature
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Documentation Support 2.8.1 Related Documentation From Texas Instruments
following documents describe TMS320C642x Fixed-Point Digital Signal Processor (DSP). Copies these documents available Internet www.ti.com. Tip: Enter literature number search provided www.ti.com. current documentation that describes C642x DSP, related peripherals, other technical collateral, available C6000 product folder www.ti.com/c6000. SPRUEM3 TMS320C642x Peripherals Overview Reference Guide. Provides overview briefly describes peripherals available TMS320C642x Digital Signal Processor (DSP). TMS320C64x TMS320C64x+ Migration Guide. Describes migrating from Texas Instruments TMS320C64x digital signal processor (DSP) TMS320C64x+ DSP. objective this document indicate differences between cores. Functionality devices that identical included. TMS320C64x/C64x+ Instruction Reference Guide. Describes architecture, pipeline, instruction set, interrupts TMS320C64x TMS320C64x+ digital signal processors (DSPs) TMS320C6000 family. C64x/C64x+ generation comprises fixed-point devices C6000 platform. C64x+ enhancement C64x with added functionality expanded instruction set. TMS320C64x+ Megamodule Reference Guide. Describes TMS320C64x+ digital signal processor (DSP) megamodule. Included discussion internal direct memory access (IDMA) controller, interrupt controller, power-down controller, memory protection, bandwidth management, memory cache.
SPRAA84
SPRU732
SPRU871
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System Module Registers
system module includes status control registers required configuration device. Brief descriptions various registers shown Table 3-1. System Module registers required device configurations discussed following sections. Table 3-1. System Module Register Memory
ADDRESS RANGE 0x01C4 0000 0x01C4 0004 0x01C4 0008 0x01C4 000C 0x01C4 0010 0x01C4 0014 0x01C4 0018 0x01C4 0027 0x01C4 0028 0x01C4 002C 0x01C4 0030 0x01C4 0034 0x01C4 0038 0x01C4 003C 0x01C4 0040 0x01C4 0044 0x01C4 0048 0x01C4 004C 0x01C4 0050 0x01C4 0080 0x01C4 0084 0x01C4 0088 0x01C4 008C REGISTER ACRONYM PINMUX0 PINMUX1 DSPBOOTADDR BOOTCOMPLT BOOTCFG JTAGID HPICTL MSTPRI0 MSTPRI1 VDD3P3V_PWDN DDRVTPER TIMERCTL EDMATCCFG DESCRIPTION Multiplexing Control (see Section 3.7.2.1, PINMUX0 Register Description). Multiplexing Control (see Section 3.7.2.2, PINMUX1 Register Description). Boot Address (see Section 3.4.2.3, DSPBOOTADDR Register). Boot Complete (see Section 3.4.2.2, BOOTCMPLT Register). Reserved Device Boot Configuration (see Section 3.4.2.1, BOOTCFG Register). Reserved JTAG (see Section 6.21.1, JTAG (JTAGID) Register Description(s)). Reserved Control (see Section 3.6.2.1, Control Register). Reserved Reserved Master Priority Control (see Section 3.6.1, Switch Central Resource (SCR) Priorities). Master Priority Control (see Section 3.6.1, Switch Central Resource (SCR) Priorities). Reserved 3.3-V Powerdown Control (see Section 3.2, Power Considerations). DDR2 Enable Register (see Section 6.9.4, DDR2 Memory Controller). Reserved Timer Control (see Section 3.6.2.2, Timer Control Register). EDMA Transfer Controller Default Burst Size Configuration (see Section 3.6.2.3, EDMA Configuration Register). Reserved
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Power Considerations
C6421 provides several means managing power consumption. described Section 6.3.4, C6421 Power Clock Domains, C6421 single power domain-the "Always power domain. Within this power domain, C6421 utilizes local clock gating Power Sleep Controller (PSC) achieve power savings. more details PSC, Section 6.3.5, Power Sleep Controller (PSC) TMS320C642x Power Sleep Controller (PSC) User's Guide (literature number SPRUEN8). Some C6421 peripherals support additional power saving features. more details power saving features supported, TMS320C642x Peripherals Overview Reference Guide (literature number SPRUEM3). Most C6421 3.3-V I/Os powered-down reduce power consumption. VDD3P3V_PWDN register System Module (see Figure 3-1) used selectively power down unused 3.3-V pins. independent control, 3.3-V I/Os separated into functional groups-most which named according multiplexing groups (see Table 3-2). these groups, only buffers needed Host/EMIFA Boot Power-Up Operations powered default (CLKOUT Block, EMIFA Block, Host Block, GPIO Block). Note: save power, other buffers powered down default. Before using these pins, user must program VDD3P3V_PWDN register power corresponding buffers. list multiplexed pins device group each belongs Section 3.7.3.1, Multiplexed Pins C6421. Note: VDD3P3V_PWDN register only controls power buffers. Power Sleep Controller (PSC) determines clock/power state peripheral.
RESERVED
R-0000 0000 0000 0000
EMBK3
UR0FC
UR0DAT
TIMER1
TIMER0
PWM1
GPIO
HOST
EMBK2
EMBK1
EMBK0
CLKOUT
RESERVED
R-00
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: Read/Write; Read only; value after reset
Figure 3-1. VDD3P3V_PWDN Register- 0x01C4 0048 Table 3-2. VDD3P3V_PWDN Register Descriptions
31:14 NAME RESERVED DESCRIPTION Reserved. Read-only, writes have effect. Reserved. proper device operation, this should programmed during device initialization (see Section 3.8, Device Initialization Sequence After Reset). EMIFA Sub-Block Power Down Control. Controls power pins EMIFA Sub-Block EMBK3 pins powered [default]. pins powered down operational. Outputs 3-stated (Hi-Z). UART0 Flow Control Block Power Down Control. Controls power pins UART0 Flow Control Block. UR0FC pins powered pins powered down operational. Outputs 3-stated (Hi-Z) [default].
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Table 3-2. VDD3P3V_PWDN Register Descriptions (continued)
NAME DESCRIPTION UART0 Data Block Power Down Control. Controls power pins UART0 Data Block. UR0DAT pins powered pins powered down operational. Outputs 3-stated (Hi-Z) [default]. Timer1 Block Power Down Control. Controls power pins Timer1 Block. TIMER1 pins powered pins powered down operational. Outputs 3-stated (Hi-Z) [default]. Timer0 Block Power Down Control. Controls power pins Timer0 Block. TIMER0 pins powered pins powered down operational. Outputs 3-stated (Hi-Z) [default]. Serial Port Block Power Down Control. Controls power pins Serial Port Block (Serial Port Sub-Block Serial Port Sub-Block pins powered pins powered down operational. Outputs 3-stated (Hi-Z) [default]. PWM1 Block Power Down Control. Controls power PWM1 Block. PWM1 pins powered pins powered down operational. Outputs 3-stated (Hi-Z) [default]. GPIO Block Power Down Control. Controls power pins GPIO Block: GP[3:0]. GPIO Note: GPIO Block contains standalone GPIO pins group. pins powered [default]. pins powered down operational. Outputs 3-stated (Hi-Z). Host Block Power Down Control. Controls power pins Host Block. HOST pins powered [default]. pins powered down operational. Outputs 3-stated (Hi-Z). EMIFA Sub-Block Power Down Control. Controls power pins EMIFA Sub-Block EMBK2 pins powered [default]. pins powered down operational. Outputs 3-stated (Hi-Z). EMIFA Sub-Block Power Down Control. Controls power pins EMIFA Sub-Block EMBK1 pins powered [default]. pins powered down operational. Outputs 3-stated (Hi-Z). EMIFA Sub-Block Power Down Control. Controls power pins EMIFA Sub-Block EMBK0 pins powered [default]. pins powered down operational. Outputs 3-stated (Hi-Z). CLKOUT Block Power Down Control. Controls power CLKOUT Block. CLKOUT pins powered [default]. pins powered down operational. Outputs 3-stated (Hi-Z).
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Clock Considerations
Global device local peripheral clocks controlled Controllers (PLLC1 PLLC2) Power Sleep Controller (PSC).
3.3.1
Clock Configurations after Device Reset
After device reset, user responsible programming Controllers (PLLC1 PLLC2) Power Sleep Controller (PSC) bring device desired clock frequency desired peripheral clock state (clock gating not). additional power savings, some C6421 peripherals support clock gating within peripheral boundary. more details clock gating power saving features supported specific peripheral, TMS320C642x Peripherals Overview Reference Guide (literature number SPRUEM3).
3.3.1.1 Device Clock Frequency C6421 defaults bypass mode. bring device desired clock frequency, user should program PLLC1 PLLC2 after device reset. C6421 supports FASTBOOT option, where upon exit from device reset internal bootloader code automatically programs PLLC1 into mode with specific multiplier divider speed device boot. While FASTBOOT option beneficial faster boot, multiplier divider selected boot exact frequency desired run-time application. user's responsibility reconfigure PLLC1 after fastboot bring device into desired clock frequency. Section 3.4.1, Boot Modes, discusses different fast boot modes more detail. user must adhere various clock requirements when programming PLLC1 PLLC2: Fixed frequency ratio requirements between CLKDIV1, CLKDIV3, CLKDIV6 clock domains. more details frequency ratio requirements, Section 6.3.4, C6421 Power Clock Domains. multiplier frequency ranges. more details multiplier frequency ranges, Section 6.7.1, PLL1 PLL2. 3.3.1.2 Module Clock State clock reset state each modules controlled Power Sleep Controller (PSC). Table shows default state each module after device-level global reset. C6421 device four different module states-Enable, Disable, SyncReset, SwRstDisable. more information definitions module states, PSC, programming, Section 6.3.5, Power Sleep Controller (PSC) TMS320C642x Power Sleep Controller (PSC) User's Guide (literature number SPRUEN8).
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Table 3-3. C6421 Default Module States
LPSC MODULE NAME EDMACC EDMATC0 EDMATC1 EDMATC2 EMAC Memory Controller MDIO EMAC McASP0 VLYNQ DDR2 Memory Contoller EMIFA Enable, configuration pins AEM[2:0] Others [010b 101b] McBSP0 UART0 PWM0 PWM1 PWM2 GPIO TIMER0 TIMER1 C64x+ SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable Enable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable, configuration pins AEM[2:0] 000b DEFAULT MODULE STATE [PSC Register MDSTATn.STATE]
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Boot Sequence
boot sequence process which device's memory loaded with program data sections, which some device's internal registers programmed with predetermined values. boot sequence started automatically after each device-level global reset. more details device-level global resets, Section 6.5, Reset. There several methods which memory register initialization take place. Each these methods referred boot mode. boot mode used selected reset. more information bootmode selections, Section 3.4.1, Boot Modes. device booted through multiple means-primary bootloaders within internal EMIFA, secondary user bootloaders from peripherals external memories. Boot modes, configurations, register configurations required booting device, described following subsections.
3.4.1
Boot Modes
C6421 boot modes determined these device boot configuration pins. information these pins sampled device reset, Section 6.5.1.2, Latching Boot Configuration Pins. BOOTMODE[3:0] FASTBOOT PLLMS[2:0] BOOTMODE[3:0] determines type boot (e.g., Boot, EMIFA Boot, Boot, etc.). FASTBOOT determines enabled during boot speed boot process. PLLMS[2:0] used bootloader code determine multiplier used during fastboot modes (FASTBOOT C6421 boot modes grouped into categories-Non-Fastboot Modes User-Select Multiplier Fastboot Modes. Non-Fastboot Modes (FASTBOOT device operates default bypass mode during boot. Non-Fastboot bootmodes available C6421 shown Table 3-4. User-Select Multiplier Fastboot Modes (FASTBOOT bootloader code speeds device during boot. multiplier selected user PLLMS[2:0] pins. User-Select Multiplier Fastboot bootmodes available C6421 shown Table 3-5.
other modes shown these tables reserved invalid settings.
Device Configurations
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TMS320C6421 Fixed-Point Digital Signal Processor
Table 3-4. Non-Fastboot Modes (FASTBOOT
DEVICE BOOT CONFIGURATION PINS BOOTMODE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Boot (Emulation Boot) Reserved Boot Reserved EMIFA Direct Boot [PLL Bypass Mode] Boot [STANDARD MODE] 16-bit Boot [McBSP0] NAND Flash Boot UART Boot without Hardware Flow Control [UART0] Reserved VLYNQ Boot Reserved Reserved Reserved UART Boot with Hardware Flow Control [UART0] 24-bit Boot (McBSP0 GP[97]) Master Slave Master Master Master Master Master Slave Master Master PLLC1 CLOCK SETTING BOOT BOOT DESCRIPTION C6421 (Master/Slave) DEVICE FREQUENCY (SYSCLK1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN DSPBOOTADDR (DEFAULT)
MODE Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass
CLKDIV1 DOMAIN (SYSCLK1 DIVIDER)
0x0010 0000 0x0010 0000 0x4200 0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000
boot modes that default DSPBOOTADDR 0x0010 0000 (i.e., boot modes except EMIFA Direct Boot, BOOTMODE[3:0] 0100, FASTBOOT bootloader code disables C64x+ cache (L2, L1P, L1D) that upon exit from bootloader code, C64x+ memories configured RAM. cache required, application code must explicitly enable cache. more information bootloader, Using TMS320C642x Bootloader Application Report (literature number SPRAAK5). MODE Non-Fastboot Modes fixed shown this table; therefore, PLLMS[2:0] configuration pins have effect MODE. Boot (BOOTMODE[3:0] 0101b) only available MXI/CLKIN frequency between MHz. Boot available MXI/CLKIN frequencies less than MHz.
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TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
Table 3-5. User-Select Multiplier Fastboot Modes (FASTBOOT
DEVICE BOOT CONFIGURATION PINS BOOTMODE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 Boot (Emulation Boot) Reserved Boot Reserved EMIFA FASTBOOT with Boot [FAST MODE] 16-bit Boot [McBSP0] NAND Flash Boot UART Boot without Hardware Flow Control [UART0] EMIFA FASTBOOT without VLYNQ Boot Reserved Reserved Reserved UART Boot with Hardware Flow Control [UART0] 24-bit Boot (McBSP0 GP[97]) Master Slave Master Master Master Master Master PLLC1 CLOCK SETTING BOOT BOOT DESCRIPTION C6421 (Master/Slave) DEVICE FREQUENCY (SYSCLK1) CLKIN Table Table Table Table Table Table DSPBOOTADDR (DEFAULT)
MODE Bypass Table Table Table Table Table Table
CLKDIV1 DOMAIN (SYSCLK1 DIVIDER)
0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000
1001 1010 1011 1100 1101 1110 1111
Master Slave Master Master
Table Table
Table CLKIN Table CLKIN
0x0010 0000 0x0010 0000 0x0010 0000
boot modes that default DSPBOOTADDR 0x0010 0000, bootloader code disables C64x+ cache (L2, L1P, L1D) that upon exit from bootloader code, C64x+ memories configured RAM. cache required, application code must explicitly enable cache.For more information bootloader, Using TMS320C642x Bootloader Application Report (literature number SPRAAK5). supported MODE available. [See Table supported C6421 MODE options]. Boot (BOOTMODE[3:0] 0101b) only available MXI/CLKIN frequency between MHz. Boot available MXI/CLKIN frequencies less than MHz.
Table 3-6. Multiplier Selection (PLLMS[2:0]) User-Select Multiplier Fastboot Modes (FASTBOOT
DEVICE BOOT CONFIGURATION PINS PLLMS[2:0] MODE PLLC1 CLOCK SETTING BOOT CLKDIV1 DOMAIN (SYSCLK1 DIVIDER) DEVICE FREQUENCY (SYSCLK1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN
Device Configurations
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TMS320C6421 Fixed-Point Digital Signal Processor
shown Table Table 3-5, device reset Boot Controller defaults DSPBOOTADDR values based boot mode selected. boot modes, C64x+ immediately released from reset begins executing from address location indicated DSPBOOTADDR. Internal Bootloader (0x0010 0000): most boot modes, DSPBOOTADDR defaults internal Bootloader that immediately execute bootloader code internal ROM. bootloader code decodes captured BOOTMODE, FASTBOOT, PLLMS information BOOTCFG register) determine proper boot operation. Note: boot modes that default DSPBOOTADDR 0x0010 0000, bootloader code disables C64x+ cache (L2, L1P, L1D) that upon exit from bootloader code, C64x+ memories configured RAM. cache required, application code must explicitly enable cache. more information boot modes, Section 3.4.1, Boot Modes. more information bootloader, Using TMS320C642x Bootloader Application Report (literature number SPRAAK5). EMIFA Chip Select Space (0x4200 0000): EMIFA Direct Boot Bypass Mode (BOOTCFG settings BOOTMODE[3:0] 0100b, FASTBOOT only exception where DSPBOOTADDR defaults EMIFA Chip Select Space begins execution directly from external this EMIFA space.
more information bootloader code handles each boot mode, Using TMS320C642x Bootloader Application Report (literature number SPRAAK5). 3.4.1.1 FASTBOOT When C6421 exits reset (RESET released), Controllers (PLLC1 PLLC2) default Bypass Mode. This means PLLs disabled, MXI/CLKIN clock input driving chip. clock domain divider ratios discussed Section 6.3.4, C6421 Power Clock Domains, still apply. example, assume MXI/CLKIN frequency MHz-meaning internal clock source EMIFA CLKDIV3 domain MHz/3 MHz, very slow clock. addition, EMIFA registers reset slowest configuration which translates very slow peripheral operation/boot. optimize boot time, user should reprogram clock settings PLLC early possible during boot process. FASTBOOT facilitates this operation allowing device boot faster clock rate. Except EMIFA Direct Boot Bypass Mode (BOOTCFG settings BOOTMODE[3:0] 0100b, FASTBOOT other boot modes default executing from Internal Bootloader ROM. first action that bootloader code takes decode boot mode. FASTBOOT option selected (BOOTCFG.FASTBOOT bootloader software begins programming PLLC1 (System PLLC) Mode give device slightly faster operation before fetching code from external devices. exact multiplier that bootloader uses determined PLLMS[2:0] settings, shown Table Table 3-6. Some boot modes must accompanied with FASTBOOT that corresponding peripheral reasonable rate communicate external device(s). Note: PLLC2 still stays Bypass Mode, bootloader does reconfigure 3.4.1.2 Selecting FASTBOOT Multiplier Table Table show multipliers used bootloader code during fastboot (FASTBOOT resulting device frequency. user responsible selecting bootmode with appropriate multiplier their MXI/CLKIN clock source that device speed frequency range requirements met. PLLC1 Clock Frequency Ranges, Table 6-15, PLLC1 Clock Frequency Ranges Section 6.7.1, PLL1 PLL2. following guidelines output frequency device speed (frequency):
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TMS320C6421 Fixed-Point Digital Signal Processor
SPRS346D JANUARY 2007 REVISED JUNE 2008 www.ti.com
Output Frequency: (PLLOUT CLKIN frequency boot Multiplier) must stay within PLLOUT frequency range Table 6-15, PLLC1 Clock Frequency Ranges. Device Frequency: (SYSCLK1) calculated from Table must exceed SYSCLK1 maximum frequency Table 6-15, PLLC1 Clock Frequency Ranges. example, 600-MHz device with CLKIN MHz, order stay within PLLOUT frequency range SYSCLK1 maximum frequency from Table 6-15, PLLC1 Clock Frequency Ranges, user must select boot mode with PLL1 multiplier between x24.
3.4.1.3 EMIFA Boot Modes shown Table Table 3-5, there different types EMIFA Boot Modes. This subsection summarizes these types EMIFA boot modes. further detailed information, Using TMS320C642x Bootloader Application Report (literature number SPRAAK5). EMIFA Direct Boot Bypass Mode (FASTBOOT BOOTMODE[3:0] 0100b) C64x+ fetches code directly from EMIFA Chip Select Space [EM_CS2] (address 0x4200 0000) Bypass Mode EMIFA configured Asynchronous EMIF. user responsible ensuring desirable Asynchronous EMIF pins available through configuration pins AEM[2:0]. AEM[2:0] must configured 010b [EMIFA (Async) Pinout Mode EMIFA Fastboot with (FASTBOOT BOOTMODE[3:0] 0100b) C64x+ begins execution from internal bootloader address 0x0010 0000. bootloader code programs PLLC1 Mode speed boot process. multiplier value determined PLLMS[2:0] configuration shown Table 3-5. bootloader code reads code from EMIFA EM_CS2 space using application image script (AIS) format. EMIFA configured Asynchronous EMIF. user responsible ensuring desirable Asynchronous EMIF pins available through config

TMS320C6421 Fixed-Point Digital Signal Processor High-Performance

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