Stereo Audio 100-dBA Signal-to-Noise Ratio 16/20/24/32-Bit Data Suppor
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
Stereo Audio 100-dBA Signal-to-Noise Ratio 16/20/24/32-Bit Data Supports Rates From Programmable Filter Engine Stereo Audio 92-dBA Signal-to-Noise Ratio Supports Rates from Programmable Filter Engine Three Dedicated Microphone Inputs Supports Single-Ended, Balanced Differential, Unbalanced Differential Configurations Stereo Line-Level Inputs Audio Output Drivers Ground-Referenced Cap-Free Stereo Single-Ended Headphone Drivers Ground-Referenced Cap-Free Stereo Single-Ended Receiver Drivers Fully Differential Stereo Line Outputs Programmable Input/Output Gains Automatic Gain Control (AGC) Record
AVDD_CP GND_CP FC_POS FC_NEG GND_REG AVDD_REG AVSS_REG AVDD2 AVDD1 AVSS1 DVDD DVSS IOVDD
Dual Programmable Microphone Bias Generators Programmable Flexible Clock Generation Advanced Microphone Impedance Detection I2CControl Audio Serial Data Supports I2STM, Left/Right Justified, DSP, Modes Alternate Serial PCM/I2S Data Stereo Digital Microphone Input Extensive Modular Power Control Integrated Charge Pump Integrated Programmable LDOs Package: 80-VFBGA
Applications
Portable Navigation Devices (PND) Portable Media Player (PMP) Mobile Handsets Communication Portable Computing
DOUT BCLK WCLK
AVDD _ADC LINEIN_L
Charge Pump
Voltage Regulators
Digital Supplies
Audio Serial
AVDD HP_COM
MIC1_P MIC1_M EXTMIC EXTMIC
RECL RECR AVSS_HP
miniDSP
miniDSP
MIC2_P MIC2_M LINEIN_R GND_ADC
LINEOUT LINEOUT LINEOUT LINEOUT AVDD _DAC AVSS_DAC
Signal Grounds
GND_HP GND_DAC VCM_ADC
Microphone Support
EXTMIC_BIAS INTMIC_BIAS HOOK DETECT AVDD_BIAS GND_BIAS
Control
GPIO
Figure 1-1. Simplified Block Diagram
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this document. MicroStar Junior trademark Texas Instruments.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
MCLK RESETB I2C_ADR1 I2C_ADR0
GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1
Copyright 2009, Texas Instruments Incorporated
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
Description
TLV320AIC36 (sometimes referred AIC36) flexible, low-power, low-voltage stereo audio codec with programmable inputs outputs, fully programmable miniDSP, fixed predefined parameterizable signal processing blocks, integrated PLL, integrated LDOs, flexible digital interfaces.
1.3.1
Detailed Description
TLV320AIC36 features fully programmable miniDSP cores that support application-specific algorithms record and/or playback path device. miniDSP cores fully software controlled. Extensive Register based control power, input/output channel configuration, gains, effects, pin-multiplexing, clocks included, allowing device precisely targeted application. device cover operations from 8-kHz mono voice playback audio stereo 192-kHz playback, making ideal portable battery-powered audio telephony applications. record path TLV320AIC36 covers operations from 8-kHz mono 192-kHz stereo recording, contains programmable input channel configurations covering single-ended differential setups, well floating mixing input signals. also includes digitally controlled stereo microphone preamplifier integrated microphone bias. Digital signal processing blocks remove audible noise that introduced mechanical coupling (for example, optical zooming digital camera). playback path offers signal-processing blocks filtering effects, supports flexible mixing analog input signals well programmable volume controls. playback path four ground-referenced capacitor-free output drivers support single-ended headphone receivers. fully differential ground-centered line output drivers also available. extensive power-management unit with integral charge pump three programmable LDOs available create positive negative analog supply voltages required TLV320AIC36 from single positive 2.1-V 2.8-V supply. Alternatively, charge pump LDOs individually bypassed support wide variety power supply configurations. required internal clock TLV320AIC36 derived from multiple sources, including MCLK pin, BCLK pin, GPIO pin, output internal PLL, where input again derived from MCLK pin, BCLK GPIO pins. Although using makes sure that suitable clock signal available, recommended lowest power settings. highly programmable accept available input clocks range MHz. device available 5-mm 5-mm, MicroStar Junior80-VFBGA package.
INTRODUCTION
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
PACKAGE SIGNAL DESCRIPTIONS
Packaging/Ordering Information
PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE -40°C 85°C ORDERING NUMBER TLV320AIC36IZQE TLV320AIC36IZQER TRANSPORT MEDIA, QUANTITY Trays, Tape reel, 2500
TLV320AIC36
BGA-80
Assignments
(ZQE) Package (Bottom View)
Figure 2-1. Assignments (not scale)
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PACKAGE SIGNAL DESCRIPTIONS
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
Functions
BALL E8,E9 C1,D2 B1,C2 H1,G3 G1,G2 NAME AVDD_ADC LINEIN_L MIC1_P MIC1_M EXTMIC_P EXTMIC_M MIC2_P MIC2_M LINEIN_R VCM_ADC GND_ADC AVDD_HP HP_COM AVSS_HP RECL GND_HP RECR AVDD_DAC GND_DAC LINEOUT_LP LINEOUT_LM LINEOUT_RP LINEOUT_RM AVSS_DAC AVDD_BIAS EXTMIC_BIAS INTMIC_BIAS DETECT HOOK GND_BIAS AVDD_CP GND_CP FC_POS FC_NEG AVDD_REG GND_REG AVSS_REG AVDD1 AVSS1 AVDD2 BCLK WCLK DOUT Positive supply Left line input Internal input (plus) Internal input (minus) External input (plus) External input (minus) Internal input (plus) Internal input (minus) Right line input common mode level Analog ground Positive supply headphone amps Left headphone output Headphone common (signal ground) Right headphone output Negative supply headphone amps Left receiver Signal ground receiver amps Right receiver Positive supply lineout amps Signal ground Left line output (Pos) Left line output (Neg) Right line (Pos) Right line (Neg) Negative supply lineout amps Supply bias detect blocks Bias voltage external microphone Bias voltage internal microphone Microphone impedance detect Hookswitch detect Ground bias detect blocks Charge pump supply Charge pump ground Flying capacitor charge pump Flying capacitor charge pump Positive regulator supply input Regulator ground Negative regulator supply input/charge pump output Primary positive output (DAC LDO) Primary negative output (DAC LDO) Secondary positive output (ADC LDO) Audio serial clock Audio serial word clock Audio serial data input (DAC Data) Audio serial data output (ADC Data) Submit Documentation Feedback DESCRIPTION
PACKAGE SIGNAL DESCRIPTIONS
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
Functions (continued)
BALL H5,B5 J4,A2 D5,E6,E4,F4 NAME I2C_ADR1 I2C_ADR0 MCLK GPIO1 GPIO2 GPIO3/DIGMIC_CLK GPIO4/DIGMIC_DATA GPIO5/BITSTREAM_CLK RESETB DVDD DVSS IOVDD serial clock data address address Master clock Interrupt request/GPIO External amplifier power control/GPIO/Secondary serial WCLK Clock digital mic/GPIO/Secondary serial BCLK/PLL Clock Output Data from digital mic/GPIO/Secondary serial Clock class-D amp/GPIO Reset Core digital supply Digital Ground digital supply Substrate ground. Connect analog ground Reserved connect DESCRIPTION
GPIO6/BITSTREAM_DATA Data class-D amp/GPIO
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PACKAGE SIGNAL DESCRIPTIONS
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
Supply voltage range
VALUE AVDD_REG, AVDD_CP, AVDD_BIAS AVSS_REG AVDD_DAC, AVDD_ADC, AVDD_AMP other AVSS DVDD IOVDD Voltage between Digital input voltage DVSS Analog input voltage Operating free-air temperature range, Storage temperature range Junction temperature, TJMAX Power dissipation Thermal impedance, package, Ratings Pins Pins except following: IOVDD, AVDD_BIAS, HOOK, VCM_ADC AVDD_HP, LINEIN_L, LINEIN_R, MIC1_P, MIC1_M, EXTMIC_P, EXTMIC_M, MIC2_P, MIC2_M, AVDD_ADC AGND DGND AVDD DVDD -0.5 -3.6 +0.5 -0.5 +1.8 -1.8 +0.5 -0.5 1.95 -0.5 -0.3 -3.6 -0.3 IOVDD -0.3-AVSS AVDD +105 (TJMax TA)/JA
UNIT °C/W
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. AVDD_REG-AVSS_REG must less than 5.6V.
Recommended Operating Conditions
-2.5 1.65 -1.65 -2.8 -1.8 1.95 UNIT
SUPPLIES AVDD_CP AVDD_BIAS AVDD_REG AVSS_REG AVDD_ADC AVDD_DAC, AVDD_HP AVSS_DAC, AVSS_HP DVDD IOVDD Operating free-air temperature Charge pump supply voltage bias supply voltage Positive regulator input voltage Negative regulator input voltage Positive supply voltages
-1.7 1.65
Positive supply voltages Negative supply voltages Digital supply voltage Output driver supply voltage
-1.4 1.65
Valid lowest power mode when bypassing negative regulator. Otherwise, MIN=2.1V. Minimum bias voltage Only relevant charge pump used Only relevant charge pump voltage regulators used AVDD_ADC, DVDD =1.4V power modes (see section 5.18.3)
ELECTRICAL SPECIFICATIONS
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
Electrical Characteristics Channel
25°C, AVDD_REG=AVDD_CP IOVDD DVDD 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER Full-scale input signal, differential inputs Full-scale input, single ended Signal-to-noise ratio, inputs Signal-to-noise ratio, line inputs Dynamic range, inputs
CONDITIONS gain gain gain gain
UNITS VRMS VRMS
gain gain gain, input 1-kHz gain, input 1-kHz 1-kHz, single-ended input 1-kHz, differential input 10-kHz, differential input 1-kHz, single-ended input 1-kHz, differential input gain, input 1-kHz gain, 1-kHz input
59.5
Total harmonic distortion, line, internal mic, external inputs PSRR, inputs
PSRR, inputs, unregulated Channel separation Gain error Programmable Gain Amplifier (PGA) maximum gain gain step Input resistance, line inputs Input resistance, inputs Input capacitance, inputs DIGITAL DECIMATION FILTER Filter gain from 0.39 Filter gain 0.4125 Filter gain 0.45 Filter gain Filter gain from 0.55 Filter group delay MICROPHONE BIAS GENERATORS
input gain input gain input gain input gain
-0.25 -17.5 17/Fs
Bias voltage Current sourcing Power supply rejection ratio
Programmable settings, load 1-kHz
Ratio output level with 1-kHz full-scale sine wave input, output level with inputs short circuited, measured weighted over 20-Hz 20-kHz bandwidth using audio analyzer. performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure such filter result higher THD+N lower dynamic range readings than shown Electrical Characteristics. low-pass filter removes out-of-band noise, which, although audible, affect dynamic specification values. input gain, gain input gain, gain AVDD_DAC AVSS_DAC connected directly supply Channel separation input connected left channel other input connected right channel Default filter configuration
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ELECTRICAL SPECIFICATIONS
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
Electrical Characteristics Channel
25°C, AVDD AVDD_REG=AVDD_CP IOVDD DVDD 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER DIGITAL INTERPOLATION FILTER Passband Passband ripple Transition band Stopband Stopband attenuation Group delay LINE OUTPUTS LOAD DIFFERENTIAL Full-scale output voltage Maximum output level gain setting Output level gain setting step Signal-to-noise ratio Dynamic range Total harmonic distortion PSRR Channel separation Gain mismatch Gain error RECEIVER HEADPHONE OUTPUTS Full-scale output voltage Full-scale output power Maximum output level gain setting Output level gain setting step Signal-to-noise ratio
CONDITIONS High-pass filter disabled High-pass filter disabled
UNIT VRMS
0.06 21/Fs
gain
1.414
gain, A-weighted, Full-scale output 1-kHz gain, A-weighted, input gain, Full-scale output gain, Full-scale input
-100 -0.4
VRMS
gain gain, full-scale output kHz, load
0.707
gain, A-weighted, Full-scale output gain, full-scale output kHz, load gain, output kHz, load gain, full-scale output kHz, load gain, output kHz, load gain, full-scale output output
Total harmonic distortion
PSRR Channel separation Mute attenuation
Default filter configuration Ratio output level with 1-kHz full-scale sine wave input, output level playing all-zero signal, measured A-weighted over 20-Hz 20-kHz bandwidth using audio analyzer. Measurements performed with stereo signals phase.
ELECTRICAL SPECIFICATIONS
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
Electrical Characteristics Power
25°C, AVDD_REG=AVDD_CP IOVDD DVDD 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER SUPPLY CURRENT Mono channel, Stereo channel, Stereo channel, Stereo headphone, Stereo headphone (2), AVDD_2P5 DVDD AVDD_2P5 DVDD AVDD_2P5 DVDD AVDD_2P5 DVDD AVDD_HP, AVDD_DAC AVSS_HP, AVSS_DAC DVDD Stereo headphone, Power Mode Stereo headphone, Ultra Power Mode Stereo line lineout Power down AVDD_2P5 DVDD AVDD_2P5 DVDD AVDD_2P5 DVDD AVDD_ADC DVDD AVDD_2P5 DVDD Additional power consumed when powered supply voltages applied, blocks programmed lowest power state Quiescent current signal) 1.5V operation. section 5.18.3. 1.8V operation. section 5.18.3. Quiescent current signal) Quiescent current signal) off, off, off, 10.4 -4.1 CONDITIONS UNIT
Charge pump regulators used. Charge pump regulators used. AVSS_HP=AVSS_DAC=-1.65
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ELECTRICAL SPECIFICATIONS
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
Electrical Characteristics
PARAMETER TEST CONDITIONS IOVDD 5µA, IOVDD <1.6 5µA, IOVDD IOVDD IOVDD IOVDD -0.3 IOVDD IOVDD IOVDD IOVDD Rate CMOS UNIT
25°C, DVDD
LOGIC FAMILY Logic level
IOVDD 5µA, IOVDD <1.6 5µA, IOVDD
Capacitive load CLOCK INPUT MCLK tw(H) tw(L) Clock pulse width high Clock pulse width Setup relative DIGMIC_CLK edge Hold relative DIGMIC_CLK edge
loads loads
DIGMIC INPUT
ELECTRICAL SPECIFICATIONS
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
3.6.1
Timing Audio Data Serial Interface Timing
WCLK td(WS) BCLK td(DO-WS) DOUT tS(DI) I2S/LJF Timing Master Mode th(DI) td(DO-BCLK)
NOTE: numbers from characterization tested final production.
Figure 3-1. I2S/LJF/RJF Timing Master Mode
3.6.2
TYPICAL TIMING CHARACTERISTICS (see Figure 3-1)
specifications 25°C, DVdd 1.8V
Table 3-1. I2S/LJF/RJF Timing Master Mode
PARAMETER td(WS) td(DO-WS) td(DO-BCLK) ts(DI) th(DI) WCLK delay WCLK DOUT delay (for Mode only) BCLK DOUT delay setup hold Rise time Fall time IOVDD=1.8 IOVDD=3.3 UNITS
Note: timing specifications measured characterization tested final test.
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ELECTRICAL SPECIFICATIONS
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
WCLK th(WS) BCLK tL(BCLK) tP(BCLK) DOUT ts(DI) th(DI) tH(BCLK) (DO-BCLK) td(DO-WS) th(WS)
Figure 3-2. I2S/LJF/RJF Timing Slave Mode
3.6.3
TYPICAL TIMING CHARACTERISTICS (see Figure 3-2)
specifications 25°C, DVdd 1.8V
Table 3-2. I2S/LJF/RJF Timing Slave Mode
PARAMETER BCLKH(BCLK) BCLKL(BCLK) ts(WS) th(WS) td(DO-WS) td(DO-BCLK) ts(DI) th(DI) BCLK high period BCLK period WCLK setup WCLK hold WCLK DOUT delay (for mode only) BCLK DOUT delay setup hold Rise time Fall time IOVDD=1.8 IOVDD=3.3 UNITS
Note: timing specifications measured characterization tested final test.
ELECTRICAL SPECIFICATIONS
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
WCLK td(WS) td(WS)
BCLK td(DO-BCLK) DOUT ts(DI) th(DI)
Figure 3-3. Timing Master Mode
3.6.3.1 Typical Timing Characteristics (see Figure 3-3)
specifications 25°C, DVdd
Table 3-3. Timing Master Mode
PARAMETER td(WS) td(DO-BCLK) ts(DI) th(DI) WCLK delay BCLK DOUT delay setup hold Rise time Fall time IOVDD=1.8 IOVDD=3.3 UNITS
Note: timing specifications measured characterization tested final test.
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ELECTRICAL SPECIFICATIONS
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
WCLK
th(ws) ts(ws) th(ws) th(ws)
BCLK
tH(BCLK) tP(BCLK)
tL(BCLK) td(DO-BCLK)
DOUT
ts(DI) th(DI)
Figure 3-4. Timing Slave Mode
3.6.3.2 Typical Timing Characteristics (see Figure 3-4)
specifications 25°C, DVdd
Table 3-4. Timing Slave Mode
PARAMETER tH(BCLK) tL(BCLK) ts(WS) th(WS) td(DO-BCLK) ts(DI) th(DI) BCLK high period BCLK period WCLK setup WCLK hold BCLK DOUT delay setup hold Rise time Fall time IOVDD=1.8 IOVDD=3.3 UNITS
Note: timing specifications measured characterization tested final test.
ELECTRICAL SPECIFICATIONS
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
3.6.4
Interface Timing
Figure 3-5. Table 3-5. INTERFACE TIMING
PARAMETER fSCL tHD;STA clock frequency Hold time (repeated) START condition. After this period, first clock pulse generated. period clock HIGH period clock Setup time repeated START condition Data hold time: devices Data set-up time rise time fall time Set-up time STOP condition free time between STOP START condition Capacitive load each line
TEST CONDITION
Standard-Mode
Fast-Mode
UNITS
tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF
1000 3.45
20+0.1Cb 20+0.1Cb
Electrical Characteristics Channel Ultra Power Mode
25°C, AVDD_REG=AVDD_CP IOVDD DVDD 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER Full-scale input signal, differential inputs Full-scale input, single ended Signal-to-noise ratio, inputs
CONDITIONS gain gain gain gain gain gain gain, input 1-kHz gain, input 1-kHz
0.25
UNITS VRMS VRMS
Signal-to-noise ratio, line inputs Dynamic range, inputs Total harmonic distortion, line, internal mic, external inputs
Ratio output level with 1-kHz full-scale sine wave input, output level with inputs short circuited, measured weighted over 20-Hz 20-kHz bandwidth using audio analyzer. performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure such filter result higher THD+N lower dynamic range readings than shown Electrical Characteristics. low-pass filter removes out-of-band noise, which, although audible, affect dynamic specification values. input gain, gain input gain, gain ELECTRICAL SPECIFICATIONS
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
Electrical Characteristics Channel Ultra Power Mode (continued)
25°C, AVDD_REG=AVDD_CP IOVDD DVDD 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER PSRR, inputs, unregulated Channel separation Gain error Programmable Gain Amplifier (PGA) gain step Input resistance, line inputs Input resistance, inputs Input capacitance, inputs DIGITAL DECIMATION FILTER Filter gain from 0.39 Filter gain 0.4125 Filter gain 0.45 Filter gain Filter gain from 0.55 Filter group delay MICROPHONE BIAS GENERATORS Bias voltage Current sourcing Power supply rejection ratio 1-kHz Programmable settings, load
CONDITIONS 1-kHz, single-ended input 1-kHz, differential input gain, input 1-kHz gain, 1-kHz input maximum gain input gain input gain input gain input gain
59.5 -0.25 -17.5 17/Fs
UNITS
AVDD_DAC AVSS_DAC connected directly supply Channel separation input connected left channel other input connected right channel Default filter configuration
Electrical Characteristics Channel Ultra Power Mode
25°C, AVDD AVDD_REG=AVDD_CP IOVDD DVDD 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER DIGITAL INTERPOLATION) FILTER Passband Passband ripple Transition band Stopband Stopband attenuation Group delay LINE OUTPUTS LOAD DIFFERENTIAL Full-scale output voltage Maximum output level gain setting Output level gain setting step Signal-to-noise ratio Dynamic range gain, A-weighted, Full-scale output 1-kHz gain, A-weighted, input gain VRMS High-pass filter disabled High-pass filter disabled 21/Fs 0.06 CONDITIONS UNIT
Default filter configuration Ratio output level with 1-kHz full-scale sine wave input, output level playing all-zero signal, measured A-weighted over 20-Hz 20-kHz bandwidth using audio analyzer. ELECTRICAL SPECIFICATIONS Submit Documentation Feedback
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
Electrical Characteristics Channel Ultra Power Mode (continued)
25°C, AVDD AVDD_REG=AVDD_CP IOVDD DVDD 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER Total harmonic distortion PSRR Channel separation Gain mismatch Gain error RECEIVER HEADPHONE OUTPUTS Full-scale output voltage Full-scale output power Maximum output level gain setting Output level gain setting step Signal-to-noise ratio
CONDITIONS gain, Full-scale output gain, Full-scale input
-0.4
UNIT VRMS
gain gain, full-scale output kHz, load
gain, A-weighted, Full-scale output gain, full-scale output kHz, load gain, output kHz, load gain, full-scale output kHz, load gain, output kHz, load
Total harmonic distortion
PSRR Channel separation Mute attenuation
gain, full-scale output output
Measurements performed with stereo signals phase.
TYPICAL CHARACTERISTICS
Typical Performance
CHANNEL GAIN
TOTAL HARMONIC DISTORTION HEADPHONE OUTPUT POWER
Total Harmonic Distortion
Signal-to-Noise Ratio
single ended single ended differential differential
Channel Gain
Headphone Output Power
Figure 4-1.
Figure 4-2.
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TYPICAL CHARACTERISTICS
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
CHANGE MICBIAS VOLTAGE MICBIAS LOAD
Change Output Voltage
-100
-120
Load Current
Figure 4-3.
MIC1 GAIN, mVrms into ohms
MIC1 GAIN, mVrms into ohms
Amplitude dBVrms
Amplitude dBVrms
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 Frequency
-100
-100
-120 -140
-120 -140
2000
4000 6000
8000 10000 12000 14000 16000 18000 20000 Frequency
Figure 4-4.
Figure 4-5.
TYPICAL CHARACTERISTICS
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
MIC1 DIFFERENTIAL INPUT dBFS
MIC1 LINEOUT GAIN mVrms into
Amplitude dBFS/bin
Amplitude dBVrms
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 Frequency
-100
-100
-120 -140
-120 -140
2000
4000 6000
8000 10000 12000 14000 16000 18000 20000 Frequency
Figure 4-6. MIC1 LINE GAIN, Vrms into
Figure 4-7. PLAYBACK HEADPHONE, gain, Vrms into
Amplitude dBVrms
Amplitude
-100
-100 -120 -140 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 Frequency -120 -140 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 Frequency
Figure 4-8.
Figure 4-9.
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TYPICAL CHARACTERISTICS
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
PLAYBACK LINE-OUT, Vrms into
CHANGE AVDD1 VOLTAGE LOAD
Change output Voltage
Amplitude dBVrms
-100 -120 -140
2000
4000 6000
8000 10000 12000 14000 16000 18000 20000 Frequency
Load Current
Figure 4-10. AVDD1 DROPOUT VOLTAGE LOAD CURRENT
Figure 4-11.
Dropout Voltage
Load Current
Figure 4-12.
TYPICAL CHARACTERISTICS
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
APPLICATION INFORMATION
Typical Circuit Configuration
Host Processor
RESETB
MCLK
BCLK
WCLK
DOUT EXT_MICBIAS
GPIO1 GPIO2
DETECT EXTMIC_P
EXTMIC_M GPIO3/DIGMIC_CLK
General Purpose
GPIO4/DIGMIC_DATA GPIO5/BITSTREAM_CLK GPIO6/BITSTREAM_DATA HOOK HP_COM INT_MICBIAS
Earjack, Microphone Headset Speakers
MIC1_P MIC1_M
TLV320AIC36
TPA2012 Class
LINEOUT_LP
4700
MIC2_P
LINEOUT_LM
MIC2_M LINEOUT_RP
4700
LINEOUT_RM
LINEIN_L
Line In/FM
RECL
LINEIN_R
RECR
Figure 5-1. Typical Circuit Configuration
Overview
TLV320AIC36 offers wide range configuration options. Figure shows basic functional blocks device.
5.2.1
Digital Pins
Only small number digital pins dedicated single function; whenever possible, digital pins have default function, also reprogrammed cover alternative functions various applications. fixed-function pins RESETB, SDA, SCL, DIN, I2C_ADDR1, I2C_ADDR0, MCLK. Other digital pins such GPIO1-GPIO6, BCLK, WCLK, DOUT, configured various functions using register control.
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APPLICATION INFORMATION
TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
5.2.2
Analog Pins
Analog functions also configured large degree. minimum power consumption, analog blocks powered down default. blocks powered with fine granularity according application needs. possible analog routings analog input pins ADCs output amplifiers well routing from DACs output amplifiers seen Figure 5-2.
5.2.3
Power Supply
TLV320AIC36 power management unit generates analog supply voltages from single nominal supply. power management unit consists positive LDOs, which generates nominal +1.75 supply input section another which generates nominal +1.65 audio amplifier section. negative charge pump generates unregulated negative voltage from unregulated positive supply; negative generates nominal -1.65 supply audio amplifier section from this unregulated negative voltage. Figure 5-48 details typical power supply connections.
5.2.4
Clocking
minimize power consumption, system ideally provides master clock that suitable integer multiple desired sampling frequencies. such cases, internal dividers programmed required internal clock signals very power consumption. cases where such master clocks available, built-in used generate clock signal that serves internal master clock. fact, this master clock also routed output used elsewhere system. clock system flexible enough that allows internal clocks derived directly from external clock source, while generates other clock that used only outside TLV320AIC36.
miniDSP
TLV320AIC36 features miniDSP cores. first miniDSP core tightly coupled ADC, second miniDSP core tightly coupled DAC. fully programmable algorithms miniDSP must loaded into device after power miniDSPs have direct access digital stereo audio stream side, offering possibility advanced, very group delay algorithms.
5.3.1
Software
Software development TLV320AIC36 supported through TI's comprehensive PurePath Studio Development Environment. powerful, easy-to-use tool designed specifically simplify software development miniDSP audio platform. Graphical Development Environment consists library common audio functions that dragged-and-dropped into audio signal flow graphically connected together. code then assembled from graphical signal flow with click mouse. Visit TLV320AIC36 product folder www.ti.com learn more about PurePath Studio latest status available, ready-to-use algorithms.
APPLICATION INFORMATION
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
Analog Routing
output Gains positive steps output Volume Gains 0.5dB steps Volume -78dB) DAC_L DAC_R LINEIN_L LINEIN_R PGA_L PGA_R (P2R54) (P2R57) (P2R52) (P2R55) (P2R53) (P2R56) Common Controls: Protection: (P2R38) Gain Soft-Stepping: (P2R40) Reduction: (P2R42) Gain: Open Circuit Detect (P2R58) (P2R108)
Gain: (P2R51)
(F7)
Volume -78dB) DAC_L DAC_R LINEIN_L LINEIN_R PGA_L PGA_R (P2R47) (P2R50) (P2R45) (P2R48) (P2R46) (P2R49)
Open Circuit Detect (P2R108)
(F9)
(P2R40) Input (P1R52)
LINEIN MIC1_P (J6) EXTMIC (H7)
LINEIN_L MIC1_P EXTMIC_P
(J8)
Gain: +46.5
(P2R36)
MIC1_M (H6)
MIC1_M EXTMIC_M VCM_ADC (P1R59)
(E7)
DAC_L DAC_R LINEIN_L LINEIN_R PGA_L PGA_R RECL Volume -78dB) (P2R61) (P2R64) (P2R59) (P2R62) (P2R60) (P2R63) Gain: (P2R65) Open Circuit Detect (P2R108)
Gain: (P2R72)
RECL (D8)
(P1R10)
Input (P1R54) Input (P1R57) VCM_ADC
VCM_ (J9)
miniDSP
miniDSP
(P2R37 Current Ctrl (P2R107
DAC_L DAC_R LINEIN_L LINEIN_R PGA_L PGA_R
RECR Volume -78dB) (P2R68) (P2R71) (P2R66) (P2R69) (P2R67) (P2R70)
Open Circuit Detect (P2R108)
EXTMIC (J7) MIC2
EXTMIC_M MIC2_M
(P1R60)
RECR
EXTMIC_P
(H8) LINEIN
MIC2_P LINEIN_R Input (P1R55)
Gain: +46.5
(P2R40)
LINEOUT_L Volume -78dB) DAC_L DAC_R LINEIN_L LINEIN_R PGA_L PGA_R (P2R82) (P2R85) (P2R80) (P2R83) (P2R81) (P2R84)
Gain:
(P2R86)
LINEOUT LINEOUT (A7)
LINEOUT_R Volume -78dB) DAC_L DAC_R LINEIN_L LINEIN_R PGA_L PGA_R (P2R89) (P2R92) (P2R87) (P2R90) (P2R88) (P2R91)
Gain:
(P2R93)
LINEOUT LINEOUT
Figure 5-2. Analog Routing Diagram
5.4.1
Analog Bypass
TLV320AIC36 offers analog-bypass modes, line input bypass bypass mode. these modes, LDOs must enabled. does need enabled save power
5.4.2
Line Input Bypass
This mode routes LINEINL/R output amplifiers configuring Page Register programming output amplifiers select both line inputs. Figure 5-2. Under normal bypass operation, line inputs AC-coupled LINEIN_L/LINEIN_R pins. generates internal commode mode voltage these signals before bypass amplifiers. bypass amplifiers have fixed gain single-ended output HPL_R RECL_R, 6-dB gain differential output LINEOUT_L/LINEOUT_R. save power, disabled external common mode voltage generated these pins. simple 20k/20k resistor divider from AVDD_ADC GND_ADC sufficient with some compromise performance.
5.4.3
Bypass
this mode, line input signals amplified routed output amplifiers. figure 5-2. This mode enabled selecting input mux, setting gain, programming output amplifiers select both outputs.
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must enabled supply biasing PGA. bypass amplifiers have fixed gain single-ended output HP_L/HP_R REC_L/REC_R, gain differential output LINEOUT_L/LINEOUT_R
5.4.4
Line Input Routing
avoid excessive internal offset, line inputs should routed Headphone Outputs whenever line inputs activated, even bypass paths Headphone Outputs needed. This accomplished writing registers Page line input-to-headphone output bypass paths needed, they muted same registers.
Device Initialization 5.5.1 Reset
TLV320AIC36 internal logic must initialized known condition proper device function. initialize device default operating condition, hardware reset (RESETB) must pulled least this initialization work, IOVDD DVdd supplies must powered recommended that while DVdd supply being powered RESETB pulled low. device also reset through software writing into Page Register followed writing into Page Register After device reset, registers initialized with default values listed Register section.
5.5.2
Device Startup Lockout Times
After initialized through hardware reset power-up software reset, internal memories initialized default values. This initialization occurs within after pulling RESETB signal high. During this initialization phase, Register read Register write operation should performed coefficient buffers. Also, block within codec should powered during initialization phase.
5.5.3
Startup
Whenever powered startup delay approximately involved after power command before clocks available codec. This delay enables stable operation clock-divider logic.
5.6.1 Concept
TLV320AIC36 includes stereo audio ADC, which uses delta-sigma modulator with programmable oversampling ratio, followed digital decimation filter. supports sampling rates from kHz. provide optimal system power management, stereo powered channel time, support case where only mono record capability required. addition, both channels fully powered entirely powered down. Because oversampling nature audio integrated digital decimation filtering, requirements analog anti-aliasing filtering very relaxed. TLV320AIC36 integrates second-order analog anti-aliasing filter with 28-dB attenuation MHz. This filter, combined with digital decimation filter, provides sufficient anti-aliasing filtering without requiring additional external components.
5.6.2
Routing
shown Figure 5-2, TLV320AIC36 includes eight analog inputs that connected fully differential input amplifiers (one ADC/PGA channel). turning only switches amplifier time, inputs effectively multiplexed each ADC/PGA channel. turning multiple sets switches amplifier time, audio sources mixed.
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most applications, high-input impedance desired analog inputs. However when used with high gain, case microphone inputs, higher-input impedance results higher noise lower dynamic range. TLV320AIC36 gives user flexibility choosing input impedance from 10k, 40k. When multiple inputs mixed together, choosing different input impedances, level adjustment achieved. example, input selected with input impedance second input selected with input impedance, then second input attenuated half compared first input. This input level control intended volume control, instead used level setting. Mixing multiple inputs easily lead outputs that exceed range internal amplifiers, resulting saturation clipping mixed output signal. Whenever mixing being implemented, system designer advised take adequate precautions avoid such saturation from occurring. general, mixed (summed) signal should exceed Typically, voice audio signal inputs capacitively coupled device. This allows device independently common mode input signals values chosen register control Page Register D(6) either 0.75 correct value maximizes dynamic range across entire analog-supply range. Failure capacitively connect input device cause high offset mismatch source common-mode device common-mode setting. extreme cases could also saturate analog channel, causing distortion.
Gain Setting
Input Selection Analog Filtering Analog Gain Digital Volume Control Digital Gain Adjust Frequency Response/ Gain
Audio Interface
Fully Programmable Coefficients
0.47.5 Step
Step
-0.4 Step
When gain channel kept common mode 0.75 single-ended input 0.375 VRMS results full-scale digital signal output channel. Similarly, when gain kept common mode single-ended input VRMS results full-scale digital signal output channel. However various block functions control gain through channel. gain applied described Table 5-1. Additionally, digital volume control adjusts gain through channel, described Section 5.7.2. finer level gain controlled fine gain control, described Section 5.7.3. decimation filters along with delta-sigma modulator contribute gain through channel.
5.7.1
Analog
TLV320AIC36 features built-in low-noise boosting low-level signals, such direct microphone inputs, full-scale achieve high SNR. This provide gain range 47.5 single-ended inputs 53.5 fully differential inputs (gain calculated with respect input impedance setting 10k; input impedance will result lower will result lower gain). This gain user controlled writing Page Register Page Register mode this gain also automatically controlled built-in hardware AGC.
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Table 5-1. Analog Input Configuration
Page Register D(6:0) Page Register D(6:0) 0000 0001 0010 1110 1111 EFFECTIVE GAIN APPLIED SINGLE-ENDED 47.0 47.5 -5.5 -5.0 41.0 41.5 -11.5 -11.0 35.0 35.5 DIFFERENTIAL 53.0 53.5 47.0 47.5 -6.0 -5.5 -5.0 41.0 41.5
gain changes implemented with internal soft-stepping algorithm that only changes actual volume level 0.5-dB step every output samples, depending register value (see registers Page D(1:0)). This soft-stepping enables smooth volume-control changes with audible artifacts. reset, gain defaults mute condition, power down, soft-steps volume mute before shutting down. read-only flag Page D(7) D(3) whenever gain applied equals desired value register. soft-stepping control also disabled programming Page D(1:0).
5.7.2
Digital Volume Control
TLV320AIC36 also digital volume-control block with range from steps 0.5-dB. programming Page Register respectively, left right channels. Table 5-2. Digital Volume Control
Desired Gain (dB) -12.0 -11.5 -11.0 -0.5 +0.5 +19.5 +20.0 0111 1000 1111 0000 (default) 0001 Left/Right Channel Page Register 83/84, D(6:0) 1000 1001 1010
During volume control changes, soft-stepping feature used avoid audible artifacts. soft-stepping rate either gain steps sample. Soft-stepping also entirely disabled. This soft-stepping configured using Page Register D(1:0), common soft-stepping control analog PGA. During power-down channel, this volume control soft-steps down -12.0 before powering down. soft-stepping control, soon after changing volume control setting powering down channel, actual applied gain different from programmed through control register. TLV320AIC36 gives feedback user, through read-only flags Page D(7) Left Channel Page D(3) right channel.
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5.7.3
Fine Digital Gain Adjustment
Additionally, gains each channels finely adjustable steps This useful when trying match gain between channels. programming Page Register gain adjusted from -0.4 steps This feature, combination with regular digital volume control allows gains through left right channels matched range -0.5 +0.5 with resolution
5.7.4
TLV320AIC36 includes Automatic Gain Control (AGC) recording. used maintain nominally-constant output level when recording speech. opposed manually setting gain, mode, circuitry automatically adjusts gain input signal becomes overly loud very weak, such when person speaking into microphone moves closer farther from microphone. algorithm several programmable parameters, including target gain, attack decay time constants, noise threshold, applicable, that allow algorithm fine tuned particular application. algorithm uses absolute average signal (which average absolute value signal) measure nominal amplitude output signal. Since gain changed sample interval time, algorithm operates sample rate. Target level represents nominal output level which attempts hold output signal level. TLV320AIC36 allows programming eight different target levels, which programmed from -5.5 relative full-scale signal. Since TLV320AIC36 reacts signal absolute average peak levels, recommended that target level with enough margin avoid clipping occurrence loud sounds. Attack time determines quickly circuitry reduces gain when output signal level exceeds target level increase input signal level. Wide range attack time programmability supported terms number samples (i.e. number sample frequency clock cycles). Decay time determines quickly gain increased when output signal level falls below target level reduction input signal level. Wide range decay time programmability supported terms number samples (i.e., number sample frequency clock cycles). Noise threshold determines level below which input signal level falls, considers silence, thus brings down gain steps every sets noise threshold flag. gain stays unless input speech signal average rises above noise threshold setting. This that noise 'gained absence speech. Noise threshold level algorithm programmable from full-scale. When Noise Threshold microphone input applicable setting must greater than equal 11.5 21.5 31.5 respectively. This operation includes hysteresis debounce avoid gain from cycling between high gain when signals near noise threshold level. noise silence) detection feature entirely disabled user. applicable allows designer restrict maximum gain applied AGC. This used limiting gain situations where environmental noise greater than programmed noise threshold. Microphone input programmed from 63.5 steps Hysteresis, name suggests, determines window around Noise Threshold which must exceeded either detect that recorded signal indeed noise signal. initially energy recorded signal greater than Noise Threshold, then recognizes noise only when energy recorded signal falls below Noise Threshold value given Hysteresis. Similarly, after recorded signal recognized noise, recognize signal, energy must exceed Noise Threshold value given Hysteresis setting. order prevent from jumping between noise signal states, (which happen when energy recorded signal very close Noise threshold) non-zero hysteresis value should chosen. Hysteresis feature also disabled.
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Debounce time (noise signal) determines hysteresis time domain noise detection. continuously calculates energy recorded signal. calculated energy less than Noise Threshold, then does increase input gain achieve Target Level. However, handle audible artifacts which occur when energy input signal very close Noise Threshold, checks energy recorded signal less than Noise Threshold time greater than Noise Debounce Time. Similarly starts increasing input-signal gain reach Target Level when calculated energy input signal greater than Noise Threshold. Again, avoid audible artifacts when input-signal energy very close Noise Threshold, energy input signal needs continuously exceed Noise Threshold value Signal Debounce Time. debounce times kept very small, then audible artifacts result rapidly enabling disabling function. same time, Debounce time kept large, then take time respond changes levels input signals with respect Noise Threshold. Both noise signal debounce time disabled. noise threshold flag read-only flag indicating that input signal levels lower than Noise Threshold, thus detected noise silence). such condition applies gain Gain applied read-only register setting which gives real-time feedback system gain applied recorded signal. This, along with Target Setting, used determine input signal level. steady state situation Target Level (dB) Gain Applied (dB) Input Signal Level (dB) When noise threshold flag set, then status gain applied should ignored. saturation flag read-only flag indicating that output signal reached Target Level. However, unable increase gain further because required gain higher than Maximum Allowed gain. Such situation happen when input signal very energy Noise Threshold also very low. When noise threshold flag set, status saturation flag should ignored. saturation flag read-only flag indicating overflow condition channel. overflow, signal clipped distortion results. This typically happens when Target Level kept very high energy input signal increases faster than Attack Time. low-pass filter used help determine average level input signal. This average level compared programmed detection levels provide correct functionality. This low-pass filter form first-order filter. 8-bit registers used form 16-bit digital coefficient shown register map. this way, total ofsix registers programmed form three coefficients. transfer function filter implemented signal level detection given
(5-1)
Where: Coefficient programmed writing into Page Registers Coefficient programmed writing into Page Registers Coefficient programmed writing into Page Registers 16-bit complement numbers their default values implement low-pass filter with cut-off 0.002735*ADC_FS. Table various programming options. used only analog microphone input routed channel. Table 5-3. Parameter Settings
Function enable Target level Control Register Left Page Register Page Register Control Register Right Page Register Page Register D(7) D(6:4)
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Table 5-3. Parameter Settings (continued)
Function Hysteresis Noise threshold applicable Time constants (attack time) Time constants(decay time) Debounce time (Noise) Debounce time (Signal) Gain applied Noise Threshold Flag Saturation flag Saturation flag Control Register Left Page Register Page Register Page Register Page Register Page Register Page Register Page Register Page Register Page Register (sticky flag), Page Register (nonsticky flag) Page Register (sticky flag) Page Register (sticky flag), Page Register (nonsticky flag) Control Register Right Page Register Page Register Page Register Page Register Page Register Page Register Page Register Page Register Page Register (sticky flag), Page Register (nonsticky flag) Page Register (sticky flag) Page Register (sticky flag), Page Register (nonsticky flag) D(7:6) D(5:1) D(6:0) D(7:0) D(7:0) D(4:0) D(3:0) D(7:0) (Read Only) D(3:2) (Read Only) D(5), D(1) (Read Only) D(4:3) (Read Only)
Input Signal
Output Signal
Target Level
Gain Decay Time Attack Time
Figure 5-3. Characteristics
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Decimation Filtering Signal Processing
TLV320AIC36 channel includes built-in digital decimation filter process oversampled data from sigma-delta modulator generate digital data Nyquist sampling rate with high dynamic range. decimation filter chosen from three different types, depending required frequency response, group delay sampling rate.
5.8.1
Processing Blocks
TLV320AIC36 offers range processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users choice much what type signal processing they which decimation filter applied. choice between these processing blocks part strategy balance power conservation signal-processing flexibility. Less signal-processing capability reduces power consumed device. Table gives overview available processing blocks channel their properties. Resource Class (RC) Column gives approximate indication power consumption. Page Register used select processing blocks. signal processing blocks available are: First-order Scalable number biquad filters Variable-tap filter processing blocks tuned common cases achieve high anti-alias filtering low-group delay combination with various signal processing effects such audio effects frequency shaping. available first-order IIR, BiQuad, filters have fully user programmable coefficients. Table 5-4. Processing Blocks
Processing Blocks PRB_R1 PRB_R2 PRB_R3 PRB_R4 PRB_R5 PRB_R6 PRB_R7 PRB_R8 PRB_R9 PRB_R10 PRB_R11 PRB_R12 PRB_R13 PRB_R14 PRB_R15 PRB_R16 PRB_R17 PRB_R18
Channel Stereo Stereo Stereo Right Right Right Stereo Stereo Stereo Right Right Right Stereo Stereo Stereo Right Right Right
Decimation Filter
First-Order Available
Number BiQuads
25-Tap 25-Tap 20-Tap 20-Tap 25-Tap 25-Tap
Required AOSR Value 128,64 128,64 128,64 128,64 128,64 128,64
Resource Class
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5.8.2
Processing Blocks Details
5.8.2.1 First-Order IIR, AGC, Filter
From Delta-Sigma Modulator Digital Microphone Filter Order Gain Compen Sation Audio Interface
From Digital Vol. Ctrl Analog
Figure 5-4. Signal Chain PRB_R1 PRB_R4 5.8.2.2 Five Biquads, First-Order IIR, AGC, Filter
From Delta-Sigma Modulator Digital Microphone
Order Gain Compen sation
Filter
Audio Interface
From Digital Vol. Ctrl
Analog
Figure 5-5. Signal Chain PRB_R2 PRB_R5 5.8.2.3 25-Tap FIR, First-Order IIR, AGC, Filter
From Delta-Sigma Modulator Digital Microphone
Filter
25-Tap
Order
Gain Compen sation
Audio Interface
From Digital Vol. Ctrl Analog
Figure 5-6. Signal Chain PRB_R3 PRB_R6 5.8.2.4 First-Order IIR, AGC, Filter
From Delta-Sigma Modulator Digital Microphone
Filter
Order
Gain Compen sation
Audio Interface
Audio Interface
From Digital Vol. Ctrl Analog
Figure 5-7. Signal Chain PRB_R7 PRB_R10
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5.8.2.5 Three Biquads, First-Order IIR, AGC, Filter
From Delta-Sigma Modulator Digital Microphone 1stOrder Gain Compen sation Audio Interface
Filter
From Digital Vol. Ctrl Analog
Figure 5-8. Signal Chain PRB_R8 PRB_R11 5.8.2.6 20-Tap FIR, First-Order IIR, AGC, Filter
From Delta-Sigma Modulator Digital Microphone
Filter
20-Tap
Order
Gain Compen sation
Audio Interface
From Digital Vol. Ctrl Analog
Figure 5-9. Signal Chain PRB_R9 PRB_R12 5.8.2.7 First-Order IIR, AGC, Filter
From Delta-Sigma Modulator Digital Microphone Order Gain Compen sation
Filter
Audio Interface
From Digital Vol. Ctrl Analog
Figure 5-10. Signal Chain PRB_R13 PRB_R16
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5.8.2.8 Five Biquads, First-Order IIR, AGC, Filter
From Delta-Sigma Modulator Digital Microphone
Filter Order Gain Compen sation
Audio Interface
From Digital Vol. Ctrl Analog
Figure 5-11. Signal Chain PRB_R14 PRB_R17 5.8.2.9 25-Tap FIR, First-Order IIR, AGC, Filter
From Delta-Sigma Modulator Digital Microphone
Order
Filter
25-Tap
Gain Compen sation
Audio Interface
From Digital Vol. Ctrl
Analog
Figure 5-12. Signal PRB_R15 PRB_R18
5.8.3
User Programmable Filters
Depending selected processing block, different types orders digital filtering available. first-order filter always available, useful efficiently filter possible components signal. biquad section alternatively 25-tap filters available specific processing blocks. coefficients available filters arranged sequentially indexed coefficients Page coefficients these filters each 16-bits wide, two's-complement occupy consecutive 8-bit registers register space. default values please Register section.
5.8.3.1 First-Order Section transfer function first-order Filter give
(5-2)
frequency response first-order section with default coefficients flat gain Table 5-5. First-Order Filter Coefficients
Filter FIlter Coefficient First-Order Coefficient Left Channel Coefficient Right Channel (Pg4, (Pg4, (Pg4,
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5.8.3.2 Biquad Section transfer function each biquad filters given
(5-3)
frequency response each biquad section with default coefficients flat gain Table 5-6. Biquad Filter Coefficients
Filter BIQUAD FIlter Coefficient BIQUAD BIQUAD BIQUAD BIQUAD Coefficient Left Channel Coefficient Right Channel 101) 103) 105) 107) 109) 111) 113) 115) 117) 119) 121) 123) 125) 127)
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5.8.3.3 Section available processing blocks offer filters signal processing. Processing blocks PRB_R9 PRB_R12 feature 20-tap filter, while PRB_R3, PRB_R6, PRB_R15, PRB_R18 feature 25-tap filter.
Firn
PRB_R3, PRB_R6, PRB_R15 PRB_R18 PRB_R9 PRB_R12
(5-4)
coefficients filters 16-bit twos complement format correspond coefficient space listed below. There default transfer function filter. When filter used applicable coefficients must programmed. Table 5-7. Filter Coefficients
Filter Fir0 Fir1 Fir2 Fir3 Fir4 Fir5 Fir6 Fir7 Fir8 Fir9 Fir10 Fir11 Fir12 Fir13 Fir14 Fir15 Fir16 Fir17 Fir18 Fir19 Fir20 Fir21 Fir22 Fir23 Fir24 Coefficient Left Channel Coefficient Right Channel 101) 103) 105) 107) 109) 111) 113) 115) 117) 119) 121) 123) 125) 127)
5.8.4
Decimation Filter
TLV320AIC36 offers three different types decimation filters. integrated digital decimation filter removes high-frequency content down samples audio data from initial sampling rate AOSR*Fs final output sampling rate decimation filtering achieved using higher-order filter followed linear-phase filters. decimation filter cannot chosen itself, implicitly through chosen processing block. following subsections describe properties available filters
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5.8.4.1 Decimation Filter This filter intended sampling rates kHz. When configuring this filter, oversampling ratio either highest performance oversampling ratio must 128. Filter also used AOSR Table 5-8. Decimation Filter Specification
Parameter AOSR Filter Gain Pass Band Filter Gain Stop Band Filter Group Delay Pass Band Ripple, ksps Pass Band Ripple, 44.1 ksps Pass Band Ripple, ksps AOSR Filter Gain Pass Band Filter Gain Stop Band Filter Group Delay Pass Band Ripple, ksps Pass Band Ripple, 44.1 ksps Pass Band Ripple, ksps Pass Band Ripple, ksps 0.0.39 0.0.39 0.0.39 0.20
Channel Response Decimation Filter (Red line corresponds
Condition 0.0.39 0.55.64 0.0.39 0.0.39 0.0.39 0.0.39 0.55.32
Value (Typical) 0.062 17/Fs 0.062 0.05 0.05 0.062 17/Fs 0.062 0.05 0.05
Units Sec. Sec.
Magnitude
-100
Frequency Normalized w.r.t.
Figure 5-13. Decimation Filter Frequency Response
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5.8.4.2 Decimation Filter Filter intended support sampling rates oversampling ratio Table 5-9. Decimation Filter Specifications
Parameter AOSR Filter Gain Pass Band Filter Gain Stop Band Filter Group Delay Pass Band Ripple, ksps Pass Band Ripple, 44.1 ksps Pass Band Ripple, ksps Pass Band Ripple, ksps 0.0.39 0.0.39 0.0.39 0.20
Channel Response Decimation Filter (Red line corresponds
Condition 0.0.39 0.60.32
Value (Typical) ±0.077 11/Fs 0.076 0.06 0.06 0.11
Units Sec.
Magnitude
Frequency Normalized w.r.t.
Figure 5-14. Decimation Filter Frequency Response
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5.8.4.3 Decimation Filter Filter along with AOSR specially designed ksps operation ADC. pass band which extends 0.11*Fs (corresponds kHz), suited audio applications. Table 5-10. Decimation Filter Specifications
Parameter Filter Gain from 0.11 Filter Gain from 0.28 Filter Group Delay Pass Band Ripple, ksps Pass Band Ripple, 44.1 ksps Pass Band Ripple, ksps Pass Band Ripple, ksps Pass Band Ripple, ksps 0.0.11 0.0.11 0.0.11 0.0.11 0.20
Channel Response Decimation Filter (Red line corresponds
Condition 0.0.11 0.28 Fs.16
Value (Typical) ±0.033 11/Fs 0.033 0.033 0.032 0.032 0.086
Units Sec.
Magnitude
-100 -120 Frequency Normalized w.r.t.
Figure 5-15. Decimation Filter Frequency Response
5.8.5
Data Interface
decimation filter signal processing block channel passes 24-bit data words audio serial interface once every cycle Fs,ADC. During each cycle Fs,ADC, pair data words (for left right channel) passed. audio serial interface rounds data required word length interface before converting serial data different modes audio serial interface.
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Special Functions 5.9.1 Digital Microphone Function
addition supporting analog microphones, TLV320AIC36 also supports interfacing digital microphone. internal ADC_MOD_CLK available pins selected with Page Registers digital microphone clock. single-bit output external digital microphone connected GPIO1, DIGMIC_DATA, pins selected with Page Register shown Figure 5-16
LEFT FILTER
miniDSP Engine
RIGHT FILTER
ADC_MOD_CLK
DIG_MIC_IN
Selected with Page0 Registers
Selected with Page0 Register
DIGMIC_DATA
DIGMIC_CLK
DSD_DATA
DSD_CLK
GPIO1
GPIO2
GPIO1
Figure 5-16. Digital Microphone TLV320AIC36 Internally, TLV320AIC36 samples digital microphone left channel data using rising edge microphone clock right channel data using falling edge clock shown Figure 5-17.
ADC_MOD_CLK
DIG_MIC_IN
LEFT
RIGHT
LEFT
RIGHT
LEFT
RIGHT
Figure 5-17. Timing Diagram Digital Microphone Interface digital-microphone mode selectively enabled only-left, only-right, stereo channels. When digital microphone mode enabled, analog section powered down bypassed power efficiency. AOSR value channel must configured select desired decimation ratio achieved based external digital microphone properties.
5.9.2
Channel-to-Channel Phase Adjustment
TLV320AIC36 built-in feature fine-adjust phase between stereo record signals. phase compensation particularly helpful adjust delays when using dual microphones noise cancellation. This delay controlled fine amounts following fashion. Delay(7:0) Page 0/Register 85/D(7:0) Where:
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RIGHT PHASE COMP RIGHT OUT(
(5-5)
Where:
(Delay( Delay(6 AOSR
AOSR
Where function decimation filter:
Decimation Filter Type 0.25
LEFT PHASE COMP LEFT Where:
Delay AOSR
(5-6)
(5-7)
5.9.3
Measurement
TLV320AIC36 supports highly flexible measurement feature using high resolution oversampling noise-shaping ADC. This mode used when particular channel used voice/audio record function. This mode enabled programming Page Register 102, D(7:6). converted data 24-bits, using 2.22 numbering format. value converted data left-channel read back from Page Register 104-106 right-channel from Page Register 107-109.
NOTE Each group three registers must read MSB-to-LSB order (ascending register numbers) properly latch converted data.
Mode DC-measurement mode variable-length averaging filter used. length averaging filter programmed from programming Page Register 102, D(4:0). choose mode Page Register 102, D(5) must programmed Mode choose mode Page Register 102, D(5) must programmed DC-measurement mode first-order filter used. coefficients this filter determined Page Register 102, D(4:0). nature filter given Table 5-11.
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Table 5-11. Measurement Bandwidth Settings
D:Page D(4:0) (kHz) 688.44 275.97 127.4 61.505 30.248 15.004 7.472 3.729 1.862 232.6 116.3 58.1 29.1 14.54 7.25 3.63 0.908 -0.5 (kHz) 236.5 96.334 44.579 21.532 10.59 5.253 2.616 1.305 81.5 40.7 20.3 10.2 5.09 2.54 1.27 0.635 0.3165
programming Page 103, D(5) averaging filter periodically reset after number ADC_MOD_CLK, where programmed Page 103, D(4:0). When Page 103, D(5) value should less than value When Page 103, D(5) programmed averaging filter never reset.
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5.10 Setup
following discussion intended guide system designer through steps necessary configure TLV320AIC36 ADC. Step system clock source (master clock) targeted sampling frequency must identified. Depending targeted performance, decimation filter type value determined. Filter with AOSR should used 48-kHz below) high-performance operation. AOSR also used 96-kHz operation Filter with AOSR should used 96-kHz operations. Filter with AOSR should used 192-kHz operations Based identified filter type required signal processing capabilities appropriate processing block determined from list available processing blocks (PRB_R1 PRB_R18) (see Table 5-4). Based available master clock, chosen targeted sampling rate, clock divider values NADC MADC determined. necessary internal will large degree flexibility. summary, Codec_Clkin which either derived directly from system clock source from internal PLL, divided MADC, NADC AOSR, must equal sampling rate ADC_FS. Clodec_Clkin clock signal shared with clock generation block. CODEC_CLKIN NADC*MADC*AOSR*ADC_FS large degree NADC MADC chosen independently range 128. general NADC should large possible long following condition still met: MADC*AOSR/32 function chosen processing block listed Table 5-4. this point following device specific parameters known: PRB_Rx, AOSR, NADC, MADC, common mode setting Additionally used parameters determined well.
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Step Setting device through register programming: following list gives sequence items that must executed between powering device reading data from device: Define starting point: Initiate Reset
Program Settings: Turn charge pump Turn with current limit Program clock setting:s Program clock dividers J,D, necessary) Power necessary) Program power NADC Program power MADC Program value Program processing block used Program Codec Interface: word length, BCLK, WCLK I/O, mode type, example I2S/DSP
Program Analog Blocks Program common mode voltage Power Program common mode startup sequence Route inputs/common mode Unmute gains Release current limit Unmute digital volume control Section 5.20 detailed application example.
5.11
TLV320AIC36 includes stereo audio supporting data rates from 192kHz. Each channel stereo audio consists signal-processing engine with fixed processing blocks, programmable miniDSP, digital interpolation filter, multi-bit digital delta-sigma modulator, analog reconstruction filter. designed provide enhanced performance sampling rates through increased oversampling image filtering, thereby keeping quantization noise generated within delta-sigma modulator signal images strongly suppressed within audio band beyond 20kHz. handle multiple input rates optimize power dissipation performance, TLV320AIC36 allows system designer program oversampling rates over wide range from 1024 configuring Page system designer choose higher oversampling ratios lower input data rates lower oversampling ratios higher input data rates. TLV320AIC36 channel includes built-in digital interpolation filter generate oversampled data sigma delta modulator. interpolation filter chosen from three different types depending required frequency response, group delay sampling rate.
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5.11.1 Processing Blocks
TLV320AIC36 implements signal processing capabilities interpolation filtering using processing blocks. These fixed processing blocks give users choice much what type signal processing they which interpolation filter applied. choice between these processing blocks part strategy balancing power conservation signal processing flexibility. Less signal processing capability will result less power consumed device. Table 5-12 gives overview over available processing blocks channel their properties. Resource Class (RC) column gives approximate indication power consumption. Page Register used select processing blocks. signal processing blocks available are: First-order Scalable number biquad filters Effect Beep Generator processing blocks tuned common cases achieve high image rejection group delay combination with various signal processing effects such audio effects frequency shaping. available first-order biquad filters have fully user-programmable coefficients. Table 5-12. Overview Predefined Processing Blocks
Processing Block PRB_P1 PRB_P2 PRB_P3 PRB_P4 PRB_P5 PRB_P6 PRB_P7 PRB_P8 PRB_P9 PRB_P10 PRB_P11 PRB_P12 PRB_P13 PRB_P14 PRB_P15 PRB_P16 PRB_P17 PRB_P18 PRB_P19 PRB_P20 PRB_P21 PRB_P22 PRB_P23 PRB_P24 PRB_P25 Interpolation Filter Channel Stereo Stereo Stereo Left Left Left Stereo Stereo Stereo Stereo Stereo Left Left Left Left Left Stereo Stereo Stereo Left Left Left Stereo Stereo Stereo First-Order Available Number Biquads Beep Generator Class
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5.11.2 Processing Blocks Details
5.11.2.1 Three Biquads, Filter
BiQuad BiQuad BiQuad Interp. Filter
from Interface
Modulator Digital Volume Ctrl
Figure 5-18. Signal Chain PRB_P1 PRB_P4 5.11.2.2 Biquads, First-Order IIR, DRC, Filter
BiQuad BiQuad BiQuad BiQuad BiQuad BiQuad Interp Filter
from Interface
Modulator Digital Volume Ctrl
Figure 5-19. Signal Chain PRB_P2, PRB_P5, PRB_P10, PRB_P15 5.11.2.3 Biquads, First-Order IIR, Filter
BiQuad BiQuad BiQuad BiQuad BiQuad BiQuad Interp Filter
from Interface
Modulator Digital Volume Ctrl
Figure 5-20. Signal Chain PRB_P3, PRB_P6, PRB_P11, PRB_P16 5.11.2.4 IIR, Filter
Interp. Filter
from Interface
Modulator Digital Volume Ctrl
Figure 5-21. Signal Chain PRB_P7, PRB_P12, PRB_P17, PRB_P20 5.11.2.5 Four Biquads, DRC, Filter
BiQuad BiQuad BiQuad BiQuad Interp Filter
from Interface
Modulator Digital Volume Ctrl
Figure 5-22. Signal Chain PRB_P8 PRB_P13
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5.11.2.6 Four Biquads, Filter
BiQuad BiQuad BiQuad BiQuad Interp. Filter
from Interface
Modulator Digital Volume Ctrl
Figure 5-23. Signal Chain PRB_P9 PRB_P14 5.11.2.7 Four Biquads, First-Order IIR, DRC, Filter
BiQuad BiQuad BiQuad BiQuad Interp. Filter
from Interface
Modulator Digital Volume Ctrl
Figure 5-24. Signal Chain PRB_P18 PRB_P21 5.11.2.8 Four Biquads, First-Order IIR, Filter
BiQuad BiQuad BiQuad BiQuad Interp. Filter
from Interface
modulator Digital Volume Ctrl
Figure 5-25. Signal Chain PRB_P19 PRB_P22 5.11.2.9 Biquads, Filter
from left channel interface
BiQuad
BiQuad
Interp. Filter
Digital Volume Ctrl
modulator
BiQuad
BiQuad
from right channel interface
BiQuad
BiQuad
Interp. Filter
Digital Volume Ctrl
modulator
Figure 5-26. Signal Chain PRB_P23
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5.11.2.10 Biquads, DRC, Filter
from Left Left Channel Interface BiQuad BiQuad BiQuad BiQuad BiQuad Interp Filter
Modulator
BiQuad BiQuad
Digital Volume Ctrl
from Right Channel Interface Right BiQuad BiQuad BiQuad BiQuad BiQuad Interp Filter
Modulator
Digital Volume Ctrl
Figure 5-27. Signal Chain PRB_P24 5.11.2.11 Five Biquads, DRC, Beep Generator, Filter
From LeftChannel Interface Left Biquad Biquad Biquad Biquad Biquad Interp. Filter
Modulator
Biquad Biquad Beep Gen.
Digital Volume Ctrl
Beep Volume Ctrl
Modulator
Beep Volume Ctrl From RightChannel Interface Right Biquad Biquad Biquad Biquad Biquad Interp. Filter
Digital Volume Ctrl
Figure 5-28. Signal Chain PRB_P25
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5.11.3 User Programmable Filters
Depending selected processing block, different types orders digital filtering available. biquad sections available specific processing blocks. coefficients available filters arranged sequentially-indexed coefficients banks. adaptive filtering chosen, coefficient banks switched on-the-fly. more details adaptive filtering please Section 5.14.3. coefficients these filters each bits wide, two's-complement occupy consecutive 8-bit registers register space. default values please Register section. 5.11.3.1 First-Order Section first-order transfer function given
(5-8)
frequency response first-order Section with default coefficients flat Table 5-13. Filter Coefficients
Filter Filter Coefficient First-order Coefficient Left Channel Coefficient Right Channel
5.11.3.2 Biquad Section transfer function each biquad filters given
(5-9)
Table 5-14. Biquad Filter Coefficients
Filter BIQUAD Coefficient BIQUAD BIQUAD BIQUAD Left Channel 172) Right Channel 101)
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Table 5-14. Biquad Filter Coefficients (continued)
Filter Coefficient BIQUAD BIQUAD Left Channel Right Channel 103) 105) 107) 109) 111) 113) 115) 117) 119) 121) 123) 125)
5.11.4 Interpolation Filter
5.11.4.1 Interpolation Filter Table 5-15. Interpolation Filter Specification
Parameter Filter gain pass band Filter gain stop band Filter group delay Condition 0.45 0.55 7.455 Value (Typical) ±0.015 21/Fs
Channel Response Interpolation Filter (Red line corresponds
Units
Magnitude
Frequency Normalized w.r.t.
Figure 5-29. Interpolation Filter Frequency Response
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5.11.4.2 Interpolation Filter Filter specifically designed above 96ksps. Thus, flat pass-band region easily covers required audio band 0-20kHz. Table 5-16. Interpolation Filter Specification
Parameter Filter gain pass band Filter gain stop band Filter group delay Condition 0.45 0.55 3.45 Value (Typical) ±0.015 18/Fs
Channel Response Interpolation Filter (Red line corresponds
Units
Magnitude
Frequency Normalized w.r.t.
Figure 5-30. Channel Interpolation Filter Frequency Response 5.11.4.3 Interpolation Filter Filter specifically designed ksps mode. pass band extends 0.40*Fs (corresponds kHz), more than sufficient audio applications.
Channel Response Interpolation Filter (Red line corresponds
Magnitude
Frequency Normalized w.r.t.
Figure 5-31. Interpolation Filter Frequency Response basic filter characteristics Interpolation Filters follows. These values ksps with droop analog reconstruction filters taken into account.
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Table 5-17. Interpolation Filter Specification
Parameter Filter gain pass band Filter gain stop band Filter group delay Condition 0.35 0.60 Value (Typical) ±0.03 13/Fs Units
5.12 Output Drivers 5.12.1 Analog Fully Differential Line Output Drivers
TLV320AIC36 fully differential line output drivers, each capable driving differential load. Each driver connect left right DAC, left right output, left right line input, combination six. design includes extensive capability adjust signal levels independently before mixing occurs, beyond that already provided gain digital volume control. Note that since both left right channel signals routed output drivers, mono stereo signals easily obtained setting volume controls both left right channel signals mixing them. Undesired signals also disconnected from well through register control. TLV320AIC36 includes output level control each output driver with limited gain adjustment from output driver circuitry this device designed provide distortion output while playing full-scale stereo signals gain setting. However, higher amplitude output obtained cost increased signal distortion output. This output level control allows user make this tradeoff based requirements equipment. Note that this output level control intended used standard output volume control. expected used only sparingly level setting, that adjustment full-scale output range device. Each differential line output driver powered down independently others when needed system. When placed into powerdown through register programming, driver output pins will placed into high-Z, high-impedance state. signal routing line level drivers configured using Page Registers through
5.12.2 Analog High-Power Output Drivers
TLV320AIC36 includes four single-ended high power output drivers arranged stereo pairs. These output drivers capable driving 0.89 Vrms each into load pair enabled Vrms each into both pairs enabled. volume control mixing blocks high-power output drivers effectively identical those line-level drivers. Note that each these drivers have output level control block like those included with line output drivers, allowing gain adjustment output signal. previous case, this output level adjustment intended used standard volume control, instead included additional full-scale output signal level control. order drive 0.89 Vrms full-scale output into load, output level adjustment must high power output drivers include additional circuitry avoid artifacts audio output during power-on power-off transient conditions. power-up delay time high power output drivers programmable over wide range time delays, from instantaneous 4-sec, using Page-2/Reg-42. When these output drivers powered down, they placed into variety output conditions based register programming. lowest power operation desired, then outputs placed into tri-state condition, power output stage removed. However, this generally results output nodes drifting rest near upper lower analog supply, small leakage currents pins. This then results longer delay requirement avoid output artifacts during driver power-on. order reduce this required power-on delay, TLV320AIC36 includes option output pins drivers weakly driven AGND level they would normally rest when powered with signal applied.
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high power output drivers also programmed power first with output level control highly attenuated state, then output driver will automatically slowly reduce output attenuation reach desired output level setting programmed. signal routing high power drivers configured using Page Registers through
5.12.3 Short-Circuit Output Protection
TLV320AIC36 includes programmable short-circuit protection high power output drivers, maximum flexibility given application. default, these output drivers shorted, they will automatically limit maximum amount current that sourced sunk from load, thereby protecting device from over-current condition. this mode, user read Page-0/Reg-95 determine whether part short-circuit protection not, then decide whether program device power down output drivers. However, device includes further capability automatically power down output driver whenever does into short-circuit protection, without requiring intervention from user. this case, output driver will stay power down condition until user specifically programs power down then power back again, clear short-circuit flag.
5.13 Gain SettING 5.13.1 Digital Volume Control
TLV320AIC36 signal processing blocks incorporate digital volume control block that control volume playback signal from -63.5 steps These controlled writing Page Register volume control left right channels default controlled independently, however programming Page D(1:0), they made interdependent. volume changes soft-stepped steps avoid audible artifacts during gain change. rate soft-stepping controlled programming Page D(1:0) either step frame (DAC_FS) step frames. soft-stepping feature also entirely disabled. During soft-stepping value actual applied gain would differ from programmed gain register. TLV320AIC36 gives feedback user form register readable flag indicate that soft-stepping currently progress. flags left right channels read back reading Page D(2) D(1) respectively. value these flags indicates soft-stepping operation progress, value indicates that soft-stepping completed. soft-stepping operation comes into effect during power-up, when volume control soft-steps from -63.5 programmed gain value volume change user when powered power-down, when volume control block soft-steps -63.5 before powering down channel.
5.13.2 Dynamic Range Compression
Typical music signals characterized crest factors, ratio peak signal power average signal power, more. order avoid audible distortions clipping peak signals, gain channel must adjusted cause hard clipping peak signals. result, during nominal periods, applied gain low, causing perception that signal loud enough. overcome this problem, TLV320AIC36 continuously monitors output Digital Volume control detect power level with respect When power level low, increases input signal gain make sound louder. same time, peaking signal detected, autonomously reduces applied gain avoid hard clipping. This results sounds more pleasing well sounding louder during nominal periods. functionality TLV320AIC36 implemented combination Processing Blocks channel described Section 5.11.2. disabled writing into Page D(6:5). typically works filtered version input signal. input signals have audio information extremely frequencies; however they significantly influence energy estimation function DRC. Also most information about signal energy concentrated frequency region input signal.
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estimate energy input signal, signal first high-pass filter, then low-pass filter. These filters implemented first-order filters given HHPF (5-10) HLPF (5-11) coefficients these filters bits wide twos complement user programmable through register write given Table 5-18 Table 5-18. Coefficients
Coefficient Location Page Register Page Register Page Register Page Register Page Register Page Register
default values these coefficients implement high-pass filter with cut-off 0.00166*DAC_FS, low-pass filter with cutoff 0.00033 DAC_FS. output high-pass filter Processing Block selected Channel. absolute value DRC-LPF filter used energy estimation within DRC. gain Digital Volume Control controlled Page Register When enabled, applied gain function Digital Volume Control register setting output DRC. parameters described sections that follow. 5.13.2.1 Threshold Threshold represents level playback signal which gain compression becomes active. output digital volume control compared with threshold. threshold value programmable writing register Page Register D(4:2). Threshold value adjusted between dBFS dBFS steps Keeping Threshold value high leave enough time block detect peaking signals, cause excessive distortion outputs. Keeping Threshold value limit perceived loudness output signal. recommended DRC-Threshold value When output signal exceeds Threshold, interrupt flag bits Page Register D(3:2) updated. These flag bits 'sticky' nature, reset only after they read back user. nonsticky versions interrupt flags also available Page Register D(3:2). 5.13.2.2 Hysteresis Hysteresis programmable writing Page Register D(1:0). programmed values between steps programmable window around programmed Threshold that must exceeded disabled become enabled, enabled become disabled. example, Threshold dBFS Hysteresis then gain compressions inactive, output Digital Volume Control must exceed dBFS before gain compression activated. Similarly, when gain
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compression active, output Digital Volume Control needs fall below dBFS gain compression deactivated. Hysteresis feature prevents rapid activation de-activation gain compression cases when output Digital Volume Control rapidly fluctuates narrow region around programmed Threshold. programming Hysteresis hysteresis action disabled. recommended value hysteresis 5.13.2.3 Hold Hold intended slow start decay specified period time response decrease energy level. minimize audible artifacts, recommended Hold time through programming Page Register D(6:3) 0000. 5.13.2.4 Attack Rate When output Digital Volume Control exceeds programmed Threshold, gain applied Digital Volume Control progressively reduced avoid signal from saturating channel. This process reducing applied gain called Attack. avoid audible artifacts, gain reduced slowly with rate equaling Attack Rate programmable using Page Register D(7:4). Attack Rates programmed from gain change 1/DAC_FS 1.2207e-5 gain change 1/DAC_FS. Attack Rates should programmed such that before output Digital Volume control clip, input signal should sufficiently attenuated. High Attack Rates cause audible artifacts, too-slow Attack Rates able prevent input signal from clipping. recommended value attack rate 1.9531e-4 1/DAC_FS. 5.13.2.5 Decay Rate When detects reduction output signal swing beyond programmed Threshold, enters Decay state, where applied gain Digital Volume Control gradually increased programmed values. avoid audible artifacts, gain slowly increased with rate equal Decay Rate programmed through Page Register D(3:0). Decay Rates programmed from 1.5625e-3 1/DAC_FS 4.7683e-7 1/DAC_FS. Decay Rates programmed high, then sudden gain changes cause audible artifacts. However, programmed slow, then output perceived long time after peak signal passed. recommended Value Attack Rate 2.4414e-5 1/DAC_FS. 5.13.2.6 Example Setup Gain Threshold Hysteresis Hold time Attack Rate 1.9531e-4 1/DAC_FS Decay Rate 2.4414e-5 1/DAC_FS
Page #DAC gain left #DAC gain right #DAC Enabled both channels, Threshold Hysteresis #DRC Hold Rate Changes Gain dB/Fs' #Attack Rate 1.9531e-4 dB/Frame Decay Rate =2.4414e-5 dB/Frame Page APPLICATION INFORMATION Submit Documentation Feedback
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
#DRC #DRC
5.14 Special Functions 5.14.1 Beep Generation
special function also been included processing block PRB_P25 generating digital sine-wave signal that sent DAC. This intended generating key-click sounds user feedback. default value sine-wave frequency, sine burst length, signal magnitude kept Tone Generator Registers Page Registers through sine wave generator very flexible, completely register programmable using nine registers 8-bits each provide many different sounds. registers used programming 16-bit, twos complement, sine-wave coefficient (Page Registers 77). other registers program 16-bit, two's-complement, cosine-wave coefficient (Page Registers 79). This coefficient resolution allows virtually frequency sine wave audio band generated DAC_FS/2. Three registers used control length sine burst waveform which located Page Registers resolution (bit) registers sine burst length sample period, this allows great control overall time sine burst waveform. This 24-bit length timer supports 16,777,215 sample periods. (For example DAC_FS kHz, registers combined value equals 96000d (01770h), then sine burst would last exactly seconds.) registers used independently control Left sine-wave volume Right sine-wave volume. 6-bit digital volume control allows level control steps. left-channel volume controlled writing Page Register D(5:0). right-channel volume controlled Page Register D(5:0). master volume control left right channel beep generator using Page Register D(7:6). default volume control setting tone generator maximum-output level. playing back sine wave, must configured with regards clock setup routing. sine wave gets started setting Beep Generator Enable (Page Register D(7)=1)). After sine wave played predefined time period this will automatically back While sine wave playing, parameters beep generator cannot changed. stop sine wave while playing Beep Generator Enable
5.14.2 Digital Auto Mute
TLV320AIC36 also incorporates special feature, which channel auto-muted when continuous stream DC-input detected. default, this feature disabled. enabled writing non-000 value into Page Register D(6:4). non-zero value controls duration continuous stream DC-input before which auto-mute feature takes effect. This feature especially helpful eliminating high-frequency-noise power being delivered into load even during silent periods speech music.
5.14.3 Adaptive Filtering
When running, user-programmable filter coefficients locked cannot accessed either read write. However TLV320AIC36 offers adaptive filter mode well. Setting Register Page D(2)=1 will turn double buffering coefficients. this mode, filter coefficients updated through host, activated without stopping restarting DAC. This enables advanced adaptive filtering applications.
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double-buffering scheme, coefficients stored buffers (Buffers When running adaptive filtering mode turned setting control Page Register D(0)=1 switches coefficient buffers next start sampling period. This back after switch occurs. same time, flag Page D(1) toggles. flag Page Register D(1) indicates which buffers actually use. Page Register D(1)=0: Buffer engine, D(1)=1: Buffer use. While device running, coefficient updates always made buffer DAC, regardless which buffer coefficients have been written.
Running Page D(1) Coefficient Buffer None None Buffer Buffer Buffer Buffer Writing Buffer Buffer Buffer Buffer Buffer Buffer Will Update Buffer Buffer Buffer Buffer Buffer Buffer
user programmable coefficients defined Pages Buffer Pages Buffer
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5.15 Setup
following paragraphs intended guide user through steps necessary configure TLV320AIC36 DAC. Step system clock source (master clock) targeted sampling frequency must identified. Depending targeted performance decimation filter type DOSR value determined. Filter should used 48-kHz high-performance operation, DOSR must multiple Filter should used 96k-Hz operations, DOSR must multiple Filter should used 192-kHz operations, DOSR must multiple cases DOSR limited range following condition: DOSR DAC_FS Based identified filter type required signal processing capabilities, appropriate processing block determined from list available processing blocks (PRB_P1 PRB_P25). Based available master clock, chosen DOSR targeted sampling rate, clock divider values NDAC MDAC determined. necessary, internal large degree flexibility. large degree, NDAC MDAC chosen independently range 128. general, NDAC should large possible long following condition still met: MADC*DOSR/32 function chosen processing block listed Table 5-12. this point following device specific parameters known: PRB_Rx, DOSR, NADC, MADC, input output common-mode values used, parameters determined well. Step Setting device through register programming: following list gives sequence items that must executed time between powering device reading data from device: Define starting point: Program settings: Program Clock Settings: Initiate Reset Turn charge pump Turn with current limit Program clock dividers necessary) Power necessary) Program power NADC Program power MADC Program value Program processing block used word length, BCLK, WCLK I/O, mode type, example, I2S/DSP
Program Codec Interface:
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Program Analog Blocks
Program headphone specific depop settings Power Modulator startup sequence Modulator taps noise driver current control power Route DAC/PGA/LINEIN outputs Release current limit Unmute, gain power outputs
obtain optimum audio quality, necessary write following sequence prior enabling DAC:
Modulator startup sequence optimum audio quality
Section 5.20 detailed application example.
5.16 Clock Generation
TLV320AIC36 supports wide range options generating clocks sections well interface other control blocks shown Figure 5-32. clocks require source reference clock. This clock provided variety device pins such MCLK, BCLK pins. source reference clock codec chosen programming CODEC_CLKIN value Page Register D(1:0). CODEC_CLKIN then routed through highly-flexible clock dividers Figure 5-32 generate various clocks required ADC, miniDSP sections. event that desired audio miniDSP clocks cannot generated from reference clocks MCLK, BCLK GPIO, TLV320AIC36 also provides option using on-chip which supports wide range fractional multiplication values generate required clocks. Starting from CODEC_CLKIN TLV320AIC36 provides several programmable clock dividers help achieve variety sampling rates ADC, clocks miniDSP.
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DIGMIC_DATA DIGMIC_CLK
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DSD_DATA
DSD_CLK
GPOI1
GPIO2
MCLK
BCLK
CODEC CLKIN NADC MADC AOSR CODEC CLKIN NADC MADC CODEC CLKIN NDAC MDAC DOSR CODEC CLKIN NDAC MDAC
Page Reg4[7:4]
PLL_CLKIN
DIGMIC_DATA
(R*J.D)/P
DSD_DATA DSD_CLK
DIGMIC_CLK
GPOI1
GPIO2
MCLK
BCLK
PLL_CLK
Page Reg4[3:0]
CODEC_CLKIN
NDAC=1,2,.,127,128 Page /NDAC /NADC
NADC=1,2,.,127,128 Page
DAC_CLK
ADC_CLK
MADC=1,2,.,127,128 Page /MDAC MDAC=1,2,.,127,128 Page ADC_MOD_CLK /MADC
DAC_MOD_CLK
AOSR=1,2,.,255,256 Page /DOSR DOSR=1,2,.,1023,1024 Page Page /AOSR
DAC_miniDSP clock generation
DAC_FS
ADC_FS
ADC_miniDSP clock generation
Figure 5-32. Clock Distribution Tree
(5-12) (5-13) (5-14) (5-15)
Table 5-19. CODEC CLKIN Clock Dividers
Divider NDAC MDAC DOSR NADC MADC AOSR Bits Page Register D(6:0) Page Register D(6:0) Page Register D(1:0) Page Register D(7:0) Page Register D(6:0) Page Register D(6:0) Page Register D(7:0)
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Modulator clocked DAC_MOD_CLK. proper power-up operating Channel, these clocks must enabled configuring NDAC MDAC clock dividers (Page Register D(7) Page Register D(7)=1). When channel powered down, device internally initiates power-down sequence proper shut-down. During this shut-down sequence, NDAC MDAC dividers must powered down, else proper power shut-down take place. user read back power-status flag Page Register D(7) Page Register D(3). When both flags indicate power-down, MDAC divider powered down, followed NDAC divider. modulator clocked ADC_MOD_CLK. proper power-up Channel, these clocks enabled NADC MADC clock dividers (Page Register D(7) Page Register D(7)=1). When channel powered down, device internally initiates power-down sequence proper shut-down. During this shut-down sequence, NADC MADC dividers must powered down, else proper power shut-down take place. user read back power-status flag Page Register D(6) Page Register D(2). When both flags indicate power-down, MADC divider powered down, followed NADC divider. When ADC_CLK derived from NDAC divider output, NDAC must kept powered till power-down status flags indicate power-down. When input AOSR clock divider derived from DAC_MOD_CLK, then MDAC must powered when ADC_FS needed that when WCLK generated TLV320AIC36 enabled) powered down only after power-down flags indicate power-down status. general, root clock dividers should powered down only after child clock dividers have been powered down proper operation. TLV320AIC36 also options routing some internal clocks output pins device used general purpose clocks system. feature shown Figure 5-33.
DAC_MOD_CLK DAC_CLK ADC_MOD_CLK
ADC_CLK
BDIV_CLKIN
1,2,.,127,128
BCLK
Figure 5-33. BCLK Output Options mode when TLV320AIC36 configured drive BCLK (Page Register D3='1') driven divided value BDIV_CLKIN. division value programmed Page Register D(6:0) from 128. BDIV_CLKIN itself configured DAC_CLK, DAC_MOD_CLK, ADC_CLK ADC_MOD_CLK configuring BDIV_CLKIN Page Register D(1:0).
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Additionally general purpose clock driven DOUT GPIO pin. This clock divided down version CDIV_CLKIN. value this clock divider programmed from writing Page Register D(6:0). CDIV_CLKIN itself programmed clocks among list shown Figure 5-34. This controlled programming Page Register D(2:0).
DAC_MOD_CLK MCLK BCLK PLL_CLK DAC_CLK ADC_MOD_CLK
ADC_CLK
Page Reg23[1:0] CDIV_CLKIN
M=1,2,3,.127,128 Page Reg26[6:0]
GPIO1 Page
GPIO2 Page
GPIO3 Page
GPIO4 Page
GPIO5 Page
GPIO6 Page
DOUT Page
Figure 5-34. General-Purpose Clock Output Options Table 5-20. Maximum TLV320AIC36 Clock Frequencies
Clock CODEC_CLKIN ADC_CLK ADC_miniDSP_CLK ADC_MOD_CLK ADC_FS DAC_CLK DAC_miniDSP_CLK DAC_MOD_CLK DAC_FS BDIV_CLKIN CDIV_CLKIN Maximum Frequency (DVDD=1.8V) 110MHz 60MHz 30MHz 6.758MHz 0.192MHz 60MHz 60MHz 6.758MHz 0.192MHz 50MHz 110MHz Maximum Frequency (DVDD=1.5V) 104MHz 34.6MHz 17.3MHz 5.77MHz 0.18MHz 34.6MHz 34.6MHz 5.77MHz 0.18MHz 34.6MHz 104MHz
5.16.1
TLV320AIC36 chip with fractional multiplication generate clock frequency needed audio ADC, DAC, Digital Signal Processing blocks. programmability allows operation from wide variety clocks that available system. input supports clocks varying from register programmable enable generation required sampling rates with fine precision. turned writing Page Register D(7). When enabled, output clock PLL_CLK given following equation:
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
CLKIN
(5-16)
Where: 9999 register programmable. programmed using Page Registers thru turned using Page Register D(7). variable programmed using Page Register D(6:4). default register value variable programmed using Page Register D(3:0). default register value variable programmed using Page Register D(5:0). variable bits programmed into registers. portion programmed using Page Register D(5:0), portion programmed using Page Register D(5:0). default register value When enabled following conditions must satisfied When enabled following conditions must satisfied PLL_CLKIN: CLKIN 512kHz 20MHz When enabled following conditions must satisfied PLL_CLKIN: CLKIN 10MHz 20MHz
(5-17)
(5-18)
powered independent blocks, also used general purpose routing output GPIO output. After powering PLL, PLL_CLK available typically after output frequency controlled dividers
Divider Bits Page Register D(5:0) Page Register D(5:0) Page Register D(7:0) Page Register D(3:0)
D-divider value 14-bits wide controlled registers. proper update D-divider value, Page Register must programmed first followed immediately Page Register Unless write Page Register completed, value will take effect. clocks codec various signal processing blocks, CODEC_CLKIN generated from MCLK input, BCLK input, GPIO inputs PLL_CLK (Page 0/Register 4/D(1:0) CODEC_CLKIN derived from PLL, then must powered first powered down last. Table 5-21 lists several example cases typical MCLK rates program achieve sample rate either 44.1 48kHz. Table 5-21. Example Configurations
44.1 MCLK (MHz) 2.8224 5.6448 PLLP PLLR PLLJ PLLD 2336 MADC NADC AOSR MDAC NDAC DOSR
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
Table 5-21. Example Configurations (continued)
44.1 MCLK (MHz) 19.2 2.048 3.072 4.096 6.144 8.192 19.2 1680 3760 4800 1680 PLLP PLLR PLLJ PLLD 2920 4100 MADC NADC AOSR MDAC NDAC DOSR
5.17 Interface 5.17.1 Audio Digital Interface
Audio data transferred between host processor TLV320AIC36 through digital audio data serial interface, audio bus. audio this device very flexible, including left right-justified data options, support protocols, programmable data length options, mode multichannel operation, very flexible master/slave configurability each clock line, ability communicate with multiple devices within system directly. audio TLV320AIC36 configured left right-justified, I2S, DSP, modes operation, where communication with standard telephony interfaces supported within mode. These modes MSB-first, with data width programmable bits configuring Page Register D(5:4). addition, word clock clock independently configured either Master Slave mode, flexible connectivity wide variety processors. word clock used define beginning frame, programmed either pulse square-wave signal. frequency this clock corresponds maximum selected sampling frequencies. clock used clock clock digital audio data across serial bus. When Master mode, this signal programmed generate variable clock pulses controlling bit-clock divider Page Register (see Figure 5-32). number bit-clock pulses frame need adjustment accommodate various word-lengths well support case when multiple TLV320AIC36s share same audio bus. TLV320AIC36 also includes feature offset position start data transfer with respect word-clock. This offset controlled terms number bit-clocks programmed Page Register TLV320AIC36 also feature inverting polarity bit-clock used transferring audio data compared default clock polarity used. This feature used independently mode audio interface chosen. This configured using Page Register D(3). TLV320AIC36 further includes programmability (Page Register 3-state DOUT line during clocks when valid data being sent. combining this capability with ability program what clock frame audio data begins, time-division multiplexing (TDM) accomplished, enabling multiple codecs single audio serial data bus. When audio serial data powered down while configured master mode, pins associated with interface into 3-state output condition.
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
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default when word-clocks bit-clocks generated TLV320AIC36, these clocks active only when codec (ADC, both) powered within device. This done save power. However, also supports feature when both word clocks bit-clocks active even when codec device powered down. This useful when using mode with multiple codecs same bus, when word-clock bit-clocks used system general-purpose clocks. 5.17.1.1 Right-Justified Mode Audio Interface TLV320AIC36 into Right Justified Mode programming Page Register D(7:6) right-justified mode, left channel valid rising edge clock preceding falling edge word clock. Similarly, right channel valid rising edge clock preceding rising edge word clock.
1/fs WCLK
BCLK
Left Channel DIN/ DOUT
Right Channel
Figure 5-35. Timing Diagram Right-Justified Mode Right-Justified mode, number bit-clocks frame should greater than twice programmed word-length data. 5.17.1.2 Left-Justified Mode Audio Interface TLV320AIC36 into Left Justified Mode programming Page Register D(7:6) left-justified mode, right channel valid rising edge clock following falling edge word clock. Similarly left channel valid rising edge clock following rising edge word clock.
WORD CLOCK
LEFT CHANNEL
RIGHT CHANNEL
CLOCK LD(n+1)
DATA
LD(n)
RD(n)
LD(n) n'th sample left channel data
RD(n) n'th sample right channel data
Figure 5-36. Timing Diagram Left-Justified Mode
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WORD CLOCK LEFT CHANNEL RIGHT CHANNEL
CLOCK LD(n+1)
DATA
LD(n)
RD(n)
LD(n) n'th sample left channel data
RD(n) n'th sample right channel data
Figure 5-37. Timing Diagram Left-Justified Mode with Offset=1
WORD CLOCK
LEFT CHANNEL
RIGHT CHANNEL
CLOCK
DATA
LD(n)
RD(n)
LD(n+1)
LD(n) n'th sample left channel data
RD(n) n'th sample right channel data
Figure 5-38. Timing Diagram Left-Justified Mode with Offset Inverted Clock Left-Justified mode, number bit-clocks frame should greater than twice programmed word-length data. Also, programmed offset value should less than number bit-clocks frame least programmed word-length data. 5.17.1.3 Mode Audio Interface TLV320AIC36 into Right Justified Mode programming Page Register D(7:6) mode, left channel valid second rising edge clock after falling edge word clock. Similarly right channel valid second rising edge clock after rising edge word clock.
WORD CLOCK
LEFT CHANNEL
RIGHT CHANNEL
CLOCK LD(n+1)
DATA
LD(n)
RD(n)
LD(n) n'th sample left channel data
RD(n) n'th sample right channel data
Figure 5-39. Timing Diagram Mode
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009 www.ti.com
WORD CLOCK LEFT CHANNEL RIGHT CHANNEL
CLOCK
DATA
(n+1)
LD(n) LD(n) n'th sample left channel data
RD(n) RD(n) n'th sample right channel data
Figure 5-40. Timing Diagram Mode With Offset
WORD CLOCK
LEFT CHANNEL
RIGHT CHANNEL
CLOCK
DATA
LD(n)
RD(n)
LD(n+1)
LD(n) n'th sample left channel data
RD(n) n'th sample right channel data
Figure 5-41. Timing Diagram Mode With Offset Clock Invert mode, number bit-clocks channel should greater than equal programmed word-length data. Also programmed offset value should less than number bit-clocks frame least programmed word-length data. 5.17.1.4 Mode Audio Interface TLV320AIC36 into Right Justified Mode programming Page Register D(7:6) mode, falling edge word clock starts data transfer with left channel data first immediately followed right channel data. Each data valid falling edge clock.
WORD CLOCK LEFT CHANNEL RIGHT CHANNEL
CLOCK
DATA
LD(n)
RD(n)
(n+1)
LD(n) n'th sample left channel data
RD(n) n'th sample right channel data
Figure 5-42. Timing Diagram Mode
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WORD CLOCK
SBAS387 2009
LEFT CHANNEL
RIGHT CHANNEL
CLOCK LD(n+1)
DATA
LD(n)
RD(n)
LD(n) n'th sample left channel data
RD(n) n'th sample right channel data
Figure 5-43. Timing Diagram Mode With Offset
WORD CLOCK
LEFT CHANNEL
RIGHT CHANNEL
CLOCK
DATA
LD(n)
RD(n)
LD(n+1)
Figure 5-44. Timing Diagram Mode With Offset Clock Inverted mode, number bit-clocks frame should greater than twice programmed word-length data. Also programmed offset value should less than number bit-clocks frame least programmed word-length data. 5.17.1.5 Secondary audio serial interface TLV320AIC36 extensive control allow communication with independent processors audio data. Each processor communicate with device time. This feature enabled register programming various selections. Figure 5-45 illustrates possible audio interface routing.
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TLV320AIC36 Power Stereo Audio Codec With Embedded miniDSP
SBAS387 2009
S_BCLK BCLK_INT BCLK S_BCLK S_WCLK Reg27[2] Reg25[3] BCLK_OUT WCLK Reg33[7] Reg32[4] DAC_WCLK_INT Reg32[3] BCLK BCLK
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Reg32[2] WCLK Primary Processor WCLK Reg27[2] Reg25[2] Reg33[5:4] DOUT Reg126[3:1] Reg33[1] DOUT Reg32[0] DOUT_INT S_DIN DIN_INT S_DIN S_WCLK ADC_FS DAC_FS WCLK Reg32[1] ADC_WCLK ADC_WCLK_INT Audio Digital Serial Interface Core
DOUT_INT BCLK WCLK Secondary Processor DOUT GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 Register Programmable Pins S_BCLK, S_WCLK, ADC_WCLK, S_DIN
BCLK_OUT ADC_FS DAC_FS Clock Generation Block
Figure 5-45. Audio Serial Interface Multiplexing
5.17.2 Control InterFACE
TLV320AIC36 supports control protocol, will respond address 0011000. two-wire, open-drain interface supporting multiple devices masters single bus. Devices only drive lines connecting them ground; they never drive lines HIGH. Instead, wires pulled HIGH pullup resistors, wires HIGH when device driving them LOW. This way, devices cannot conflict; devices drive simultaneously, there driver contention. Communication always takes place between devices, acting master other acting slave. Both masters slaves read write, slaves only under direction master. Some devices masters slaves, TLV320AIC36 only slave device. consists lines, SCL. carries data, signal provides clock. data transmitted across groups bits. send bus, line driven appropriate level while indicates zero, while HIGH indicates one). Once line settled, line brought HIGH, then LOW. This pulse line clocks into receiver's shift register. bidirectional: line used both transmitting receiving data. When master reads from slave, slave drives data line; when master sends slave, master drives data line. Most time idle, communication taking place, both lines HIGH. When communication taking place, active. Only master devices start communication bus. Normally, data line only allowed change state while clock line LOW. data line changes state while clock line HIGH, either START condition counterpart, STOP condition. START condition when clock line HIGH data line goes from HIGH LOW. STOP condition when clock line HIGH data line goes from HIGH.
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After master issues START condition, sends byte that selects slave device communication. This byte called address byte. Each device unique 7-bit address which responds. (Slaves also have 10-bit addresses; specification details.) master sends address address byte, together with that indicates whether wishes read from write slave device. Every byte transmitted bus, whether address data, acknowledged with acknowledge bit. When master finished sending byte (eight data bits) slave, stops driving waits slave acknowledge byte. slave acknowledges byte pulling LOW. master then sends clock pulse clock acknowledge bit. Similarly, when master finished reading byte, pulls acknowledge this slave. then sends clock pulse clock bit. (Remember that master always drives clock line.) not-acknowledge performed simply leaving HIGH during acknowledge cycle. device present bus, master attempts address will receive not-acknowledge because device present that address pull line LOW. When master finished communicating with slave, issue STOP condition. When STOP condition issued, becomes idle again. master also issue another START condition. When START condition issued while active, called repeated START condition. TLV320AIC36 also respond acknowledge General Call, which consists master issuing command with slave address byte 00H. This feature disabled default, enabled using Page Register D(5).
Start
DA(6)
DA(0)
Write Slave
RA(7)
RA(0)
Slave
D(7)
D(0)
Slave Stop
7-bit Device Address
8-bit Register Address
8-bit Register Data
Controlled Master Controlled Slave
Figure 5-46. Write
DA(6)
Slave Repeat Start
Start
DA(6)
DA(0)
Write Slave
RA(7)
RA(0)
DA(0)
Rea
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