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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Features
channel Programmable Audio Digital Signal Processor (DSP) 135-MHz Maximum Speed, >2800 Processing Cycles Sample Sample Rates 48-Bit Data Path 28-Bit Coefficients Single-Cycle, 76-Bit Multiply Accumulate Five Simultaneous Operations Clock Cycle 1022 Words 48-Bit Data Memory 1022 Words 28-Bit Coefficient Memory Words 54-Bit Program 5.88K Words 24-Bit Delay Memory (122.5 kHz) Stereo/TDM Data Formats Independent Input/Output Data Formats 16-, 20-, 24-, 32-Bit Word Sizes 64-fS, 128-fS, 192-fS, 256-fS SCLK Support Discrete channel TDM, channel TDM, channel Data-Transfer Formats Ports Slave Master Download Soft Volume Controller Dither Generator Efficient log2/2x Estimator Single 3.3-V Power Supply 38-Pin Thin Shrink Small-Outline Package (TSSOP) (DCP) AEC-Q100 (Grade -40°C 105°C) Compliant Automotive Applications (TAS3108IA)
Applications
Automotive Sound Systems Digital Televisions Home Theater Systems Mini-Component Audio
TAS3108/TAS3108IA SDIN1 SDIN2 SDIN3 SDIN4 Serial Audio Input Port Audio Core 48-Bit Data Path 28-Bit Coefficients 76-Bit Code Data Coeff. 5.8K Delay Boot Volume Update 8051 Port Port Interface 8-Bit Microprocessor IRAM ERAM Code
B0074-01
Serial Audio Output Port
SDOUT1 SDOUT2 SDOUT3 SDOUT4
MCLK LRCLK SCLKIN SCLKOUT1 SCLKOUT2
Clock Control
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this document.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2005-2007, Texas Instruments Incorporated
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Contents
Introduction
Features Applications
Register
Clock Control Register (0x00)
Functional Description
Device Description Power Supply Clock Control Serial Audio Ports (SAPs) M8051Warp Microprocessor. Control Interface Audio Core
Status Register (0x02) Memory Load Control Data Registers (0x04 0x05) Memory Access Registers (0x06 0x07)
Electrical Specifications
8.5.1 8.5.2 Absolute Maximum Ratings Over Operating Temperature Range (unless otherwise noted) Package Dissipation Ratings (TAS3108/TAS3108IA) Recommended Operating Conditions (TAS3108/TAS3108IA) Electrical Characteristics (TAS3108/TAS3108IA) Timing Characteristics.
Physical Characteristics
Terminal Assignments Terminal Descriptions Reset (RESET) Power-On Reset (RESET). Power Down (PDN) Control (CS0) Programmable General Purpose (GPIO) Input Output Serial Audio Ports
Master Clock Signals (TAS3108/TAS3108IA) Serial Audio Port Slave Mode Signals (TAS3108/TAS3108IA) 8.5.3 Serial Audio Port Master Mode Signals (TAS3108/TAS3108IA) 8.5.4 Pin-Related Characteristics Stages F/S-Mode 2C-Bus Devices
Algorithm Software Development Tools TAS3108/TAS3108IA Clock Controls Microprocessor Controller
Detailed Operation Master-Mode Device Initialization
General Operations
Application Information Schematics Recommended Oscillator Circuit
8.5.6 Reset Timing (TAS3108/TAS3108IA)
Recommended Design TAS3108IA Applications
Contents
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Functional Description
Device Description
TAS3108 TAS3108IA fully programmable high-performance audio processors. devices efficient, custom, multi-instruction programming environment optimized digital audio processing algorithms. TAS3108/TAS3108IA architecture provides high-quality audio processing using 48-bit data path, 28-bit filter coefficients, single-cycle 48-bit multiplier with 76-bit accumulator. embedded 8051 microprocessor provides algorithm data control TAS3108/TAS3108IA. TAS3108 commercial version intended home audio other commercial applications. TAS3108IA automotive version that qualified automotive applications.
Audio Core Channels
SDIN1 SDIN2 SDIN3 SDIN4 Serial Audio Port SDOUT1 SDOUT2 SDOUT3 SDOUT4
Coef. (1022
Data Path Data (1022 Channels
MCLK LRCLK SCLKIN SCLKOUT1 SCLKOUT2 Clock Control Controller Memory Interface Code
Microprocessor Core Internal Data (256
Delay Memory (5.8K
External Data (2048
8-Bit (8051) Control Registers
Volume Update 2ySDA Control Interface 2ySCL GPIO AVDD DVDD
Code (12K
Code Power Supply
B0075-01
Figure 2-1. Expanded TAS3108/TAS3108IA Functional Block Diagram
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Functional Description
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Power Supply
power supply contains supply regulators that provide analog digital regulated power various sections TAS3108/TAS3108IA. Only external 3.3-V supply required. other voltages generated on-chip from external 3.3-V supply.
Clock Control
TAS3108/TAS3108IA audio data clock-master clock-slave device. clock-master mode, generates MCLK, SCLK, LRCLK. clock-slave mode, accepts MCLK, SCLK, LRCLK. generate accept master clocks from 24.576 MHz. Master slave operation register 0x00. TAS3108/TAS3108IA 6-MHz 20-MHz crystal 6-MHz 24.576-MHz, 3.3-V MCLKI digital input master clock either clock-master clock-slave mode. clock-slave mode, master clock frequency does need integer multiple sample rate. TAS3108/TAS3108IA does support clock error detection. clock error occurs, TAS3108/TAS3108IA does prevent invalid data clocks from being output. This means that application system must designed handle clock errors.
Serial Audio Ports (SAPs)
Serial audio data input pins SDIN1, SDIN2, SDIN3, SDIN4. Serial audio data output pins SDOUT1, SDOUT2, SDOUT3, SDOUT4. TAS3108/TAS3108IA accepts 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, 192-kHz serial data 16-, 20-, 24-, 32-bit data left justified, right justified, serial data formats. four ports accommodate these three channel data formats. addition supporting channel formats, SDIN1 SDOUT1 also provide support time-division multiplex (TDM) data formats channels. data formats selectable register 0x00. input channels must same data format. output channels must same data format. However, input output formats different.
M8051Warp Microprocessor
M8051Warp (8051) microprocessor controls reads writes participates some audio processing tasks requiring multiframe period) processing cycles. 8051 processor performs some control calculations exchanges data between audio core interface. also provides mode control interface clock control. microcode program GPIO post-boot-up operation input output. more information, TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
Control Interface
TAS3108/TAS3108IA slave-only interface (SDA1 SCL1) receiving commands providing status system controller, separate master interface (SDA2 SCL2) download programs data from external memory such EEPROM. Section more information.
Functional Description
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Audio Core
audio core arithmetic unit fixed-point computational engine consisting arithmetic unit data coefficient memory blocks. primary features audio core are: 48-bit data path with 76-bit accumulator Hardware multiplier 48bit) Read/write single-cycle memory access Input 48-bit 2s-complement data multiplexed from immediately following LRCLK pulse. Output 32-bit 2s-complement data four buses. Separate control writing delay memory Separate coefficient memory bit) data memory bit) Linear feedback shift register (LFSR) random-number generator that used dither audio. Coefficient RAM, data RAM, LFSR seed, program counter, memory pointers mapped into same 5.88K memory space convenient addressing microprocessor. Memory interface block contains four pointers data memory coefficient memory. audio core used implement audio processing functions.
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Functional Description
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Physical Characteristics
Terminal Assignments
PACKAGE (TOP VIEW)
AVSS VR_PLL XTALI XTALO MCLKI MICROCLK_DIV GPIO DVDD DVSS SDIN1 SDIN2 SDIN3 SDIN4 SDA1 SCL1 SDA2 SCL2 LRCLK
AVDD RESERVED PLL2 PLL1 PLL0 RESERVED RESET DVDD DVSS VR_DIG SDOUT1 SDOUT2 SDOUT3 SDOUT4 SCLKOUT2 SCLKOUT1 MCLKO SCLKIN
P0033-01
Physical Characteristics
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Terminal Descriptions
TERMINAL NAME AVDD AVSS DVDD DVSS GPIO LRCLK MCLKIN MCLKO MICROCLK_DIV PLL0 PLL1 PLL2 RESERVED RESET SCL1 SCL2 SCLKIN SCLKOUT1 SCLKOUT2 SDA1 SDA2 SDIN1 SDIN2 SDIN3 SDIN4 SDOUT1 SDOUT2 SDOUT3 SDOUT4 VR_PLL XTALI XTALO VR_DIG Pulldown Pulldown Pulldown Pulldown Pulldown Pullup Pulldown Pullup Pullup Pulldown Pullup Pullup Pulldown Pulldown INPUT/ OUTPUT PULLUP/ PULLDOWN Analog power supply (3.3 Analog ground Chip select Digital power supply input (3.3 Digital ground GPIO control (user programmable) Sample rate clock (fS) Master clock input (connect ground when use) Master clock output Internal microprocessor clock divide control Power down. Powers down logic stops clocks, active low. Coefficient memory remains stable through power-down cycle. control control control Reserved. Connect ground Reset, active port clock (always slave) port clock (always master) clock input clock out. Used receive input serial data. clock out. Used clock output serial data. port data (always slave) port data (always master) Serial data input Serial data input Serial data input Serial data input Serial data output Serial data output Serial data output Serial data output Internal regulator. This must used power external devices. Oscillator input (connect ground when use) Oscillator output Internal regulator. This must used power external devices. DESCRIPTION
input, output pullups 20-µA weak pullups, pulldowns 20-µA weak pulldowns. pullups pulldowns included ensure proper input logic levels terminals left unconnected (pullups logic input; pulldowns logic input). Devices that drive inputs with pullups must able sink while maintaining logic-0 drive level. Devices that drive inputs with pulldowns must able source while maintaining logic-1 drive level.
Reset (RESET)
RESET asynchronous control signal that restores TAS3108/TAS3108IA components default configuration. When reset occurs, audio core into idle state 8051 starts initialization. valid MCLKI XTLI must present when clearing RESET initiate device reset. reset initiated applying logic RESET. reset also issued power turnon three internal power supplies.
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
long RESET held LOW, device reset state. During reset, serial data operations ignored. interface lines into high-impedance state remain that state until device initialization completed. rising edge reset pulse begins initialization housekeeping functions clearing memory setting default register values. Once these complete, TAS3108/TAS3108IA enables master interface disables slave interface. Then TAS3108/TAS3108IA looks EEPROM described Section 2.6, Control Interface.
Power-On Reset (RESET)
power recommended that TAS3108/TAS3108IA RESET held until DVDD reached This done programming system controller using external delay circuit. 1-µF values provide delay approximately values adjusted provide other delay values necessary.
Power Down (PDN)
user-firmware-definable that programmed default TAS3108 TAS3108IA configuration stop clocks TAS3108/TAS3108IA, while preserving state device. more information, TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
Control (CS0)
TAS3108/TAS3108IA control specify slave master address. This control permits TAS3108/TAS3108IA devices placed system without external logic. Section complete description this pin.
Programmable General Purpose (GPIO)
TAS3108/TAS3108IA GPIO that 8051 firmware programmable. power following reset, GPIO becomes input. Afterwards, microprocessor program GPIO input output. more information, TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
3.7.1
EEPROM Present Memory Error Occurs
Following reset power-up initialization with EEPROM present memory error occurs, TAS3108/TAS3108IA modes, depending setting GPIO pin. GPIO logic HIGH (through 20-k resistor) With GPIO held HIGH during initialization, TAS3108/TAS3108IA comes default configuration with serial data outputs active. Once TAS3108/TAS3108IA completed default initialization procedure after status register updated slave interface enabled, GPIO output driven LOW. Following HIGH-to-LOW transition GPIO pin, system controller access TAS3108/TAS3108IA through interface read status register determine load status. memory-read error occurs, TAS3108/TAS3108IA reports error status register (I2C subaddress 0x02). GPIO logic (through 20-k resistor) With GPIO held during initialization, TAS3108/TAS3108IA comes test configuration. this case, once TAS3108/TAS3108IA completes default test initialization procedure, status register updated, slave interface enabled, TAS3108/TAS3108IA streams audio unaltered from input output SDIN1 SDOUT1, SDIN2 SDOUT2, etc. this configuration, GPIO output signal that driven LOW. external logic
Physical Characteristics
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
longer driving GPIO after load completed (~100 following reset EEPROM present), state GPIO observed. Then system controller access TAS3108/TAS3108IA through interface read status register determine load status. GPIO state observed, only indication that device completed initialization procedure that TAS3108/TAS3108IA streams audio slave interface been enabled.
3.7.2
GPIO Function After Device Programmed
Once TAS3108/TAS3108IA been programmed, either through successful boot load slave download, operation GPIO programmed input and/or output.
Input Output Serial Audio Ports
TAS3108/TAS3108IA supports system architectures that require data format conversions between non-TDM same format type without need additional glue logic. addition, TAS3108/TAS3108IA supports data format conversions between right justified between left justified I2S. supported conversions listed Table 3-1. input port configured format, only SDIN1 active. format selected output port, only SDOUT1 active. Table 3-1. Supported Conversions
INPUT (SDIN1, SDIN2, SDIN3, SDIN4) channel left justified channel left justified left justified channel channel channel channel right justified
OUTPUT (SDOUT1, SDOUT2, SDOUT3, SDOUT4) left justified channel channel left justified channel channel leftjustified channel right justified channel
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Physical Characteristics
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Table 3-2. Serial Data Input Output Formats
MODE INPUT CONTROL IM[3:0] 0000 channel 0001 0010 0011 Time-division multiplexed channel) 0110 0100 0111 0101 1000 OUTPUT CONTROL OM[3:0] 0000 0001 0010 0011 0110 0100 0111 0101 1000 SERIAL FORMAT Left justified Right justified channel left justified channel channel left justified channel channel left justified channel
WORD LENGTHS
Input Port Word Size
DATA RATES (kHz)
SCLK
32-192
12.288
32-96 MCLK 32-48 crystal 32-96 32-192 MCLK 32-96 crystal
Output Port Word Size
24.576 MCLK 12.288 crystal 18.432 24.576 MCLK 12.288 crystal
0x00
Slave Addr Subaddr
xxxxxxxx
xxxxxxxx
Figure 3-1. Serial Data Controls Table 3-3. Serial Data Input Output Data Word Sizes
IW1, IW0, FORMAT 32-bit data 16-bit data 20-bit data 24-bit data
Physical Characteristics
IW[2:0] OW[2:0] DWFMT (Data Word Format)
DWFMT
IM[3:0]
OM[3:0]
Input Port Format
Output Port Format
R0003-01
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Following reset, ensure that clock register (0x00) written before performing volume, treble, bass updates. Commands reconfigure accompanied mute unmute commands quiet operation. However, care must taken ensure that mute command completed before commanded reconfigure. Similarly, TAS3108/TAS3108IA should commanded unmute until after completed reconfiguration. reason this that configuration change while volume bass treble update taking place cause update completed properly. When TAS3108/TAS3108IA transmitting serial data, uses negative edge SCLK output data bit. TAS3108/TAS3108IA samples incoming serial data rising edge SCLK. TAS3108/TAS3108IA only supports TDM, left justified, right justified, formats.
3.8.1
channel Timing
channel timing, LRCLK when left channel data transmitted HIGH when right channel data transmitted. SCLK clock running which clocks each data. There delay clock from time LRCLK signal changes state first data data lines. data written first valid rising edge clock. TAS3108/TAS3108IA masks unused trailing data-bit positions.
2-Channel (Philips Format) Stereo Input/Output Clks Clks
LRCLK (Note Reversed Phase)
Left Channel
Right Channel
SCLK
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0034-04
Figure 3-2. 64-fS Format
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Physical Characteristics
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
3.8.2
Channel Left Justified Timing
channel left justified timing, LRCLK HIGH when left channel data transmitted when right channel data transmitted. SCLK clock running which clocks each data. first data appears data lines same time LRCLK toggles. data written first valid rising edge clock. TAS3108/TAS3108IA masks unused trailing data-bit positions.
2-Channel Left-Justified Stereo Input Clks LRCLK Left Channel Right Channel Clks
SCLK
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0034-02
Figure 3-3. Left justified 64-fS Format
Physical Characteristics
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SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
3.8.3
Channel Right Justified Timing
2-channel right-justified timing, LRCLK HIGH when left channel data transmitted when right channel data transmitted. SCLK clock running which clocks each data. first data appears data lines bit-clock periods (for 24-bit data) after LRCLK toggles. right-justified mode, last clock before LRCLK transitions always clocks data. data written first valid rising edge clock. TAS3108/TAS3108IA masks unused leading data-bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input Clks LRCLK Left Channel Right Channel Clks
SCLK
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0034-03
Figure 3-4. Right justified 64-fS Format
3.8.4
Modes
modes TAS3108/TAS3108IA provide left justified formats. Each word data stream adheres placement shown Figure Figure 3-6. cases illustrated-an data format left-justified data format.
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Physical Characteristics
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Clks LRCLK Left Channels
Clks
Right Channels
32-Bit Word (DAC1)
32-Bit Word (DAC3)
32-Bit Word (DAC5)
32-Bit Word (DAC7)
32-Bit Word (DAC2)
32-Bit Word (DAC4)
32-Bit Word (DAC6)
32-Bit Word (DAC8)
Clks LRCLK Left Channels
Clks
Right Channels
32-Bit Word (DAC1)
32-Bit Word (DAC3)
32-Bit Word (DAC5)
32-Bit Word (DAC2)
32-Bit Word (DAC4)
32-Bit Word (DAC6)
Clks LRCLK Left Channels LRCLK
Clks
Right Channels
32-Bit Word (DAC1)
32-Bit Word (DAC3)
32-Bit Word (DAC2)
32-Bit Word (DAC4)
1-Chip, 4-Channel Multiplexed 6-Channel Operation Left-Justified Format
SCLK
LRCLK 32-Bit Mode 24-Bit Mode 20-Bit Mode 16-Bit Mode
T0085-01
SCLK
(Example)
Figure 3-5. Left-Justified Formats
Physical Characteristics
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Clks LRCLK Left Channels
Clks
Right Channels
32-Bit Word (DAC1)
32-Bit Word (DAC3)
32-Bit Word (DAC5)
32-Bit Word (DAC7)
32-Bit Word (DAC2)
32-Bit Word (DAC4)
32-Bit Word (DAC6)
32-Bit Word (DAC8)
Clks LRCLK Left Channels
Clks
Right Channels
32-Bit Word (DAC1)
32-Bit Word (DAC3)
32-Bit Word (DAC5)
32-Bit Word (DAC2)
32-Bit Word (DAC4)
32-Bit Word (DAC6)
Clks LRCLK Left Channels LRCLK
Clks
Right Channels
32-Bit Word (DAC1)
32-Bit Word (DAC3)
32-Bit Word (DAC2)
32-Bit Word (DAC4)
1-Chip, 4-Channel Multiplexed 6-Channel Operation Format
SCLK
LRCLK 24-Bit Mode 20-Bit Mode 16-Bit Mode
T0085-02
SCLK
(Example)
Figure 3-6. Formats
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Physical Characteristics
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
3.8.5
Input Output-Processing Flow
data format options other than result two-sample delay from input output, shown Figure 3-7. formatting used both input output SAP, polarity LRCLK Figure must inverted. However, format conversions performed between input output, delay becomes either samples samples, depending processing clock frequency selected audio core relative sample rate incoming data. format uses falling edge LRCLK begin sample period, whereas other formats rising edge LRCLK begin sample period. This means that input audio core operate sample windows that 180° phase, with respect sample window used output SAP. This phase difference results output outputting data sample midpoint sample period used audio core process data. processing cycle completes processing tasks before midpoint processing sample period, output outputs this processed data. However, processing time extends past midpoint processing sample period, output outputs data processed during previous processing sample period. former case, delay from input output samples. latter case, delay from input output samples. Therefore, delay from input output either sample times when data format conversions performed that involve format. However, which delay time obtained particular application determinable fixed that application, providing care taken selection MCLKI/XTALI with respect incoming sample clock, LRCLK.
Physical Characteristics
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Half Sample Time
Sample Time Sample Time Sample Time Sample Time Sample Time
Half Sample Time
Sample Time
Serial Input Holding Regs Regs SDOUT1 Channel SDOUT2 Channel
Input Output
Input Holding Regs SDIN1 Channel
Serial Input Holding Regs Regs
Input Holding Regs
SDOUT1
SDIN1
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SDOUT2 SDIN2 Channel SDOUT3 Channel SDIN3 Channel
Input Output
SDIN2
SDOUT3
SDIN3
SDIN4
SDIN4
Sample Time
Sample Time Sample Time Sample Time
Sample Time
Sample Time Sample Time
Sample Time
Serial Input Holding Regs Regs SDOUT1 Channel SDOUT2 Channel
Input Output
Input Holding Regs SDIN1
Serial Input Holding Regs Regs
Input Holding Regs Channel
SDOUT1
Figure 3-7. Input-to-Output Latency
SDIN2 Channel SDOUT3 Channel SDIN3 Channel
Input
SDIN1
SDOUT2
Output
SDIN2
SDOUT3
SDIN3
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Physical Characteristics
SDIN4
SDIN4
B0076-01
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Algorithm Software Development Tools TAS3108/TAS3108IA
TAS3108/TAS3108IA algorithm software development tool combination classical development tools graphical development tools. tool used build, debug, execute programs both audio 8051 sections TAS3108/TAS3108IA. Classical development tooling includes text editors, compilers, assemblers, simulators, source-level debuggers. 8051 programmed exclusively ANSI 8051 tool off-the-shelf tool set, with modifications specified this document. 8051 tool complete environment with IDE, editor, compiler, debugger, simulator. audio core programmed exclusively assembly. audio tool complete environment with IDE, context-sensitive editor, assembler, simulator/debugger. Graphical development tooling provides means programming audio core 8051 through graphical drag-and-drop interface using modular audio software components from component library. graphical tooling produces audio assembly 8051 ANSI code, well coefficients data. classical tools also used produce executable code. addition building applications, tool supports debug execution audio 8051 code both simulators hardware.
Algorithm Software Development Tools TAS3108/TAS3108IA
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Clock Controls
Clock management TAS3108/TAS3108IA consists control structures: Master clock management Oversees selection clock frequencies 8051 microprocessor, controller, audio core master clock (MCLKI XTALI) source these clocks. most applications, master clock drives on-chip digital phase-locked loop (DPLL), DPLL output drives microprocessor audio clocks. Also available DPLL bypass mode, which high-speed master clock directly drives microprocessor audio clocks. Serial audio port (SAP) clock management Oversees master/slave mode Controls output SCLKOUT1, SCLKOUT2, LRCLK master mode Figure shows clock circuitry TAS3108/TAS3108IA. Input MCLKI XTALI provides master clock TAS3108/TAS3108IA. Within TAS3108/TAS3108IA, these inputs combined gate and, thus, only these sources active time. source that active must logic normal operation, determined logic levels input pins PLL0 PLL1) divides master clock. DPLL then multiplies this signal frequency (PLL2 LOW). multiplier ratio always (pin PLL2 LOW). DPLL output processing clock used audio core.
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Clock Controls
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Table 5-1. PLL2, PLL1, PLL0 Configuration Controls
PLL2 PLL1 PLL0 AUDIO CLOCK MCLK/1 MCLK/2 MCLK/4 Reserved Reserved
Audio clock audio clock/4 used clock on-chip microprocessor. input MICROCLK_DIV makes this clock choice. logic-1 input level this selects audio clock microprocessor clock; logic-0 input level this selects audio clock/4 microprocessor clock. microprocessor clock must MHz. Table 5-2. MICROCLK_DIV Configuration Control
MICROCLK_DIV MICROPROCESSOR CLOCK Audio clock/4 Audio clock
NOTE state PLL0, PLL1, PLL2, MICROCLK_DIV only changed while TAS3108 TAS3108IA RESET held low.
TAS3108/TAS3108IA only supports dynamic sample-rate changes between supported sample frequencies when fixed-frequency master clock provided. During dynamic sample-rate changes, TAS3108/TAS3108IA remains normal operation register contents preserved. avoid producing audio artifacts during sample-rate changes, volume mute control included application firmware that mutes output signal during sample-rate change. fixed-frequency clock provided crystal, attached XTLI XTLO, external 3.3-V fixed-frequency source attached MCLKI. When TAS3108/TAS3108IA used system which master clock frequency (fMCLK) change, TAS3108/TAS3108IA must reset during frequency change. these cases, procedure shown Figure should used.
Clock Controls
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SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Enable Mute Wait Completion
RESET
Change fMCLK
Clocks Stable?
RESET High
After TAS3108/TAS3108IA Initializes, Re-initialize Registers
F0007-01
Figure 5-1. Master Clock Frequency (fMCLK) Change Procedure
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Clock Controls
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
SCLKIN
MCLKI
XTALI
XTALO
MCLKO
PLL2
PLL1 PLL0
SCLKOUT1 LRCLK
MICROCLK_DIV SCLKOUT2
MCLK
2DEFAULT
1DEFAULT
64DEFAULT
Clock Management
Input
Audio Core Output Microprocessor Controller
Oversample Clock Master/Slave Controller (Default) 1/2N
Master
1/(M+1)
8-Bit WARP 8051 Microprocessor
(Default)
2xSDA
2xSCL
B0078-01
Figure 5-2. DPLL Clock Management Block Diagram
Clock Controls
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
CRYSTAL MCLKI DIGITAL AUDIO PROCESSOR CLOCK MICROPROCESSOR CLOCK SAMPLING CLOCK MODULE 1/(M+1)
PLL2
PLL1 PLL0
MCLKO
XTALI
XTALO
assigns time slots those outputs involving TAS3108s. these output formats, TAS3108 chips must defined `0'. other TAS3108 chip must defined `1'. Word Size Code IW2/OW2 IW1/OW1 IW0/OW0
[1:0]
Word Size
32-bit 16-bit 20-bit 24-bit
Data Word Format (DWMFT)
IW[2:0] OW[2:0]
NOTE: Input output word sizes independent.
0x00
1918
N[2:0]
M[3:0]
Slave Addr
Sub-Addr w[1:0] y[2:0] x[2:0] z[2:0] DWMFT
0x01
MASTER
Slave Addr Sub-Addr 00000000 00000000 00000000 0xxxxxxx
1000
÷128 ÷192 ÷256 ÷384 ÷512 SCLKOUT2 SCLKOUT1 SCLKIN
IM[3:0]
OM[3:0]
Serial Audio Port (AP) Mode Code Mode IM3/OM3 IM2/OM2 IM1/OM1 IM0/OM0 Discrete, left justified Discrete, right justified Discrete, TDM_LJ_8 TDM_LJ_6 TDM_LJ_4 TDM_I2S_8 TDM_I2S_6 TDM_I2S_4 Discrete, Discrete, Discrete, Discrete, Discrete, Discrete, Discrete,
Figure 5-3. Serial Data Format, Clock Management, Assignments
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When serial audio port (SAP) master mode, uses MCLKI XTALI master clock drive serial port clocks SCLKOUT1, SLCKOUT2, LRCLK. When slave mode, LRCLK input SCLKOUT2 SCLKOUT1 derived from SCLKIN. shown Figure 5-2, SCLKOUT1 clocks data into input SCLKOUT2 clocks data from output SAP. distinct clocks required support TDM-to-discrete discrete-to-TDM data-format conversions. Such format conversions also require that SCLKIN higher-valued bit-clock frequency. TDM-in/discrete-out format conversions, SCLKIN must equal input clock. discrete-in/TDM-out format conversions, SCLKIN must equal output clock. frequency settings SCLKOUT1, SCLKOUT2, LRCLK master mode, well master/slave mode selection, controlled commands. Table lists default settings power turnon after received reset. Table 5-3. TAS3108/TAS3108IA Clock Default Settings
CLOCK SCLKOUT1 SCLKOUT2 MCLKO LRCLK Audio clock Microprocessor clock multiply ratio sampling clock master DEFAULT SETTING SCLKIN SCLKIN MCLKI XTALI Input pins PLL0 PLL1 MICROCLK_DIV
selections provided dedicated TAS3108/TAS3108IA input pins programmable settings provided subaddress commands give TAS3108/TAS3108IA variety clocking options. However, following clocking restrictions must adhered MCLKI XTALI
NOTE some modes, MCLKI XTALI must
Audio clock <136 Microprocessor clock/20 clock Microprocessor clock oversample clock/20 clock XTALI MCLKI
long these restrictions met, other clocking options allowed. Section information programming clock register.
Clock Controls
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Table 5-4. TAS3108/TAS3108IA MCLK LRCLK Common Values (MCLK 12.288 MCLK 11.2896 MHz)
Sample Rate (kHz) SDIN MCLK/ LRCLK MCLK Freq Ratio (MHz) SCLKIN Rate SCLKIN Freq (MHz) MCLK/ SCLK SCLK OUT1 Rate SCLK OUT2 Rate LRCLK Rate 128, 192, 256, 384, Input Divider (pins PLL0, PLL1) Multiplier (pin PLL2) fDSPCLK (MHz) 135.2
SDOUT
fDSPCLK/fS
Slave Mode, Channels Channels 44.1 88.2 176.4 44.1 88.2 44.1 88.2 44.1 88.2 44.1 88.2 176.4 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 12.288 11.2896 12.288 11.2896 12.288 11.2896 2.048 2.822 3.072 5.645 6.144 11.290 12.288 11.290 12.288 11.290 6.144 11.290 12.288 11.290 12.288 11.290 12.288 11.290 12.288 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 135.2 124.2 135.2 124.2 135.2 124.2 4224 2816 2816 1408 1408 2816 2816 1408 1408 2816 2816 1408 1408 2816 2816 1408 1408 4224 2816 2816 1408 1408
Slave Mode, Channels
Slave Mode, Channels
Slave Mode,
Master Mode, Channels Channels
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Table 5-4. TAS3108/TAS3108IA MCLK LRCLK Common Values (MCLK 12.288 MCLK 11.2896 MHz) (continued)
Sample Rate (kHz) 44.1 88.2 44.1 44.1 88.2 44.1 44.1 88.2 44.1 SDIN MCLK/ LRCLK MCLK Freq Ratio (MHz) 12.288 11.2896 12.288 11.2896 12.288 12.288 11.2896 12.288 12.288 11.2896 12.288 11.2896 12.288 12.288 11.2896 12.288 12.288 11.2896 12.288 11.2896 12.288 12.288 11.2896 12.288 12.288 SCLKIN Rate SCLKIN Freq (MHz) MCLK/ SCLK SCLK OUT1 Rate SCLK OUT2 Rate LRCLK Rate 128, 192, 256, 384, Input Divider (pins PLL0, PLL1) Multiplier (pin PLL2) fDSPCLK (MHz) 135.2 135.2 124.2 135.2 124.2 135.2 135.2 124.2 135.2 135.2 124.2 135.2 124.2 135.2 135.2 124.2 135.2 135.2 124.2 135.2 124.2 135.2 135.2 124.2 135.2 135.2
SDOUT
fDSPCLK/fS
2816 2816 1408 1408 4224 2816 2816 4224 2816 2816 1408 1408 4224 2816 2816 4224 2816 2816 1408 1408 4224 2816 2816 4224
Master Mode, Channels
Master Mode, Channels
Master Mode,
Clock Controls
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Microprocessor Controller
8051 microprocessor receives distributes write data, retrieves outputs controllers required read data, participates most processing tasks requiring multiframe processing cycles. microprocessor data storing intermediate values queuing commands, fixed boot-program ROM, program RAM. microprocessor boot program cannot altered. microprocessor controller specialized hardware master slave interface operation, volume updates, programmable interval timer interrupt. more information, TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067). TAS3108/TAS3108IA slave-only interface that compatible with inter-IC (I2C) protocol supports both 100-kbps 400-kbps data-transfer rates multiple 4-byte write read operations (maximum bytes). slave control interface used program registers device read device status. TAS3108/TAS3108IA also master-only interface that compatible with protocol supports 375-kbps data transfer rates multiple 4-byte write read operations (maximum bytes). master interface used load program data from external EEPROM. power TAS3108/TAS3108IA, slave interface disabled master interface enabled. Following reset, TAS3108/TAS3108IA disables slave interface enables master interface. Using master interface, TAS3108/TAS3108IA automatically tests EEPROM address 1010xxx. value chip select, other information, don't cares, depending EEPROM selected. memory present contains correct header information more blocks program/memory data, TAS3108/TAS3108IA loads program, coefficient, and/or data memories from EEPROM. memory present, download complete when header read that zero-length data segment. this point, TAS3108/TAS3108IA disables master interface, enables slave interface, starts normal operation. memory present error occurred during EEPROM read, TAS3108/TAS3108IA disables master interface, enables slave interface, loads unprogrammed default configuration. this default configuration, TAS3108/TAS3108IA streams eight channels audio from input output GPIO LOW. master slave interfaces operate simultaneously. slave mode, used Load program coefficient data Microprocessor program memory Microprocessor extended memory Audio core program memory Audio core coefficient memory Audio core data memory Update coefficient other control values Read status flags Once microprocessor program memory been loaded, cannot updated until TAS3108/TAS3108IA been reset. master slave modes operate simultaneously. When acting master, data transfer rate fixed kHz, assuming MCLKI XTALI 12.288 MHz, PLL0 PLL1 MICROCLK_DIV When acting slave, data transfer rate determined master device bus. communication protocol slave mode shown Figure 6-1.
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Start Master) Slave Address Master)
Read Write Master) Data Byte Transmitter) Data Byte Transmitter)
Stop Master)
Acknowledge TAS3108/TAS3108IA)
Acknowledge Receiver)
Acknowledge Receiver)
Start Condition While
MSB-1 MSB-2
Stop Condition While
T0087-01
Figure 6-1. Slave-Mode Communication Protocol
General Operations
shown Figure 6-2, read transaction requires that master device first issue write transaction give TAS3108/TAS3108IA subaddress used read transaction that follows. This subaddress assignment write transaction then followed read transaction. write transactions, subaddress supplied first byte data written, this byte followed data written. write transactions, subaddress must always included data written. There cannot separate write transaction supply subaddress, required read transactions. subaddress assignment-only write transaction followed second write transaction supplying data, erroneous behavior results. first byte second write transaction interpreted TAS3108/TAS3108IA another subaddress replacing previously written.
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Read Transaction
Start Master) Write Master) TAS3108/ TAS3108IA Subaddress Master) Stop Start Master) Master) Read Master) Data TAS3108/ TAS3108IA) Data TAS3108/ TAS3108IA) Stop Master)
TAS3108/ TAS3108IA Address
Subaddress
TAS3108/ TAS3108IA Address
Data
Data
7-Bit Slave Address Master)
Acknowledge TAS3108/ TAS3108IA)
Acknowledge TAS3108/ TAS3108IA)
7-Bit Slave Address Master)
Acknowledge TAS3108/ TAS3108IA)
Acknowledge Master)
Acknowledge Master)
Acknowledge Master)
Write Transaction
TAS3108/ TAS3108IA Subaddress Master)
Start Master)
Write Master)
Data Master)
Data Master)
Stop Master)
TAS3108/ TAS3108IA Address
Subaddress
Data
Data
7-Bit Slave Address Master)
Acknowledge TAS3108/ TAS3108IA)
Acknowledge TAS3108/ TAS3108IA)
Acknowledge TAS3108/ TAS3108IA)
Acknowledge TAS3108/ TAS3108IA)
Acknowledge TAS3108/ TAS3108IA)
R0006-01
Figure 6-2. Subaddress Access Protocol
Detailed Operation
slave mode mode that used change configuration parameters during operation perform program coefficient downloads from master device. latter used replace master-mode EEPROM download. TAS3108/TAS3108IA supports both random sequential transactions. TAS3108/TAS3108IA slave address 011010xy, where first bits TAS3108/TAS3108IA device address CS0, which TAS3108/TAS3108IA internal microprocessor power bit. pulldown resistance creates default address when connection made pin. Table Table show legal addresses slave master modes. TAS3108/TAS3108IA block does respond broadcast address (00h). Table 6-1. Slave Addresses
BASE ADDRESS 0110 0110 0110 0110 SLAVE ADDRESS 0x68 0x69 0x6A 0x6B
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Table 6-2. Master Addresses
BASE ADDRESS 1010 1010 1010 1010 MASTER ADDRESS 0xA0 0xA1 0xA2 0xA3
following example master address access external EEPROM. TAS3108/TAS3108IA address EEPROMs depending state CS0. Initially, TAS3108/TAS3108IA comes master mode. finds memory such 24C512 EEPROM, reads headers data previously described. this master mode, TAS3108/TAS3108IA addresses EEPROMs shown Table Table 6-4. Table 6-3. EEPROM Address TAS3108/TAS3108IA Master Mode 0xA1/A0
(EEPROM)
Table 6-4. EEPROM Address TAS3108/TAS3108IA Master Mode 0xA3/A2
(EEPROM)
Random Transactions Supplying subaddress each subaddress transaction referred random addressing. random read commands, TAS3108/TAS3108IA responds with data, byte time, starting subaddress assigned, long master device continues respond with acknowledges. given subaddress does bits, unused bits read logic write commands, however, treated accordance with data assignment that address space. write command received biquad subaddress, example, TAS3108/TAS3108IA expects five 32-bit words. fewer than five data words have been received when stop command another start command) received, data received discarded. Sequential Transactions TAS3108/TAS3108IA also supports sequential addressing. write transactions, subaddress issued followed data that subaddress subaddresses that follow, sequential write transaction taken place, data subaddresses successfully received TAS3108/TAS3108IA. sequential write transactions, subaddress then serves start address, amount data subsequently transmitted before stop start transmitted determines many subaddresses written true random addressing, sequential addressing requires that complete data transmitted. only partial data written last subaddress, data last subaddress discarded. However, other data written accepted; just incomplete data discarded. Sequential read transactions have restrictions outputting only complete subaddress data sets. master does issue enough data-received acknowledges receive data given subaddress, master device does receive data. master device issues more data-received acknowledges than required receive data given subaddress, master device simply receives complete partial sets data, depending many data-received acknowledges issued from subaddress(es) that follow. read transactions, both sequential random, impose wait states.
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standard mode (SCL kHz), worst-case wait state time 8-MHz microprocessor clock order Nominal wait-state time same 8-MHz microprocessor clock order fast mode (SCL kHz) same 8-MHz microprocessor clock, worst-case wait-state time extend 10.5 duration. Nominal wait-state time this same case lies range from Increasing microprocessor clock frequency lowers wait-state time standard mode, faster microprocessor clock totally eliminate presence wait states. example, increasing microprocessor clock results wait states. fast mode, faster microprocessor clocks shorten wait-state time encountered, totally eliminate wait states.
6.2.1
Multiple-Byte Write
Multiple data bytes transmitted master device slave shown Figure 6-3. After receiving each data byte, TAS3108/TAS3108IA responds with acknowledge bit.
Start Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Device Address Read/Write
Subaddress
First Data Byte
Other Data Bytes
Last Data Byte
Stop Condition
T0036-02
Figure 6-3. Multiple-Byte Write Transfer
6.2.2
Multiple-Byte Read
Multiple data bytes transmitted TAS3108/TAS3108IA master device shown Figure 6-4. Except last data byte, master device responds with acknowledge after receiving each data byte.
Repeat Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
Start Condition
Device Address Read/Write
Subaddress
Device Address Read/Write
First Data Byte
Other Data Bytes
Last Data Byte
Stop Condition
T0036-04
Figure 6-4. Multiple-Byte Read Transfer
Master-Mode Device Initialization
master-mode operation enabled following reset power-on reset. Master-mode transactions start until idle. TAS3108/TAS3108IA uses master mode download from EEPROM memory contents microprocessor program memory, microprocessor extended memory, audio core program memory, audio core coefficient memory, audio core data memory. TAS3108/TAS3108IA, when operating master, execute complete download internal memory section internal memory without requiring wait states.
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When TAS3108/TAS3108IA operates master, TAS3108/TAS3108IA generates repeated start without intervening stop command while downloading program memory data from EEPROM. When repeated start sent EEPROM read mode, EEPROM enters sequential read mode transfer large blocks data quickly. TAS3108/TAS3108IA queries EEPROM address 1010xxx. value chip select, other information, don't cares, depending EEPROM selected. first action TAS3108/TAS3108IA master transmit start condition along with device address EEPROM with read/write cleared indicate write. EEPROM acknowledges address byte, TAS3108/TAS3108IA sends subaddress byte, which EEPROM acknowledges. Most EEPROMs have least 2-byte addresses acknowledge many appropriate. this point, EEPROM sends last acknowledge becomes slave transmitter. TAS3108/TAS3108IA acknowledges each byte repeatedly continue reading each data byte that stored memory. memory load information starts with reading header data information that starts subaddress EEPROM. This information must then stored sequential memory addresses with intervening gaps. data blocks contiguous blocks data that immediately follow header locations. TAS3108/TAS3108IA memory data stored loaded (almost) order. Additionally, this addressing scheme permits portions TAS3108/TAS3108IA internal memories loaded.
EEPROM Memory
Block Header
Data Block
Block Header
Data Block
Block Header
Data Block
M0040-01
Figure 6-5. EEPROM Address TAS3108/TAS3108IA sequentially reads EEPROM memory loads internal memory unless does find valid memory header block, able read next memory location because memory reached, detects checksum error, reads end-of-program header block. When encounters invalid header read error, TAS3108/TAS3108IA attempts read header memory location three times before determines that error. TAS3108/TAS3108IA encounters checksum error attempts reread entire block memory more times before determines that error.
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Once microprocessor program memory been loaded, cannot reloaded until TAS3108/TAS3108IA been reset. error encountered, TAS3108/TAS3108IA terminates memory-load operation, loads default configuration, disables further master operations. end-of-program data block read, TAS3108/TAS3108IA completed initial program load. master mode uses starting ending checksums verify proper EEPROM download. first 16-bit data word received from EEPROM, checksum subaddress 0x00, stored compared against 16-bit data word received last subaddress, ending checksum, checksum that computed during download. These three values must equal. read computed values match, TAS3108/TAS3108IA sets memory read error bits status register repeats download from EEPROM more times. comparison check fails third time, TAS3108/TAS3108IA sets microprocessor program default value. Table shows format EEPROM other external memory load file. Each line file byte ASCII format). checksum summation bytes (with beginning ending checksum fields 00). final checksum inserted into checksum field lowest significant four bytes checksum. Example: Given following example 8051 data program block (must multiple bytes these blocks): checksum 240h, values checksum fields byte byte 40h. checksum FFFFh, 2-byte checksum field least-significant bytes. example, checksum 45B6h, checksum field byte byte B6h.
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Table 6-5. TAS3108/TAS3108IA Memory Block Structures
STARTING BYTE DATA BLOCK FORMAT SIZE 12-Byte Header Block Checksum code byte Checksum code byte Header byte 0x00 Header byte 0x1F Memory loaded byte 0x00 Microprocessor program memory termination header 0x01 Microprocessor external data memory 0x02 Audio core program memory 0x03 Audio core coefficient memory 0x04 Audio core data memory 0x05-0x0F Reserved future expansion Unused this termination header, this value 0000. bytes Must 0x001F TAS3108/TAS3108IA load bytes Checksum bytes through NOTES
0x00 Start TAS3108/TAS3108IA memory address byte Start TAS3108/TAS3108IA memory address byte Total number bytes transferred byte Total number bytes transferred byte 0x00 0x00 Data byte byte) Data byte Data byte Data byte byte)
byte bytes
bytes bytes bytes bytes
data bytes last checksum bytes. this termination header, this value 0000. Unused Unused microprocessor bytes
Data Block Microprocessor Program Data Memory (Following 12-Byte Header)
Data byte Data byte Data byte Data byte
bytes
microprocessor bytes
Data byte 4*(Z Data byte 4*(Z Data byte 4*(Z Data byte 4*(Z
bytes
0x00 0x00 Checksum code byte Checksum code byte
bytes
Repeated checksum bytes through
Data Block Audio Core Coefficient Memory (Following 12-Byte Header) Data byte byte) Data byte Data byte Data byte byte) bytes Coefficient word (valid data D27-D0) D7-D0 D15-D8 D23-D16 D31-D24
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Table 6-5. TAS3108/TAS3108IA Memory Block Structures (continued)
STARTING BYTE DATA BLOCK FORMAT Data byte Data byte Data byte Data byte Data byte 4*(Z Data byte 4*(Z Data byte 4*(Z Data byte 4*(Z 0x00 0x00 Checksum code byte Checksum code byte Data Block Audio Core Data Memory (Following 12-Byte Header) Data byte byte) Data byte Data byte Data byte Data byte Data byte byte) Data byte Data byte Data byte Data byte Data byte Data byte Data byte 6*(Z Data byte 6*(Z Data byte 6*(Z Data byte 6*(Z Data byte 6*(Z Data byte 6*(Z 0x00 0x00 0x00 0x00 Checksum code byte Checksum code byte bytes Repeated checksum bytes through bytes Data bytes bytes Data word D7-D0 D15-D8 D23-D16 D31-D24 D39-D32 D47-D40 Data bytes Repeated checksum bytes through bytes Coefficient word SIZE bytes Coefficient word NOTES
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Table 6-5. TAS3108/TAS3108IA Memory Block Structures (continued)
STARTING BYTE DATA BLOCK FORMAT SIZE NOTES
Data Block Audio Core Program Memory (Following 12-Byte Header) Program byte byte) Program byte Program byte Program byte Program byte Program byte Program byte byte) Program byte Program byte Program byte Program byte Program byte Program byte Program byte Program byte 7*(Z Program byte 7*(Z Program byte 7*(Z Program byte 7*(Z Program byte 7*(Z Program byte 7*(Z Program byte 7*(Z 0x00 0x00 0x00 0x00 0x00 Checksum code byte Checksum code byte 20-Byte Termination Block (Last Block Entire Load Block) BLAST BLAST BLAST BLAST BLAST 0x00 0x00 0x00 0x1F 0x00 0x00 0x00 byte byte byte Last bytes must each 0x00. bytes Second bytes always 0x001F. bytes First bytes termination block always 0x0000. bytes Repeated checksum bytes through bytes Program word bytes bytes Program word (valid data D53-D0) D7-D0 D15-D8 D23-D16 D31-D24 D39-D32 D47-D40 D55-D48 Program word
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Register
SUBADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0xFE 0xFF indicates unused bits. User-defined User-defined
REGISTER NAME Clock control register Reserved Status register Unused memory load control register memory load data register PEEK/POKE address PEEK/POKE data Version number User-defined User-defined
BYTES
CONTENTS Description shown Section Reserved Description shown Section Description shown Section Description shown Section u(31:24) (1), MemSelect(23:16), Addr(15:8), Addr(7:0) D(63:56), D(55:48), D(47:40), D(39:32), D(31:24), D(23:16), D(15:8), D(7:0) TAS3108/TAS3108IA version User-defined register User-defined register User-defined register User-defined register
INITIALIZATION VALUE 0x01, 0x00, 0x1B, 0x22 0x00, 0x00, 0x00, 0x40 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x01 User-defined User-defined
User-defined User-defined
following sections, BOLD indicates default state fields.
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Clock Control Register (0x00)
Register 0x00 provides user with control over MCLK, LRCLK, SCLKOUT1, SCLKOUT2, data-word size, serial audio port modes. Register 0x00 default 0x0100 1B22. Table 7-1. Clock Control Register (0x00)
Input data format Output data format Don't care Don't care Input audio data word size Don't care Output audio data word size DESCRIPTION Used Master clock output divider Master mode LRCLK divider DESCRIPTION SCLKOUT select (default master/slave select master mode, slave mode) SCLKIN SCLKOUT clock divide MCLK, SCLK ratio (master mode only) DESCRIPTION DESCRIPTION
7.1.1
Master Clock Output Divider
Bits 28-27 define ratio between MCLKI crystal frequency) MCLKO. This allows accommodation devices that require MCLK LRCLK devices that require MCLK LRCLK, without having glue logic divide that clock down. This meaning whether clock-master clock-slave mode.
MCLKO MCLKI MCLKO MCLKI/2 MCLKO MCLKI/4 MCLKO MCLKI/4
DESCRIPTION
Register
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7.1.2
Master Mode LRCLK Divider
Bits 26-24 (Y2, define ratio between SCLK LRCLK, only have meaning clock-master mode where LRCLK output. clock-slave mode, LRCLK input.
LRCLK SCLK/32 LRCLK SCLK/64 LRCLK SCLK/128 LRCLK SCLK/192 LRCLK SCLK/256 LRCLK SCLK/384 LRCLK SCLK/512 LRCLK SCLK/32
DESCRIPTION
7.1.3
SCLKIN SCLKOUT Clock Divide
Bits 21-19 (X2, define ratio between SCLKIN SCLKOUT. These control bits only used when input output rates different, which happen discrete modes both used (for example, input output discrete). Normally, these bits 000, that SCLKOUT1 (input SCLK) SLCKOUT2 (output SCLK) same. (Note that SCLKIN input SCLK, used clock-slave mode derive SCLKOUT1.)
IMS_MUX/2 IMS_MUX/3 IMS_MUX/4 IMS_MUX/6 IMS_MUX/8 IMS_MUX/16 IMS_MUX/32
DESCRIPTION IMS_MUX (master/slave SCLK)
7.1.4
MCLK, SCLK Ratio (Master Mode Only)
Bits 18-16 (Z2, define ratio between MCLK SCLK when TAS3108/TAS3108IA clock master. clock-slave mode, these bits don't care.
MCLK/2 MCLK/3 MCLK/4 MCLK/6 MCLK/8 MCLK/16 MCLK/32
DESCRIPTION MCLK (MCLKI crystal oscillator)
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7.1.5
Audio Data Word Size
Bits 12-11 (IW1 IW0) define data word size input SAP. Bits (OW1 OW0) define data word size output SAP.
IW1/OW1
IW0/OW0 32-bit audio data 16-bit audio data 20-bit audio data 24-bit audio data
DESCRIPTION
7.1.6
Input Output Data Format
Bits (IM3, IM2, IM1, IM0) define input data format. Bits (OM3, OM2, OM1, OM0) define output data format. formats need same, only compatible.
IM3/OM3
IM2/OM2
IM1/OM1
IM0/OM0 channel, left justified channel, right justified channel, TDM, left justified channels) TDM, left justified channels) TDM, left justified channels) TDM, channels) TDM, channels) TDM, channels) channel, channel, channel, channel, channel, channel, channel,
DESCRIPTION
Register
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Status Register (0x02)
During download, write operation indicate that particular memory written causes TAS3108/TAS3108IA error indicate load that memory type. This error cleared when operation completes successfully. Table 7-2. Status Register (0x02)
Firmware definable DESCRIPTION Microprocessor program memory load error Microprocessor external data memory load error Audio core program memory load error Audio core coefficient memory load error Audio core data memory load error Invalid memory select End-of-load header error EPROM present errors Firmware definable DESCRIPTION Firmware definable DESCRIPTION DESCRIPTION
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Memory Load Control Data Registers (0x04 0x05)
Registers 0x04 (Table 7-3) 0x05 (Table 7-4) allow user download TAS3108/TAS3108IA program code data directly from system controller. This mode called slave mode (from TAS3108/TAS3108IA point-of-view). TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) more details. Table 7-3. TAS3108/TAS3108IA Memory Load Control Register (0x04)
BYTE DATA BLOCK FORMAT Checksum code Memory loaded SIZE bytes bytes NOTES Checksum bytes through this termination header, this value 0000. Microprocessor program memory Microprocessor external data memory Audio core program memory Audio core coefficient memory Audio core data memory 5-15 Reserved future expansion Reserved future expansion this termination header this value 0000. this termination header this value 0000.
Unused Starting TAS3108/TAS3108IA memory address Number data bytes transferred
byte bytes bytes
Table 7-4. TAS3108/TAS3108IA Memory Load Data Register (0x05)
BYTE 8-BIT DATA Datum D7-D0 Datum D7-D0 Datum D7-D0 Datum D7-D0 Datum D7-D0 Datum D7-D0 Datum D7-D0 Datum D7-D0 28-BIT DATA 0000 D27-D24 D7-D0 D15-D8 D7-D0 0000 D27-D24 D23-D16 D15-D8 D7-D0 48-BIT DATA 0000 0000 0000 0000 D47-D40 D39-D32 D31-D24 D23-D16 D15-D8 D7-D0 54-BIT DATA 0000 0000 D53-D48 D47-D40 D39-D32 D31-D24 D23-D16 D15-D8 D7-D0
Register
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
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Memory Access Registers (0x06 0x07)
Registers 0x06 (Table 7-5) 0x07 (Table 7-6) allow user access internal resources TAS3108/TAS3108IA. TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) more details. Table 7-5. Memory Select Address Register (0x06)
Memory address Memory address DESCRIPTION Unused DESCRIPTION Audio core coefficient memory select Audio core data memory select Reserved Microprocessor internal data memory select Microprocessor external data memory select select Microprocessor program select Audio core program select DESCRIPTION DESCRIPTION
Table 7-6. Data Register (Peek Poke) (0x07)
Data written read Data written read DESCRIPTION Data written read DESCRIPTION Data written read DESCRIPTION Data written read DESCRIPTION Data written read DESCRIPTION Data written read DESCRIPTION Data written read DESCRIPTION DESCRIPTION
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Register
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Electrical Specifications
Absolute Maximum Ratings Over Operating Temperature Range (unless otherwise noted)
Supply voltage range, DVDD Supply voltage, AVDD Tstg Input voltage range Output voltage range 3.3-V LVCMOS (XTLI) LVCMOS (XTLO) -0.5 -0.5 -0.5 DVDD -0.5 -0.5 DVDD -0.5 2.3V 70°C -40°C 105°C -65°C 150°C
Input clamp current DVDD Output clamp current DVDD) TAS3108 operating free-air temperature TAS3108IA operating free-air temperature Storage temperature range
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. XTALO only TAS3108/TAS3108IA output that derived from internal 1.8-V logic supply. absolute maximum rating listed reference; only crystal should connected XTALO.
Package Dissipation Ratings (TAS3108/TAS3108IA)
PACKAGE TYPE TSSOP COUNT DESIGNATOR TAS3108IA (°C/W) 27.41 (°C/W) 0.72 52.93 TAS3108 (°C/W) (°C/W) 0.72
trace thermal with solder trace thermal without solder
Application Information, Section recommendations TAS3108IA applications.
Recommended Operating Conditions (TAS3108/TAS3108IA)
Digital supply voltage, DVDD LVCMOS (XTL_IN) LVCMOS (XTL_IN) TAS3108 TAS3108IA TAS3108 TAS3108IA UNIT
High-level input voltage Low-level input voltage Operating ambient temperature Operating junction temperature
Electrical Specifications
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Electrical Characteristics (TAS3108/TAS3108IA)
over recommended operating conditions (unless otherwise noted)
PARAMETER 3.3-V High-level output voltage 1.8-V LVCMOS (XTL_OUT) 3.3-V Low-level output voltage High-impedance output current Low-level input current High-level input current 1.8-V LVCMOS (XTL_OUT) 3.3-V 3.3-V 1.8-V LVCMOS (XTL_IN) 3.3-V 1.8-V LVCMOS (XTL_IN) TEST CONDITIONS -0.55 0.75 MCLKI 24.576 MHz, LRCLK IDVDD Digital supply current Normal operation MCLKI 12.288 MHz, LRCLK MCLKI 8.192 MHz, LRCLK Power down enabled IA_DVDD Analog supply current Normal operation Power down enabled LRCLK, SCLK, MCLKI running MCLKI 24.576 MHz, LRCLK LRCLK, SCLK, MCLKI running 1.44 UNIT
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Timing Characteristics
following sections describe timing characteristics TAS3108/TAS3108IA.
8.5.1
Master Clock Signals (TAS3108/TAS3108IA)
PARAMETER TEST CONDITIONS
over recommended operating conditions (unless otherwise noted)
UNIT
f(XTALI) tc(1) f(MCLKI) tw(MCLKI) f(MCLKO) tr(MCLKO) tf(MCLKO) tw(MCLKO)
Frequency, XTALI tc(1)) Cycle time, XTALI Frequency, MCLKI tc(2)) Pulse duration, MCLKI high MCLKI jitter Frequency, MCLKO tc(3)) Rise time, MCLKO Fall time, MCLKO Pulse duration, MCLKO high MCLKO jitter XTALI master clock source
tc(2)
tc(2) tc(2)
HMCLKO
MCLKI master clock source
td(MI-MO)
Delay time, MCLKI rising MCLKO MCLKI edge MCLKO rising MCLKO MCLKI edge
Duty cycle 50/50. This measurement specified design. Period MCLKI TMCLKI fMCLKI HMCLKO 1/(2 MCLKO). MCLKO same duty cycle MCLKI when MCLKO MCLKI. When MCLKO MCLKI 0.25 MCLKI, duty cycle MCLKO typically 50%. When MCLKO derived from MCLKI, MCLKO jitter MCLKI jitter Only applies when MCLKI selected master source clock Also applies MCLKO falling edge when MCLKO MCLKI/2 MCLKI/4.
XTALI tc(1) tw(MCLKI) MCLKI tc(2) tw(MCLKO) tf(MCLKO) MCLKO tc(3)
T0088-01
td(MI-MO) tr(MCLKO)
Figure 8-1. Master Clock Signal Timing Waveforms
Electrical Specifications
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SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
8.5.2
Serial Audio Port Slave Mode Signals (TAS3108/TAS3108IA)
PARAMETER TEST CONDITIONS
over recommended operating conditions (unless otherwise noted)
tc(SCLKIN)
UNIT
fLRCLK fSCLKIN tpd1 tsu1 tsu2 tpd2
Frequency, LRCLK (fS) Frequency, SCLKIN Propagation delay, SCLKIN falling edge SDOUT Setup time, LRCLK SCLKIN rising edge Hold time, LRCLK from SCLKIN rising edge Setup time, SDIN SCLKIN rising edge Hold time, SDIN from SCLKIN rising edge Propagation delay, SCLKIN falling edge SCLKOUT2 falling edge
tw(SCLKIN) Pulse duration, SCLKIN high
tc(SCLKIN) tc(SCLKIN)
tc(SCLKIN)
This measurement specified design. Period SCLKIN TSCLKIN 1/fSCLKIN Duty cycle 50/50.
tw(SCLKIN) tc(SCLKIN)
SCLKIN
tsu1 LRCLK (Input)
tpd1 SDOUT1 SDOUT2 SDOUT3 SDOUT4 tsu2 SDIN1 SDIN2 SDIN3 SDIN4 tpd2 SCLKOUT2
T0090-01
Figure 8-2. Serial Audio Port Slave Mode Timing Waveforms
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
8.5.3
Serial Audio Port Master Mode Signals (TAS3108/TAS3108IA)
PARAMETER TEST CONDITIONS
over recommended operating conditions (unless otherwise noted)
UNIT
f(LRCLK) tr(LRCLK) tf(LRCLK) f(SCLKOUT) tr(SCLKOUT) tf(SCLKOUT) tpd1(SCLKOUT1) tpd1(SCLKOUT2) tpd2 t(SKEW)
Frequency LRCLK Rise time, LRCLK Fall time, LRCLK
Duty cycle 50/50.
Frequency, SCLKOUT1/SCLKOUT2 Rise time, SCLKOUT1/SCLKOUT2 Fall time, SCLKOUT1/SCLKOUT2 Propagation delay, SCLKOUT1 falling edge LRCLK edge Propagation delay, SCLKOUT2 falling edge LRCLK edge Propagation delay, SCLKOUT2 falling edge SDOUT Setup time, SDIN SCLKOUT1 rising edge Hold time, SDIN from SCLKOUT1 rising edge Skew time, SCLKOUT1 SCLKOUT2
This measurement specified design. Rise time fall time measured from maximum height waveform.
tr(SCLKOUT) tf(SCLKOUT)
SCLKOUT2 tr(SCLKOUT) tf(SCLKOUT) SCLKOUT1 tpd1(SCLKOUT2) tpd1(SCLKOUT1) LRCLK (Output) tf(LRCLK), tr(LRCLK) SDOUT1 SDOUT2 SDOUT3 SDOUT4 tpd2
SDIN1 SDIN2 SDIN3 SDIN4
T0091-01
Figure 8-3. TAS3108/TAS3108IA Serial Audio Port Master Mode Timing Waveforms
Electrical Specifications
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SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
8.5.4 Pin-Related Characteristics Stages F/S-Mode 2C-Bus Devices
PARAMETER Vhys VOL1 tSP(SCL) tSP(SDA) LOW-level input voltage HIGH-level input voltage Hysteresis inputs LOW-level output voltage (open drain open collector) Output fall time from VIHmin VILmax Input current, each pulse duration spikes that must suppressed input filter pulse duration spikes that must suppressed input filter Capacitance, each 3-mA sink current capacitance from TEST CONDITIONS STANDARD MODE -0.5 FAST MODE -0.5 0.05
UNIT
This measurement specified design. capacitance line output fall time faster than standard specification. pins fast-mode devices must obstruct lines switched off. These values valid 135-MHz clock rate. clock reduced half, doubles.
NOTE does have standard specification 300-ns internal hold time. must valid rising falling edges SCL.
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
8.5.5
Bus-Related Characteristics Stages F/S-Mode 2C-Bus Devices
values referred VIHmin VILmax (see Section 8.5.4).
PARAMETER fSCL tHD-STA tLOW tHIGH tSU-STA tSU-DAT tHD-DAT tSU-STO tBUF clock frequency Hold time (repeated) START condition. After this period, first clock pulse generated. period clock HIGH period clock Setup time repeated START Data setup time Data hold time
TEST CONDITIONS
STANDARD MODE
FAST MODE
UNIT
3.45 1000
Rise time both signals Fall time both Setup time STOP condition free time between STOP START condition Capacitive load each line Noise margin level each connected device (including hysteresis) Noise margin HIGH level each connected device (including hysteresis) VDVDD
VDVDD
VDVDD
VDVDD
This measurement specified design. master mode, maximum speed kHz. Note that does have standard specification 300-ns internal hold time. must valid rising falling edges SCL. recommends that pullup resistor used avoid potential timing issues. fast-mode I2C-bus device used standard-mode I2C-bus system, requirement tSU-DAT must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line tr-max tSU-DAT 1000 1250 (according standard-mode specification) before line released. total capacitance line
tLOW tSU-DAT tHD-STA tBUF
tHD-DAT tHD-STA tHIGH
tSU-STA
tSU-STO
T0114-01
Figure 8-4. Start Stop Conditions Timing Waveforms
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TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
8.5.5.1 Recommended Pullup Resistors recommended that pullup resistors (see Figure 8-5). series resistor circuit (see Figure 8-6), then series resistor should less than equal
DVDD TAS3108/TAS3108IA VI(SDA) VI(SCL) External Microcontroller
B0099-03
Figure 8-5. Pullup Circuit (With Series Resistor)
DVDD TAS3108/TAS3108IA
External Microcontroller
B0100-03
DVDD RS/S RP). When driven low, requirements.
Figure 8-6. Pullup Circuit (With Series Resistor)
8.5.6 Reset Timing (TAS3108/TAS3108IA)
control signal parameters over recommended operating conditions; these measurements specified design (unless otherwise noted)
PARAMETER tw(RESET) tr(run) Pulse duration, RESET active Time enable
TEST CONDITIONS PLL0 PLL1 MICROCLK_DIV
UNIT
This measurement specified design.
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Electrical Specifications
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
RESET Start Boot Sequence tw(RESET) Outputs Inactive tr(run) Enable Start System
T0029-02
NOTE: MCLK input 12.288
Figure 8-7. Reset Timing
Electrical Specifications
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SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Application Information
Schematics
Figure shows typical TAS3108/TAS3108IA application. this application, following conditions apply: TAS3108/TAS3108IA clock-slave mode. audio (SDIN1, SDIN2, SDIN3, SDIN4) clock source (MCLKI) external. MCLKI 12.288 Because MCLKI sourced externally, TAS3108/TAS3108IA crystal interface used. MCLKI XTLI logically ORed together, meaning that when MCLKI used, XTALI must grounded. register 0x00 contains default settings which means: Audio data word size 24-bit input 24-bit output. Serial data format channel, input output. data transfer approximately kbps both master slave interfaces. PLL0 PLL1 PLL2 means that fDSPCLK MCLKI 135.2 that fI2CSCL kHz. Sample frequency (fS) kHz, which requires that fLRCLK fSCLKIN 3.072 MHz. Application code data loaded from external EEPROM using master interface. Application commands come from system microprocessor TAS3108/TAS3108IA using slave interface.
Good design practice requires isolation between digital analog power shown. Power-supply capacitors should placed near power-supply pins AVDD (AVSS) DVDD (DVSS). TAS3108/TAS3108IA reset needs external glitch protection. Also, reset going HIGH should delayed until TAS3108/TAS3108IA internal power good (~200 µs). This provided resistor, 1-µF capacitor, diode placed near RESET pin. recommended that 4.7-µF capacitor (fast ceramic type) placed near (VR_DIG). This must used source external components.
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Application Information
TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
0.01 Audio Clock Source System Microprocessor System Reset
AVSS VR_PLL XTALI XTALO MCLKI MICROCLK_DIV GPIO DVDD DVSS SDIN1 SDIN2 SDIN3 SDIN4 SDA1 SCL1 SDA2 SCL2 LRCLK TAS3108 (TAS3108IA)
AVDD RESERVED PLL2 PLL1 PLL0 RESERVED RESET DVDD DVSS VR_DIG SDOUT1 SDOUT2 SDOUT3 SDOUT4 SCLKOUT2 SCLKOUT1 MCLKO SCLKIN
3.3V_AVDD
System Reset
Audio Output
DVDD EEPROM (Program Code Data) TAS3108/ TAS3108IA Power Supply µF(1) 3.3V_AVDD AVDD µF(1)
Ferrite Bead
S0123-01
Capacitors should placed close possible power-supply pins.
Figure 9-1. Typical Application Diagram
Application Information
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SLES152B OCTOBER 2005 REVISED NOVEMBER 2007
Recommended Oscillator Circuit
TAS3108/TAS3108IA
Circuit
AVSS
S0114-01
MCLKI XTLI logically ORed together, meaning that when XTALI used, MCLKI must grounded. Crystal type Parallel-mode, fundamental-mode crystal Drive-level control resistor vendor specified Crystal load capacitance (capacitance circuitry between terminals crystal) C2)/C1 (where board stray capacitance,
Recommended Design TAS3108IA Applications
Automotive applications require that TAS3108IA operates properly while ambient temperature range -40° 105°C. Under high-temperature condition 105°C ambient, TAS3108IA thermal must soldered copper area designed thermal relief. High-temperature applications also require that application built high-K dielectric PCB. High-K dielectric requirements using TAS3108IA with soldered thermal pad: 0.062 thick Minimum 3-in 3-in 2-oz copper traces located board (0,071 thick) Copper area located bottom soldering Power ground planes, 1-oz. copper (0,036 thick) Thermal vias, 0.3-mm diameter, 1.5-mm pitch Thermal isolation power plane target application limits ambient temperature 70°C (standard commercial temperature range), thermal does need soldered PCB. more information, PowerPADThermally Enhanced Package (SLMA002) PowerPADMade Easy (SLMA004).
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Application Information
PACKAGE OPTION ADDENDUM
9-Jul-2007
PACKAGING INFORMATION
Orderable Device TAS3108DCP TAS3108DCPG4 TAS3108DCPR TAS3108DCPRG4 TAS3108IADCP TAS3108IADCPG4 TAS3108IADCPR TAS3108IADCPRG4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type HTSSOP HTSSOP HTSSOP HTSSOP HTSSOP HTSSOP HTSSOP HTSSOP
Package Drawing
Pins Package Plan Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-3-260C-168 Level-3-260C-168 Level-3-260C-168 Level-3-260C-168 Level-3-260C-168 Level-3-260C-168 Level-3-260C-168 Level-3-260C-168
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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