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PGA112, PGA113 PGA116, PGA1 www.ti.com SBOS424B MARCH 2008 REVISE


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PGA112, PGA113 PGA116, PGA1
www.ti.com SBOS424B MARCH 2008 REVISED SEPTEMBER 2008
PROGRAMMABLE GAIN AMPLIFIER with
FEATURES
Rail-to-Rail Input/Output Offset: 25µV (typ), 100µV (max) Drift: 0.35µV/°C (typ), 1.2µV/°C (max) Noise: 12nV/Hz Input Offset Current: ±5nA (+25°C) Gain Error: 0.1% 32), 0.3% Binary Gains: (PGA112, PGA116) Scope Gains: 100, (PGA113, PGA117) Gain Switching Time: 200ns Channel MUX: PGA112, PGA113 Channel MUX: PGA116, PGA117 Four Internal Calibration Channels Amplifier Optimized Driving CDAC ADCs Output Swing: 50mV Supply Rails AVDD DVDD Mixed Voltage Systems 1.1mA (typ) Software/Hardware Shutdown: (typ) Temperature Range: -40°C +125°C SPIInterface (10MHz) with Daisy-Chain Capability
CBYPASS 0.1mF AVDD
APPLICATIONS
Remote e-Meter Reading Automatic Gain Control Portable Data Acquisition PC-Based Signal Acquisition Systems Test Measurement Programmable Logic Controllers Battery-Powered Instruments Handheld Test Equipment
DESCRIPTION
PGA112 PGA113 (binary/scope gains) offer analog inputs, three-pin interface, software shutdown MSOP-10 package. PGA116 PGA117 (binary/scope gains) offer analog inputs, four-pin interface with daisy-chain capability, hardware software shutdown TSSOP-20 package. versions provide internal calibration channels system-level calibration. channels tied GND, 0.9VCAL, 0.1VCAL, VREF, respectively. VCAL, external voltage connected Channel used system calibration reference. Binary gains are: 128; scope gains are: 100, 200.
CBYPASS 0.1mF DVDD
CBYPASS 0.1mF MSP430 Microcontroller
PGA112 PGA113 VCAL/CH0 10kW 0.9VCAL 0.1VCAL 80kW CAL1 CAL2 CAL3 CAL4 VREF Interface SCLK Output Stage VOUT
10kW
CAL2/3
VREF
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademark Motorola. other trademarks property their respective owners.
Copyright 2008, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
PGA112, PGA113 PGA116, PGA1SBOS424B MARCH 2008 REVISED SEPTEMBER 2008 www.ti.com
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
PACKAGE MODEL COMPARISON
DEVICE PGA112 PGA113 PGA116 PGA117 INPUTS GAINS (Eight Each) Binary Scope Binary Scope DAISY-CHAIN SHUTDOWN HARDWARE SOFTWARE PACKAGE MSOP-10 MSOP-10 TSSOP-20 TSSOP-20
ORDERING INFORMATION
PRODUCT PGA112 PGA113 PGA116 PGA117 DESCRIPTION (Gains/Channels) Binary (2)/2 Channels Scope (3)/2 Channels Binary Channels Scope (3)/10 Channels
PACKAGE-LEAD MSOP-10 MSOP-10 TSSOP-20 TSSOP-20
PACKAGE DESIGNATOR
PACKAGE MARKING P112 P113 PGA116 PGA1
most current package ordering information Package Option Addendum this document, site www.ti.com. Binary gains: 128. Scope gains: 100, 200.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range, unless otherwise noted.
PGA112, PGA113, PGA116, PGA117 Supply Voltage Signal Input Terminals, Voltage Signal Input Terminals, Current Output Short-Circuit Operating Temperature Storage Temperature Junction Temperature Human Body Model (HBM) Ratings: Charged Device Model (CDM) Machine Model (MM)
UNIT
(AVDD) Continuous +125 +150 +150 3000 1000
Stresses above these ratings cause permanent damage. Exposure absolute maximum conditions extended periods degrade device reliability. These stress ratings only, functional operation device these other conditions beyond those specified implied. Input terminals diode-clamped power-supply rails. Input signals that swing more than 0.5V beyond supply rails should current limited 10mA less.
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ELECTRICAL CHARACTERISTICS: AVDD DVDD
Boldface limits apply over specified temperature range, -40°C +125°C. +25°C, 10k//CL 100pF connected DVDD/2, VREF GND, unless otherwise noted.
PGA112, PGA113, PGA116, PGA117 PARAMETER OFFSET VOLTAGE Input Offset Voltage AVDD DVDD +5V, VREF AVDD/2, 2.5V AVDD DVDD +5V, VREF AVDD/2, 4.5V Temperature, -40°C +125°C Temperature, -40°C +85°C Temperature, -40°C +125°C Temperature, -40°C +85°C Power Supply Over Temperature, -40°C +125°C INPUT ON-CHANNEL CURRENT Input On-Channel Current (Ch0, Ch1) Over Temperature, -40°C +125°C INPUT VOLTAGE RANGE Input Voltage Range Overvoltage Input Range INPUT IMPEDANCE (Channel Channel Input Capacitance Channel Switch Resistance Amplifier Input Capacitance Amplifier Input Resistance VCAL/CH0 GAIN SELECTIONS Nominal Gains Binary gains: Scope gains: 100, Gain Error Gain Drift CAL2 Gain Error
CONDITIONS
UNIT
0.35 0.15
±100 ±325
µV/°C µV/°C µV/°C µV/°C µV/V µV/V
dVOS/dT
AVDD DVDD +5V, 2.5V AVDD DVDD +5V, 2.5V AVDD DVDD +5V, 4.5V AVDD DVDD +5V, 4.5V
PSRR
AVDD DVDD +2.2V +5.5V, 0.5V, VREF AVDD/2 AVDD DVDD +2.2V +5.5V, 0.5V, VREF AVDD/2
VREF AVDD/2 VREF AVDD/2
±1.5
Typical Characteristics
Output Phase Reversal
AVDD AVDD
CAMP RAMP Input Resistance CAL1 CAL2 Selected
0.006
0.02 0.02 ppm/°C ppm/°C ppm/°C ppm/°C ppm/°C
VOUT 85mV DVDD 85mV VOUT 85mV DVDD 85mV VOUT 85mV DVDD 85mV VOUT 85mV DVDD 85mV VOUT 85mV DVDD 85mV VOUT 85mV DVDD 85mV Input 0.9VCAL, VREF VCAL AVDD/2, Input 0.9VCAL, VREF VCAL AVDD/2, Input 0.1VCAL, VREF VCAL AVDD/2, Input 0.1VCAL, VREF VCAL AVDD/2,
CAL2 Gain Drift CAL3 Gain Error CAL3 Gain Drift INPUT IMPEDANCE (Channel Off) Input Impedance INPUT OFF-CHANNEL CURRENT Input Off-Channel Current (Ch0, Ch1) Over Temperature, -40°C +125°C Channel-to-Channel Crosstalk ILKG
Figure
VREF GND, VOFF-CHANNEL AVDD/2, VON-CHANNEL AVDD/2 0.1V VREF GND, VOFF-CHANNEL AVDD/2, VON-CHANNEL AVDD/2 0.1V
±0.05
Typical Characteristics
Gain error function input voltage. Gain error outside range (GND 85mV VOUT DVDD 85mV) increases 0.5% (typical). Input voltages beyond this range must current limited |10mA| through input protection diodes each channel prevent permanent destruction device. Figure Total VOUT error must computed using input offset voltage error multiplied gain. Includes error. Maximum specification limitation limited final test time capability.
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ELECTRICAL CHARACTERISTICS: AVDD DVDD (continued)
Boldface limits apply over specified temperature range, -40°C +125°C. +25°C, 10k//CL 100pF connected DVDD/2, VREF GND, unless otherwise noted.
PGA112, PGA113, PGA116, PGA117 PARAMETER OUTPUT Voltage Output Swing from Rail IOUT ±0.25mA, AVDD DVDD IOUT ±5mA, AVDD DVDD Output Nonlinearity Short-Circuit Current Capacitive Load Drive NOISE Input Voltage Noise Density 10kHz, 100pF, 10kHz, 100pF, 2.2V Input Voltage Noise 0.1Hz 10Hz, 100pF, 0.1Hz 10Hz, 100pF, 2.2V Input Current Density SLEW RATE Slew Rate SETTLING TIME Settling Time FREQUENCY RESPONSE Frequency Response NOISE 1kHz, VOUT 4VPP 2.5VDC, 100pF 1kHz, VOUT 4VPP 2.5VDC, 100pF 1kHz, VOUT 4VPP 2.5VDC, 100pF 128, 1kHz, VOUT 4VPP 2.5VDC, 100pF 200, 1kHz, VOUT 4VPP 2.5VDC, 100pF 20kHz, VOUT 4VPP 2.5VDC, 100pF 20kHz, VOUT 4VPP 2.5VDC, 100pF 20kHz, VOUT 4VPP 2.5VDC, 100pF 128, 20kHz, VOUT 4VPP 2.5VDC, 100pF 200, 20kHz, VOUT 4VPP 2.5VDC, 100pF POWER SUPPLY Operating Voltage Range AVDD DVDD Quiescent Current Analog Over Temperature, -40°C +125°C Quiescent Current Digital
(10)
CONDITIONS
UNIT
0.05 0.25 0.0015 -30/+60
DVDD 0.05 DVDD 0.25
%FSR
VOUT 85mV DVDD 85mV CLOAD
Typical Characteristics
0.362 0.736
nV/Hz nV/Hz µVPP µVPP fA/Hz
10kHz, 100pF
Table
V/µs
Table
Table
0.003 0.005 0.03 0.08 0.02 0.01 0.03 0.08 0.11
VOUT VREF 0.33
0.45 0.45
VOUT VREF, SCLK 10MHz, Logic Logic VOUT VREF, SCLK 10MHz, Logic Logic
0.75
Over Temperature, -40°C +125°C (9)(10) Shutdown Current Analog Digital
ISDA ISDD
VOUT VREF, SCLK Idle VOUT SCLK 10MHz, Logic Logic
POWER-ON RESET (POR) Trip Voltage Digital interface disabled Command Register values DVDD Trip Voltage
(10)
When AVDD less than DVDD, output clamped AVDD 300mV. Measurement limited noise test equipment test time. Does include current into VREF pin. Internal always connected between VOUT VREF. Digital logic levels: logic 10µA internal pull-down current source. Includes current from output structure.
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ELECTRICAL CHARACTERISTICS: AVDD DVDD (continued)
Boldface limits apply over specified temperature range, -40°C +125°C. +25°C, 10k//CL 100pF connected DVDD/2, VREF GND, unless otherwise noted.
PGA112, PGA113, PGA116, PGA117 PARAMETER TEMPERATURE RANGE Specified Range Operating Range Thermal Resistance MSOP-10 DIGITAL INPUTS (SCLK, DIO, DIN) Logic Input Leakage Current (SCLK only) Weak Pull-Down Current (DIO, only) Logic High Hysteresis DIGITAL OUTPUT (DIO, DOUT) Logic High Logic CHANNEL GAIN TIMING Channel Select Time Gain Select Time SHUTDOWN MODE TIMING Enable Time Disable Time POWER-ON-RESET (POR) TIMING Power-Up Time Power-Down Time DVDD DVDD 1.5V VOUT goes high-impedance, remain connected between VOUT VREF -3mA (sourcing) +3mA (sinking) DVDD DVDD 0.7DVDD DVDD 0.3DVDD °C/W +125 +125 CONDITIONS UNIT
Table Frequency Response versus Gain 100pF, 10k)
TYPICAL -3dB BINARY FREQUENCY GAIN (V/V) (MHz) 0.35 SLEW RATEFALL (V/µs) 12.8 12.8 12.8 12.8 SLEW RATERISE (V/µs) 10.6 10.6 12.8 13.3 0.1% 0.01% SETTLING SETTLING TIME: TIME: 4VPP 4VPP (µs) (µs) 2.55 SCOPE GAIN (V/V) TYPICAL -3dB FREQUENCY (MHz) 0.38 0.23 SLEW RATEFALL (V/µs) 12.8 12.8 12.8 SLEW RATERISE (V/µs) 10.6 10.6 0.1% 0.01% SETTLING SETTLING TIME: TIME: 4VPP 4VPP (µs) (µs) 2.55
Switch (Input)
CAMP RAMP VREF VOUT
Break-Before-Make
Figure Equivalent Input Circuit
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TIMING: AVDD DVDD +2.2V
Boldface limits apply over specified temperature range, -40°C +125°C. +25°C, 10k//CL 100pF connected DVDD/2, VREF GND, unless otherwise noted.
PGA112, PGA113, PGA116, PGA117 PARAMETER Input Capacitance (SCLK, pins) Input Rise/Fall Time (CS, SCLK, pins) Output Rise/Fall Time (DIO pin) High Time pin)
TEST CONDITIONS
UNIT
tRFI tRFO tCSH tCSO tCSSC fSCLK tSCCS tCS1
CLOAD 60pF
SCLK Edge Fall Setup Time Fall First SCLK Edge Setup Time SCLK Frequency SCLK High Time SCLK Time SCLK Last Edge Rise Setup Time Rise SCLK Edge Setup Time Setup Time Hold Time SCLK DOUT Valid Propagation Delay Rise DOUT Forced Hi-Z
tSOZ
Ensured design; production tested. When using devices daisy-chain mode, maximum clock frequency SCLK limited SCLK rise/fall time, setup time, DOUT propagation delay. Figure Based this limitation, maximum SCLK frequency daisy-chain mode 9.09MHz. must less than 1/SCLK (max).
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TIMING DIAGRAMS
tCSH tCSSC SCLK 1/fSCLK tSCCS tCS1 tCS0
Hi-Z DOUT
tSOZ Hi-Z
Figure Mode
tCSH tCSSC SCLK 1/fSCLK tSCCS tCS1 tCS0
Hi-Z DOUT tSOZ Hi-Z
Figure Mode
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CONFIGURATIONS
MSOP-10 PACKAGE (TOP VIEW)
AVDD VCAL/CH0 VREF VOUT PGA112 PGA113 DVDD SCLK
PGA112, PGA113 TERMINAL FUNCTIONS
MSOP PACKAGE
NAME AVDD
DESCRIPTION Analog supply voltage (+2.2V +5.5V) Input channel Input channel VCAL input. system calibration purposes, connect this low-impedance external reference voltage internal calibration channels. four internal calibration channels connected GND, 0.9VCAL, 0.1VCAL, VREF, respectively. VCAL loaded with 100k (typical) when internal calibration channels CAL2 CAL3 selected. Otherwise, VCAL/CH0 appears high impedance. Reference input pin. Connect external reference VOUT offset shift midsupply midsupply referenced systems. VREF must connected low-impedance reference capable sourcing sinking least VREF must connected GND. Analog voltage output. When AVDD DVDD, VOUT clamped AVDD 300mV. Ground Clock input serial interface Data input/output serial interface. contains weak, 10µA internal pull-down current source. Chip select line serial interface Digital output stage supply voltage (+2.2V +5.5V). Useful multi-supply systems prevent overvoltage/lockup condition analog-to-digital (ADC) input (for example, microcontroller with running powered from +5V). Digital levels relative DVDD. DVDD should bypassed with 0.1µF ceramic capacitor, DVDD must supply current digital portion well load current output stage.
VCAL/CH0
VREF VOUT SCLK
DVDD
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TSSOP-20 PACKAGE (TOP VIEW)
AVDD VCAL/CH0 VREF VOUT
PGA116 PGA1
DVDD DOUT SCLK ENABLE
PGA116, PGA117 TERMINAL FUNCTIONS
TSSOP PACKAGE
NAME AVDD
DESCRIPTION Analog supply voltage (+2.2V +5.5V) Input channel Input channel Input channel Input channel Input channel Input channel VCAL input. system calibration purposes, connect this low-impedance external reference voltage internal calibration channels. four internal calibration channels connected GND, 0.9VCAL, 0.1VCAL, VREF, respectively. VCAL loaded with 100k (typical) when internal calibration channels CAL2 CAL3 selected. Otherwise, VCAL/CH0 appears high impedance. Reference input pin. Connect external reference VOUT offset shift midsupply midsupply referenced systems. VREF must connected low-impedance reference capable sourcing sinking least GND. Analog voltage output. When AVDD DVDD, VOUT clamped AVDD 300mV. Input channel Input channel Input channel Hardware enable pin. Logic puts part into Shutdown mode 1µA). Ground Clock input serial interface Data input serial interface. contains weak, 10µA internal pull-down current source allow ease daisy-chain configurations. Data output serial interface. DOUT goes high-Z state when goes high standard interface. Chip select line serial interface Digital output stage supply voltage (+2.2V +5.5V). Useful multi-supply systems prevent overvoltage/lockup condition input (for example, microcontroller with running powered from +5V). Digital levels relative DVDD. DVDD should bypassed with 0.1µF ceramic capacitor, DVDD must supply current digital portion well load current output stage. Input channel
VCAL/CH0
VREF VOUT ENABLE SCLK DOUT
DVDD
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TYPICAL APPLICATION CIRCUITS
CBYPASS 0.1mF AVDD PGA112 PGA113 VCAL/CH0 10kW 0.9VCAL 0.1VCAL 80kW CAL1 CAL2 CAL3 CAL4 VREF Interface SCLK Output Stage VOUT DVDD MSP430 Microcontroller CBYPASS 0.1mF CBYPASS 0.1mF
10kW
CAL2/3
VREF
Figure PGA112, PGA113 (MSOP-10)
CBYPASS 0.1mF AVDD VCAL/CH0 10kW 0.9VCAL 0.1VCAL 80kW CAL1 CAL2 CAL3 CAL4 VREF Interface 10kW CAL2/3 VREF ENABLE SCLK DOUT Output Stage VOUT MSP430 Microcontroller PGA116 PGA117 DVDD CBYPASS 0.1mF CBYPASS 0.1mF
Figure PGA116, PGA117 (TSSOP-20)
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TYPICAL CHARACTERISTICS
+25°C, AVDD DVDD connected DVDD/2, VREF GND, 100pF, unless otherwise noted.
OFFSET VOLTAGE
2.5V
OFFSET VOLTAGE
4.5V
Population
-100
Population
Offset Voltage (mV)
Figure OFFSET VOLTAGE DRIFT (-40°C +85°C)
2.5V 4.5V
Population
-0.90 -0.81 -0.72 -0.63 -0.54 -0.45 -0.36 -0.27 -0.18 -0.09 0.09 0.18 0.27 0.36 0.45 0.54 0.63 0.72 0.81 0.90
Population
Offset Voltage Drift (mV/°C)
Figure OFFSET VOLTAGE DRIFT (-40°C +125°C)
2.5V
4.5V
Population
-1.20 -1.08 -0.96 -0.84 -0.72 -0.60 -0.48 -0.36 -0.24 -0.12 0.12 0.24 0.36 0.48 0.60 0.72 0.84 0.96 1.08 1.20
Population
Offset Voltage Drift (mV/°C)
Figure
-1.80 -1.62 -1.44 -1.26 -1.08 -0.90 -0.72 -0.54 -0.36 -0.18 0.18 0.36 0.54 0.72 0.90 1.08 1.26 1.44 1.62 1.80
Offset Voltage Drift (mV/°C)
-1.30 -1.17 -1.04 -0.91 -0.78 -0.65 -0.52 -0.39 -0.26 -0.13 0.13 0.26 0.39 0.52 0.65 0.78 0.91 1.04 1.17 1.30
Offset Voltage Drift (mV/°C)
-325.0 -292.5 -260.0 -227.5 -195.0 -162.5 -130.0 -97.5 -65.0 -32.5 32.5 65.0 97.5 130.0 162.5 195.0 227.5 260.0 292.5 325.0
Offset Voltage (mV)
Figure OFFSET VOLTAGE DRIFT (-40°C +85°C)
Figure OFFSET VOLTAGE DRIFT (-40°C +125°C)
Figure
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TYPICAL CHARACTERISTICS (continued)
+25°C, AVDD DVDD connected DVDD/2, VREF GND, 100pF, unless otherwise noted.
INPUT OFFSET VOLTAGE INPUT VOLTAGE
Output Nonlinearity Error (%FSR)
PGA112/PGA116 NONLINEARITY
0.0010 0.0008 0.0006 0.0004 0.0002 -0.0002 -0.0004 -0.0006 -0.0008 -0.0010 AVDD DVDD
Input Offset Voltage (mV)
-100 Input Voltage
VOUT
Figure GAIN ERROR
Figure GAIN ERROR
Population
-0.10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
Population
Gain Error
Figure GAIN ERROR
Population
Population
-0.300 -0.270 -0.240 -0.210 -0.180 -0.150 -0.120 -0.090 -0.060 -0.030 0.030 0.060 0.090 0.120 0.150 0.180 0.210 0.240 0.270 0.300
Gain Error
Figure
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0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00
Gain Error Drift (ppm/°C)
-0.10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
Gain Error
Figure GAIN ERROR DRIFT (-40°C +125°C)
Figure
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TYPICAL CHARACTERISTICS (continued)
+25°C, AVDD DVDD connected DVDD/2, VREF GND, 100pF, unless otherwise noted.
GAIN ERROR DRIFT (-40°C +125°C)
GAIN ERROR DRIFT (-40°C +125°C)
Population
Population
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00
Gain Error Drift (ppm/°C)
Figure CAL2 GAIN ERROR
Population
Population
-0.10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
Gain Error
Figure CAL2 GAIN ERROR DRIFT (-40°C +125°C)
Population
-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2
Population
Gain Error Drift (ppm/°C)
Figure
-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2
Gain Error Drift (ppm/°C)
-0.10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
Gain Error
10.0
Gain Error Drift (ppm/°C)
Figure CAL3 GAIN ERROR
Figure CAL3 GAIN ERROR DRIFT (-40°C +125°C)
Figure
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TYPICAL CHARACTERISTICS (continued)
+25°C, AVDD DVDD connected DVDD/2, VREF GND, 100pF, unless otherwise noted.
0.1Hz 10Hz NOISE
2.2V
0.1Hz 10Hz NOISE
250nV/div
2.5s/div
100nV/div
2.5s/div
Figure SPECTRAL NOISE DENSITY
Figure PGA112, PGA116 NOISE FREQUENCY (VOUT 2VPP)
Current Noise
Voltage Noise
THD+N
Current Noise,
0.01
Voltage Noise, 2.2V Voltage Noise,
0.001 Frequency (Hz)
Frequency (Hz)
100k
0.0001 100k
Figure PGA112, PGA116 NOISE FREQUENCY (VOUT 4VPP)
THD+N THD+N
Figure PGA113, PGA117 NOISE FREQUENCY (VOUT 2VPP)
0.01
0.01
0.001 0.0001 Frequency (Hz) 100k 0.0001 Frequency (Hz) 100k 0.001
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
+25°C, AVDD DVDD connected DVDD/2, VREF GND, 100pF, unless otherwise noted.
PGA113, PGA117 NOISE FREQUENCY (VOUT 4VPP)
THD+N
QUIESCENT CURRENT TEMPERATURE
Digital
0.01 0.001 0.0001 Frequency (Hz) 100k
(mA)
Analog Temperature (°C) 5.5V 2.2V fSCLK 10MHz
Figure TOTAL QUIESCENT CURRENT SUPPLY VOLTAGE
SCLK 5MHz SCLK 10MHz
Figure SHUTDOWN QUIESCENT CURRENT TEMPERATURE
Digital
(mA)
SCLK 500kHz Supply Voltage SCLK 2MHz
Shutdown (mA)
Analog
Temperature (°C)
Figure OUTPUT VOLTAGE OUTPUT CURRENT
Output Current (mA) +125°C +25°C -40°C
Figure OUTPUT VOLTAGE OUTPUT CURRENT
2.2V
+125°C +25°C -40°C
5.5V
Output Voltage
Output Voltage
Output Current (mA)
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
+25°C, AVDD DVDD connected DVDD/2, VREF GND, 100pF, unless otherwise noted.
PGA112, PGA116 OUTPUT VOLTAGE SWING FREQUENCY
AVDD DVDD 2.2V AVDD DVDD 2.2V
PGA112, PGA116 OUTPUT VOLTAGE SWING FREQUENCY
Output Voltage
Output Voltage
100k Frequency (Hz) 100k Frequency (Hz)
Figure PGA112, PGA116 OUTPUT VOLTAGE SWING FREQUENCY
AVDD DVDD 5.5V 100k
Figure PGA112, PGA116 OUTPUT VOLTAGE SWING FREQUENCY
Output Voltage
Output Voltage
AVDD DVDD 5.5V 100k
Frequency (Hz)
Frequency (Hz)
Figure PGA113, PGA117 OUTPUT VOLTAGE SWING FREQUENCY
Figure PGA113, PGA117 OUTPUT VOLTAGE SWING FREQUENCY
Output Voltage
AVDD DVDD 2.2V 100k Frequency (Hz)
Output Voltage
AVDD DVDD 2.2V 100k Frequency (Hz)
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
+25°C, AVDD DVDD connected DVDD/2, VREF GND, 100pF, unless otherwise noted.
PGA113, PGA117 OUTPUT VOLTAGE SWING FREQUENCY
PGA113, PGA117 OUTPUT VOLTAGE SWING FREQUENCY
Output Voltage
AVDD DVDD 5.5V 100k Frequency (Hz)
Output Voltage
AVDD DVDD 5.5V 100k Frequency (Hz)
Figure SMALL-SIGNAL OVERSHOOT LOAD CAPACITANCE
Figure GAIN SETTLING TIME
100pF//RL 10kW VOUT 4VPP 0.01% 0.1%
Load Capacitance (pF)
Settling Time (ms)
Overshoot
Gain
Figure INPUT ON-CHANNEL CURRENT TEMPERATURE
Channel Input Off-Channel Current (nA)
Figure INPUT OFF-CHANNEL LEAKAGE CURRENT TEMPERATURE
-0.01 -0.15 Temperature (°C) Measurement made with channel connected midsupply 0.15 Channel Channel Input Off-Channel Current (nA) 0.10 0.05 -0.05
Input On-Channel Current (nA)
Measurement made with channel connected midsupply
Temperature (°C)
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
+25°C, AVDD DVDD connected DVDD/2, VREF GND, 100pF, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO FREQUENCY
CROSSTALK FREQUENCY
PSRR (dB)
Crosstalk (dB)
100k
100k Frequency (Hz)
Frequency (Hz)
Figure SMALL-SIGNAL PULSE RESPONSE
Figure SMALL-SIGNAL PULSE RESPONSE
100mV
100mV Output VIN/G
VIN/G
Output
100,
Input
Input
2.5ms/div
2.5ms/div
Figure LARGE-SIGNAL PULSE RESPONSE
Figure LARGE-SIGNAL PULSE RESPONSE
2V/div
Input
2V/div
Output
Output
100,
Input
2.5ms/div
2.5ms/div
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
+25°C, AVDD DVDD connected DVDD/2, VREF GND, 100pF, unless otherwise noted.
POWER-UP/POWER-DOWN TIMING OUTPUT OVERDRIVE PERFORMANCE
Output (1V/div) Supply (5V/div) 10kW 100pF 1ms/div
25ms/div
Figure OUTPUT VOLTAGE SHUTDOWN MODE
Active Shutdown Output Shutdown Active
Output
1V/div
VOUT
Figure PGA116, PGA117 HARDWARE SHUTDOWN MODE
2V/div
2V/div
Output
Enable
10ms/div
10ms/div
Figure
Figure
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SERIAL INTERFACE INFORMATION
Mode (CPOL CPHA
SCLK DOUT
Mode (CPOL CPHA
SCLK DOUT
Figure Mode Mode Table Mode Setting Description
MODE CPOL CPHA CPOL DESCRIPTION Clock idles Clock idles high CPHA DESCRIPTION Data read rising edge clock. Data change falling edge clock. Data read rising edge clock. Data change falling edge clock.
CPHA means sample first clock edge (rising falling) after valid CPHA means sample second clock edge (rising falling) after valid
SERIAL DIGITAL INTERFACE: MODES
uses standard serial peripheral interface (SPI). Both Mode Mode supported, shown Figure described Table there even-numbered increments clocks (that forth) between going (falling edge) going high (rising edge), device takes action. This condition provides reliable serial communication. Furthermore, this condition also provides quickly reset interface known starting condition data synchronization. Transmitted data latched internally rising edge PGA116/PGA117, DIN, SCLK Schmitt-triggered CMOS logic inputs. weak internal pull-down support daisy-chain communications PGA116/PGA117. DOUT CMOS logic output. When high, state DOUT high-impedance. When low, DOUT driven illustrated Figure
DOUT
10mA PGA116 PGA1
Figure Digital Structure-PGA116/PGA1
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PGA112/PGA113, there digital output digital input gates both internally connected pin. input-only gate DOUT digital output that give 3-state output. weak 10µA pull-down current source prevent from floating systems with high-impedance DOUT line. When high, state internal DOUT gate high-impedance. When low, state depends previous valid communication; either becomes output clock data remains input receive data. This structure shown Figure
used (see Table ensure that data written read proper sequence. There special daisy-chain command OPeration) which, when presented desired device daisy-chain, causes changes that respective device. Detailed timing diagrams daisy-chain operation shown Figure through Figure
SCLK DOUT
PGA116/PGA1CS SCLK DIN1
PGA116/PGA1CS SCLK DIN2
MSP430
DOUT1
DOUT2
DOUT
Figure Daisy-Chain Read/Write Configuration PGA112/PGA113 used last device daisy-chain shown Figure write-only communication acceptable, because PGA112/PGA113 have separate DOUT connect back microcontroller order read back data this configuration.
SCLK DOUT
10mA PGA112 PGA113
Figure Digital Structure-PGA112/PGA113
PGA116/PGA1CS SCLK DIN1
PGA112/PGA113
SCLK
MSP430
DOUT1
SERIAL DIGITAL INTERFACE: DAISY-CHAIN COMMUNICATIONS
reduce number port pins used microcontroller, PGA116/PGA117 support daisy-chain communications with full read/write capability. two-device daisy-chain configuration shown Figure although number devices daisy-chained. daisy-chain communication uses common SCLK line devices daisy chain, rather than each device requiring separate line. daisy-chain mode communication routes data serially through each device chain using respective DOUT pins shown. Special commands
Figure Daisy-Chain Write-Only Configuration
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maximum SCLK frequency that used daisy-chain operation directly related SCLK rise/fall times, setup time, DOUT propagation delay. number more devices have same limitations because timing considerations between adjacent devices that limit clock speed. Figure analyzes maximum SCLK frequency daisy-chain mode based circuit Figure clock rise fall time 10ns assumed allow extra capacitance that could occur result multiple devices daisy-chain.
SCLK
tRFI 10ns
tRFI 10ns
25ns
DOUT1
10ns
DIN2
tMIN 55ns SCLKMAX 9.09MHz
tMIN 55ns
Figure Daisy-Chain Maximum SCLK Frequency
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Write, Mode
SERIAL INTERFACE
SCLK
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Hi-Z
DOUT
Write, Mode
SCLK
Hi-Z
DOUT
Read, Mode
SCLK
Hi-Z
DOUT
Hi-Z
Read, Mode
Figure Serial Interface Timing Diagrams
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SCLK
DOUT
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Hi-Z
PGA112, PGA113 PGA116, PGA1
MSP430
DOUT1 DOUT2 SCLK DIN1 SCLK DIN2 SCLK DOUT
PGA112, PGA113 PGA116, PGA1
PGA116/PGA117 PGA116/PGA117
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Daisy-Chain Write, Mode
Command DOUT Hi-Z Pulled Weak Pull-Down Command Command
SCLK
DOUT DIN1
DOUT1 DIN2
Daisy-Chain Write, Mode
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Figure Daisy-Chain Write Timing Diagrams
Product Folder Link(s): PGA112 PGA113 PGA116 PGA12 Command DOUT Hi-Z Pulled Weak Pull-Down Command Command
SCLK
DOUT DIN1
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DOUT1 DIN2
MSP430
DOUT1 DOUT2 SCLK DIN1 SCLK DIN2
SCLK DOUT
PGA116/PGA117 PGA116/PGA117
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Daisy-Chain Read, Mode
Command DOUT Hi-Z Pulled Weak Pull-Down Command Command
Data Byte Data Byte Data Byte Hi-Z
SCLK
DOUT DIN1
DOUT1 DIN2
Figure Daisy-Chain Read Timing Diagram (Mode 0,0)
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SCLK
DOUT1 DIN2
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DOUT2
PGA112, PGA113 PGA116, PGA1
MSP430
DOUT1 DOUT2 SCLK DIN1 SCLK DIN2 SCLK DOUT
PGA112, PGA113 PGA116, PGA1
PGA116/PGA117 PGA116/PGA117
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Daisy-Chain Read, Mode
Command DOUT Hi-Z Pulled Weak Pull-Down Command Command
Data Byte Data Byte Data Byte Hi-Z
SCLK
DOUT DIN1
DOUT1 DIN2
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Figure Daisy-Chain Read Timing Diagram (Mode 1,1)
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SCLK
DOUT1 DIN2
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DOUT2
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COMMANDS
Table Commands (PGA112/PGA113)
THREE-WIRE COMMAND READ WRITE WRITE SDN_DIS WRITE SDN_EN WRITE
Shutdown mode. Enter Shutdown mode issuing SDN_EN command. Shutdown mode cleared (returned last valid write configuration) SDN_DIS command valid Write command. (Power-on-Reset) value internal Gain/Channel Select Register this value sets Gain Channel VCAL/CH0.
Table Daisy-Chain Commands
DAISY-CHAIN COMMAND SDN_DIS SDN_EN READ WRITE
Shutdown Mode. Shutdown Mode entered SDN_EN command. Shutdown Mode cleared (returned last valid write configuration) SDN_DIS command valid Write command. (Power-on-Reset) value internal Gain/Channel Register this value sets Gain VCAL/CH0 selected.
Table Gain Selection Bits (PGA112/PGA113)
BINARY GAIN SCOPE GAIN
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Table Channel Selection Bits
PGA112, PGA113 VCAL/CH0 Factory Reserved CAL1 CAL2 CAL3 CAL4
PGA116, PGA117 VCAL/CH0 Factory Reserved CAL1 CAL2 CAL3 CAL4
channel used. CAL1: connects GND. CAL2: connects 0.9VCAL. CAL3: connects 0.1VCAL. CAL4: connects VREF.
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APPLICATION INFORMATION FUNCTIONAL DESCRIPTION
PGA112/PGA113 PGA116/PGA117 single-ended input, single-supply, programmable gain amplifiers (PGAs) with input multiplexer. Multiplexer channel selection gain selection done through standard interface. PGA112/PGA113 have two-channel input PGA116/PGA117 have 10-channel input MUX. PGA112 PGA116 provide binary gain selections 128) PGA113 PGA117 provide scope gain selections 100, 200). models split-supply architecture with analog supply, AVDD, digital supply, DVDD. This split-supply architecture allows ease interface analog-to-digital converters (ADCs) microcontrollers mixed-supply voltage systems, such where analog supply digital supply +3V. Four internal calibration channels provided system-level calibration. channels tied GND, 0.9VCAL, 0.1VCAL, VREF, respectively. VCAL, external voltage connected VCAL/CH0, acts system calibration reference. VCAL system reference, then gain offset calibration easily accomplished through using only input. calibration used, then VCAL/CH0 used standard input. four versions provide VREF that tied ground ease scaling, midsupply single-supply systems where midsupply used virtual ground. PGA112/PGA113 offer software-controlled shutdown feature standby power. PGA116/PGA117 offer both hardwareand software-controlled shutdown standby power. PGA112/PGA113 have three-wire digital interface; PGA116/PGA117 have four-wire digital interface. PGA116/117 also have daisy-chain capability. PMOS transistors. result this transition appears small input offset voltage transition that reflected output selected gain. This transition either increasing decreasing, differs from part part described Figure Figure These figures illustrate possible differences input offset voltage between different devices when used with AVDD +5V. Because exact transition region varies from device device, Electrical Characteristics table specifies input offset voltage above below this input transition region.
AVDD Reference Current
VIN+
VIN-
Figure Rail-to-Rail Input Stage
Input Offset Voltage (mV)
AVDD Input Voltage
AMP: INPUT STAGE
rail-to-rail input output (RRIO) single-supply amp. input topology uses separate input stages parallel achieve rail-to-rail input. Figure shows, there PMOS transistor each input operation down ground; there also NMOS transistor each input parallel operation positive supply rail. When common-mode input voltage (that single-ended input, because this configured internally noninverting gain) crosses level that typically about 1.5V below positive supply, there transition between NMOS
Figure versus Input Voltage-Case
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Input Offset Voltage (mV)
AVDD
VIN0
PGA112 PGA113 VOUT
Input Voltage
VIN1
VREF
VS/2
Figure PGA112/PGA113 Configuration Positive Negative Excursions Around Midsupply Virtual Ground
VOUT0 VIN0 AVDD/2
Figure versus Input Voltage-Case
When: Then: VOUT0 VIN0
AMP: GENERAL GAIN EQUATIONS
Figure shows basic configuration using gain block. VOUT/VIN selected noninverting gain, depending model selected, either binary scope gains.
VOUT1 (VIN1 AVDD/2) AVDD/2 VOUT1 VIN1 AVDD/2, where: -AVDD/2 VIN1 +AVDD/2
VREF VOUT
Where: (binary gains) 100, (scope gains) Table details internal typical values internal feedback resistor (RF) internal input resistor (RI) both binary scope gains. Table Typical versus Gain
Figure Used Gain Block
VOUT
Binary Gain (V/V)
3.25k 9.75k 22.75k 48.75k 100.75k 204.75k 412.75k
3.25k 3.25k 3.25k 3.25k 3.25k 3.25k 3.25k 3.25k
Scope Gain (V/V)
3.25k 29.25k 61.75k 159.25k 321.75k 646.75k
3.25k 3.25k 3.25k 3.25k 3.25k 3.25k 3.25k 3.25k
Where: (binary gains) 100, (scope gains) Figure shows configuration gain equations VREF AVDD/2. VOUT0 VOUT when selected VOUT1 VOUT when selected. Notice VREF effect because internal feedback resistor, shorted out. This configuration allows positive negative voltage excursions around midsupply virtual ground.
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AMP: FREQUENCY RESPONSE VERSUS GAIN
Table documents small-signal bandwidth slew rate change correspond changes gain. Full power bandwidth (that highest frequency that sine wave pass through given gain) related slew rate Equation (V/ms) 10-6) Where: Slew rate V/µs Frequency Output peak voltage volts Example: then 10.6V/µs (slew rate rise minimum slew rate). system, choose 0.1V VOUT 4.9V VOUTPP 4.8V VOUTP 2.4V. (V/µs) 10-6). 10.6 (2.4) 10-6) 702.9kHz This example shows that configuration produce 4.8VPP sine wave with frequency 702.9kHz. This computation only shows theoretical upper limit frequency this example, does indicate distortion sine wave. acceptable distortion depends specific application. general guideline, maintain three times calculated slew rate minimize distortion sine wave. this example, application should only 4.8VPP, frequency range 234kHz 351kHz, depending upon acceptable distortion. given gain slew rate requirement, check adequate small-signal bandwidth (typical -3dB frequency) order assure that frequency signal passed without attenuation.
ANALOG
analog input provides input channels PGA112/PGA113 input channels PGA116/PGA117. switches designed break-before-make thereby eliminate concerns about shorting input signal sources together. Four internal channels included analog ease system calibration. These channels allow gain offset errors calibrated out. This calibration does remove offset gain errors gains greater than most systems should significant increase accuracy. addition, these channels used read minimum maximum possible voltages from PGA. With these minimum maximum levels known, system architecture designed indicate out-of-range condition measured analog input signals these levels ever measured. channels, VCAL/CH0 must permanently connected system reference. There typical 100k load from VCAL/CH0 ground. Table illustrates channels with VREF ground. Table describes channels with VREF AVDD/2. VREF must connected source that low-impedance both order maintain gain nonlinearity accuracy. Worst-case current demand VREF occurs when because there 3.25k resistor between VOUT VREF. system with AVDD/2 2.5V, VREF buffer must source sink 2.5V/3.25k 0.7mA minimum VOUT that swing from ground +5V.
Table Frequency Response versus Gain 100pF, 10k)
TYPICAL -3dB BINARY FREQUENCY GAIN (V/V) (MHz) 0.35 SLEW RATEFALL (V/µs) 12.8 12.8 12.8 12.8 SLEW RATERISE (V/µs) 10.6 10.6 12.8 13.3 0.1% 0.01% SETTLING SETTLING TIME: TIME: 4VPP 4VPP (µs) (µs) 2.55 SCOPE GAIN (V/V) TYPICAL -3dB FREQUENCY (MHz) 0.38 0.23 SLEW RATEFALL (V/µs) 12.8 12.8 12.8 SLEW RATERISE (V/µs) 10.6 10.6 0.1% 0.01% SETTLING SETTLING TIME: TIME: 4VPP 4VPP (µs) (µs) 2.55
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CBYPASS 0.1mF AVDD PGA112 PGA113 VCAL/CH0 10kW 0.9VCAL 0.1VCAL 80kW CAL1 CAL2 CAL3 CAL4 VREF Interface SCLK MSP430 Microcontroller Output Stage VOUT DVDD REF3225 2.5V CBYPASS 0.1mF CBYPASS 0.1mF
10kW
CAL2/3
VREF
Figure Using Channels with VREF Ground Table Using Channels with VREF (AVDD DVDD 2.5V, VREF GND)
FUNCTION Minimum Signal SELECT CAL1 GAIN SELECT INPUT (+In) (VOUT) 50mV DESCRIPTION Minimum signal level that MUX, amp, read. VOUT limited negative saturation. system full-scale gain calibration ADC. Maximum signal level that MUX, amp, read. VOUT limited positive saturation. System limited input 2.5V (ADC 2.5V). system offset calibration ADC. Minimum signal level that MUX, amp, read. VOUT limited negative saturation.
Gain Calibration
CAL2
(VCAL/CH0)
2.25V
2.25V
Maximum Signal
CAL2
(VCAL/CH0)
2.25V
2.95V
Offset Calibration
CAL3
(VCAL/CH0) VREF
0.25V
0.25V
Minimum Signal
CAL4
50mV
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CBYPASS 0.1mF CBYPASS 0.1mF CBYPASS 0.1mF
AVDD
DVDD
PGA112 PGA113 VCAL/CH0 10kW 0.9VCAL 0.1VCAL 80kW CAL1 CAL2 CAL3 CAL4 VREF Interface SCLK Output Stage VOUT
MSP430 Microcontroller
10kW
CAL2/3
10kW 2.7nF 100kW 100kW CBYPASS 0.1mF (1.5V) OPA364
VREF
0.1mF
0.1mF
Figure Using Channels with VREF AVDD/2 Table Using Channels with VREF AVDD/2 (AVDD DVDD VREF 1.5V)
FUNCTION Minimum Signal Gain Calibration Maximum Signal Offset Calibration VREF Check SELECT CAL1 CAL2 CAL2 CAL3 CAL4 GAIN SELECT INPUT (VCAL/CH0) (VCAL/CH0) (VCAL/CH0) VREF (+In) 2.7V 2.25V 0.3V 1.5V (VOUT) 50mV 2.7V 2.95V 0.3V 1.5V DESCRIPTION Minimum signal level that MUX, amp, read. VOUT limited negative saturation. system full-scale gain calibration ADC. Maximum signal level that MUX, amp, read. VOUT limited positive saturation. system offset calibration ADC. Midsupply voltage used VREF.
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SYSTEM CALIBRATION USING
Analog-to-digital converters (ADCs) contain major errors that easily removed calibration system level. These errors gain error offset error, shown Figure Figure shows typical transfer function 12-bit ADC. analog input x-axis with range from (VREF_ADC 1LSB), where VREF_ADC reference voltage. y-axis hexadecimal equivalent digital codes that result from conversions. dotted line represents ideal transfer function with 0000h representing analog input 0FFFh representing analog input (VREF_ADC 1LSB). solid blue line illustrates offset error. Although solid blue line includes both offset error gain error, analog input offset error voltage, VZ_ACTUAL, measured. dashed black line represents transfer function with gain error. dashed black line equivalent solid blue line without offset error, measured computed using VZ_ACTUAL VZ_IDEAL. difference between dashed black line dotted line gain error. Gain offset error computed taking zero input full-scale input readings. Using these error calculations, compute calibrated reading remove gain offset error.
VFS_ACTUAL
practice, zero input (0V) full-scale input (VREF_ADC 1LSB) ADCs cannot always measured because internal offset error gain error. However, measurements made very close full-scale input zero input, both zero full-scale calibrated very accurately with assumption linearity from calibration points desired points ideal transfer function. zero calibration, choose 10%VREF_ADC; this value should above internal offset error sufficiently noise floor range ADC. gain calibration, choose 90%VREF_ADC; this value should less than internal gain error sufficiently below tolerance VREF. These points summarized this way: zero calibration: cannot read ideal zero because offset error Must enough above ground above noise floor offset error Therefore, choose 10%VREF_ADC zero calibration gain calibration: cannot read ideal full-scale because gain error Must enough below full-scale below VREF tolerance gain error Therefore, choose 90%VREF_ADC gain calibration
0FFFh
Gain Error VFS_IDEAL Transfer Function with Offset Error Gain Error Transfer Function with Gain Error Only
Digital Output
VZ_ACTUAL
0000h Offset Error VZ_IDEAL Analog Input VREF_ADC 1LSB
Figure Offset Gain Error
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12-bit example Figure illustrates technique calibrating using 10%VREF_ADC 90%VREF_ADC reading where VREF_ADC reference voltage. Note that 10%VREF reading also contains gain error because calibration point. First, 90%VREF 10%VREF points compute measured gain error. measured gain error then used remove gain error from 10%VREF reading, giving measured 10%VREF number. measured 10%VREF number used compute measured offset error.
VREF Offset Error +4LSB Gain Error +6LSB
VREF90 0.9(VREF_ADC) VREF10 0.1(VREF_ADC)
VMEAS90 ADCMEASUREMENT VREF90 VMEAS10 ADCMEASUREMENT VREF10
0FFFh (4.99878V) (4.5114751443V)
Compute measured gain. slope curve connecting measured 10%VREF measured 90%VREF point computed compared slope between ideal 10%VREF ideal 90%VREF. This result measured gain. VMEAS90 VMEAS10 GMEAS VREF90 VREF10 Compute measured offset. measured offset computed taking difference between measured 10%VREF (ideal 10%VREF) (measured gain). OMEAS VMEAS10 (VREF10 GMEAS) Compute calibrated readings. VAD_MEAS ADCMEASUREMENT
VADC_CAL VAD_MEAS OMEAS GMEAS
(12)
(10)
Digital Output (VAD_MEAS)
Transfer Function with Offset Error Gain Error
(11)
(0.5056191443V)
0000h (0V) 0.5V (0.1 VREF_ADC) 4.5V (0.9 VREF_ADC) 4.99878V (VREF_ADC 1LSB)
Figure 12-Bit Example Calibration Gain Offset Error gain error offset error readings calibrated using 10%VREF_ADC 90%VREF_ADC calibration points. Because calibration ratiometric VREF_ADC, exact value VREF_ADC does need known application. Follow these steps compute calibrated reading: Take reading VREF VREF. readings 10%VREF 90%VREF taken.
reading therefore calibrated removing gain error offset error. measured offset subtracted from reading then divided measured gain give corrected reading. this calibration performed timed basis, relative specific application, gain offset error over temperature also removed from reading calibration. example; given: 12-Bit Gain Error +6LSB Offset Error +4LSB Reference (VREF_ADC) Temperature +25°C Table shows resulting system accuracy.
Table Bits System Accuracy 0.5LSB)
10%VREF_ADC 90%VREF_ADC ACCURACY WITHOUT CALIBRATION 8.80 Bits 7.77 Bits ACCURACY WITH PGA112 CALIBRATION 12.80 Bits 11.06 Bits
Difference maximum input offset voltage 10%VREF_ADC 90%VREF_ADC reason different accuracies.
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APPLICATIONS: GENERAL-PURPOSE INPUT SCALING
Figure example application that demonstrates flexibility general-purpose input scaling. VIN0 ±100mV input that ac-coupled into CH0. PGA112/PGA113 powered from supply voltage, configured with VREF connected VS/2 (+2.5V). VCH0 ±100mV input, level-shifted centered VS/2 (+2.5V). gain applied CH0, because PGA113 configuration, output voltage VOUT centered VS/2 (+2.5V). through resistive divider scalar network, read This setting provides bipolar single-ended input scaling.
VIN0 +100mV -100mV VIN0 200mVPP VCH0 +2.6V +2.5V +2.4V
Table summarizes scaling resistor values different voltages. VREF_ADC reference voltage used connected PGA112/PGA113 output. assumed input range VREF_ADC. Bipolar Input Single-Supply Scaling section gives algorithm compute resistor values references listed Table general guideline, should chosen such that input on-channel current multiplied less than equal input offset voltage. This value ensures that scaling network contributes more error than input offset voltage. Individual applications require other design trade-offs.
PGA112 PGA113
(+5V) AVDD DVDD
VOUT0 +4.5V +2.5V +0.5V VOUT VOUT1
VREF
VREF_ADC VS/2 (+2.5V)
+4.9625V +37.5mV
VIN1
Figure General-Purpose Input Scaling
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Table Bipolar Single-Ended Input Scaling
VREF_ADC VIN1 4.096 4.096 INPUT 0.047613 1.247613 2.447613 0.050317 1.250317 2.450317 0.058003 1.498003 2.938003 0.059303 1.499303 2.939303 0.082224 2.048304 4.014384 0.086018 2.052098 4.018178 0.093506 2.493506 4.893506 0.095227 2.495227 4.895227 4.81k 6.49 3.92k 7.87k 4.02 2.87k 13.5 5.76k 3.16 2.4k 4.81k
Scaling based 0.02(VREF_ADC) 0.98(VREF_ADC), using standard 0.1% resistor values. Assumes symmetrical symmetrical scaling input minimum maximum.
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Bipolar Input Single-Supply Scaling Note that this process assumes symmetrical VIN1 that symmetrical scaling used input minimum maximum values. following steps give algorithm compute resistor values references listed Table Step Choose following: VREF_ADC 2.5V (ADC reference voltage) VIN1 (magnitude VIN, assuming scaling ±VIN1) Choose standard resistor value. input on-channel current multiplied should less than input offset voltage, such that major source inaccuracy. (select starting value resistors) most negative VIN1, choose percentage decimal format) VREF_ADC desired input. kVO- 0.02 (CH1 input kVO- VREF_ADC when VIN1 -VIN1) most positive VIN1, choose percentage decimal format) VREF_ADC desired input. Since this scaling based symmetry, kVO+ must same percentage away from VREF_ADC upper limit lower limit where kVO- computed. kVO+ kVO- kVO+ 0.02 0.98 (CH1 input kVO+ VREF_ADC when VIN1 +VIN1) Step Compute following: simplify analysis, create constant called kVO. kVO+ kVO0.96 0.98 0.02 constant, created simplify resistor value computations. VREF_ADC |VIN1| VREF_ADC
0.315789474 0.96 0.96 selected from starting value constant.
9.23077kW
10kW 0.315789474 0.315789474 computed from starting value computed value
4.81kW
10kW 9.23077kW 10kW 9.23077kW
4.81kW
Input (2.447817V, 0.0474093V)
VREF_ADC (2.5V)
10kW
VIN1 (+5V, -5V)
9.2kW
Figure Bipolar Single-Ended Input Algorithm
APPLICATIONS: HIGH GAIN/WIDE BANDWIDTH CONSIDERATIONS
result combination wide bandwidth high gain capability PGA112/PGA113 PGA116/PGA117, there several printed circuit board (PCB) design system recommendations consider optimum application performance. Power-supply bypass. Bypass each power-supply separately. ceramic capacitor connected directly from power-supply ground same plane. Vias then used connect ground voltage planes. This configuration keeps parasitic inductive paths local bypass PGA. Good analog design practice dictates large value tantalum bypass capacitor each respective voltage.
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Signal trace routing. Keep VOUT other impedance traces away from channel inputs that high impedance. Poor signal routing cause positive feedback, unwanted oscillations, excessive overshoot ringing step-changing signals. input signals particularly noisy, separate input channels with guard traces either side signal traces. Connect guard traces ground near signal entry point into PCB. multilayer PCBs, ensure that there parallel traces near input traces adjacent layers; capacitive coupling from other layers problem. ground planes isolate input signal traces from signal traces other layers. Additionally, group route digital signals into away possible from analog input signals. Most digital signals fast rise/fall time signals with low-impedance drive capability that easily couple into high-impedance inputs input channels. This coupling create unwanted noise that gains VOUT. Input channels source impedance. Input channels high-impedance; when combined with high gain, channels pick unwanted noise. Keep input signal sources low-impedance 10k). Also, consider bypassing input channels with ceramic bypass capacitor directly input pin.
CBYPASS 0.1mF AVDD 10kW 0.9VCAL 0.1VCAL 80kW CAL1 CAL2 CAL3 CAL4 VREF Interface PGA112 PGA113 (MSOP-10) Output Stage DVDD
Bypass capacitors greater than 100pF recommended. Lower impedances bypass capacitor placed directly input channels keep crosstalk between channels minimum result parasitic capacitive coupling from adjacent traces pin-to-pin capacitance.
APPLICATIONS: DRIVING/INTERFACING ADCS
CDAC ADCs contain input sampling capacitor, CSH, sample input signal during sample period shown Figure After sample period, removed from input signal. Subsequent comparisons charge stored performed during conversion process. achieve optimal stability, input signal settling, demands charge from input signal conditioning circuitry, most applications optimized resistor (RFILT) capacitor (CFILT) filter placed between output input. PGA112/PGA113, PGA116/PGA117, setting CFILT RFILT yields optimum system performance sampling converters operating speeds 500kHz, depending upon application settling time accuracy requirements.
CBYPASS 0.1mF
CBYPASS 0.1mF
VCAL/CH0
VOUT
RFILT 100W CFILT (1nF) 40pF CDAC
SCLK
10kW
CAL2/3
VREF
12-Bit Settling 500kHz 16-Bit Settling 300kHz
Figure Driving/Interfacing ADCs
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POWER SUPPLIES
Figure shows typical mixed-supply voltage system where analog supply, AVDD, digital supply voltage, DVDD, +3V. analog output stage interface digital circuitry both powered from DVDD. When considering power required DVDD, Electrical Characteristics table load current anticipated VOUT; this load current must provided DVDD. This split-supply architecture ensures compatible logic levels with microcontroller. also ensures that output cannot input onboard into overvoltage condition; this condition could cause device latch-up system lock-up, require power-supply sequencing. Each supply should individually bypassed with 0.1µF ceramic capacitor directly device ground. there only power supply system, AVDD DVDD both connected same supply; however, recommended individual bypass capacitors directly each respective supply single point ground. VOUT diode-clamped AVDD shown Figure 80); therefore, DVDD less than equal AVDD 0.3V. DVDD AVDD must within operating voltage range +2.2V +5.5V.
initial power-on, state Channel active. CAUTION: most applications, AVDD DVDD prevent VOUT from driving current into AVDD raising voltage level AVDD.
SHUTDOWN POWER-ON-RESET (POR)
PGA112/PGA113 have software shutdown mode, PGA116/PGA117 offer both hardware software shutdown mode. When shut down, goes into low-power standby mode. Electrical Characteristics table details current draw shutdown mode with without interface being clocked. shutdown mode, remain connected between VOUT VREF. When DVDD less than 1.6V, digital interface disabled channel gain selections held respective states Gain Channel VCAL/CH0. When DVDD above 1.8V, digital interface enabled gain channel states remain unchanged until valid communication received.
AVDD PGA112 PGA113 (MSOP-10) Output Stage CAL1 0.9VCAL 0.1VCAL 80kW CAL2 CAL3 CAL4 VREF Interface SCLK VOUT DVDD MSP430 Microcontroller
VCAL/CH0
10kW
10kW
CAL2/3
VREF
Figure Split Power-Supply Architecture: AVDD DVDD
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Nov-2008
PACKAGING INFORMATION
Orderable Device PGA112AIDGSR PGA112AIDGSRG4 PGA112AIDGST PGA112AIDGSTG4 PGA113AIDGSR PGA113AIDGSRG4 PGA113AIDGST PGA113AIDGSTG4 PGA116AIPW PGA116AIPWG4 PGA116AIPWR PGA116AIPWRG4 PGA117AIPW PGA117AIPWG4 PGA117AIPWR PGA117AIPWRG4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type MSOP MSOP MSOP MSOP MSOP MSOP MSOP MSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
Package Drawing
Pins Package Plan 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
Addendum-Page
PACKAGE OPTION ADDENDUM
www.ti.com
13-Nov-2008
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jan-2009
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing MSOP MSOP MSOP MSOP TSSOP TSSOP
Reel Reel Diameter Width (mm) (mm) 330.0 180.0 330.0 180.0 330.0 330.0 12.4 12.4 12.4 12.4 16.4 16.4
(mm)
(mm)
(mm)
(mm)
Pin1 (mm) Quadrant 12.0 12.0 12.0 12.0 16.0 16.0
PGA112AIDGSR PGA112AIDGST PGA113AIDGSR PGA113AIDGST PGA116AIPWR PGA117AIPWR
2500 2500 2000 2000
6.95 6.95
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jan-2009
*All dimensions nominal
Device PGA112AIDGSR PGA112AIDGST PGA113AIDGSR PGA113AIDGST PGA116AIPWR PGA117AIPWR
Package Type MSOP MSOP MSOP MSOP TSSOP TSSOP
Package Drawing
Pins
2500 2500 2000 2000
Length (mm) 370.0 195.0 370.0 195.0 346.0 346.0
Width (mm) 355.0 200.0 355.0 200.0 346.0 346.0
Height (mm) 55.0 45.0 55.0 45.0 33.0 33.0
Pack Materials-Page
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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DALLAS, TEXAS 75265
IMPORTANT NOTICE
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