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SLAS551 JULY 2007 16-Bit, Low-Power Stereo Audio With Analog Mixi


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PCM1774
SLAS551 JULY 2007
16-Bit, Low-Power Stereo Audio With Analog Mixing, Line Headphone Outputs
FEATURES
Analog Front End: Stereo Single-Ended Input Microphone Amplifier Analog Back End: Stereo/Mono Line Output With Volume Stereo/Mono Headphone Amplifier With Volume Analog Performance: Dynamic Range: 40-mW 40-mW Headphone Output Power Supply Voltage 1.71 Digital Section 1.71 Digital Core Section Analog Section Power Amplifier Section Power Dissipation: Playback, V/2.4 44.1 Power Down Sampling Frequency: Operation From Single Clock Input Without System Clock: Common-Audio Clock (256 fS/384 fS), 12/24, 13/26, 13.5/27, 19.2/38.4, 19.68/39.36 (I2CTM) (SPI) Wire Serial Control Programmable Function Register Control: Digital Attenuation: Digital Gain DAC: Power Up/Down Control Each Module 6-dB -70-dB Gain Analog Outputs 0/12/20 Microphone Input 0-dB -21-dB Gain Analog Mixing Three-Band Tone Control Sound Analog Mixing Control Pop-Noise Reduction Circuit Short Protection Circuit Package: 4-mm 4-mm Package Operation Temperature Range: -40°C 85°C
APPLICATIONS
Portable Audio Player, Cellular Phone Video Camcorder, Digital Still Camera PMP/DMB/PND
DESCRIPTION
PCM1774 low-power stereo designed portable digital audio applications. device integrates headphone amplifier, line amplifier, line input, boost amplifier, programmable gain control, analog mixing, sound effects. available small-footprint, 4-mm 4-mm package. PCM1774 supports right-justified, left-justified, I2S, formats, providing easy interfacing audio decoder/encoder chips. Sampling rates supported. user-programmable functions accessible through two- three-wire serial control port.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademark Philips Electronics.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2007, Texas Instruments Incorporated
PCM1774
SLAS551 JULY 2007
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This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage Input voltage Input current (any except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (reflow, peak) VDD, VIO, VCC, -0.3 ±0.1 -0.3 Ground voltage differences: DGND, AGND, PGND UNIT
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
Analog supply voltage, VCC, Digital supply voltage, VDD, Digital input logic family Digital input clock frequency Analog output load resistance Analog output load capacitance Digital output load capacitance Operating free-air temperature SCKI system clock LRCK sampling clock HPOL HPOR 3.072 1.71 CMOS 18.432 UNIT
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PCM1774
SLAS551 JULY 2007
ELECTRICAL CHARACTERISTICS
specifications 25°C, kHz, system clock 16-bit data (unless otherwise noted).
PARAMETER Audio Data Characteristics DATA FORMAT Resolution
TEST CONDITIONS
UNIT
left-, right-justified, first, complement CMOS compatible 0.75 0.25
Bits
Audio data interface format Audio data length Audio data format Sampling frequency (fS) System clock Digital Input/Output Logic family Input logic level Input logic current Output logic level
Bits
Digital Input Line Output Through (LOL LOR) volume analog mixing disabled DYNAMIC PERFORMANCE Full-scale output voltage Dynamic range THD+N Signal-to-noise ratio Channel separation Total harmonic distortion noise Load resistance Line Input Line Output Through Mixing Path (LOL LOR) volume analog mixing enabled DYNAMIC PERFORMANCE Full-scale input output voltage Signal-to-noise ratio EIAJ, A-weighted 2.828 Vrms EIAJ, A-weighted EIAJ, A-weighted 2.828 0.008% Vrms
Digital Input Headphone Output Through (HPOL HPOR) OFF, volume speaker powered down, analog mixing disabled, capless mode DYNAMIC PERFORMANCE Full-scale output voltage Signal-to-noise ratio EIAJ, A-weighted volume volume 2.828 0.1% 0.03% Vrms
THD+N
Total harmonic distortion noise
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PCM1774
SLAS551 JULY 2007
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ELECTRICAL CHARACTERISTICS (continued)
specifications 25°C, kHz, system clock 16-bit data (unless otherwise noted).
PARAMETER Load resistance mVPP PSRR Power-supply rejection ratio kHz, mVPP kHz, mVPP Line Input Headphone Output Through Mixing Path (HPOL HPOR) OFF, volume speaker powered down, analog mixing enabled, capless mode DYNAMIC PERFORMANCE Full-scale output voltage Signal-to-noise ratio Load resistance Filter Characteristics INTERPOLATION FILTER Pass band Stop band Pass-band ripple Stop-band attenuation Group delay De-emphasis error ANALOG FILTER Frequency response Power Supply Supply Current Supply current Power dissipation Temperature Condition Operation temperature Thermal resistance °C/W input, active, load inputs held static input inputs held static Voltage range 1.71 1.71 14.8 ±0.2 19/fs ±0.1 0.546 ±0.04 0.454 EIAJ, A-weighted 2.828 Vrms TEST CONDITIONS UNIT
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PCM1774
SLAS551 JULY 2007
ASSIGNMENTS
PCM1774RGP (TOP VIEW)
HPOR/LOR
HPOL/LOL
PGND
VCOM AGND AIN1R AIN1L
LRCK
SCKI DGND
MODE
MS/ADR
MD/SDA
Table TERMINAL FUNCTIONS
TERMINAL NAME AGND AIN1L AIN1R DGND HPOL/LOL HPOR/LOR LRCK MC/SCL MD/SDA MODE MS/ADR PGND SCKI VCOM Ground analog Analog input L-channel Analog input R-channel Serial clock Digital ground Serial audio data input Headphone/lineout R-channel Headphone/lineout L-channel Left right channel clock Mode control clock three-wire/two-wire interface Mode control data three-wire/two-wire interface Two- three-wire interface selection (LOW: SPI, HIGH: I2C) Mode control select three-wire/two-wire interface Ground speaker power amplifier System clock Analog power supply Analog common voltage Power supply digital core Power supply digital Power supply power amplifier DESCRIPTION
MC/SCL
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Module Possible Power Up/Down
PCM1774
SLAS551 JULY 2007
SCKI LRCK MD/SDA MC/SCL MS/ADR MODE
Power Reset Power Up/Down Manager
Clock Manager Audio Interface
FUNCTIONAL BLOCK DIAGRAM
Serial Interface (SPI/I2C)
-62dB Mute
Analog Input L-ch
AIN1L
0/12/20dB -21dB
LOUT
Digital Filter
-70dB
MONO
HPOL/
ROUT
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Digital Filter
Analog Input R-ch 0/12/20dB -21dB
AIN1R
-70dB
HPOR/
VCOM
VCOM
DGND
PGND
AGND
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PCM1774
SLAS551 JULY 2007
TYPICAL PERFORMANCE CURVES
specifications 25°C, kHz, system clock 16-bit data, unless otherwise noted.
INTERPOLATION FILTER, STOP BAND
INTERPOLATION FILTER, PASS BAND
Amplitude
Amplitude
Frequency
-0.1 -100
-120
-0.2 Frequency
Figure THREE-BAND TONE CONTROL (BASS, MIDRANGE, TREBLE)
Figure
THREE-BAND TONE CONTROL (BASS)
Figure
Figure
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PCM1774
SLAS551 JULY 2007
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TYPICAL PERFORMANCE CURVES (continued)
specifications 25°C, kHz, system clock 16-bit data, unless otherwise noted.
THREE-BAND TONE CONTROL (MIDRANGE) THREE-BAND TONE CONTROL (TREBLE)
Figure THD+N/SNR POWER SUPPLY HEADPHONE OUTPUT,
0.05 0.012 0.04 THD+N 0.03
Figure THD+N/SNR POWER SUPPLY LINE OUTPUT, 10-k
THD+N Total Harmanic Distortion Noise
THD+N Total Harmanic Distortion Noise
0.011 0.01
Signal Noise Ratio
0.02
0.009 THD+N 0.008
0.01
Power Supply
0.007 Power Supply
Figure
Figure
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Signal Noise Ratio
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PCM1774
SLAS551 JULY 2007
TYPICAL PERFORMANCE CURVES (continued)
specifications 25°C, kHz, system clock 16-bit data, unless otherwise noted.
OUTPUT POWER POWER SUPPLY (HEADPHONE, 16-)
THD+N OUTPUT POWER (HEADPHONE, 16-, VOLUME
THD+N Total Harmanic Distortion Noise
fIN=
Output Power
Power Supply
0.01
Output Power
Figure THD+N OUTPUT POWER (HEADPHONE, 16-, VOLUME
Figure OUTPUT SPECTRUM (DAC HEADPHONE OUTPUT, 16-)
fIN=
THD+N Total Harmanic Distortion Noise
1kHz
Amplitude
-100
-120
0.01 Output Power
-140 Frequency
Figure
Figure
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PCM1774
SLAS551 JULY 2007
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DETAILED DESCRIPTION
Analog Input AIN1L AIN1R pins used microphone line inputs with selectable 12-, 20-dB boost 1-Vrms input. these analog inputs have high input impedance which changed gain settings. pair inputs selected register (AIL0 AIR0). Gain Settings Analog Input gain analog signals adjusted from 1-dB steps following 12-, 20-dB boost amplifier. gain level each channel registers (GMR[2:0], [2:0]. Converter includes multilevel delta-sigma modulator interpolation filter. These used obtain high PSRR, jitter sensitivity, out-of-band noise quickly easily. interpolation filter includes digital attenuator, digital soft mute, three-band tone control (bass, midrange treble), sound controlled registers de-emphasis filter (32, 44.1 kHz) controlled registers (ATL[5:0], ATR[5:0], PMUL, PMUR, DEM[1:0]). Oversampling rate control reduce out-of-band noise when operating sampling rates using register (OVER). Common Voltage VCOM normally biased VCC, provides common voltage internal circuitry. recommended that 4.7-F capacitor connected between this AGND provide clean voltage avoid noise. PCM1774 have little noise each analog output capacitor smaller than used. Line Output HPOL/LOL HPOR/LOR pins drive 10-k load configured register (HPS[1:0]) monaural single-ended, monaural differential, stereo single-line output with 1-Vrms output. These outputs include analog volume amplifier that from mute steps 0.5-, 4-dB. Each output controlled registers (HLV[5:0], HRV[5:0], HMUL, HMUR). blocking capacitor required when connecting external speaker amplifier with monaural differential input. center voltage with zero data input. Headphone Output HPOL/LOL HPOR/LOR pins configured stereo, monaural, monaural differential headphone output register (HPS[1:0]). These pins have more than mWrms output power into load, either through blocking capacitor without capacitor. These outputs include analog volume amplifier that from steps 0.5, Each controlled registers (HLV[5:0], HRV[5:0], HMUL, HMUR). center voltage with zero data input. Analog Mixing Bypass Mixing amplifiers (MXL, MXR) inputs from pins. analog inputs selected register (AIR0, AIL0) bypass connect mixed signal headphone speaker outputs register (MXR[2:0], MXL[2:0]). gain analog inputs controlled register (GMR[2:0], GML[2:0]). These functions suitable radio, headset, other analog sources without ADC. Digital Gain Control portable application with small speakers require high sound level when playing back audio data recorded level. Digital gain control (DGC) used amplify digital input data setting register (SPX[1:0]).
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PCM1774
SLAS551 JULY 2007
Sound sound effect provided mixing L-channel R-channel data with band-pass filter with parameters, mixing ratio band pass filter characteristic, that controlled register (3DP[3:0], 3FLO). Three-Band Tone Control Tone control bass, midrange, treble controls that adjusted from 1-dB steps registers (LGA[4:0], MGA[4:0] HGA[4:0]). Register (LPAE) attenuates digital input signal automatically prevent clipping output signal settings above bass control. LPAE effect midrange treble controls. Digital Monaural Mixing audio data converted from stereo digital data mixed monaural digital data. conversion occurs internal audio interface section controlled register (MXEN). Zero-Cross Detection Zero-cross detection minimizes audible zipper noise while changing analog volume digital attenuation. This function applies digital input digital output defined register (ZCRS). Short Protection short-circuit protection each headphone output prevents damage device while output shorted VPA, output shorted PGND, outputs shorted together. When short circuit detected outputs, PCM1774 powers down shorted amplifier immediately. short-protection status monitored reading register (STHC, STHL, SCHR) through interface. Short-circuit protection operates enabled headphone amplifier. Pop-Noise Reduction Circuit pop-noise reduction circuit prevents audible noise when turning power supply on/off powering device up/down portable applications. recommended establish register settings sequence that shown Table Table particular external parts required. Power Up/Down Each Module Using register (PMXL, PMXR), register (PBIS, PDAR, PDAL, PHPR, PHPL) register (PCOM), unused modules powered down minimize power consumption during playback only). Digital Audio Interface PCM1774 receive I2S, right-justified, left-justified, formats both master slave modes. These options selected register (PFM[1:0]), register (RFM[1:0]) register (MSTR). Digital Interface digital pins interface various power supply voltages. connected 1.71-V 3.6-V power supply. Power Supply connected same voltage must applied both pins. connected 1.71 different voltage applied each these pins (for example,
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PCM1774
SLAS551 JULY 2007
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DESCRIPTION OPERATION
System Clock Input PCM1774 accept clocks various frequencies without PLL. They used clocking digital filters automatic level control delta-sigma modulators classified common-audio application-specific clocks. Table shows frequencies common-audio clock application-specific clock. Figure shows timing requirements system clock inputs. sampling rate frequency system clocks determined settings register (MSR[2:0]) register (NPR[5:0]). Note that sampling rate application-specific clock little sampling error. details shown Table Table System Clock Frequencies
CLOCK Common-audio clock Application-specific clock FREQUENCIES 11.2896, 12.288, 16.9344, 18.432 13.5, 19.2, 19.68, 38.4, 39.36
tw(SCKH) SCKI tw(SCKL)
T0005-12
PARAMETERS System-clock pulse duration, high System-clock pulse duration,
SYMBOL tw(SCKH) tw(SCKL)
UNITS
Figure System Clock Timing Power-On Reset System Reset power-on-reset circuit outputs reset signal, typically this circuit does depend voltage other power supplies (VCC, VPA, VIO). Internal circuits cleared default status, then analog digital outputs have signal. PCM1774 does require power supply sequencing. Register data after turning power supplies System reset enabled setting register (SRST After reset sequence, register data reset SRST automatically. circuits cleared their default status once system reset. Note that PCM1774 audible noise analog outputs when enabling SRST. Power On/Off Sequence reduce audible noise, sequence register settings required after turning power supplies when powering before turning power supplies when powering down. some modules required particular application operation, they should placed power-down state after performing power-on sequence. recommended power-on power-off sequences shown Table Table respectively.
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PCM1774
SLAS551 JULY 2007
Table Recommended Power-On Sequence
STEP REGISTER SETTINGS 4027h 4127h 4427h 4527h 4620h 49E0h 5601h 4803h 5811h 49ECh 4A01h 5230h 5711h Turn power supplies Headphone amplifier L-ch volume Headphone amplifier R-ch volume Digital attenuator L-ch (-24 Digital attenuator R-ch (-24
NOTE
audio interface format (left-justified) (DAL, DAR) analog bias power Zero-cross detection enable Analog mixer (MXL, MXR) power Analog mixer input (SW2, SW5) select Headphone amplifier (HPL, HPR, HPC) power VCOM power Analog front (D2S, MCB, PG1, power Analog input (MUX3, MUX4) select. Analog input (MUX1, MUX2) select
should turned prior simultaneously with, other power supplies. recommended register data with system clock input after turning power supplies level acceptable volume attenuation. Level should resumed register data recorded when system powers off. Audio interface format should match decoder being used.
Table Recommended Power-Off Sequence
STEP REGISTER SETTINGS 447Fh 457Fh 5811h 49ECh 5200h 5A00h 4A00h 49E0h 4800h 4900h L-ch digital soft-mute enable R-ch digital soft-mute enable Analog mixer input (SW2, SW5) select Headphone amplifier (HPL, HPR, HPC) power Analog front (D2S, MCB, PG1, power down PG1, gain control VCOM power down Wait time (750
NOTE
Headphone amplifier (HPL, HPR, HPC) power down, speaker amplifier (SPL, SPR) power down Analog mixer (MXL, MXR) power down (DAL, DAR) analog bias power down Turn power supplies.
level acceptable volume attenuation. headphone amplifier must operating during power-off sequence. PCM1774 requires time VCOM reach ground level from common level. wait time allowed depends settings register PTM[1:0], RES[4:0]. default setting VCOM Power supply sequencing required. recommended turn power supplies after setting registers with system clock input.
Power-Supply Current current consumption PCM1774 depends power up/down status each circuit module. order reduce power consumption, disabling each module recommended when used application operation. Table shows current consumption some states.
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Table Power Consumption Table
OPERATION MODE CONDITION Zero Data 44.1 Power Down Zero Data 44.1 Active Zero Data 44.1 Line Output Zero Data 44.1 Headphone Output Zero Data 44.1 Headphone Output with Sound Effect Zero Data 44.1 Headphone Output with Stereo Analog Mixing Zero Data 44.1 Headphone Output with Mono Analog Mixing POWER SUPPLY CURRENT [mA] 0.000 0.000 0.000 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.03 0.04 0.000 0.000 0.000 0.84 1.47 1.84 0.84 1.47 1.84 0.84 1.47 1.84 1.29 2.26 2.82 0.84 1.47 1.84 0.84 1.47 1.84 0.001 0.001 0.001 1.68 1.81 1.96 1.38 1.50 1.64 1.38 1.50 1.65 1.38 1.50 1.64 1.68 1.81 1.96 1.53 1.66 1.81 0.000 0.000 0.000 0.38 0.41 0.46 0.38 0.41 0.46 0.38 0.41 0.46 0.38 0.42 0.46 0.38 0.41 0.46 0.38 0.41 0.46 [mW] TOTAL 0.000 0.000 0.000 0.002 0.003 0.003
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PCM1774
SLAS551 JULY 2007
Table Power Consumption Table (continued)
OPERATION MODE CONDITION Zero Data 44.1 Digital Input Zero Data 44.1 Digital Input digital inputs held static. POWER SUPPLY CURRENT [mA] 0.68 0.69 0.71 0.52 0.54 0.55 0.38 0.41 0.46 0.38 0.42 0.46 [mW] TOTAL
Headphone Output with Stereo Analog Mixing
Headphone Output with Mono Analog Mixing
Audio Serial Interface audio serial interface PCM1774 comprises LRCK, BCK, DIN, DOUT. Sampling rate (fS), left right channel present LRCK. receives serial data interpolation filter, DOUT transmits serial data from decimation filter. clocks transfer serial audio data DOUT high-to-low transition. LRCK should synchronized with audio system clock. Ideally, recommended that they derived from PCM1774 requires LRCK synchronized with system clock. PCM1774 does require specific phase relationship between LRCK system clock. PCM1774 both master mode slave mode interface formats, which selected register (MSTR). master mode, PCM1774 generates LRCK from system clock.
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Audio Data Formats Timing PCM1774 supports I2S, right-justified, left-justified, formats. data formats shown Figure selected using registers (RFM[1:0], PFM[1:0]). formats require binary 2s-complement, MSB-first audio data. default format I2S. Figure shows detailed timing diagram.
LRCK
tw(BCH)
tw(BCL)
t(LB)
tw(BCY) t(BL)
t(DS)
t(DH)
PARAMETERS t(BCY) tw(BCH) tw(BCL) t(BL) t(LB) t(DS) t(DH) pulse cycle time (I2S, left- right-justified formats) pulse cycle time (DSP format) high-level time low-level time rising edge LRCK edge LRCK edge rising edge time hold time Rising time signals Falling time signals sampling frequency.
1/(64 1/(256
UNITS
Figure Audio Interface Timing (Slave Mode)
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PCM1774
SLAS551 JULY 2007
t(SCY)
SCKI
t(DL)
LRCK (Output)
tw(BCH) tw(BCL) t(DB) t(DB)
(Output)
t(BCY)
t(DS)
t(DH)
PARAMETERS t(SCY) t(DL) t(DB) t(BCY) tw(BCH) tw(BCL) t(DS) t(DH) SCKI pulse cycle time LRCK edge from SCKI rising edge edge from SCKI rising edge pulse cycle time high level time level time DATA setup time DATA hold time kHz. sampling frequency.
1/(256 1/(64
UNIT
Figure Audio Interface Timing (Master Mode)
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PCM1774
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Right-Justified Data Format; L-Channel HIGH, R-Channel LOW, LRPC
1/fS LRCK L-Channel R-Channel
16-Bit Right-Justified
Data Format; L-Channel LOW, R-Channel HIGH, LRPC
1/fS LRCK L-Channel R-Channel
Left-Justified Data Format; L-Channel HIGH, R-Channel LOW, LRPC
1/fS LRCK L-Channel R-Channel
Burst Interface Format Master Mode; L-Channel HIGH, R-Channel LOW, LRPC
1/fS LRCK L-Channel R-Channel
Format, LRPC
1/fS LRCK
T0009-07
NOTE: audio interface formats support master mode (register MSTR setting multi-sampling rate (register NPR[5:0] MSR[2:0]) shown Table Table
Figure Audio Data Formats
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PCM1774
SLAS551 JULY 2007
THREE-WIRE INTERFACE (SPI, MODE (PIN LOW)
write operations serial control port 16-bit data words. Figure shows control data word format. most-significant must There seven bits, labeled IDX[6:0], that register address write operation. least-significant eight bits, D[7:0], contain data written register specified IDX[6:0]. Figure shows functional timing diagram writing serial control port. write data into mode register, data clocked into internal shift register rising edge clock. serial data should change falling edge clock, should during write mode. rising edge should aligned with falling edge last clock pulse 16-bit frame. continuously between transactions while state.
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
Register Index Address)
Register Data
R0001-01
Figure Control Data Word Format
Single Write Operation Bits
Continuous Write Operation Bits Frames
Register Index Bits
Register Data
Register (N+1) Data
Register (N+2) Data
Frames
T0012-03
Figure Register Write Operation
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Three-Wire Interface (SPI) Timing Requirements Figure shows detailed timing diagram serial control interface. These timing parameters critical proper control port operation.
tw(MHH) t(MLS) tw(MCH) t(MCY) t(MDS) t(MDH)
T0013-08
tw(MCL) t(MLH)
PARAMETERS t(MCY) tw(MCL) tw(MCH) tw(MHH) t(MLS) t(MLH) t(MDH) t(MDS) pulse cycle time level time high level time high level time falling edge rising edge hold time hold time setup time
UNIT
3/(128 (min), where sampling rate.
Figure Interface Timing
TWO-WIRE INTERFACE [I2C, MODE (PIN HIGH]
PCM1774 supports serial data transmission protocol standard slave device. This protocol explained specification 2.0. mode, control terminals changed follows.
TERMINAL NAME MS/ADR MD/SDA MC/SCL PROPERTY Input Input/output Input DESCRIPTION address data clock
SLAVE ADDRESS
PCM1774 7-bit slave address. first bits (MSBs) slave address factory preset 100011. last address byte device select bit, which user-defined terminal. maximum PCM1774 connected same time. PCM1774 responds when receives slave address.
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PCM1774
SLAS551 JULY 2007
Packet Protocol master device must control packet protocol, which consists start condition, slave address with read/write bit, data write) acknowledgment read), stop condition. PCM1774 supports only slave receiver slave transmitter.
Slave Address
DATA
DATA
Start Condition
R/W: Read Operation Otherwise, Write Operation ACK: Acknowledgement Byte DATA: Bits (Byte)
Stop Condition
Write Operation
Transmitter Data Type
Slave Address
DATA
DATA
Read Operation
Transmitter Data Type
Master Device Start Condition
Slave Address Slave Device Stop Condition
DATA
DATA
NACK
T0049-03
Figure Basic Framework WRITE OPERATION master write PCM1774 registers single access. master sends PCM1774 slave address with write bit, register address, data. When undefined registers accessed, PCM1774 does send acknowledgment. Figure shows diagram write operation.
Transmitter Data Type
Slave Address
Address
Write Data
Master Device Slave Device Start Condition Write ACK: Acknowledge Stop Condition
R0002-01
Figure Framework Write Operation READ OPERATION master read PCM1774 register. value register address stored indirect index register advance. master sends PCM1774 slave address with read after storing register address. Then PCM1774 transfers data which index register specifies. Figure shows diagram read operation.
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Transmitter Data Type
Slave Address
Address
Slave Address
Read Data NACK
Master Device Slave Device Start Condition Repeated Start Condition ACK: Acknowledge Stop Condition NACK: Acknowledge Write Read
R0002-02
NOTE: slave address after repeated start condition must same previous slave address.
Figure Read Operation Timing Diagram
PARAMETERS fSCL t(BUF) t(LOW) t(HI) t(RS-SU) t(S-HD) t(D-SU) t(D-HD) t(SCL-R) t(SCL-R1) t(SCL-F) t(SDA-R) t(SDA-F) t(P-SU) t(SP) clock frequency free time between STOP START condition period clock High period clock Setup time START condition Hold time START condition Data setup time Data hold time Rise time signal Rise time signal after repeated START condition after acknowledge Fall time signal Rise time signal Fall time signal Setup time STOP condition Capacitive load line Pulse duration suppressed spike
CONDITIONS Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard
UNIT
1000 1000 1000 1000 1000
Figure Interface Timing
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PCM1774
SLAS551 JULY 2007
USER-PROGRAMMABLE MODE CONTROLS
Register mode control register shown Table Each register includes index address) indicated IDX[6:0] bits. Table Mode Control Register
REGISTER Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register IDX[6:0] (B14-B8) Volume (L-ch) Volume (R-ch) digital attenuation soft mute (L-ch) digital attenuation soft mute (R-ch) over sampling, de-emphasis, audio interface, Analog mixer power up/down power up/down Analog output configuration select insertion detection, short protection Shut down status read back PG1, power up/down Master mode System reset, sampling rate control, data swap configuration, sampling rate control, zero-cross Analog input select (MUX1, Analog mixing switch (SW1, Analog analog path (PG5, gain Microphone boost Bass boost gain level Middle boost gain level Treble boost gain level Sound effect source select, sound digital monaural mixing PG1/PG2 additional Gain Power up/down time control DAC: converter DESCRIPTION DEM1 PBIS SRST MBST LPAE HMUL HMUR PMUL PMUR DEM0 PDAR LRPC MSR2 MXR2 GMR2 3DEN PTM1 HLV5 HRV5 ATL5 ATR5 PFM1 PDAL PAIR NPR5 MSR1 AIR1 MXR1 GMR1 PTM0 HLV4 HRV4 ATL4 ATR4 PFM0 PAIL NPR4 MSR0 AIR0 MXR0 GMR0 LGA4 MGA4 HGA4 3FL0 RES4 HLV3 HRV3 ATL3 ATR3 SPX1 PHPR HPS1 SDHR STHR NPR3 LGA3 MGA3 HGA3 3DP3 RES3 HLV2 HRV2 ATL2 ATR2 SPX0 PHPL HPS0 SDHL STHL MSTR NPR2 MXL2 GML2 LGA2 MGA2 HGA2 3DP2 RES2 HLV1 HRV1 ATL1 ATR1 PMXR NPR1 AIL1 MXL1 GML1 G20R LGA1 MGA1 HGA1 3DP1 G12R RES1 HLV0 HRV0 ATL0 ATR0 OVER PMXL PCOM BIT0 NPR0 ZCRS AIL0 MXL0 GML0 G20L LGA0 MGA0 HGA0 3DP0 MXEN G12L RES0
HPA: Headphone amplifier PGx: Analog input buffer
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Register Definitions Registers
Register Register IDX6 IDX6 IDX5 IDX5 IDX4 IDX4 IDX3 IDX3 IDX2 IDX2 IDX1 IDX1 IDX0 IDX0 HMUL HMUR HLV5 HRV5 HLV4 HRV4 HLV3 HRV3 HLV2 HRV2 HLV1 HRV1 HLV0 HRV0
IDX[6:0]: 0000b (40h): Register IDX[6:0]: 0001b (41h): Register HMUL: Analog Mute Control (Line Headphone L-Channel) HMUR: Analog Mute Control (Line Headphone R-Channel) Default value: HPOL/LOL HPOR/LOR independently muted zero level when HMUL HMUR These settings take precedence over analog volume level settings.
HMUL, HMUR HMUL, HMUR Mute disabled Mute enabled (default)
HLV[5:0]: Analog Volume (Headphone L-Channel) HRV[5:0]: Analog Volume (Headphone R-Channel) Default value: 0000. HPOL/LOL HPOR/LOR independently controlled between with step size depending gain level shown Table Outputs have zipper noise while changing levels. This noise reduced selecting zero-cross detection (register ZCRS). Table Headphone Gain Level Setting
HLV[5:0], HRV[5:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 STEP GAIN LEVEL SETTING -0.5 -1.5 -2.5 -3.5 -4.5 HLV[5:0], HRV[5:0] 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 STEP GAIN LEVEL SETTING -5.5 -6.5 -7.5 -8.5 -9.5 -10.5 HLV[5:0], HRV[5:0] 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 STEP GAIN LEVEL SETTING
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PCM1774
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Registers
Register Register IDX6 IDX6 IDX5 IDX5 IDX4 IDX4 IDX3 IDX3 IDX2 IDX2 IDX1 IDX1 IDX0 IDX0 PMUL PMUR ATL5 ATR5 ATL4 ATR4 ATL3 ATR3 ATL2 ATR2 ATL1 ATR1 ATL0 ATR0
IDX[6:0]: 0100b (44h): Register IDX[6:0]: 0101b (45h): Register PMUL: Digital Soft Mute Control (DAC L-Channel) PMUR: Digital Soft Mute Control (DAC R-Channel) Default value: digital inputs independently muted setting PMUL PMUR digital data changed from current attenuation level mute level 1-dB step every 8/fS time period. When PMUL PMUR digital data changed from mute level current attenuation level 1-dB step every 8/fS time period. PCM1774, audible zipper noise reduced selecting zero-cross detection (register ZCRS).
PMUL, PMUR PMUL, PMUR Mute disabled (default) Mute enabled
ATL[5:0]: Digital Attenuation Setting (DAC L-Channel) ATR[5:0]: Digital Attenuation Setting (DAC R-Channel) Default value: 1111b digital inputs independently attenuated. attenuation digital input changed 1-dB step every 8/fS time period. Audible zipper noise PCM1774 reduced selecting zero-cross detection (register ZCRS). Table Digital Attenuation Setting
ATL[5:0], ATR[5:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 ATTENUATION LEVEL SETTING (default) ATL[5:0], ATR[5:0] 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 ATTENUATION LEVEL SETTING ATL[5:0], ATR[5:0] 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 ATTENUATION LEVEL SETTING Mute
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 DEM1 DEM0 PFM1 PFM0 SPX1 SPX0 OVER
IDX[6:0]: 0110b (46h): Register DEM[1:0]: De-Emphasis Filter Selection Default value: digital de-emphasis filter front interpolation filter. three de-emphasis filters selected corresponding sampling rate, kHz, 44.1 kHz, kHz.
DEM[1:0] De-Emphasis Filter Selection (default) 44.1
PFM[1:0]: Audio Interface Selection (Digital Input) Default value: audio interface digital input I2S, right-justified, left-justified, formats.
PFM[1:0] Audio Interface Selection Digital Input format (default) Right-justified format Left-justified format format
SPX[1:0]: Digital Gain Control Input Default value: These bits used gain digital input data.
SPX[1:0] Digital Gain Control input (default)
OVER: Oversampling Control Delta-Sigma Default value: This used control oversampling rate delta-sigma DAC. When PCM1774 operates sampling rates (less than kHz) SCKI frequency less than 12.5 MHz, OVER recommended.
OVER OVER (default)
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 PMXR PMXL
IDX[6:0]: 1000b (48h) Register PMXR: Power Up/Down (Mixer R-Channel) PMXL: Power Up/Down (Mixer L-Channel) Default value: These bits used control power up/down analog mixer.
PMXL, PMXR PMXL, PMXR Power down (default) Power
Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 PBIS PDAR PDAL PHPR PHPL
IDX[6:0]: 1001b (49h): Register PBIS: Power Up/Down Control Bias Default value: This used control power up/down analog bias circuit.
PBIS PBIS Power down (default) Power
PDAR: Power Up/Down Control (DAC R-Channel Digital Filter) PDAL: Power Up/Down Control (DAC L-Channel Digital Filter) Default value: These bits used control power up/down interpolation filter.
PDAR, PDAL PDAR, PDAL Power down (default) Power
PHPR: Power Up/Down Control (Line R-Channel Headphone Output) PHPL: Power Up/Down Control (Line L-Channel Headphone Output) Default value: These bits used control power up/down headphone amplifier.
PHPR, PHPL PHPR, PHPL Power down (default) Power
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 HPS1 HPS0 PCOM
IDX[6:0]: 1010b (4Ah): Register HPS[1:0]: Line Headphone Output Configuration Default value: HPOL/LOL HPOR/LOR configured selected follows.
HPS[1:0] Line Headphone Output Configuration Stereo output (default) Single monaural output Differential monaural output Reserved
PCOM: Power Up/Down Control VCOM Default value: This used control power up/down VCOM.
PCOM PCOM Power down (default) Power
Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SDHR SDHL
IDX[6:0]: 1011b (4Bh): Register SDHR: Short Protection Status (R-Channel Headphone) SDHL: Short Protection Status (L-Channel Headphone) Default value: Short-circuit protection disabled this function needed application.
SDHR, SDSL SDHR, SDHL Enabled (default) Disabled
Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 STHR STHL
IDX[6:0]: 1101b (4Dh): Register STHR: Short Protection Status (R-Channel Headphone) STHL: Short Protection Status (L-Channel Headphone) These bits used read short protection status through interface.
STHR, STHL STHR, STHL Detect short circuit detect short circuit
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 PAIR PAIL
IDX[6:0]: 0010b (52h): Register PAIR: Power Up/Down (Gain Amplifier R-Channel Analog Input) PAIL: Power Up/Down (Gain Amplifier L-Channel Analog Input) Default value: These bits used control power up/down (gain amplifier analog input).
PAIR, PAIL PAIR, PAIL Power down (default) Power
Registers 84-86
Register Register Register IDX6 IDX6 IDX6 IDX5 IDX5 IDX5 IDX4 IDX4 IDX4 IDX3 IDX3 IDX3 IDX2 IDX2 IDX2 IDX1 IDX1 IDX1 IDX0 IDX0 IDX0 SRST MBST LRPC MSR2 NPR5 MSR1 NPR4 MSR0 NPR3 MSTR NPR2 NPR1 BIT0 NPR0 ZCRS
IDX[6:0]: 0100b (54h): Register IDX[6:0]: 0101b (55h): Register IDX[6:0]: 0110b (56h): Register MSTR: Master Slave Selection Audio Interface Default value: This used select either master slave mode audio interface. master mode, PCM1774 generates LRCK from system clock. slave mode, receives LRCK from another device.
MSTR MSTR Slave interface (default) Master interface
BIT0: Length Selection Audio Interface Default value: This used select data length input.
BIT0 BIT0 Reserved bits (default)
SRST: System Reset Default value: This used enable system reset. circuits reset setting SRST After completing reset sequence, SRST automatically.
SRST SRST Reset disabled (default) Reset enabled
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LRPC: LRCK Polarity Control Default value: This used reverse L-channel R-channel audio data.
LRPC LRPC Normal (default) Reverse
NPR[5:0]: System Clock Rate Selection Default value: 000000 MSR[2:0]: System Clock Dividing Rate Selection Master Mode (Register Default value: These bits used select system clock rate dividing rate input system clock. Table details.
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Table System Clock Frequency Common-Audio Clock
SYSTEM CLOCK (MHz) SAMPLING RATE (kHz) SAMPLING RATE (kHz) REGISTER SETTINGS MSR[2:0] NPR[5:0] 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CLOCK (fS)
(SCK/256) (SCK/384) 6.144 (SCK/512) (SCK/768) (SCK/1024) (SCK/1536) (SCK/256) 8.192 (SCK/512) (SCK/1024) (SCK/256) (SCK/384) 12.288 (SCK/512) (SCK/768) (SCK/1024) (SCK/1536) (SCK/384) 18.432 (SCK/768) (SCK/1536) 22.05 (SCK/256) 14.7 (SCK/384) 5.6448 11.025 (SCK/512) 7.35 (SCK/768) 5.5125 (SCK/1024) 3.675 (SCK/1536) 44.1 (SCK/256) 29.4 (SCK/384) 11.2896 22.05 (SCK/512) 14.7 (SCK/768) 11.025 (SCK/1024) 7.35 (SCK/1536) Other settings reserved.
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Table System Clock Frequency Application-Specific Clock
SYSTEM CLOCK (MHz) SAMPLING RATE (kHz) SAMPLING RATE (kHz) REGISTER SETTINGS MSR[2:0] NPR[5:0] 0010 0001 0010 0010 0001 0010 0010 0010 0010 0001 0010 0010 0001 0010 0010 0010 0100 0011 0100 0100 0011 0100 0100 0100 0100 0011 0100 0100 0011 0100 0100 0100 0110 0101 0110 0110 0101 0110 0110 0110 CLOCK (fS)
48.214 (SCK/280) 44.407 (SCK/304) 32.142 (SCK/420) 13.5 24.107 (SCK/560) 22.203 (SCK/608) 16.071 (SCK/840) 12.053 (SCK/1120) 8.035 (SCK/1680) 48.214 (SCK/560) 44.407 (SCK/608) 32.142 (SCK/840) 24.107 (SCK/1120) 22.203 (SCK/1216) 16.071 (SCK/1680) 12.053 (SCK/2240) 8.035 (SCK/3360) 48.387 (SCK/248) 44.117 (SCK/272) 32.258 (SCK/372) 24.193 (SCK/496) 22.058 (SCK/544) 16.129 (SCK/744) 12.096 (SCK/992) 8.064 (SCK/1488) 48.387 (SCK/496) 44.117 (SCK/544) 32.258 (SCK/744) 24.193 (SCK/992) 22.058 (SCK/1088) 16.129 (SCK/1488) 12.096 (SCK/1984) 8.064 (SCK/2976) 48.484 (SCK/396) 44.444 (SCK/432) 32.323 (SCK/594) 19.2 24.242 (SCK/792) 22.222 (SCK/864) 16.161 (SCK/1188) 12.121 (SCK/1584) 8.080 (SCK/2376)
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Table System Clock Frequency Application-Specific Clock (continued)
SYSTEM CLOCK (MHz) SAMPLING RATE (kHz) SAMPLING RATE (kHz) REGISTER SETTINGS MSR[2:0] NPR[5:0] 0110 0101 0110 0110 0101 0110 0110 0110 1000 0111 1000 1000 0111 1000 1000 1000 1000 0111 1000 1000 0111 1000 1000 1000 1010 1001 1010 1010 1001 1010 1010 1010 1010 1001 1010 1010 1001 1010 1010 1010 CLOCK (fS)
48.484 (SCK/792) 44.444 (SCK/864) 32.323 (SCK/1188) 38.4 24.242 (SCK/1584) 22.222 (SCK/1728) 16.161 (SCK/2376) 12.121 (SCK/3168) 8.080 (SCK/4752) 47.794 (SCK/272) 43.918 (SCK/296) 31.862 (SCK/408) 23.897 (SCK/544) 21.959 (SCK/592) 15.931 (SCK/816) 11.948 (SCK/1088) 7.965 (SCK/1632) 47.794 (SCK/544) 43.918 (SCK/592) 31.862 (SCK/816) 23.897 (SCK/1088) 21.959 (SCK/1184) 15.931 (SCK/1632) 11.948 (SCK/2176) 7.965 (SCK/3264) 48.235 (SCK/408) 44.324 (SCK/444) 32.156 (SCK/612) 19.68 24.117 (SCK/816) 22.162 (SCK/888) 16.078 (SCK/1224) 12.058 (SCK/1632) 8.039 (SCK/2448) 48.235 (SCK/816) 44.324 (SCK/888) 32.156 (SCK/1224) 39.36 24.117 (SCK/1632) 22.162 (SCK/1776) 16.078 (SCK/2448) 12.058 (SCK/3264) 8.039 (SCK/4896)
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MBST: Output Configuration Master Mode Default value: This used control output configuration master mode. master mode, this sets output configuration normal mode burst mode. normal mode (MBST clock runs continuously. burst mode (MBST clock runs intermittently, number clock cycles LRCK period reduced equal number bits audio data being transmitted. Operating burst mode reduces power consumption (I/O cell power supply). This effective master mode (register MSTR
MBST MBST Normal mode (default) Burst mode
ZCRS: Zero-Cross Digital Attenuation/Mute Analog Gain Setting Default value: This used enable zero-cross detector, which reduces zipper noise while digital soft mute, digital attenuation analog gain setting, analog volume setting being changed. zero-cross data input 512/fS period (10.6 48-kHz sampling rate), then time-out occurs PCM1774 starts changing attenuation, gain, volume level. zero-cross detector cannot used with continuous-zero data.
ZCRS ZCRS Zero-cross disabled (default) Zero-cross enabled
Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AIR1 AIR0 AIL1 AIL0
IDX[6:0]: 0111b (57h): Register AIL0: AIN1L Selector (MUX1) Default value: This used select analog input, AIN1L.
AIL0 L-channel Select Disconnect (default) AIN1L
AIR0: AIN1R Selector (MUX2) Default value: This used select three stereo analog inputs, AIN1R.
AIR0 R-channel Select Disconnect (default) AIN1R
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MXR2 MXR1 MXR0 MXL2 MXL1 MXL0
IDX[6:0]: 1000b (58h): Register MXR2: Mixing (R-Channel Mixing Amplifier) From L-Channel Analog Input Default value: This used analog source into (R-ch mixing amplifier) from L-ch analog input.
MXR2 MXR2 Disable (default) Enable
MXR1: Mixing (R-Channel Mixing Amplifier) From R-Channel Analog Input Default value: This used analog source into (R-ch mixing amplifier) from R-ch analog input.
MXR1 MXR1 Disable (default) Enable
MXR0: Mixing (R-Channel Mixing Amplifier) From R-Channel Default value: This used analog source into (R-ch mixing amplifier) from R-ch DAC.
MXR0 MXR0 Disable (default) Enable
MXL2: Mixing (L-Channel Mixing Amplifier) From R-Channel Analog Input Default value: This used analog source into (L-ch mixing amplifier) from R-ch analog input.
MXL2 MXL2 Disable (default) Enable
MXL1: Mixing (L-Channel Mixing Amplifier) From L-Channel Analog Input Default value: This used analog source into (L-ch mixing amplifier) from L-ch analog input.
MXL1 MXL1 Disable (default) Enable
MXL0: Mixing (L-Channel Mixing Amplifier) From L-Channel Default value: This used analog source into (L-ch mixing amplifier) from L-ch DAC.
MXL0 MXL0 Disable (default) Enable
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 GMR2 GMR1 GMR0 GML2 GML1 GML0
IDX[6:0]: 1001b (59h): Register GMR[2:0]: Gain Level Control (Gain Amplifier Analog Input R-Channel Bypass) GML[2:0]: Gain Level Control (Gain Amplifier Analog Input L-Channel Bypass) Default value: These bits used setting gain level analog source mixing amplifier. recommended gain level avoid saturation analog mixer.
GMR[2:0] GML[2:0] Gain Level Control Gain Level Control (default)
Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 G20R G20L
IDX[6:0]: 1010b (5Ah): Register G20R: 20-dB Boost (Gain Amplifier AIN1R) Default value: This used boost microphone signal when analog input small.
G12R (REGISTER 124) G20R (REGISTER (default) Reserved GAIN
G20L: 20-dB Boost (Gain Amplifier AIN1L) Default value: This used boost microphone signal when analog input small.
G12L (REGISTER 124) G20L (REGISTER (default) Reserved GAIN
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 LPAE LGA4 LGA3 LGA2 LGA1 LGA0
IDX[6:0]: 1100b (5Ch): Register LPAE: Gain Adjustment Bass Boost Gain Control Default value: gain setting bass boost cause digital data saturation, depending input data level. Where this could occur, LPAE used same attenuation level bass boost gain level digital input data.
LPAE LPAE Disable (default) Enable
LGA[4:0]: Bass Boost Gain Control Default value: 0000 These bits used bass boost gain level digital data. detailed characteristics shown Typical Performance Curves.
LGA[4:0] 0000 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 TONE CONTROL GAIN (BASS) (default) LGA[4:0] 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 TONE CONTROL GAIN (BASS)
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MGA4 MGA3 MGA2 MGA1 MGA0
IDX[6:0]: 1101b (5Dh): Register MGA[4:0]: Middle Boost Gain Control Default value: 0000 These bits used midrange boost gain level digital data. detailed characteristics shown Typical Performance Curves.
MGA[4:0] 0000 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 TONE CONTROL GAIN (MIDRANGE) (default) MGA[4:0] 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 TONE CONTROL GAIN (MIDRANGE)
Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 HGA4 HGA3 HGA2 HGA1 HGA0
IDX[6:0]: 1110b (5Eh): Register HGA[4:0]: Treble Boost Gain Control kHz) Default value: 0000 These bits used treble boost gain level digital data. detailed characteristics shown Typical Performance Curves.
HGA[4:0] 0000 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 TONE CONTROL GAIN (TREBLE) (default) HGA[4:0] 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 TONE CONTROL GAIN (TREBLE)
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 3DEN 3FL0 3DP3 3DP2 3DP1 3DP0
IDX[6:0]: 1111b (5Fh): Register 3DEN: Sound Effect Enable Default value: This used enabling sound effect filter. This filter independently controlled parameters.
3DEN 3DEN Disable (default) Enable
3FL0: Filter Selection Sound Default value: This used selecting from types filter, narrow wide. These filters have different performance effect.
3FL0 3FL0 Narrow (default) Wide
3DP[3:0]: Efficiency Sound Effects Default value: 0000 These bits used adjusting sound efficiency. Higher percentages have greater efficiency.
3DP[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1111 Sound Effect Efficiency (default) 100% Reserved Reserved
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MXEN
IDX[6:0]: 0000b (60h): Register MXEN: Digital Monaural Mixing Default value: This used enable disable monaural mixing section that combines L-ch data R-ch data.
MXEN MXEN Stereo (default) Monaural Mixing
Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 G12R G12L
IDX[6:0]: 1100b (7Ch): Register G12R: Boost (Gain AIN1R AIN2R) G12L: Boost (Gain AIN1L AIN2L) Default value: This used boost small analog signal, microphone input. Register information detail settings.
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Register
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 PTM1 PTM0 RES4 RES3 RES2 RES1 RES0
IDX[6:0]: 1101b (7Dh): Register PTM[1:0]: Power-Up/Down Time Control Default value: RES[4:0]: Resister Value Control Default value: 1100 These bits used optimize audible noise ramp time headphone output device power on/off. Table Power Up/Down Time Control
RES[1:0] 0000 1000 1100 1110 Others VCOM CAPACITOR RES[4:0] 1110 1100 1000 0000 1110 1100 1000 0000 1110 1100 1000 0000 1110 1100 1000 0000 VCOM REGISTER VALUE Reserved PTM[1:0] set. set. set. set. POWER-UP TIME [ms] POWER-DOWN TIME [ms] 1500 1500 1500 Default NOTE
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CONNECTION DIAGRAMS
Regulator Pull Down MS/ADR MD/SDA MC/SCL MODE PCM1774 SCKI LRCK DGND AGND PGND
AIN1L AIN1R VCOM HPOL/LOL HPOR/LOR
Stereo Headphone
Figure Connection Diagram Table Recommended External Parts
C1-C2 1-4.7 1-4.7 10-220
HPOL
HPOL
HPOR HPOR
S0223-01
Figure High-Pass Filter Headphone Output
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device PCM1774RGPR PCM1774RGPRG4 PCM1774RGPT PCM1774RGPTG4
Status ACTIVE ACTIVE ACTIVE ACTIVE
Package Type
Package Drawing
Pins Package Plan 3000 Green (RoHS Sb/Br) 3000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
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11-Mar-2008
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing
Reel Reel Diameter Width (mm) (mm) 330.0 180.0 12.4 12.4
(mm)
(mm)
(mm)
(mm)
Pin1 (mm) Quadrant 12.0 12.0
PCM1774RGPR PCM1774RGPT
3000
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
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11-Mar-2008
*All dimensions nominal
Device PCM1774RGPR PCM1774RGPT
Package Type
Package Drawing
Pins
3000
Length (mm) 346.0 190.5
Width (mm) 346.0 212.7
Height (mm) 29.0 31.8
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IMPORTANT NOTICE
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