SLAS490 OCTOBER 2005 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, ANALO
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ADS8413
SLAS490 OCTOBER 2005
16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, ANALOG-TO-DIGITAL CONVERTER
FEATURES
2-MHz Sample Rate 16-Bit Resolution -107 Typ, +0.7/-0.5 Typ, +1.5/-1 Unipolar Differential Input Range: Internal Reference Internal Reference Buffer 200-Mbps LVDS Serial Interface Optional 200-MHz Internal Interface Clock 16-/8-Bit Data Frame Zero Latency Full Speed Power Dissipation: MSPS Mode (125 Power Dissipation) Power Down 48-Pin Package
APPLICATIONS
Medical Instrumentation HIgh-Speed Data Acquisiton Systems High-Speed Close-Loop Systems Communication
DESCRIPTION
ADS8413 16-bit, 2-MSPS, analog-to-digital (A/D) converter with internal reference. device includes capacitor based converter with inherent sample hold. ADS8413 also includes 200-Mbps, LVDS, serial interface. This interface designed support daisy chaining cascading multiple devices. selectable 16-/8-bit data frame mode enables single shift register chip (SN65LVDS152) converting data parallel format. ADS8413 unipolar differential input range supports differential input swing -Vref +Vref with common-mode voltage +Vref/2. feature provides substantial power saving when used lower conversion rates. ADS8413 available 48-pin package.
High-Speed Converter Family
Type/Speed 18-Bit Pseudo-Diff 18-Bit Pseudo-Bipolar, Fully Diff 16-Bit Pseudo-Diff ADS8383 ADS8381 ADS8380 ADS8382 ADS8411 ADS8370 ADS8371 ADS8401/05 ADS8410 (S-LVDS) ADS8412 16-Bit Pseudo-Bipolar, Fully Diff 14-Bit Pseudo-Diff 12-Bit Pseudo-Diff ADS8372 ADS8402/06 ADS7890 ADS8413 (S-LVDS) ADS7891 ADS7881 1.25
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2005, Texas Instruments Incorporated
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SLAS490 OCTOBER 2005
AGND
BDGND
Core Supply
Supply
LVDS CDAC Comparator CMOS REFIN Clock Internal Reference Conversion Control Logic Mode Selection
CSTART SYNC_O, CLK_O, SYNC_I, CLK_I,
CONVST BUSY BUSY LAT_Y/N BYTE, MODE_C/D, CLK_I/E,
REFOUT
ORDERING INFORMATION
MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) 1.5/-1 MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE -40°C 85°C -40°C 85°C ORDERING INFORMATION ADS8413IBRGZT ADS8413IBRGZR ADS8413IRGZT ADS8413IRGZR TRANSPORT MEDIA QUANTITY 2000 2000
ADS8413lB
ADS8413l
3/-1
most current package ordering information, Package Option Addendum this document, website www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
UNIT AGND AGND AGND +VBD BDGND Digital input voltage Digital output Operating temperature range Storage temperature range Junction temperature (TJmax) package Lead temperature, soldering Power dissipation Thermal impedance Vapor phase sec) Infrared sec) -0.3 -0.3 -0.3 -0.3 -0.3 (+VBD -0.3 (+VBD -40°C 85°C -65°C 150°C 150°C TA)/ 86°C/W 215°C 220°C
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
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SPECIFICATIONS
-40°C 85°C, V,+VBD Vref 4.096 sample (unless otherwise noted)
PARAMETER ANALOG INPUT Full-scale input voltage span Absolute input voltage range Input common-mode voltage range Input capacitance Input leakage current SYSTEM PERFORMANCE Resolution missing codes Integral linearity ADS8413IB ADS8413I ADS8413IB ADS8413I ADS8413IB ADS8413I ADS8413IB ADS8413I ADS8413IB ADS8413I External reference -4.0 -1.0 -3.0 -0.1 -0.15 0.7/-0.5 1.5/-0.8 ±0.2 ±0.03 ±0.1 0.15 Bits Bits
TEST CONDITIONS
UNIT
(-IN)
-Vref -0.2 -0.2 Vref/2-0.2 Vref/2
Vref Vref Vref Vref/2+0.2
Differential linearity
CMMR PSRR
Offset error Gain error Common-mode rejection ratio Power supply rejection ratio
External reference With common mode input signal mVp-p FFF0H output code +VBD +VBD +VBD +VBD
SAMPLING DYNAMICS Conversion time
Acquisition time Maximum throughput rate with without latency Aperture delay Aperture jitter Step response Overvoltage recovery DYNAMIC CHARACTERISTICS
psec
below Total harmonic distortion below below below Signal-to-noise ratio below below below SINAD Signal-to-noise distortion below below below SFDR Spurious free dynamic range below below Small signal bandwidth
-107 -113 37.5
Ideal input span; does include gain offset error. This endpoint INL, best fit. Least significant Measured relative actual measured reference. Calculated first nine harmonics input frequency.
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SPECIFICATIONS (continued)
-40°C 85°C, V,+VBD Vref 4.096 sample (unless otherwise noted)
PARAMETER EXTERNAL REFERENCE INPUT Input voltage range, VREF Resistance INTERNAL REFERENCE OUTPUT Start-up time Reference voltage range, Vref Source current Line regulation Drift POWER SUPPLY REQUIREMENTS Power supply voltage +VBD 4.75 5.25 5.25 From (+VA), with 1-µF storage capacitor REFOUT AGND room temperature Static load 4.75 5.25 IOUT 4.080 4.096 4.112 PPM/°C internal reference voltage 4.096 TEST CONDITIONS UNIT
Supply current, 2-MHz sample rate Power dissipation, 2-MHz sample rate MODE Supply current POWER DOWN Supply current Powerdown time Powerup time Invalid conversions after power reset TEMPERATURE RANGE Operating free LOGIC FAMILY CMOS DRIVER |VOD(SS)| |VOD(SS)| VOC(SS) |VOC(SS)| VOC(pp) Steady-state differential output voltage magnitude Change steady-state differential output voltage magnitude between logic states Steady-state common-mode output voltage Change steady-state common-mode output voltage between logic states Peak peak change common-mode output voltage Short circuit output current High impedance output current +VBD Figure Figure Figure 1.125 High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage loads loads +VBD -0.3 +VBD With 1-µF storage capacitor REFOUT AGND
Numbers
+VBD +0.3 +VBD
LOGIC FAMILY LVDS
1.375
vary ±20% values ensured design.
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SPECIFICATIONS (continued)
-40°C 85°C, V,+VBD Vref 4.096 sample (unless otherwise noted)
PARAMETER RECEIVER VITH+ VITHVIC Positive going differential voltage threshold Negative going differential voltage threshold Common mode input voltage Input capacitance TEST CONDITIONS UNIT
TIMING REQUIREMENTS
-40°C 85°C, +VBD (unless otherwise noted)
PARAMETER SAMPLING CONVERSION RELATED tacq tcnv Acquisition time Conversion time Pulse duration, CONVST high Pulse duration, CONVST Delay time, CONVST rising edge sample start Delay time, CONVST falling edge conversion start Delay time, CONVST falling edge busy high +VBD +VBD +VBD +VBD Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Table Figure Figure Table Figure Table Figure Figure Table Figure Figure Table UNIT
Delay time, conversion busy Pulse duration, CSTART high
Pulse duration, CSTART
Delay time, CSTART rising edge sample start
Delay time, CSTART falling edge conversion start +VBD
16.5 15.5
Delay time, CSTART falling edge busy high
+VBD
RELATED td10 td11 td12 td13 td14 td15 Delay time, falling edge while BUS_BUSY high Delay time, falling edge while SYNC_O 3-state condition (for device with LAT_Y/N pulled low) +VBD +VBD +VBD +VBD 4*tCLK 4*tCLK +VBD +VBD +VBD +VBD 4*tCLK- 4*tCLK- 4*tCLK- 4*tCLK- tCLK 5*tCLK 5*tCLK Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Delay time, pre_conversion (point SYNC_O 3-state condition Delay time, pre_conversion (point BUS_BUSY high Delay time, conversion phase SYNC_O high Delay time, falling edge while SYNC_O high Pulse duration, device latency mode Delay time, CLK_O rising edge data valid Delay time, BUS_BUSY SYNC_O high daisy chain mode indicating receiving device output data +VBD
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TIMING REQUIREMENTS (continued)
-40°C 85°C, +VBD (unless otherwise noted)
PARAMETER UNIT Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
td16 tpd1 td17 td18 td19
Delay time, CLK_O SYNC_O 3-state
Propagation delay time, SYNC_I SYNC_O daisy chain mode Delay time, SYNC_O 3-state BUS_BUSY cascade mode. Delay time, rising edge BUS_BUSY high device with LAT_Y/N Delay time, point indicating clear 3-state release BUSY falling edge Rise time, differential LVDS output signal Fall time, differential LVDS output signal frequency (serial data rate) +VBD +VBD +VBD +VBD
0.5*tCLK 40.5
td20 td21 td22 td23 td24
Delay time, from falling edge 3-state Delay time, from falling edge device powerdown Delay time, from rising edge device powerup Settling time, internal reference after first three conversions Delay time, CONVST falling edge start restricted zone start data read cycle Delay time, CONVST falling edge restricted zone start data read cycle
Figure Figure Figure Figure Figure Figure Figure Figure Figure
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DEVICE INFORMATION
PACKAGE (TOPVIEW)
MODE_C/D LAT_Y/N CONVST
REFM
REFM
CLK_I/E
AGND
BYTE
REFIN REFOUT AGND AGND AGND AGND
BUS_BUSY BUSY BDGND +VBD SYNC_O SYNC_O CLK_O CLK_O
(M2+) (M2-) CLK_I
CLK_I
AGND
AGND
SYNC_I
CSTART+
CSTART-
internal connection
TERMINAL FUNCTIONS
TERMINAL NAME REFM REFIN REFOUT ANALOG PINS Reference ground. Connect analog ground plane. Reference (positive) input. Decouple with REFM using 0.1-µF bypass capacitor 1-µF storage capacitor. Internal reference output. Short REFIN when internal reference used. connect REFIN when external reference used. Always decouple with AGND using 0.1-µF bypass capacitor. Noninverting analog input channel Inverting analog input channel LVDS PINS CSTART+ CSTART- Device sample convert control input. Device enters sample phase with rising edge CSTART conversion phase starts with falling edge CSTART (provided other conditions satisfied). CSTART when CONVST input used. DESCRIPTION
LVDS inputs outputs differential with signal+ signal- lines. Whenever only 'signal' mentioned refers signal+ line signal- line compliment. example CLK_O refers CLK_O+.
SYNC_I
AGND
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DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL NAME SYNC_I SYNC_I- SDI+ SDI- CLK_I+ CLK_I- CLK_O- CLK_O+ SDO- SDO+ SYNC_O SYNC_O CONVST BYTE MODE_C/D CLK_I/E LAT_Y/N BUSY BUS_BUSY Dasiy Chain DESCRIPTION Connect previous device SYNC_O with same polarity, while device selected operate daisy chain mode.
Mode (valid cascade mode only). CLK_O available while M1=1 (LVDS) pulled +VBD grounded (AGND). CLK_O goes 3-state when (LVDS) Cascade grounded (AGND) pulled +VBD. allow these pins float. Daisy Chain Serial data input. Connect previous device with same polarity, while device selected operate daisy chain mode.
Mode (valid cascade mode only). Doubles LVDS current while (LVDS) pulled +VBD grounded (AGND). LVDS current normal (3.4 typ) when Cascade (LVDS) grounded (AGND) pulled +VBD. allow these pins float. Serial external clock input. CLK_I/E (pin select external clock source. Serial clock out. Data latched rising edge CLK_O captured next falling edge. Serial data out. Data latched rising edge CLK_O with first format. Synchronizes data frame.
CMOS PINS Chip select, active signal. LVDS except CLK_O 3-state this high. CMOS equivalent CSTART input. functionality same CSTART input. CONVST when CSTART input used. Controls data frame duration. frame duration CLKs BYTE CLKs BYTE Active input, acts device power down. Selects mode while high. Device enters state conversion remains until next acquisition phase begins. Selects cascade (MODE_C/D daisy chain mode (MODE_C/D Selects source clock. CLK_I/E selects internally generated clock with 200-MHz frequency. CLK_I/E selects CLK_I clock. Controls data read with latency (LAT_Y/N without latency ((LAT_Y/N essential LAT_Y/N first device daisy chain cascade. Active high signal, indicates conversion progress. Data read request device, also acts hand shake signal daisy chain cascade operation. Status output. Indicates that being used device. Connect next device daisy chain cascade operation. POWER SUPPLY PINS Analog power supply LVDS input buffer power supply.
AGND +VBD BDGND
Analog ground pins. Short analog ground plane below device. Digital power supply CMOS digital inputs CMOS, LVDS outputs. Digital ground digital inputs outputs. Short analog ground plane below device.
duration from first rising edge SYNC_O second rising edge SYNC_O data frame. data frame duration CLKs BYTE CLKs BYTE
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DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL NAME DESCRIPTION CONNECTED PINS connection pins
Table Device Configuration Various Modes Operation
DEVICE PINS RECOMMENDED LOGIC LEVELS OPERATION MODE MODE_C/D CLK_I/E LAT_Y/N COMMENTS REFERENCE FIGURES SAMPLING CONVERSION Recommended configuration LVDS Single device comments comments SYNC_I logic terminal AGND terminal +VBD SYNC_I logic terminal AGND terminal +VBD Maximum devices supported MSPS with 200-MHz Figures 5,6,7 more details Figures 3,4,11 6,12 more details LVDS DATA READ Figures 5,6,8 more details
+VBD
AGND
AGND
+VBD
Multiple devices daisy chain
Device last device Device last device
comments
comments
comments +VBD AGND
comments AGND +VBD
Multiple devices cascade
LVDS +VBD LVDS AGND
LVDS AGND +VBD
Maximum devices supported MSPS
Figures 3,4,14 6,15 more details
LVDS
Specified polarity suitable 100- differential load across LVDS outputs. However, polarity reversed double output current order support 100- loads both ends transmission lines, resulting load.
DETAILED DESCRIPTION SAMPLE CONVERT
sampling conversion process controlled CSTART (LVDS) CONVST (CMOS) signal. Both signals functionally identical. following diagrams show control with CONVST. rising edge CONVST CSTART) starts sample phase, conversion completed device wait state. Figure shows case when device conversion phase rising edge CONVST. this case, sample phase starts immediately conversion phase there wait state.
CONVST
BUSY
Wait Sample Phase tacq Conversion Phase tcnv Wait
Figure Sample Convert With Wait (Less Than MSPS Throughput)
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DETAILED DESCRIPTION (continued)
CONVST
less than avoid device entering wait state
BUSY Sample Phase tacq Conversion Phase tcnv
Sample Phase
Figure Sample Convert With Wait Back Back MSPS Throughput) device ends sample phase enters conversion phase falling edge CONVST (CSTART). high level BUSY output indicates ongoing conversion. device conversion time fixed. falling edge CONVST (CSTART) during conversion phase aborts ongoing conversion. data read after conversion abort fetches invalid data. Valid data only available after sample phase conversion phase completed. timing diagram control with CSTART similar Figure Figure Table shows equivalent timing control with CONVST CSTART. Table CONVST CSTART Timing Control
TIMING CONTROL WITH CONVST TIMING CONTROL WITH CSTART
DATA READ OPERATION
ADS8413 supports 200-MHz serial LVDS interface data read operation. three signal LVDS interface (SDO, CLK_O, SYNC_O) well suited high-speed data transfers. application with single device multiple devices implemented with daisy chain cascade configuration. following sections discuss data read timing when single device used. DATA READ SINGLE DEVICE (See Table Device Configuration) single device, there possible read cycle starts: data read cycle start during wait sample phase data read cycle start conversion phase. Read cycle conditions change depending MODE selection. Figure explains data read cycle. details read frame start with previous listed conditions read cycle with MODE selection explained Figure Figure Figure Figure respectively.
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Figures
Figures
SYNC_O CLK_O
BUSY
Figure Data Read With BYTE shown Figure data read cycle initiated with falling edge device wait sample phase. device releases LVDS (SYNC_O, SDO) from 3-state sets BUS_BUSY high start read cycle. SYNC_O cycle clocks wide (rising edge rising edge) BYTE held used synchronize data frame. clock count begins with first CLK_O falling edge after SYNC_O rising edge. latched second rising edge (2R) each subsequent data latched rising edge clock. receiver shift data bits falling edges clock. next rising edge SYNC_O coincides with 16th rising edge clock. latched 17th rising edge clock. receiver latch de-serialized 16-bit word 18th rising edge (18R, second rising edge after SYNC_O rising edge). high during data read 3-states SYNC_O SDO. These signals remain 3-state until start next data read cycle. DATA READ BYTE MODE Byte mode selected setting BYTE this mode allowed condition listed Table Figure shows data read operation byte mode.
SYNC_O CLK_O
BUSY
Figure Data Read Timing Diagram with BYTE Similar Figure data read cycle initiated with falling edge device wait sample phase. device releases LVDS (SYNC_O, SDO) from 3-state sets BUS_BUSY high start read cycle. SYNC_O cycle clocks wide (rising edge rising edge) BYTE held high used synchronize data frame. clock count begins with first CLK_O falling edge after SYNC_O rising edge. latched second rising edge (2R) each subsequent data latched rising edge clock. receiver shift data bits falling edges clock. next rising edge SYNC_O coincides with rising edge clock. latched rising edge clock. receiver latch de-serialized higher byte 10th rising edge (10R, second rising edge after SYNC_O rising edge). de-serialized lower byte latched 18th rising edge (18R).
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high during data read 3-states SYNC_O SDO. These signals remain 3-state until start next data read cycle. DATA READ CYCLE START DURING WAIT SAMPLE PHASE shown Figure falling edge with device wait sample phase, triggers start read cycle. cycle starts when BUS_BUSY goes high SYNC_O, released from 3-state. SYNC_O start rises high level td13 after falling edge shown Figure shifted rising edge clock (2R). Other details about data read cycle discussed previous section (see Figure
td13 BUSY
BUS_BUSY CLK_O
SYNC_O td14 SDO_O
Figure Start Data Read Cycle with with Device Wait Sample Phase DATA READ CYCLE START CONVERSION PHASE (Read Without Latency, Back-to-Back) This mode optimized data read immediately after conversion phase ensures data read complete before sample while running MSPS. Point Figure indicates 'pre_conversion_end'; occurs td19 before falling edge BUSY [(td2 tcnv td4) td19] after falling edge CONVST. read cycle initiated point issued before point while low. Alternately, held low. start read cycle, BUS_BUSY rises high level LVDS outputs released from 3-state. rising edge SYNC_O occurs td12 after conversion end. shown Figure shifted rising edge clock (2R). Other details about data read cycle discussed previous section (see Figure
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Conversion Phase td19 RD_REQ (Int) td11 BUSY td10 BUS_BUSY CLK_O td12 SYNC_O td14 SDO_O Conversion
Figure Start Data Read Cycle with Conversion DATA READ CYCLE (With MODE data read cycle ends after bits have been serially latched out. Figure shows timing falling edge BUS_BUSY rising edge SYNC_O with respect SDO. SYNC_O rises 16th rising edge CLK_O. shown Figure Figure shifted rising edge CLK_O. Therefore, LSB-1 shifted 16th rising edge CLK_O.
CONVST
BUS_BUSY td15 SYNC_O
CLK_O
td16
Figure Data Read Cycle with MODE
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next rising edges CLK_O shown Figure latched out, SYNC-O 3-state. Note that BUS_BUSY falls td15 before rising edge SYNC_O when MODE Care must taken allow LVDS usage other device until read cycle (td15 2/fclk td16) after falling edge BUS_BUSY. DATA READ CYCLE (With MODE data read cycle ends after bits have been serially latched out. Figure shows timing falling edge BUS_BUSY rising edge SYNCO with respect SDO. SYNC_O rises 16th rising edge CLK_O. shown Figure Figure shifted rising edge CLK_O. Therefore, LSB-1 shifted 16th rising edge CLK_O.
CONVST
BUS_BUSY td17 SYNC_O
CLK_O
td16
Figure Data Read Cycle with MODE next rising edges CLK_O shown Figure latched SYNC_O 3-state. cascade mode (with MODE unlike daisy chain mode BUS_BUSY falling edge occurs after LVDS outputs 3-state. BUS_BUSY falling edge allow LVDS usage other device. RESTRICTIONS READ CYCLE START
CONVST td23 td24 BUSY
Read cycle allowed start this region
Figure Read Cycle Restriction Region start data read cycle allowed region bound td23 td24. Previous conversion results available data read cycle start before this region, current conversion results available read cycle start after this region.
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MULTIPLE DEVICES DAISY CHAIN CASCADE
Multiple devices connected either daisy chain cascade configuration. following sections describes detailed timing diagrams electrical connections. ADS8413 provides hand-shake signals required both these modes. CONVST CSTART only external signal needed operation. DAISY CHAIN Figure shows first devices daisy chain. signals shown double lines LVDS others CMOS. Daisy chain mode selected setting MODE_C/D first device chain identified selecting LAT_Y/N
Device Table External Clock (Optional) Table Last_Device BUS_BUSY CLK_I SYNC_I CLK_0 SYNC_0 CLK_I SYNC_I Device CLK_0 SYNC_0
Next Device Receiver
BUS_BUSY CLK_I/E LAT_Y/N
CLK_I/E MODE_C/D
BUS_BUSY LAT_Y/N
MODE_C/D
From Controller
Figure Connecting Multiple Devices Daisy Chain other devices chain LAT_Y/N Table more details device configurations. SDO, CLK_O, SYNC_O device connected SDI, CLK_I, SYNC_I device. SDO, CLK_O, SYNC_O last device chain receiver. BUS_BUSY device connected device Finally, BUS_BUSY last device chain connected device This ensures necessary handshake seamlessly propagate data devices through chain also allowed device TIMING DIAGRAMS DAISY CHAIN OPERATION conversion speed devices chain must selected such that: 1/conversion speed read startup delay n*(data frame duration) td16 Read startup delay (td19 td4) td12 2/fCLK Data frame duration 16/fCLK Note that necessary devices chain sample data simultaneously. devices must operate with same exact conversion speed.
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CONV CONVST
Tracking
Conversion
Figure details BUS_BUSY (Last device) BUS_BUSY
16-Bit Data conversion Figure details
SYNC_O SYNC_I td18 BUS_BUSY 16-Bits conversion 16-Bits conversion
SYNC_O SYNC_I
Figure Data Read Operation Devices Daisy Chain DATA READ OPERATION power BUS_BUSY devices low. devices receive CONVST CSTART sample start conversion. first device chain starts data read cycle conversion. BUS_BUSY device (connected device goes high read cycle start. Device BUS_BUSY goes high rising edge This propagates until last device chain. Device receives CLK_I, SDI, SYNC_I from device passes these signals next device. Device (and every subsequent device chain) passes received signals output until sees falling edge (same BUS_BUSY previous device). daisy chain mode, BUS_BUSY device falls when passed previous device data followed data. falling edge BUS_BUSY occurs before rising edge SYNC_O. This indicates receiving device that previous data chain over turn output data. device outputs data from last completed conversion. BUS_BUSY last device chain back first device shown Figure device tied This makes sure that device before conversion over. chain continues with only external signal (CONVST CSTART) when held low. Every device LVDS output goes 3-state once data transfer through device been completed. going high during data read cycle device 3-states SYNC_O SDO. This halts propagation data through chain. reset this condition necessary assert high devices. read sequence starts only after devices before point shown Figure high pulse must least wide. better connect devices together avoid undesired halting daisy chain.
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BUS_BUSY td15 SYNC_O SYNC_I CLK_O CLK_I td16
BUSY_BUS CLK_O
tpd1 SYNC_O DATA
DATA
Figure Data Propagation from Device Device Daisy Chain Mode shown Figure there propagation delay tpd1 from SYNC_I SYNC_O SDO. Note that data frames devices chain appear seamless last device output. rising edge SYNC_O occurs interval clocks clocks BYTE mode); this used data frame sync. deserializer output last device shift data every falling edge clock latch parallel 16-bit word second rising edge CLK_O (shown 18R) after every rising edge SYNC_O. CASCADE Figure shows cascade connection. signals shown with double lines LVDS others CMOS. Cascade mode selected setting MODE_C/D Similar daisy chain, first device chain identified selecting LAT_Y/N other devices chain LAT_Y/N Table more details device configuration. SDO, CLK_O, SYNC_O connected common bus. This means only device occupies time, while LVDS drivers other devices 3-state. Unlike SYNC_O, clock cannot switched from device device receiver requires continuous clock. only device outputs clock CLK_O other devices 3-stated appropriately setting M1as listed Table
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Device External Clock CLK_I CLK_0 SYNC_0 BUS_BUSY Last Device BUS_BUSY M1+,M2- CLK_I/E, LAT_Y/N,
Receiver
MODE_C/D M1-,M2+ From Controller Device CLK_I CLK_0 SYNC_0 BUS_BUSY M1-,M2-,LAT_Y/N M1+,M2+, MODE_C/D CLK_I/E From Controller Next Device
Figure Cascade Connection CLOCK SOURCE this mode very critical control skew between three LVDS signals. recommended external clock mode only devices cascade. BUS_BUSY device connected device Finally BUS_BUSY last device chain connected device This ensures necessary handshake control sequence data reads devices cascade. also allowed device TIMING DIAGRAMS CASCADE OPERATION conversion rate devices cascade must selected such that: 1/conversion speed first device read cycle duration next device read cycle duration First device read cycle duration read startup delay_1 data frame duration (td16 td17) Next device read cycle duration read startup delay_n data frame duration (td16 td17) Read startup delay_1 (td19 td12) 2/fclk Read startup delay_n (td13 2/fclk) Data frame duration 16/fclk Note that necessary that devices chain sample data simultaneously. devices must operate with same exact conversion speed.
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CONV CONVST
Tracking
Conversion
Figure details
BUS_BUSY (Last device) Figure details BUS_BUSY td18 BUS_BUSY
16-Bits conversion
16-Bits conversion
SYNC_O
SYNC_O
SYNC_O
Figure Data Read Operation Devices Cascade Mode DATA READ OPERATION power BUS_BUSY devices low. devices receive CONVST CSTART sample start conversion. first device starts data read cycle conversion. BUS_BUSY device (connected device goes high read cycle start, indicating that wants occupy bus. Device BUS_BUSY goes high rising edge This propagates until last device. Device BUS_BUSY goes after outputs data, this time SYNC_O device 3-state. falling edge BUS_BUSY next device) indicates next device that turn output data. next device outputs data from last completed conversion. BUS_BUSY last device goes SYNC_O 3-state after outputs data. BUS_BUSY last device back first device shown Figure also tied device This ensures that device before conversion over. data read sequence continues with only external signal, CONVST CSTART, when device, high during data read cycle 3-states SYNC_O device halts data read sequence. reset this condition necessary assert high devices. read sequence starts only after devices before point shown Figure high pulse must least wide. better connect devices together avoid undesired halting data read sequence.
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BUS_BUSY td17 SYNC_O
CLK_O
td16
BUSY_BUS SYNC_O
td13
Figure Device Read Cycle Device Read Cycle Start Unlike daisy chain, data frames devices cascade seamless there loss time between device 3-state other device data valid wakeup time from 3-state clock phase shift between SYNC data (see Figure details). result, number data frames second this mode less than daisy chain mode. Also, maximum devices cascaded same bus. But, power device considerably lower cascade compared daisy chain each device LVDS goes 3-state after data transfer. deserializer output last device shift data every clock falling edge, latch parallel 16-bit word second CLK_O rising edge (shown 18R) after every SYNC_O rising edge.
THEORY OPERATION
ADS8413 member high-speed successive approximation register (SAR) analog-to-digital converters family. architecture based charge redistribution, which inherently includes sample/hold function. device includes built-in conversion clock, internal reference, 200-MHz LVDS serial interface. device operated maximum throughput MSPS. ANALOG INPUT analog input provided input pins: -IN. When conversion initiated, voltage difference between these pins sampled internal capacitor array. While conversion progress, both inputs disconnected from internal function.
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THEORY OPERATION (continued)
ADS8413
AGND
AGND
Figure Simplified Input Circuit When converter enters hold mode, voltage difference between inputs captured internal capacitor array. input current analog inputs depends upon number factors: sample rate, input voltage, signal frequency, source impedance. Essentially, current into ADS8413 charges internal capacitor array during sample period. After this capacitance been fully charged, there further input current (this happen when signal moving continuously). source analog input voltage must able charge input capacitance better than 16-bit settling level with step input within acquisition time device. calculation, step size selected equal maximum voltage difference between consecutive samples maximum signal frequency (see TYPICAL ANALOG INPUT CIRCUIT section). When converter goes into hold mode, input impedance greater than
49.9 VCC+ THS4031 THS4031 REFM REFIN ADS8413 REFM
INPUT+
NULL NULL VCC- 49.9 VCC+
INPUT-
NULL NULL VCC-
Figure Typical Analog Input Schematic
ADS8413
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SLAS490 OCTOBER 2005
THEORY OPERATION (continued)
Care must taken regarding absolute analog input voltage. maintain linearity converter, both inputs should within limits specified. Outside these ranges, converter linearity meet specifications. Care should taken ensure that same impedance respective sources. this observed, inputs could have different setting times. This result offset error, gain error, linearity error which changes with temperature input voltage. REFERENCE ADS8413 built-in 4.096-V (nominal value) reference. ADS8413 also operate with external reference. When internal reference used, (REFOUT) should connected (REFIN), 0.1-µF decoupling capacitor 1-µF storage capacitor must connected between (REFOUT) pins (REFM) (see Figure 18). internal reference converter buffered.
ADS8413 REFOUT REFM AGND REFIN
Figure Using Internal Reference REFIN also internally buffered. This eliminates need high bandwidth buffer onboard drive reference saves system area power. When external reference used, reference must noise, which achieved additional bypass capacitor from REFIN REFM (see Figure 19). REFM must connected analog ground plane.
ADS8413 REFOUT REF3040 AGND REFM AGND REFIN
Figure Using External Reference DIGITAL INTERFACE TIMING CONTROL Refer timing diagrams TIMING REQUIREMENTS table detailed information. SAMPLING CONVERSION Sampling conversion controlled CONVST pin. higher noise performance essential have jitter falling edge CONVST. device uses internally generated clock conversion, hence fixed conversion time.
ADS8413
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THEORY OPERATION (continued)
READING DATA ADS8413 includes high-speed LVDS serial interface. discussed prior, external clock (CLK_I, less than MHz) internal 200-MHz clock used data read. device outputs data two's compliment format. Table lists ideal output codes. Table Ideal Input Voltages Output Codes
DESCRIPTION Full-scale range Least significant (LSB) Full scale Midscale Midscale 1LSB -Full scale 2(+Vref) 2(+Vref)/216 Vref -Vref ANALOG VALUE (+IN (-IN)) 7FFF 0000 FFFF 8000 CODE
ADS8413
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SLAS490 OCTOBER 2005
restrictions read cycle start described section RESTRICTIONS READ CYCLE START (see Figure
ADS8413 SDO+ BYTE SDO- SYNC_O+ SYNC_O- CLK_O+ CLK_O- MCI- LCI- MCI+ LCI+ CO_EN D15-D6 D9-D0 SN65LVDS152
SN65LVDS152 LCI+ D5-D0 D9-D4 LCI- MCI+
MCI- CO_EN
Figure 16-Bit Data De-Serialization While BYTE
ADS8413
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SLAS490 OCTOBER 2005
ADS8413 +VBD SDO+ BYTE SDO- SYNC_O+ SYNC_O- CLK_O+ CLK_O-
SN65LVDS152 LCI+ D7-D0 D9-D2 LCI- MCI+
MCI- CO_EN
Figure 8-Bit Data De-Serialization While BYTE Data POWER SAVING converter provides power saving modes, full powerdown nap. Table lists information activation/deactivation resumption times both modes. Table Powerdown Modes
POWERDOWN MODE Normal operation Full powerdown (internal reference) Full powerdown (external reference) powerdown Refer DATA READ OPERATION section Stated Stated stated POWER CONSUMPTION ACTIVATED ACTIVATION TIME td21 td21 RESUME POWER Sample start
FULL POWERDOWN MODE Full powerdown mode activated deasserting device takes td21 reach full powerdown state. device return normal mode from full powerdown asserting powerup sequence different device operation with internal reference external reference shown Figure Figure
ADS8413
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SLAS490 OCTOBER 2005
Invalid Conversion
Valid Conversion
td20
td22 BUSY td21 VREF
Full
Full
Figure Device Full Powerdown Powerup Sequence with Device Operation Internal Reference Mode When internal reference used, conversion started td22 after asserting After first three conversions, required reference voltage settling trimmed value. conversions after this provide data specified accuracy.
td20 td22 BUSY td21 Invalid Conversion Valid Conversion
Full
Full
Figure Device Full Powerdown Powerup Sequence with Device Operation External Reference Mode When external reference used, conversion started td22 after asserting first three conversions required internal circuit stabilization. conversions after this provide data specified accuracy. MODE device automatically enters state conversion, remains state until start sampling phase. minimum required after sample start device come state perform normal sampling. minimum sampling time needed mode tacq(min) maximum conversion speed mode MHz.
ADS8413
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SLAS490 OCTOBER 2005
LAYOUT
optimum performance, care should taken with physical layout ADS8413 circuitry. device offers single-supply operation, often used close proximity with digital logic, FPGA, microcontrollers, microprocessors, digital signal processors. more digital logic present design higher switching speed, more difficult achieve good performance from converter. basic architecture sensitive glitches sudden changes power supply, reference, ground connections, digital inputs that occur just prior sampling just prior latching output analog comparator during conversion phase. Such glitches might originate from switching power supplies, nearby digital logic, high power devices. Noise during sampling later half conversion must kept minimum (the former half conversion very sensitive since device uses proprietary error correction algorithm correct transient errors during this period). degree error digital output depends reference voltage, layout, exact timing external event. average, device draws very little current from external reference reference voltage internally buffered. reference voltage external originates from amp, make sure that drive bypass capacitor capacitors without oscillation. 0.1-µF bypass capacitor 1-µF storage capacitor recommended from REFIN directly REFM. AGND BDGND pins should connected clean ground point. cases, this should analog ground. Avoid connections that close grounding point microcontroller digital signal processor. required, ground trace directly from converter power supply entry point. ideal layout consists analog ground plane dedicated converter associated analog circuitry. with AGND connections, should connected +5-V power supply plane that separate from connection +VBD digital logic until they connected power entry point onto PCB. Power should clean well bypassed. 0.1-µF ceramic bypass capacitor should placed close device possible. Table placement capacitor. addition 0.1-µF capacitor, 1-µF capacitor recommended. some situations, additional bypassing required, such 100-µF electrolytic capacitor even filter made inductors capacitors; designed essentially low-pass filter +5-V supply, thus removing high frequency noise. Table Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE SUPPLY PINS CONVERTER ANALOG SIDE CONVERTER DIGITAL SIDE (44,45)
Pair pins require shortest path decoupling (9,10) (16,17) (20,21) (22,23) (26,27 25,26) capacitors (36,37)
TYPICAL CHARACTERISTICS
HISTOGRAM CODE SPREAD CENTER CODE)
120000 108126 100000 25°C, MSPS, Vref 4.096
Number Hits 120000 100000
HISTOGRAM CODE SPREAD WITH CLOSE
140000
EFFECTIVE NUMBER BITS FREE-AIR TEMPERATURE
15.25 ENOB Effective Number Bits Bits 15.2 15.15 15.1 15.05 14.95 14.9 14.85 14.8 14.75 kHz, MSPS, Vref 4.096
25°C, MSPS, Vref 4.096
121865
80000 Number Hits
80000 60000
60000
40000
40000 30724 11013 65504 65505 65506 Code 65507 65508
20721 20000 32763 32764 32765 Code 32766 32767 8436
20000
Free-Air Temperature
Figure
Figure
Figure
ADS8413
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SLAS490 OCTOBER 2005
TYPICAL CHARACTERISTICS (continued)
SIGNAL NOISE DISTORTION FREE-AIR TEMPERATURE
SINAD Signal Noise Distortion 92.8 92.6 92.4 92.2 91.8 91.6 91.4 91.2 Free-Air Temperature kHz, MSPS, Vref 4.096 92.8 Signal-to-Noise Ratio 92.6 92.4 92.2 91.8 91.6 91.4 91.2 Free-Air Temperature
SFDR Spurious Free Dynamic Range
SIGNAL NOISE RATIO FREE-AIR TEMPERATURE
SPURIOUS FREE DYNAMIC RANGE FREE-AIR TEMPERATURE
-105
kHz, MSPS, Vref 4.096
-106 -107 -108 -109 -110 -111 -112 -113 -114 -115
kHz, MSPS, Vref 4.096
Free-Air Temperature
Figure TOTAL HARMONIC DISTORTION FREE-AIR TEMPERATURE
-100
ENOB Effective Number Bits Bits
Figure EFFECTIVE NUMBER BITS INPUT FREQUENCY
SINAD Signal Noise Distortion 25°C, MSPS, Vref 4.096 25°C, MSPS, Vref 4.096
Figure SIGNAL NOISE DISTORTION INPUT FREQUENCY
Total Harmonic Distortion
-101 -102 -103 -104 -105 -106 -107 -108 -109 -110
kHz, MSPS, Vref 4.096
Free-Air Temperature
1000
Input Frequency
Input Frequency
1000
Figure
Figure
Figure
ADS8413
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SLAS490 OCTOBER 2005
TYPICAL CHARACTERISTICS (continued)
SIGNAL NOISE RATIO INPUT FREQUENCY
25°C, MSPS, Vref 4.096
SFDR Spurious Free Dynamic Range
SPURIOUS FREE DYNAMIC RANGE INPUT FREQUENCY
TOTAL HARMONIC DISTORTION INPUT FREQUENCY
Total Harmonic Distortion 25°C, MSPS, Vref 4.096
Signal-to-Noise Ratio
25°C, MSPS, Vref 4.096
-100 -105 -110 -115
-100
-105
-110
-115
-120
Input Frequency
1000
Input Frequency
1000
Input Frequency
1000
Figure OFFSET ERROR SUPPLY VOLTAGE
0.08 0.06 Offset Error
Gain Error 0.01 0.009 0.008 0.007 0.006 0.005 0.004 0.003 25°C, MSPS, Vref 4.096
Figure GAIN ERROR SUPPLY VOLTAGE
0.15 0.13 0.11 Offset Error 0.09 0.07 0.05 0.03 0.01
4.85 4.95 5.05 5.15 Supply Voltage 5.25
Figure OFFSET ERROR FREE-AIR TEMPERATURE
MSPS, Vref 4.096
0.04 0.02 -0.02 -0.04 -0.06 -0.08 -0.1 4.75 25°C, MSPS, Vref 4.096
0.002 0.001 4.75
4.85
4.95
5.05
5.15
5.25
Supply Voltage
-0.01
Free-Air Temperature
Figure GAIN ERROR FREE-AIR TEMPERATURE
0.015 MSPS, Vref 4.096
Figure POWER DISSIPATION SAMPLE RATE
Figure POWER DISSIPATION SUPPLY VOLTAGE
25°C, MSPS, Vref 4.096
Normal Power Dissipation
Power Dissipation
0.01
Gain Error
0.005
-0.005
-0.01
25°C, Vref 4.096
-0.015
Free-Air Temperature
Sample Rate MSPS
4.75
4.85
4.95
5.05
5.15
5.25
Supply Voltage
Figure
Figure
Figure
ADS8413
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SLAS490 OCTOBER 2005
TYPICAL CHARACTERISTICS (continued)
POWER DISSIPATION FREE-AIR TEMPERATURE
Power Dissipation MSPS, Vref 4.096
DIFFERENTIAL NONLINEARITY FREE-AIR TEMPERATURE
MSPS, Vref 4.096
Integral Nonlinearity -0.5 -1.5
INTEGRAL NONLINEARITY FREE-AIR TEMPERATURE
MSPS, Vref 4.096
Differential Nonlinearity
-0.5
Free-Air Temperature
Free-Air Temperature
Free-Air Temperature
Figure POSITIVE INTEGRAL NONLINEARITY DISTRIBUTION OVER UNITS
Figure NEGATIVE INTEGRAL NONLINEARITY DISTRIBUTION OVER UNITS
4.112 4.108 25°C, MSPS, Vref 4.096
Figure INTERNAL REFERENCE OUTPUT SUPPLY VOLTAGE
Internal Reference Output 4.104 4.096 4.092 4.088 4.084
Number Devices
Number Devices
4.08 4.75 4.85 4.95 5.05 5.15 5.25
Integral Nonlinearity
-1.4
-1.2 -1.0 -0.8 -0.6 Integral Nonlinearity
Supply Voltage
Figure
Figure
Figure
ADS8413
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SLAS490 OCTOBER 2005
TYPICAL CHARACTERISTICS (continued)
INTERNAL REFERENCE OUTPUT FREE-AIR TEMPERATURE
4.112 4.108 Internal Reference Output 4.104 4.096 4.092 4.088 4.084 4.08 MSPS, Vref 4.096
Free-Air Temperature
Figure
LSBs -0.5 32767 Figure Typical 65535
LSBs -0.5 -1.5 32767 Figure Typical 65535
ADS8413
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SLAS490 OCTOBER 2005
TYPICAL CHARACTERISTICS (continued)
Amplitude -100 -120 -140 -160 -180
Frequency
Figure Typical
PARAMETER MEASUREMENT INFORMATION DRIVER
Driver Enable
Driver Enable Input Places)
Figure Driver Voltage Current Definitions
ADS8413
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SLAS490 OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
100% Differential Output VOD(H) VOD(L)
Figure Timing Voltage Definitions Differential Output Signal
Driver Enable Input Places) VOC(PP) VOC(SS) 49.9 Places)
Figure Test Circuit Definitions Driver Common-Mode Output Voltage
Figure Receiver Voltage Definitions
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device ADS8413IBRGZR ADS8413IBRGZRG4 ADS8413IBRGZT ADS8413IBRGZTG4 ADS8413IRGZR ADS8413IRGZRG4 ADS8413IRGZT ADS8413IRGZTG4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type
Package Drawing
Pins Package Plan 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing
Reel Reel Diameter Width (mm) (mm) 330.0 330.0 330.0 330.0 16.4 16.4 16.4 16.4
(mm)
(mm)
(mm)
(mm) 12.0 12.0 12.0 12.0
Pin1 (mm) Quadrant 16.0 16.0 16.0 16.0
ADS8413IBRGZR ADS8413IBRGZT ADS8413IRGZR ADS8413IRGZT
2500 2500
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions nominal
Device ADS8413IBRGZR ADS8413IBRGZT ADS8413IRGZR ADS8413IRGZT
Package Type
Package Drawing
Pins
2500 2500
Length (mm) 333.2 333.2 333.2 333.2
Width (mm) 345.9 345.9 345.9 345.9
Height (mm) 28.6 28.6 28.6 28.6
Pack Materials-Page
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