SLAS451 JUNE 2005 16-BIT, 600-kHz, FULLY DIFFERENTIAL PSEUDO-BIPO

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SLAS451 JUNE 2005 16-BIT, 600-kHz, FULLY DIFFERENTIAL PSEUDO-BIPO

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ADS8372
SLAS451 JUNE 2005
16-BIT, 600-kHz, FULLY DIFFERENTIAL PSEUDO-BIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE REFERENCE
FEATURES
600-kHz Sample Rate ±0.35 Typ, ±0.75 ±0.25 Typ, ±0.5 16-Bit SINAD 93.5 SFDR High-Speed Serial Interface Onboard Reference Buffer Onboard 4.096-V Reference Pseudo-Bipolar Input, ±4.2 Onboard Conversion Clock Zero Latency Wide Digital Supply Power During Mode During Power Down 28-Pin Package Compatible With 18-Bit ADS8382
APPLICATIONS
Medical Instruments Optical Networking Transducer Interface High Accuracy Data Acquisition Systems Magnetometers
DESCRIPTION
ADS8372 high performance 16-bit, 600-kHz converter with fully differential, pseudo-bipolar input. device includes 16-bit capacitor-based converter with inherent sample hold. ADS8372 offers high-speed CMOS serial interface with clock speeds MHz. ADS8372 available lead package characterized over industrial -40°C 85°C temperature range.
High Speed Converter Family
Type/Speed 18-Bit Pseudo-Diff 18-Bit Pseudo-Bipolar, Fully Diff 16-Bit Pseudo-Diff 16-Bit Pseudo-Bipolar, Fully Diff 14-Bit Pseudo-Diff 12-Bit Pseudo-Diff ADS7886 ADS8383 ADS8381 ADS8380 ADS8382 ADS8370 ADS8372 ADS8371 ADS8401/05 ADS8402/06 ADS7890 ADS8411 ADS8412 ADS7891 ADS7881 1.25
REFIN 4.096-V Internal Reference
CDAC Comparator
Output Latches 3-State Drivers
SCLK
REFOUT
Clock
Conversion Control Logic
CONVST BUSY
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2005, Texas Instruments Incorporated
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SLAS451 JUNE 2005
These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
ORDERING INFORMATION
MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATUR RANGE ORDERING INFORMATION TRANSPORT MEDIA QUANTITY Small Tape Reel Tape Reel 2500 Small Tape Reel Tape Reel 2500
ADS8372I
±1.5
ADS8372IRHPT -40°C 85°C ADS8372IRHPR ADS8372IBRHPT -40°C 85°C ADS8372IBRHPR
ADS8372IB
±0.75
±0.5
most current package ordering information, Package Option Addendum this document, website www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
UNIT AGND Voltage AGND AGND +VBD BDGND Digital input voltage BDGND Digital input voltage Operating free-air temperature range, Storage temperature range, Tstg Junction temperature max) package Lead temperature, soldering Power dissipation thermal impedance Vapor phase sec) Infrared sec) -0.3 -0.3 -0.3 -0.3 -0.3 +VBD +0.3 -40°C 85°C -65°C 150°C 150°C TA)/JA 86°C/W 215°C 220°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
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SPECIFICATIONS
-40°C 85°C, +VBD +VBD +2.7 using internal external reference, fSAMPLE kHz, unless otherwise noted. (All performance parameters valid only after device properly resumed from power down, Table
PARAMETER ANALOG INPUT Full-scale input voltage Absolute input voltage Input common mode range Sampling capacitance (measured between AGND AGND) Input leakage current SYSTEM PERFORMANCE Resolution missing codes Integral linearity Differential linearity Offset error Offset temperature drift Gain error Gain error temperature drift CMRR Common-mode rejection ratio Noise PSRR Power supply rejection ratio [+IN (-IN)]/2 mVp-p Vref/2 00000H output code 10000H output code
TEST CONDITIONS
ADS8372IB
ADS8372I
UNIT
(-IN)
-Vref -0.2 -0.2 (Vref/2) -0.2
Vref Vref Vref (Vref/2) +0.2
-Vref -0.2 -0.2 (Vref/2) -0.2
Vref Vref Vref (Vref/2) +0.2
Quiet zones observed Quiet zones observed Quiet zones observed Quiet zones observed -0.75 -0.5 0.75 ±0.35 ±0.75 ±0.25 ±0.5 ±0.25 ±0.2 -0.075 ±1.5 0.075 -0.15 0.75 -1.5 0.75 -1.5
Bits Bits bit) bit) ppm/°C 0.15 ppm/°C
±0.2
±1.5
SAMPLING DYNAMICS Conversion time Acquisition time Throughput rate Aperture delay Aperture jitter Step response Overvoltage recovery
1.16
1.16
Ideal input span; does include gain offset error. means least significant bit. Measured using analog input circuit Figure digital stimulus Figure Figure reference voltage 4.096 This endpoint INL, best fit. Measured using external reference source does include internal reference voltage error drift. Defined sampling time necessary settle initial error 2Vref sampling capacitor final error 16-bit level. Measured using input circuit Figure
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SPECIFICATIONS (continued)
-40°C 85°C, +VBD +VBD +2.7 using internal external reference, fSAMPLE kHz, unless otherwise noted. (All performance parameters valid only after device properly resumed from power down, Table
PARAMETER DYNAMIC CHARACTERISTICS Vp-p Total harmonic distortion Vp-p Vp-p Vp-p Signal-to-noise ratio Vp-p Vp-p Vp-p SINAD Signal-to-noise distortion Vp-p Vp-p Vp-p SFDR Spurious free dynamic range -3dB Small signal bandwidth REFERENCE INPUT Vref Reference voltage input range Resistance INTERNAL REFERENCE OUTPUT Vref Reference voltage range Source current Line regulation Drift DIGITAL INPUT/OUTPUT Logic family CMOS High level input voltage level input voltage High level output voltage level output voltage loads loads +VBD -0.3 +VBD -0.6 +VBD +VBD -0.3 +VBD -0.6 +VBD IOUT 30°C Static load 4.75 5.25 IOUT 4.088 4.096 4.104 4.088 4.096 4.104 ppm/°C 4.096 4.096 Vp-p Vp-p -116 -115 93.5 93.5 93.5 93.5 -106 -116 -115 93.5 93.5 93.5 93.5 TEST CONDITIONS ADS8372IB ADS8372I UNIT
Data format complement (MSB first) POWER SUPPLY REQUIREMENTS Power supply voltage +VBD 4.75 5.25 5.25 4.75 5.25 5.25
Supply current, 600-kHz sample rate (10)
POWER DOWN ICC(PD) ICC(NAP) Supply current, power down
MODE Supply current, mode Power-up time from TEMPERATURE RANGE Specified performance
(10)
Measured using analog input circuit Figure digital stimulus Figure Figure reference voltage 4.096 Calculated first nine harmonics input frequency. vary +/-30%. This includes only current. With +VBD +VBD current typically with 10-pF load capacitance digital output pins.
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TIMING REQUIREMENTS
PARAMETER tconv tacq1 tacq2 Conversion time Acquisition time normal mode Acquisition time mode (tacq2 tacq1 td18) Quite sampling time (last toggle interface signals convert start command) Quite sampling time (convert start command first toggle interface signals) Quite conversion time (last toggle interface signals fall BUSY) Setup time, CONVST before BUSY fall Setup time, before BUSY fall (only conversion/sampling control) Setup time, CONVST before rise CONVST recognized) Hold time, after BUSY fall (only conversion/sampling control) Hold time, CONVST after rise Hold time, CONVST after fall ensure width CONVST_QUAL) CONVST pulse duration pulse duration Pulse duration, time between conversion start command conversion abort command successfully abort ongoing conversion SCLK period SCLK duty cycle tsu5 tsu6 tsu7 tsu2 tsu3 Setup time, fall before first SCLK fall Setup time, fall before rise Setup time, fall before first SCLK fall Hold time, fall after SCLK fall Hold time, fall after SCLK fall Setup time, fall before BUSY fall (only read control) Setup time, fall before BUSY fall (only read control) Hold time, fall after BUSY fall (only read control) Hold time, fall after BUSY fall (only read control) pulse duration pulse duration pulse duration reset power down unspecified pulse durations
ADS8372I/ADS8372IB 1000 1160
UNIT
FIGURE 41,42,44 45,47 40,41 41,43,44 41,42
CONVERSION SAMPLING tquiet1 tquiet2 tquiet3 tsu1 tsu2 tsu4 1000
DATA READ OPERATION tcyc 46,47 46,47 46,47 40,45 40,47 40,45 40,47 46,47 53,54
MISCELLANEOUS
input signals specified with (10% VDD) timed from voltage level (VIL VIH)/2. specifications typical -40°C 85°C, +4.75 +5.25 +VBD +2.7 +5.25 digital output signals loaded with 10-pF capacitors. CONVST_QUAL CONVST latched value (see Figure 39). Reference figure indicated only representative where timing applicable exhaustive. Quiet time zones meeting performance functionality.
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TIMING CHARACTERISTICS
PARAMETER CONVERSION SAMPLING Delay time, conversion start command conversion start (aperture delay) Delay time, conversion BUSY fall Delay time, conversion start command BUSY rise Delay time, CONVST rise sample start Delay time, fall sample start Delay time, conversion abort command BUSY fall td11 conversions 41,43 46,47 53,54 53,54 53,54 ADS8372I/ADS8372IB UNIT FIGURE
DATA READ OPERATION td12 Delay time, fall valid td15 Delay time, rise valid Delay time, BUSY fall valid high when BUSY falls) td13 Delay time, SCLK rise valid td14 Delay time, rise 3-state MISCELLANEOUS td10 Delay time, rise 3-state mode td18 Delay time, total device resume time Full power down (external reference used with without 1-µF||0.1-µF capacitor REFOUT) Full power down (internal reference used with without 1-µF||0.1-µF capacitor REFOUT) Full power down (internal/external reference used)
td11 Delay time, untrimmed circuit full power-down resume time td16 td17 Delay time, device power-down time
Delay time, trimmed internal reference settling (either turning supply resuming from full power-down mode), with 1-µF||0.1-µF capacitor REFOUT
input signals specified with (10% VDD) timed from voltage level (VIL VIH)/2. specifications typical -40°C 85°C, +4.75 +5.25 +VBD +2.7 +5.25 digital output signals loaded with 10-pF capacitors. Including td11, conversions (time cycle CONVST twice), td17.
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ASSIGNMENTS
VIEW
BUSY BDGND +VBD AGND
CONVST
SCLK
AGND AGND AGND AGND REFM REFOUT REFIN
ADS8372
AGND AGND
Note:
package thermal must soldered printed circuit board thermal mechanical performance.
TERMINAL FUNCTIONS
NAME AGND BDGND BUSY CONVST REFIN REFM REFOUT SCLK +VBD DESCRIPTION Analog ground pins. AGND must shorted analog ground plane below device. Digital ground digital inputs outputs. BDGND must shorted analog ground plane below device. Status output. This high when conversion progress. Convert start. This signal qualified with internally. Chip select Frame sync. This signal qualified with internally. Noninverting analog input channel Inverting analog input channel connection Power down. Device resets powers down when this signal high. Reference (positive) input. REFIN must decoupled with REFM using 0.1-µF bypass capacitor 1-µF storage capacitor. Reference ground. connected analog ground plane. Internal reference output. Shorted REFIN only when internal reference used. Serial clock. Data shifted onto with rising edge this clock. This signal qualified with internally. Serial data out. bits except shifted rising edge SCLK. Analog power supplies Digital power supply digital inputs outputs.
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TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE RATIO REFERENCE VOLTAGE
SINAD Signal-to-Noise Distortion +VBD kHz, 25°C +VBD kHz, 25°C
SIGNAL-TO-NOISE DISTORTION REFERENCE VOLTAGE
Signal-to-Noise
Vref Reference Voltage
Vref Reference Voltage
Figure SPURIOUS FREE DYNAMIC RANGE REFERENCE VOLTAGE
SFDR Spurious Free Dynamic Range +VBD kHz, 25°C Total Harmonic Distortion
Figure TOTAL HARMONIC DISTORTION REFERENCE VOLTAGE
-112 -113 -114 +VBD kHz, 25°C
-115 -116 -117 -118
Vref Reference Voltage
Vref Reference Voltage
Figure EFFECTIVE NUMBER BITS REFERENCE VOLTAGE
15.4 ENOB Effective Number Bits Bits +VBD kHz, 25°C ENOB Effective Number Bits Bits 15.5
Figure EFFECTIVE NUMBER BITS FREE-AIR TEMPERATURE
15.3 15.2
15.4
15.3
15.1
15.2 +VBD REFIN 4.096 kHz,
14.9 14.8 Vref Reference Voltage
15.1
Free-Air-Temperature
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE RATIO FREE-AIR TEMPERATURE
SINAD Signal-to-Noise Distortion 95.5 94.5 +VBD REFIN 4.096 kHz, 95.5 94.5 93.5 Free-Air-Temperature +VBD REFIN 4.096 kHz,
SIGNAL-TO-NOISE DISTORTION FREE-AIR TEMPERATURE
Signal-to-Noise
93.5
Free-Air-Temperature
Figure SPURIOUS FREE DYNAMIC RANGE FREE-AIR TEMPERATURE
SFDR Spurious Free Dynamic Range Total Harmonic Distortion +VBD REFIN 4.096 kHz,
Figure TOTAL HARMONIC DISTORTION FREE-AIR TEMPERATURE
-110
-112 -114
-116 -118 -120 +VBD REFIN 4.096 kHz,
Free-Air-Temperature
-122 Free-Air-Temperature
Figure
Figure SIGNAL-TO-NOISE DISTORTION INPUT FREQUENCY
SINAD Signal-to-Noise Distortion Input Frequency +VBD REFIN 4.096 25°C
EFFECTIVE NUMBER BITS INPUT FREQUENCY
ENOB Effective Number Bits Bits
15.5
14.5 +VBD REFIN 4.096 25°C Input Frequency
13.5
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE RATIO INPUT FREQUENCY
SFDR Spurious Free Dynamic Range 94.5
SPURIOUS FREE DYNAMIC RANGE INPUT FREQUENCY
+VBD REFIN 4.096 25°C Input Frequency
Signal-to-Noise
93.5 92.5 Input Frequency +VBD REFIN 4.096 25°C
Figure TOTAL HARMONIC DISTORTION INPUT FREQUENCY
Total Harmonic Distortion +VBD REFIN 4.096 25°C
Figure
-104
-114
-124
Input Frequency
Figure HISTOGRAM INPUT ZERO SCALE
16000 14000 12000 10000 Hits 8000 6000 4000 2000 +VBD REFIN 4.096 25°C
HISTOGRAM INPUT CLOSE FULL SCALE
18000 16000 14000 12000 Hits 10000 8000 6000 4000 2000 32510 32512 32513 32514 32515 32516 32517 32518 +VBD REFIN 4.096 25°C
Code (2's Complement Code Decimal)
Code (2's Complement Code Decimal)
Figure
Figure
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32519
32511
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TYPICAL CHARACTERISTICS (continued)
GAIN ERROR REFERENCE VOLTAGE
Gain Error -0.2 -0.4 -0.6 -0.8 4.75 Vref Reference Voltage Analog Supply Voltage 5.25 +VBD 25°C Gain Error +VBD REFIN 4.096 25°C
GAIN ERROR ANALOG SUPPLY VOLTAGE
Figure GAIN ERROR FREE-AIR TEMPERATURE
+VBD REFIN 4.096 Offset Error Gain Error 0.75 0.25
Figure OFFSET ERROR REFERENCE VOLTAGE
+VBD 25°C
-0.25 -0.5
-0.75 Vref Reference Voltage
Free-Air-Temperature
Figure OFFSET ERROR FREE-AIR TEMPERATURE
0.75 Offset Error 0.25 +VBD REFIN 4.096 Offset Error -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 4.75
Figure OFFSET ERROR SUPPLY VOLTAGE
-0.25 -0.5
-0.75 Free-Air-Temperature
+VBD REFIN 4.096 25°C Analog Supply Voltage 5.25
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
POWER DISSIPATION SUPPLY VOLTAGE
Power Dissipation Power Dissipation 4.75 Analog Supply Voltage 5.25 +VBD KSPS 25°C Mode Current Sample Rate KSPS +VBD 5.25 25°C Normal Mode Current
POWER DISSIPATION SAMPLE RATE
Figure POWER DISSIPATION FREE-AIR TEMPERATURE
+VBD KSPS Diffreential Nonlinearity -0.2 -0.4 -0.6 -0.8
Figure DIFFERENTIAL NONLINEARITY REFERENCE VOLTAGE
Power Dissipation
+VBD 25°C
Free-Air Temperature
Vref Reference Voltage
Figure INTEGRAL NONLINEARITY REFERENCE VOLTAGE
Diffreential Nonlinearity Integral Nonlinearity -0.2 -0.4 -0.6 -0.8 Vref Reference Voltage +VBD 25°C -0.2 -0.4 -0.6 -0.8
Figure DIFFERENTIAL NONLINEARITY FREE-AIR TEMPERATURE
+VBD REFIN 4.096
Free-Air-Temperature
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
INTEGRAL NONLINEARITY FREE-AIR TEMPERATURE
Internal Reference Output Voltage Integral Nonlinearity -0.2 -0.4 -0.6 -0.8 Free-Air-Temperature +VBD REFIN 4.096
INTERNAL REFERENCE OUTPUT VOLTAGE FREE-AIR TEMPERATURE
4.126 +VBD 4.116 4.106
4.096
4.086 4.076 4.066 Free-Air Temperature
Figure INTERNAL REFERENCE OUTPUT VOLTAGE SUPPLY VOLTAGE
4.126 Internal Reference Output Voltage 4.116 4.106 SCLK Delay Time (td13 +VBD 25°C 85°C
Figure DELAY TIME LOAD CAPACITANCE
+VBD
4.096 4.086
+VBD
4.076 4.066 4.75
Analog Supply Voltage
5.25
Load Capacitance
Figure DIFFERENTIAL NONLINEARITY
LSBs -0.2 -0.4 -0.6 -0.8 +VBD REFIN 4.096 KSPS, 25°C -16384 Output Code (2's Complement Code Decimal) 16384
Figure
-32768
32768
Figure
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TYPICAL CHARACTERISTICS (continued)
INTEGRAL NONLINEARITY
-0.2 -0.4 -0.6 -0.8 +VBD REFIN 4.096 KSPS, 25°C -16384 Output Code (2's Complement Code Decimal) 16384 32768
-32768
Figure (100 Input)
Amplitude -100 -120 -140 -160 -180 -200 50000 100000 150000 Frequency 200000 250000 300000 +VBD REFIN 4.096 KSPS, 25°C
Figure Input)
Amplitude -100 -120 -140 -160 -180 -200 50000 100000 150000 Frequency 200000 250000 300000 +VBD REFIN 4.096 KSPS, 25°C
Figure
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Power
BUSY=0
+VBD Reach Operation Range
Sample
BUSY=0
CONVST
Falling Edge CONVST_QUAL
CONVST
BUSY=0
CONVST Back Back Cycle CONVERSION
Falling Edge CONVST_QUAL BUSY
Abort
BUSY= 1->0
CONVST_QUAL
CONVST_QUAL
BUSY=0
Wait
BUSY=0
conversion, Start conversion, CONVST_QUAL CONVST latched Figure
Figure Device States Ideal Transitions
CONVST
LATCH
CONVST_QUAL
LATCH
Figure Relationship Between CONVST_QUAL, CONVST
TIMING DIAGRAMS
following descriptions, signal CONVST_QUAL represents CONVST latched value (see Figure 39). avoid performance degradation, there three quiet zones observed (tquiet1 tquiet2 zones before after falling edge CONVST_QUAL while tquiet3 time zone before falling edge BUSY) where there should activities. Interface control signals, including serial clock should remain steady. Typical degradation performance these quiet zones observed depicted specifications section. avoid data loss read operation should start around BUSY falling edge. This constrained tsu2, tsu3, th2, th8.
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CONVST_QUAL tquiet1 BUSY tquiet3 Quiet Zones tquiet2
tsu3 tsu2 BUSY Read Zone Initiated) BUSY Read Zone Initiated)
Figure Quiet Zones No-Read Zones CONVERSION SAMPLING Convert start command: device enters conversion phase from sampling phase when falling edge detected CONVST_QUAL. This shown Figure Figure Figure Sample (acquisition) start command: device starts sampling from wait/nap state conversion CONVST detected high low. This shown Figure Figure Figure Maintaining this condition (holding low) when device just finished conversion shown Figure takes device immediately into sampling phase after conversion phase (back-to-back conversion) hence achieves maximum throughput. Otherwise, device enters wait state state.
tsu4 CONVST CONVST_QUAL (Device Internal) tquiet1 SAMPLE DEVICE STATE BUSY tquiet3 CONVERT tCONV tquiet2 tquiet1 SAMPLE tacq1 tsu1 tquiet2 tsu2
Figure Back-to-Back Conversion Sample
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Wait/Nap entry stimulus: device enters wait phase conversion sample start command given. This shown Figure
tsu4
CONVST
CONVST_QUAL (Device Internal) tquiet2 tquiet1 tquiet1 tquiet2
DEVICE STATE SAMPLE CONVERT tCONV BUSY tquiet3 WAIT SAMPLE tacq1
Figure Convert Sample with Wait lower power dissipation desired throughput compromised, state inserted between cycles shown Figure 43). device enters power state called conversion happens when CONVST_QUAL low. cost using this special wait state longer sampling time (tacq2) plus time.
CONVST
CONVST_QUAL (Device Internal) tquiet1 tquiet2
tquiet2 tquiet1
DEVICE STATE SAMPLE tCONV BUSY tquiet3 tquiet3 CONVERT SAMPLE tacq2 CONVERT SAMPLE
Figure Convert Sample with Conversion abort command:
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ongoing conversion aborted using conversion abort command. This done forcing another start conversion valid CONVST_QUAL falling edge) onto ongoing conversion shown Figure device enters wait state after aborted conversion. previous conversion successfully aborted, device output reads 0xFF00 SDO.
CONVST
tsu4
CONVST_QUAL (Device Internal)
DEVICE STATE SAMPLE CONVERT
Incomplete Conversion
WAIT
SAMPLE
CONVERT
Incomplete Conversion
WAIT
tCONV BUSY
tacq1
tCONV
Figure Conversion Abort DATA READ OPERATION Data read control independent conversion control. Data read either during conversion during sampling. Data that read during conversion involves latency sample. start data frame around fall BUSY constrained tsu2, tsu3, th2, th8. interface: data read operation interface mode shown Figure must tied high operating this mode. output data available falling edge shifted first rising edge after first falling edge SCLK after falling edge. Subsequent bits shifted subsequent rising edges SCLK. another data frame attempted pulling high subsequently low) during active data frame, then ongoing frame aborted frame started.
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SCLK
tsu5
tcyc td14
tquiet2 CONVST tquiet1 td13 tquiet3 td12
Repeated
There 19th SCLK Don't Care Repeated) Conversion
BUSY
Conversion tsu2 Fall Before This Point Reads Data From Conversion
Fall Zone
Fall After This Point Reads Data From Conversion
Figure Read Frame Controlled another data frame attempted pulling high then low) during active data frame, then ongoing frame aborted frame started. Serial interface using data read operation this mode shown Figure Figure output data available rising edge shifted first rising edge after first falling edge SCLK after falling edge. Subsequent bits shifted subsequent rising edges SCLK.
SCLK
tsu6
tcyc tsu7
CONVST td15
td13
Conversion
tquiet1
tquiet2
Repeated
There 19th SCLK BUSY
Conversion
Don't Care Repeated)
Conversion
Figure Read Frame Controlled When BUSY Falls) high when BUSY falls, updated again with when BUSY falls. This shown Figure
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SCLK
tsu6
tcyc tsu7
CONVST td15
Conversion Conversion
tquiet1
tquiet2
td13
Repeated
tquiet3 BUSY
Conversion
There 19th SCLK Don't Care Repeated)
Conversion
tsu3 Fall Before This Point Reads Data From Conversion
Fall Zone
Fall After This Point Reads Data From Conversion
Figure Read Frame Controlled High When BUSY Falls) another data frame attempted pulling during active data frame, then ongoing frame aborted frame started.
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THEORY OPERATION
ADS8372 high-speed successive approximation register (SAR) analog-to-digital converter (ADC). architecture based charge redistribution, which inherently includes sample/hold function. device includes built-in conversion clock, internal reference, 40-MHz compatible serial interface. maximum conversion time which capable sustaining 600-kHz throughput. analog input provided input pins: -IN. When conversion initiated, differential input these pins sampled internal capacitor array. While conversion progress, both inputs disconnected from internal function.
REFERENCE
ADS8372 built-in 4.096-V (nominal value) reference operate with external reference also. When internal reference used, (REFOUT) should shorted (REFIN) 0.1-µF decoupling capacitor 1-µF storage capacitor must connected between (REFIN) (REFM) (see Figure 48). internal reference converter buffered.
ADS8372 REFOUT REFM AGND REFIN
Figure ADS8372 Using Internal Reference REFIN also internally buffered. This eliminates need high bandwidth buffer board drive reference saves system area power. When external reference used, reference must noise, which achieved addition bypass capacitors from REFIN REFM pin. Figure operation ADS8372 with external reference. REFM must connected analog ground plane.
ADS8372 REFOUT REF3240 AGND REFM AGND REFIN
Figure ADS8372 Using External Reference
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THEORY OPERATION (continued)
ADS8372
AGND
AGND
Figure Simplified Analog Input
ANALOG INPUT
When converter enters hold mode, voltage difference between inputs captured internal capacitor array. Both inputs have range -0.2 (+VREF input span (+IN (-IN)) limited from -VREF VREF. input current analog inputs depends upon throughput frequency content analog input signals. Essentially, current into ADS8372 charges internal capacitor array during sampling (acquisition) time. After this capacitance been fully charged, there further input current. source analog input voltage must able charge device sampling capacitance each from +IN/-IN AGND) 16-bit settling level within sampling (acquisition) time device. When converter goes into hold mode, input resistance greater than Care must taken regarding absolute analog input voltage. maintain linearity converter, +IN, inputs span (+IN (-IN)) should within limits specified. Outside these ranges, converter's linearity meet specifications. Care should taken ensure that output impedance sources driving inputs matched. this observed, inputs have different settling times. This result offset error, gain error, linearity error which vary with temperature input voltage. typical input circuit using TI's THS4031 shown Figure figure, input from single-ended source converted into differential signal ADS8372. case where source differential, circuit Figure used. Most specified performance figure were measured using circuit Figure
Input Signal THS4031 ADS8372
THS4031 AGND
Figure Single-Ended Input, Differential Output Configuration
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THEORY OPERATION (continued)
Input Signal (V+) THS4031 ADS8372
VPP, Common Mode
THS4031 Input Signal (V-)
Figure Differential Input, Differential Output Configuration
DIGITAL INTERFACE TIMING CONTROL
Conversion sampling controlled CONVST pins. timing diagrams detailed information timing signals their requirements. ADS8372 uses internally generated clock control conversion rate turn throughput converter. SCLK used reading converted data only. clean jitter conversion start command important performance converter. There minimal quiet zone requirement around conversion start command mentioned timing requirements table.
READING DATA
ADS8372 offers high speed serial interface that compatible with protocol. device outputs data complement format. Refer Table ideal output codes. Table Input Voltages Ideal Output Codes
DESCRIPTION Full-scale range Least significant (LSB) Full scale scale scale -Full scale ANALOG VALUE (-IN) 2(+VREF) 2(+VREF)/216 VREF -VREF DIGITAL OUTPUT (HEXADECIMAL) Complement 7FFF 0000 FFFF 8000
avoid performance degradation toggling device buffers, read operation must performed specified quiet zones (tquiet1, tquiet2, tquiet3). Internal device, previously converted data updated with data near fall BUSY. Hence, fall fall around fall BUSY constrained. This specified tsu2, tsu3, th2, timing requirements table.
POWER SAVING
converter provides power saving modes, full power down nap. Refer Table information activation/deactivation resumption time both modes.
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Table Power Save
TYPE POWER DOWN Normal operation Full power down (Int Ref, 1-µF capacitor REFOUT pin) Full power down (Ext Ref, 1-µF capacitor REFOUT pin) power down stated Stated (td10 timing) Stated (td10 timing) stated POWER CONSUMPTION ACTIVATED CONVST_QUAL ACTIVATION TIME (td16) RESUME POWER Sample Start command
FULL POWER-DOWN MODE
Full power-down mode activated turning supply asserting Figure Figure device resumed from full power down either turning power supply de-asserting pin. first conversions produce inaccurate results because during this period device loads trim values ensure specified accuracy. internal reference used (with 1-µF capacitor installed between REFOUT REFM pins), total resume time (td18) After first conversions, td17 required trimmed internal reference voltage settle specified accuracy. Only then converted results match specified accuracy.
td10
td11 BUSY
REFOUT td16 Full
Figure Device Full Power Down/Resume (Internal Reference Used)
td10
td11 BUSY td16 Full
Figure Device Full Power Down/Resume (External Reference Used)
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Invalid Data td18 td17 Full
Valid Data
Invalid Data td18 tacq1 Full
Valid Data
ADS8372
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MODE
mode automatically inserted conversion CONVST_QUAL held EOC. device operated mode every conversion saving power lower throughputs. Another this mode convert multiple times then enter mode. minimum sampling time after state tacq1 td18 tacq2.
CONVST CONVST_QUAL DEVICE STATE SAMPLE tCONV BUSY REFIN REFOUT) td16 Full CONVERT Hi-Z LSB+1 MSB-1 SAMPLE
td18 Full
Figure Device Power Down/Resume
LAYOUT
optimum performance, care should taken with physical layout ADS8372 circuitry. Since ADS8372 offers single-supply operation, often used close proximity with digital logic, microcontrollers, microprocessors, digital signal processors. more digital logic design higher switching speed, greater need better layout isolation critical analog signals from these switching digital signals. basic architecture sensitive glitches sudden changes power supply, reference, ground connections digital inputs that occur just prior sampling just prior latching analog comparator. Such glitches might originate from switching power supplies, nearby digital logic, high power devices. Noise during sampling latter half conversion must kept minimum (the former half conversion very sensitive since device uses proprietary error correction algorithm correct transient errors made here). degree error digital output depends reference voltage, layout, exact timing degree external event. average, ADS8372 draws very little current from external reference reference voltage internally buffered. reference voltage external, must ensured that reference source drive bypass capacitor without oscillation. 0.1-µF bypass capacitor recommended from directly (REFM). AGND BDGND pins should connected clean ground point. cases, this should analog ground. Avoid connections that close grounding point microcontroller digital signal processor. required, ground trace directly from converter power supply entry point. ideal layout consists analog ground plane dedicated converter associated analog circuitry.
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LAYOUT (continued)
with AGND connections, should connected +5-V power-supply plane trace that separate from connection digital logic until they connected power entry point. Power ADS8372 should clean well bypassed. 0.1-µF ceramic bypass capacitor should placed close device possible. Table placement these capacitors. addition, 1-µF capacitor recommended. some situations, additional bypassing required, such 100-µF electrolytic capacitor even filter made inductors capacitors-all designed essentially low-pass filter +5-V supply, removing high frequency noise. Table Power Supply Decoupling Capacitor Placement
SUPPLY PINS Pair pins requiring shortest path decoupling capacitors Pins requiring decoupling CONVERTER ANALOG SIDE (2,3); (5,6); (15,16); (17,18) CONVERTER DIGITAL SIDE (20,21)
When using internal reference, ensure shortest path from REFOUT (pin REFIN (pin with bypass capacitor directly between pins
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APPLICATION INFORMATION EXAMPLE DIGITAL STIMULUS
ADS8372 very straightforward. following timing diagram shows example achieve 600-KSPS throughput using compatible serial interface.
BUSY
DEVICE STATE CONVERT SAMPLE CONVERT
CONVST Frequency
SCLK 12.5
Figure Example Stimulus Mode Back-To-Back Conversion that Achieves KSPS also possible frame sync signal, following timing diagram shows achieve 600-KSPS throughput using modified serial interface with active.
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APPLICATION INFORMATION (continued)
BUSY
DEVICE STATE CONVERT SAMPLE CONVERT
Frequency CONVST
SCLK 12.5 LSBn-1 MSBn LSBn
Figure Example Stimulus Serial Interface With Active, Back-To-Back Conversion that Achieves KSPS
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device ADS8372IBRHPR ADS8372IBRHPRG4 ADS8372IBRHPT ADS8372IBRHPTG4 ADS8372IRHPR ADS8372IRHPRG4 ADS8372IRHPT ADS8372IRHPTG4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type
Package Drawing
Pins Package Plan 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
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19-Mar-2008
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing
Reel Reel Diameter Width (mm) (mm) 330.0 330.0 330.0 330.0 16.4 16.4 16.4 16.4
(mm)
(mm)
(mm)
(mm) 12.0 12.0 12.0 12.0
Pin1 (mm) Quadrant 16.0 16.0 16.0 16.0
ADS8372IBRHPR ADS8372IBRHPT ADS8372IRHPR ADS8372IRHPT
2500 2500
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
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19-Mar-2008
*All dimensions nominal
Device ADS8372IBRHPR ADS8372IBRHPT ADS8372IRHPR ADS8372IRHPT
Package Type
Package Drawing
Pins
2500 2500
Length (mm) 333.2 333.2 333.2 333.2
Width (mm) 345.9 345.9 345.9 345.9
Height (mm) 28.6 28.6 28.6 28.6
Pack Materials-Page
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SLAS451 JUNE 2005 16-BIT, 600-kHz, FULLY DIFFERENTIAL PSEUDO-BIPO

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