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ADS836
www.ti.com. SBAS362C AUGUST 2006 REVISED MARCH 2008
16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS
FEATURES
Input Channels Fully Differential Inputs Independent 16-Bit ADCs Total Throughput Channel Power: 200mW Normal Mode Mode 50µW Power-Down Mode TQFP-64 Package Package
DESCRIPTION
ADS8365 includes six, 16-bit, 250kSPS analog-to-digital converters (ADCs) with fully differential input channels grouped into three pairs high-speed simultaneous signal acquisition. Inputs sample-and-hold amplifiers fully differential maintained differential input ADC. This architecture provides excellent common-mode rejection 80dB 50kHz, which important high-noise environments. ADS8365 offers flexible, high-speed parallel interface with direct address mode, cycle, FIFO mode. output data each channel available 16-bit word.
APPLICATIONS
Motor Control Multi-Axis Positioning Systems 3-Phase Power Control
CDAC Comp
HOLDA
A1S/H B0S/H
CDAC Comp
Interface
Conversion Control CDAC Comp
RESET BYTE
HOLDB B1S/H C0S/H HOLDC C1S/H REFIN REFOUT Internal 2.5V Reference CDAC Comp FIFO Register CDAC Comp
Data Input/Output CDAC Comp
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademarks property their respective owners.
Copyright 2006-2008, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
ADS836SBAS362C AUGUST 2006 REVISED MARCH 2008. www.ti.com
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
ORDERING INFORMATION
MAXIMUM INTEGRAL MISSING LINEARITY CODES ERROR ERROR PACKAGEPACKAGE (LSB) (LSB) LEAD DESIGNATOR TQFP-64
PRODUCT ADS836
SPECIFIED TEMPERATURE RANGE -40°C +85°C
PACKAGE MARKING ADS8365AI
ORDERING NUMBER ADS8365IPAG ADS8365IPAGR
TRANSPORT MEDIA, QUANTITY Tray, Tape Reel, 1500
most current package ordering information, Package Option Addendum located this data sheet, website www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
ADS8365 Supply voltage, AGND AVDD Supply voltage, BGND BVDD Analog input voltage range Reference input voltage range Digital input voltage range Ground voltage differences, AGND BGND Voltage differences, BVDD AGND Input current except supply Power dissipation Operating virtual junction temperature range, Operating free-air temperature range, Storage temperature range, TSTG -0.3 -0.3 AGND AVDD AGND AVDD BGND BVDD ±0.3 -0.3 Dissipation Ratings Table +150 +150 UNIT
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under Recommended Operating Conditions implied. Exposure absolute-maximum rated conditions extended periods affect device reliability.
DISSIPATION RATINGS
BOARD Low-K High-K PACKAGE 8.6°C/W 8.6°C/W 68.5°C/W 42.8°C/W DERATING FACTOR ABOVE +25°C 14.598mW/°C 23.364mW/°C +25°C POWER RATING 1824mW 2920mW +70°C POWER RATING 1168mW 1869mW +85°C POWER RATING 949mW 1519mW
JEDEC (1s) board design used derive this data 3-inch 3-inch, two-layer board with 2-ounce copper traces board. JEDEC High (2s2p) board design used derive this data 3-inch 3-inch, multilayer board with 1-ounce internal power ground planes, 2-ounce copper traces bottom board.
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RECOMMENDED OPERATING CONDITIONS
Supply voltage, AVDD AGND Supply voltage, BVDD BGND Reference input voltage Operating common-mode signal, Analog inputs, (-IN) Operating junction temperature range, Low-voltage levels logic levels 4.75 5.25 ±VREF +125 UNIT
ELECTRICAL CHARACTERISTICS: 100kSPS
Over recommended operating free-air temperature range -40°C +85°C, AVDD BVDD VREF internal +2.5V, fCLK 2MHz, fSAMPLE 100kSPS, unless otherwise noted.
ADS8365 PARAMETER ANALOG INPUT Full-scale range Operating common-mode signal Input resistance Input capacitance Input leakage current Differential input resistance Differential input capacitance Common-mode rejection ratio Bandwidth ACCURACY Resolution missing codes Integral linearity error Differential nonlinearity Bipolar offset error Bipolar offset error match Bipolar offset error drift Gain error Gain error match Gain error drift Noise Power-supply rejection ratio SAMPLING DYNAMICS Conversion time Acquisition time Aperture delay Aperture delay matching Aperture jitter Clock frequency 0.05 tCONV 50kHz fCLK 5MHz fCLK 5MHz PSRR 4.75V AVDD 5.25V TCGERR TCVOS GERR Referenced VREF Only pair-wise matching Only pair-wise matching ±1.5 ±1.5 ±0.05 0.005 ±0.25 0.05 ±2.3 Bits Bits ppm/°C %FSR %FSR ppm/°C µVrms CMRR VREF VREF VREF VREF VREF ±1.25VPP 50kHz (-IN) 1500 ±VREF TEST CONDITIONS UNIT
sinewave, -3dB
typical values +25°C.
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ELECTRICAL CHARACTERISTICS: 100kSPS (continued)
Over recommended operating free-air temperature range -40°C +85°C, AVDD BVDD VREF internal +2.5V, fCLK 2MHz, fSAMPLE 100kSPS, unless otherwise noted.
ADS8365 PARAMETER ACCURACY Total harmonic distortion Spurious-free dynamic range Signal-to-noise ratio Signal-to-noise distortion Channel-to-channel isolation Effective number bits VOLTAGE REFERENCE OUTPUT Reference voltage output Initial accuracy Output voltage temperature drift Output voltage noise Power-supply rejection ratio Output impedance Short-circuit current Turn-on settling time VOLTAGE REFERENCE INPUT Reference voltage input Reference input resistance Reference input capacitance Reference input current DIGITAL INPUTS Logic family High-level input voltage Low-level input voltage Input current Input capacitance DIGITAL OUTPUTS Logic family High-level output voltage Low-level output voltage High-impedance state output current Output capacitance Load capacitance DIGITAL INPUTS Logic family High-level input voltage Low-level input voltage Input current Input capacitance BVDD 3.6V BVDD 2.7V BVDD -0.3 LVCMOS BVDD BVDD 4.5V, -100µA BVDD 4.5V, 100µA BVDD, BVDD 4.44 CMOS BVDD BVDD -0.3 CMOS BVDD BVDD PSRR ROUT 0.1% dVOUT/dT 0.1Hz 10Hz, 10µF 10Hz 10kHz, 10µF 1.25 VOUT 2.475 2.525 ppm/°C µVPP µVrms ENOB ±2.5VPP 50kHz SFDR ±2.5VPP 50kHz ±2.5VPP 10kHz SINAD ±2.5VPP 10kHz 14.3 Bits TEST CONDITIONS UNIT
Applies 5.0V nominal supply: BVDD (min) 4.5V BVDD (max) 5.5V. Applies 3.0V nominal supply: BVDD (min) 2.7V BVDD (max) 3.6V.
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ELECTRICAL CHARACTERISTICS: 100kSPS (continued)
Over recommended operating free-air temperature range -40°C +85°C, AVDD BVDD VREF internal +2.5V, fCLK 2MHz, fSAMPLE 100kSPS, unless otherwise noted.
ADS8365 PARAMETER DIGITAL OUTPUTS Logic family High-level output voltage Low-level output voltage High-impedance state output current Output capacitance Load capacitance DATA FORMAT Data format POWER SUPPLY Analog supply voltage Buffer supply voltage Analog operating supply current Buffer operating supply current AVDD BVDD AIDD BIDD BVDD BVDD BVDD Power dissipation BVDD mode enabled Powerdown enabled Low-voltage levels logic levels 4.75 5.25 Binary two's complement Straight binary coding BVDD 2.7V, -100µA BVDD 2.7V, 100µA BVDD, BVDD BVDD
TEST CONDITIONS
UNIT
LVCMOS
Applies 3.0V nominal supply: BVDD (min) 2.7V BVDD (max) 3.6V.
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ELECTRICAL CHARACTERISTICS: 250kSPS
Over recommended operating free-air temperature range -40°C +85°C, AVDD BVDD VREF internal +2.5V, fCLK 5MHz, fSAMPLE 250kSPS, unless otherwise noted
ADS8365 PARAMETER ANALOG INPUT Full-scale range Operating common-mode signal Input resistance Input capacitance Input leakage current Differential input resistance Differential input capacitance Common-mode rejection ratio Bandwidth ACCURACY Resolution missing codes Integral linearity error Differential nonlinearity Bipolar offset error Bipolar offset error match Bipolar offset error drift Gain error Gain error match Gain error drift Noise Power-supply rejection ratio SAMPLING DYNAMICS Conversion time Acquisition time Throughput rate Aperture delay Aperture delay matching Aperture jitter Clock frequency ACCURACY Total harmonic distortion Spurious-free dynamic range Signal-to-noise ratio Signal-to-noise distortion Channel-to-channel isolation Effective number bits ENOB ±2.5VPP 50kHz SFDR ±2.5VPP 50kHz ±2.5VPP 10kHz SINAD ±2.5VPP 10kHz 14.3 Bits 0.05 tCONV 50kHz fCLK 5MHz fCLK 5MHz kSPS PSRR 4.75V AVDD 5.25V TCGERR TCVOS GERR Referenced VREF Only pair-wise matching Specified Only pair-wise matching ±1.5 ±0.05 0.005 ±0.25 0.05 ±2.3 Bits Bits ppm/°C %FSR %FSR ppm/°C µVrms CMRR VREF VREF VREF VREF VREF ±1.25VPP 50kHz (-IN) 1500 ±VREF TEST CONDITIONS UNIT
sinewave, -3dB
typical values +25°C.
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ELECTRICAL CHARACTERISTICS: 250kSPS (continued)
Over recommended operating free-air temperature range -40°C +85°C, AVDD BVDD VREF internal +2.5V, fCLK 5MHz, fSAMPLE 250kSPS, unless otherwise noted
ADS8365 PARAMETER VOLTAGE REFERENCE OUTPUT Reference voltage output Initial accuracy Output voltage temperature drift Output voltage noise Power-supply rejection ratio Output impedance Short-circuit current Turn-on settling time VOLTAGE REFERENCE INPUT Reference voltage input Reference input resistance Reference input capacitance Reference input current DIGITAL INPUTS Logic family High-level input voltage Low-level input voltage Input current Input capacitance DIGITAL OUTPUTS Logic family High-level output voltage Low-level output voltage High-impedance state output current Output capacitance Load capacitance DIGITAL INPUTS Logic family High-level input voltage Low-level input voltage Input current Input capacitance DIGITAL OUTPUTS Logic family High-level output voltage Low-level output voltage High-impedance state output current Output capacitance Load capacitance BVDD 2.7V, -100µA BVDD 2.7V, 100µA BVDD, BVDD BVDD LVCMOS BVDD 3.6V BVDD 2.7V BVDD -0.3 LVCMOS BVDD BVDD 4.5V, -100µA BVDD 4.5V, 100µA BVDD, BVDD 4.44 CMOS BVDD BVDD -0.3 CMOS BVDD BVDD PSRR ROUT 0.1% dVOUT/dT 0.1Hz 10Hz, 10µF 10Hz 10kHz, 10µF 1.25 VOUT 2.475 2.525 ppm/°C µVPP µVrms TEST CONDITIONS UNIT
Applies 5.0V nominal supply: BVDD (min) 4.5V BVDD (max) 5.5V. Applies 3.0V nominal supply: BVDD (min) 2.7V BVDD (max) 3.6V.
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ELECTRICAL CHARACTERISTICS: 250kSPS (continued)
Over recommended operating free-air temperature range -40°C +85°C, AVDD BVDD VREF internal +2.5V, fCLK 5MHz, fSAMPLE 250kSPS, unless otherwise noted
ADS8365 PARAMETER DATA FORMAT Data format POWER SUPPLY Analog supply voltage Buffer supply voltage Analog operating supply current Buffer operating supply current AVDD BVDD AIDD BIDD BVDD BVDD BVDD Power dissipation BVDD mode enabled Powerdown enabled Low-voltage levels logic levels 4.75 5.25 Binary two's complement Straight binary coding TEST CONDITIONS UNIT
EQUIVALENT INPUT CIRCUIT
AVDD 750W C(SAMPLE) 20pF BVDD Diode Turn-on Voltage: 0.35V
AGND Equivalent Analog Input Circuit
BGND Equivalent Digital Input Circuit
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CONFIGURATION
PACKAGE TQFP-64 (TOP VIEW)
REFOUT HOLDC A0HOLDB HOLDA RESET AGND BGND REFIN BVDD AVDD
A1CH AVDD AGND SGND B0AVDD AGND SGND B1CH AVDD AGND SGND
ADS8369
AGND
AVDD
BYTE
BVDD
2BGND
BGND
TERMINAL FUNCTIONS
TERMINAL NAME AVDD AGND SGND AVDD AGND SGND AVDD AGND SGND DESCRIPTION Inverting input channel Noninverting input channel Analog power supply Analog ground Signal Ground Noninverting input channel Inverting input channel Analog power supply Analog ground Signal ground Inverting input channel Noninverting input channel Analog power supply Analog ground Signal ground Noninverting input channel Inverting input channel Inverting input channel
Analog Input, Analog Output, Digital Input, Digital Output, Digital Input/Output, Power Supply Connection. Submit Documentation Feedback Product Folder Link(s): ADS8365
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TERMINAL FUNCTIONS (continued)
TERMINAL NAME AGND AVDD BYTE BVDD BGND BGND BGND BVDD RESET HOLDA HOLDB HOLDC AVDD AGND REFOUT REFIN DESCRIPTION Noninverting input channel mode.Low level unconnected normal operation; high level mode. Analog ground power supply output capability (active high) Power supply digital interface from Buffer digital ground First data data) conversion (active low) external CMOS compatible clock applied input synchronize conversion process external source. Read (active low) Write (active low) Chip select (active low) Buffer digital ground Data (MSB) Data Data Data Data Data Data Data Data (software input Data (software input Data (software input Data (software input Data (software input Data (software input Data (software input Data (software input (LSB) Buffer digital ground Power supply digital interface from Global reset (active low) Address mode select Address line Address line Address line Hold command (active low) Hold command (active low) Hold command (active low) Analog power supply Analog ground Reference output; attach 0.1µF 10µF capacitors Reference input Noninverting input channel Inverting input channel
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TIMING INFORMATION
CONVERSION tCONV ACQUISITION tACQ
HOLDX
D15-D8 Bits 15-8
Bits 15-8
D7-D0
Bits
Bits
BYTE
Figure Read Convert Timing
DB7:0 tD10 tD11
Figure Write Timing
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TIMING CHARACTERISTICS
Over recommended operating free-air temperature range, TMIN TMAX, AVDD REFIN REFOUT, VREF internal +2.5V, fCLK 5MHz, fSAMPLE 250kSPS, BVDD unless otherwise noted,
SYMBOL tACQ tCONV
DESCRIPTION Acquisition time Conversion time Cycle time Delay time rising edge after falling edge HOLDX Delay time first hold after RESET Delay time falling edge after falling edge Delay time rising edge after rising edge Delay time data valid after falling edge Delay time data hold from rising edge Delay time high after Delay time after address setup Delay time data valid Delay time high data release Pulse width high time time Pulse width HOLDX high time recognized again Pulse width HOLDX time Pulse width RESET Pulse width high time Pulse width both time BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD
UNIT
tD10 tD11
Assured design. input signals specified with rise time fall time (10% BVDD timed from voltage level (VIL )/2. Figure BYTE asynchronous; when BYTE bits appear DB15 DB0. When BYTE bits appear DB0. remain between changes BYTE. Only important when synchronization clock important.
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TYPICAL CHARACTERISTICS
+25°C, AVDD +5V, BVDD +3V, VREF internal +2.5V, fCLK 5MHz, fSAMPLE 250kSPS, unless otherwise noted.
INTEGRAL LINEARITY ERROR CODE (100kSPS)
DIFFERENTIAL LINEARITY ERROR CODE (100kSPS)
(LSB)
(LSB)
8192 16384 24576 32768 40960 49152 57344 65535 Code
-0.5 -1.0 8192 16384 24576 32768 40960 49152 57344 65535 Code
Figure MINIMUM MAXIMUM CHANNELS TEMPERATURE (100kSPS)
0.INL (LSB)
Figure MINIMUM MAXIMUM CHANNELS TEMPERATURE (250kSPS)
0.INL (LSB)
-0.5 -1.0 -1.5 -2.0 -2.5 Temperature (°C)
-0.5 -1.0 -1.5 -2.0 -2.5 Temperature (°C)
Figure MINIMUM MAXIMUM CHANNELS TEMPERATURE (100kSPS)
1.DNL (LSB)
Figure MINIMUM MAXIMUM CHANNELS TEMPERATURE (250kSPS)
1.DNL (LSB)
-0.5 -1.0 -1.5 -2.0 Temperature (°C)
-0.5 -1.0 -1.5 -2.0 Temperature (°C)
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
+25°C, AVDD +5V, BVDD +3V, VREF internal +2.5V, fCLK 5MHz, fSAMPLE 250kSPS, unless otherwise noted.
FREQUENCY SPECTRUM (16384 point FFT, 10kHz, -0.2dB)
Amplitude (dB)
FREQUENCY SPECTRUM (16384 point FFT, 45kHz, -0.2dB)
Amplitude (dB)
-100 -120 -140 -160 Frequency (kHz)
-100 -120 -140 -160 Frequency (kHz)
Figure SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE DISTORTION INPUT FREQUENCY (ALL CHANNELS)
Figure SPURIOUS-FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION INPUT FREQUENCY (ALL CHANNELS)
SINAD (dB)
SINAD Frequency (kHz)
SFDR (dB)
SFDR
Frequency (kHz)
Figure SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE DISTORTION TEMPERATURE (ALL CHANNELS)
90.0 89.5 89.0
SINAD (dB)
Figure SPURIOUS-FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION TEMPERATURE (ALL CHANNELS)
88.5 88.0 87.5 87.0 86.5 86.0 85.5 85.0 Temperature (°C)
SFDR (dB)
SFDR Temperature (°C)
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
+25°C, AVDD +5V, BVDD +3V, VREF internal +2.5V, fCLK 5MHz, fSAMPLE 250kSPS, unless otherwise noted.
OFFSET CHANNELS TEMPERATURE
-0.8 -0.9 -1.0 -1.1 -1.2 -1.3 -1.4 Temperature (°C) 0.25 0.20
OFFSET MATCHING CHANNEL PAIRS TEMPERATURE
Offset Matching (mV)
0.10 0.05 -0.05 -0.10 -0.15 -0.20 -0.25 Temperature (°C)
Offset (mV)
Figure GAIN ERROR CHANNELS TEMPERATURE
Figure GAIN-ERROR MATCHING CHANNEL PAIRS TEMPERATURE
Gain Match (ppm FSR)
Gain Error (ppm FSR)
-100
-100
-150 Temperature (°C)
-150 Temperature (°C)
Figure REFERENCE VOLTAGE OUTPUT TEMPERATURE
2.498 2.496
Figure ANALOG SUPPLY CURRENT TEMPERATURE
250kSPS
IDDA (mA)
VREFOUT
2.494
100kSPS
2.492 2.490 Temperature (°C) Temperature (°C)
Figure
Figure
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INTRODUCTION
ADS8365 high-speed, low-power, six-channel simultaneous sampling converting, 16-bit that operates from single supply. input channels fully differential with typical common-mode rejection 80dB. ADS8365 contains successive approximation ADCs, differential sample-and-hold amplifiers, internal +2.5V reference with REFIN REFOUT pins, high-speed parallel interface. There analog inputs that grouped into three channel pairs There ADCs, each input that sampled converted simultaneously, thus preserving relative phase information signals both analog inputs. Each pair channels hold signal (HOLDA, HOLDB, HOLDC) allow simultaneous sampling each channel pair, four channels. part accepts differential analog input voltage range -VREF +VREF, centered common-mode voltage (see Analog Input section). ADS8365 also accepts bipolar input ranges when level shift circuit used front (see Figure 26). conversion initiated ADS8365 bringing HOLDX minimum 20ns. HOLDX places sample-and-hold amplifiers channels hold state simultaneously conversion process started each channel. output goes half clock cycle when conversion latched into output register. data read from parallel output following conversion bringing both low. Conversion time ADS8365 3.2µs when 5MHz external clock used. corresponding acquisition time 0.8µs. achieve maximum output data rate (250kSPS), read function performed during next conversion. NOTE: This mode operation described more detail Timing Control section this data sheet. 5ns. average delta repeated aperture delay values (also known aperture jitter) typically 50ps. These specifications reflect ability ADS8365 capture input signals accurately exact same moment time.
REFERENCE
Under normal operation, REFOUT (pin directly connected REFIN (pin provide internal +2.5V reference ADS8365. ADS8365 operate, however, with external reference range 1.5V 2.6V, corresponding full-scale range 3.0V 5.2V, long input does exceed AVDD 0.3V limit. reference output ADS8365 impedance high impedance reference input driven directly. external resistive load, additional buffer required. load capacitance 0.1µF 10µF should applied reference output minimize noise. external reference used, three input buffers provide isolation between external reference CDACs. These buffers also used recharge capacitors CDACs during conversion.
ANALOG INPUT
analog input bipolar fully differential. There general methods driving analog input ADS8365: single-ended differential, shown Figure Figure When input single-ended, input held common-mode voltage. input swings around same common voltage peak-to-peak amplitude (common-mode VREF) (common-mode -VREF). value VREF determines range over which common-mode voltage vary (see Figure 23).
Single-Ended Input
SAMPLE HOLD
sample-and-hold amplifiers ADS8365 allow ADCs accurately convert input sine wave full-scale amplitude 16-bit resolution. input bandwidth sample-and-hold amplifiers greater than Nyquist rate (Nyquist sampling rate) ADC, even when operated maximum throughput rate 250kSPS. typical small-signal bandwidth sample-and-hold amplifiers 10MHz. Typical aperture delay time time takes ADS8365 switch from sample hold mode following negative edge HOLDX signal)
-VREF +VREF peak-to-peak Common Voltage
ADS836
Differential Input VREF peak-to-peak Common Voltage ADS8365 VREF peak-to-peak
Figure Methods Driving ADS8365 Single-Ended Differential
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+VREF
+VREF
Voltage Voltage -VREF -VREF +VREF Voltage Single-Ended Inputs
+1/2VREF
-VREF -1/2VREF Differential Inputs
NOTES:
Common-mode voltage (Differential mode)
(+IN) (-IN) Common-mode voltage (Single-ended mode)
maximum differential voltage between ADS8365 VREF. Figure Figure further explanation common voltage range single-ended differential inputs.
Figure Using ADS8365 Single-Ended Differential Input Modes
AVDD
AVDD Differential Input
Common-Mode Voltage Range
Common-Mode Voltage Range
Single-Ended Input
VREF
VREF
Figure Single-Ended Input: Common-Mode Voltage Range VREF When input differential, amplitude input difference between input, (+IN) (-IN). peak-to-peak amplitude each input ±1/2VREF around this common voltage. However, since inputs 180° out-of-phase, peak-to-peak amplitude differential voltage +VREF -VREF. value VREF also determines range voltage that common both inputs, shown Figure
Figure Differential Input: Common-Mode Voltage Range VREF each case, care should taken ensure that output impedance sources driving inputs matched. Often, small capacitor (20pF) between positive negative input helps match impedance. Otherwise, mismatch result offset error, which will change with both temperature input voltage. input current analog inputs depends number factors, such sample rate input
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voltage. Essentially, current into ADS8365 charges internal capacitor array during sampling period. After this capacitance been fully charged, there further input current. source analog input voltage must able charge input capacitance (25pF) 16-bit settling level within three clock cycles minimum acquisition time used. When converter goes into hold mode, input impedance greater than Care must taken regarding absolute analog input voltage. inputs should always remain within range AGND 0.3V AVDD 0.3V. OPA365 good choice driving analog inputs single-supply application.
BIPOLAR INPUTS
differential inputs ADS8365 were designed accept bipolar inputs (-VREF +VREF) around common-mode voltage (2.5V), which corresponds input range with 2.5V reference. using simple circuit featuring four, high-precision external resistors, ADS8365 configured accept bipolar input range. conventional ±2.5V, ±5V, ±10V input ranges could interfaced ADS8365 using resistor values shown Figure
1.2kW 20kW OPA227 1.2kW OPA227 ADS8365
TRANSITION NOISE
transition noise ADS8365 itself low, shown Figure These histograms were generated applying low-noise input initiating 8000 conversions. digital output will vary output code internal noise ADS8365; this feature true 16-bit, successive approximation register (SAR) type ADCs. Using histogram plot output codes, distribution should appear bell-shaped, with peak bell curve representing nominal code input value. distributions represent 68.3%, 95.5%, 99.7%, respectively, codes. transition noise calculated dividing number codes measured yielding distribution, 99.7%, codes. Statistically, three codes could fall outside distribution when executing 1000 conversions. Remember, order achieve this low-noise performance, peak-to-peak noise input signal reference must 50µV.
4000 3500 3000 3290 3379
Bipolar Input
REFOUT (pin 2.5V
BIPOLAR INPUT ±10V ±2.5V
10kW 20kW
Figure Level Shift Circuit Bipolar Input Ranges
TIMING CONTROL
ADS8365 uses external clock (CLK, that controls conversion rate CDAC. With 5MHz external clock, sampling rate 250kSPS which corresponds maximum throughput time. Acquisition conversion take total clock cycles.
Occurrences
2500 2000 1500 1000 32782 32783 32784 32785 Code 32786 32787
Figure 8000 Conversion Histogram Input
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THEORY OPERATION
ADS8365 contains 16-bit ADCs that operate simultaneously pairs. three hold signals (HOLDA, HOLDB, HOLDC) initiate conversion specific channels. simultaneous hold channels occur with three hold signals strobed together. converted values saved registers. each read operation, ADS8365 outputs bits information data channel address, data valid, some synchronization information). address/mode signals (A0, select data read from ADS8365. These address/mode signals define selection single channel, cycle mode that cycles through channels, FIFO mode that sequences data determined order hold signals. FIFO mode will allow registers used single-channel pair; therefore, three locations three locations updated before they read from device. output registers, aborts conversion process, closes sampling switches. reset signal must stay least 20ns (see Figure tW4). reset signal should back high least 20ns (Figure tD2) before starting next conversion (negative hold edge). conversion goes when data from internal latched into output registers, which usually happens 16.5 clock cycles after hold initiated conversion. remains half clock cycle. more than channel pair converted simultaneously, A-channels stored registers first (16.5 clock cycles after hold), followed B-channels clock cycle later, finally C-channels another clock cycle later. reading (both low) process, then latch process delayed until read operation finished. First data data high channel chosen read next. FIFO mode, channel (X0) that written FIFO first latched into register. example, when FIFO empty, first result latched into FIFO register therefore, chosen read next, rises. After first channel read (one three read cycles, depending BYTE ADD), goes again.
EXPLANATION CLOCK, RESET, PINS
Clock external clock provided ADS8365. maximum clock frequency 5MHz. minimum clock cycle 200ns (see Figure tC1), clock remain high (Figure tW1) least 60ns. RESET Bringing RESET signal will reset ADS8365. Resetting clears control register
HOLD
HOLD
HOLD RESET
Figure Start Conversion
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START CONVERSION READING DATA
bringing one, two, three HOLDX signals low, input data corresponding channel immediately placed hold mode (5ns). conversion this channel follows with next rising edge clock. important detect hold command during certain clock-cycle, then falling edge hold signal occur least 10ns before rising edge clock, shown Figure tD1. hold signal remain without initiating conversion. hold signal must high least 15ns shown Figure tW2) before brought again, hold must stay least 20ns (Figure tW3). Once particular hold signal goes low, further impulses this hold signal ignored until conversion finished device reset. When conversion finished (after clock cycles) sampling switches close sample selected channel. start next conversion must delayed allow input capacitor ADS8365 fully charged. This delay time depends driving amplifier, should least 800ns.
ADS8365 also convert channel continuously (see Figure 28). Therefore, HOLDA HOLDC kept high time. gain acquisition time, falling edge HOLDB takes place just before rising edge clock. conversion requires clock cycles. Here, data read after next conversion initiated HOLDB. read data from channel high low. Since during first reading 010), data output. Before second switches high 011) that data from channel read, shown Table However, reading data during conversion falling hold edge might cause loss performance. Table Address Control Functions
CHANNEL READ Cycle mode reads registers successive transitions read line FIFO mode
CONVERSION
ACQUISITION
HOLD
Figure Timing Conversion Cycle
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Reading data general, channel/data outputs tri-state. Both must enable these outputs. must stay together least 40ns (see Figure tD6) before output data valid. must remain HIGH least 30ns (see Figure tW5) before bringing back subsequent read command. data latched into output register 16.5 clock cycles after start conversion (next rising edge clock after falling edge HOLDX). Even ADS8365 forced wait until read process finished signal going high) before data latched into output register, possibility still exists that data latched output register just before falling edge read process initiated around 16.5 clock cycles after conversion started, should stay least 50ns (see Figure tW6) data stored register switched output.
being tells ADS8365 that board assigned ADS8365. shares with digital gates, there possibility that digital (high-frequency) noise will coupled into ADC. just used ADS8365, hardwired ground. Reading data falling edge HOLDX signals might cause noise. BYTE there only 8-bit available board, then BYTE high (see Figure 29). this case, lower eight bits read output pins first signal, higher bits after second signal. ADS8365 used cycle FIFO mode, then address data valid information added data high). this case, address will read first, then lower eight bits, finally higher eight bits. BYTE low, then ADS8365 operates 16-bit output mode. Here, data read between pins DB15 DB0. long low, with every impulse, data from channel brought output. high cycle FIFO mode chosen; first output word contains address, while second output word contains 16-bit data.
BYTE
HIGH
HIGH
HIGH
Figure Reading Data Cycling Mode
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Signal cycle FIFO mode, might desirable have address information with 16-bit output data. Therefore, high. this case, signals three readings part operated with BYTE being high) necessary read data channel, while ADS8365 provides channel information first signal (see Table Table Soft Trigger Mode Signals NAP, ADD, RESET, HOLDA, HOLDB, HOLDC accessible through data control word. Bits NAP, ADD, configuration with hardware pins. When software configuration used, these pins must connected ground. Conversely, RESET, HOLDA, HOLDB, HOLDC bits NAND configuration with hardware pins. When software configuration used, these pins must connected BVDD. conversion timing between ADCs critical, Soft Trigger mode allow three HOLDX signals triggered simultaneously. This simultaneous triggering done tying three HOLDX pins high, issuing write low) with DB0, DB1, DB2, bits low, reset (DB3) high. Writing reset (DB3) while RESET high forces device reset, HOLDX signals that occur during that time ignored. HOLDX signals start conversion automatically next clock cycle. format words that written ADS8365 shown Table Bits have corresponding hardware pins. enables Powerdown mode. inverts output data, putting output data two's complement format. When low, data straight binary format.
Table Overview Output Formats Depending Mode When
DB15.DB0 DB15.DB0 DB15.DB0 DB15.DB0 DB15.DB0 DB15.DB0 DB15.DB0 DB15.DB0 BYTE DB7.DB0 DB7.DB0 DB7.DB0 DB7.DB0 DB7.DB0 DB7.DB0 DB7.DB0 DB7.DB0 BYTE DB15.DB8 DB15.DB8 DB15.DB8 DB15.DB8 DB15.DB8 DB15.DB8 DB15.DB8 DB15.DB8
Table Overview Output Formats Depending Mode When
DB15.DB0 DB15.DB0 DB15.DB0 DB15.DB0 DB15.DB0 DB15.DB0 1000 0000 0000 1000 0000 0000 BYTE DB15.DB0 DB15.DB0 DB7.DB0 DB7.DB0 DB7.DB0 DB7.DB0 DB7.DB0 DB7.DB0 BYTE DB15.DB8 DB15.DB8 DB15.DB8 DB15.DB8 DB15.DB8 DB15.DB8 DB7.DB0 DB7.DB0 DB15.DB8 DB15.DB8
Table Control Register Bits
(MSB) Invert RESET HOLDA HOLDB (LSB) HOLDC
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POWERDOWN MODE CONTROL
order minimize power consumption when ADS8365 use, low-power options available. mode minimizes power without shutting down biasing circuitry internal reference, allowing immediate recovery after disabled. enabled either going high, setting data register high. Enabling Powerdown mode results lower power consumption than mode, requires short recovery period after disabling. only enabled setting data register high.
finally, before reading again. Data from channel brought output first after reset signal, after powering device. third mode FIFO mode that addressed with (A2, 111). Data channel that converted first read first. particular channel pair most interesting converted more frequently (for example, history particular channel pair), then there three output registers channel available store data. output registers filled with unread data data from additional conversion must latched then oldest data discarded. read process going signal low) data must stored, then ADS8365 waits until read process finished signal going high) before data gets latched into output register. Again, with signal, chosen whether address should added output data. data always written into next available register. (see Figure 31), reset deletes existing data. data channels into registers dummy read low) performed latch address data correctly. read process channel data finished; therefore, these data dumped data shifted register data available, this time from channels These data written into next available registers (registers
GETTING DATA
Flexible Output Modes: ADS8365 three different output modes that selected with pins held with transparent latch that triggers falling edge negative-ANDed with (that either low, falling edge other will latch A0-2). When (A2, 101, particular channel directly addressed (see Table Figure 30). channel address should least 10ns (see Figure tD9) before falling edge should change long low. this standard address mode, will ignored, should connected either ground supply. When (A2, 110, interface running cycle mode (see Figure 29). Here, data down data channel read first signal, data down data second BYTE high. Then second followed
HOLD tACQ
Figure Timing Reading Data
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RESET
Conversion Channel
Conversion Channels
Conversion Channel
Register Register Register Register Register Register
empty empty empty empty empty empty
empty empty empty empty
empty empty empty empty empty
empty
empty empty
Figure Functionality Diagram FIFO Registers read process channel data finished. data channel (registers Cycle mode FIFO mode, ADS8365 offers ability address channel output data. Since there only 16-bit available 8-bit case BYTE high), additional signal necessary information (see Table Table FIFO mode, dummy read signal (RD) required after reset signal address bits appropriately; otherwise, first conversion will valid. This only necessary FIFO mode. Output Code (DB15 .DB0) standard address mode 000.101), ADS8365 16-bit output word pins DB15.DB0, BYTE BYTE then impulses necessary first read lower bits, then higher bits either DB7.DB0 DB15.DB8. ADS8365 operates Cycle FIFO mode high, then address channel (A2A1A0) data valid (DV) added data. BYTE then data valid address channel active during first impulse (1000 0000 0000 A0). During second 16-bit data word read (DB15.DB0). BYTE then three impulses needed. first impulse, data valid, three address bits, data bits DB3.DB0 (DV, DB3, DB2, DB1, DB0) read, followed eight lower bits 16-bit data word (db7.db0), finally higher eight data bits (DB15.DB8). 1000 0000 0000 added before address case BYTE DB3.DB0 added after address BYTE This provides possibility check counting signals inside ADS8365 still tracking with external interface (see Table Table data valid useful FIFO mode. Valid data simply read until data valid equals three address bits listed Table FIFO empty, zeroes loaded output. Table Address Output Data
DATA FROM Channel Channel Channel Channel Channel Channel
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Binary Two's Complement (BTC) 0111111111111111 0111111111111110 0111111111111101 65535 65534 65533
Digital Output Code
0000000000000001 0000000000000000 1111111111111111
32769 32768 32767
1000000000000010 1000000000000001 1000000000000000
VNFS VREF 0.000038V 0.000076V 0.000152V 16-BIT
2.499962V
2.500038V VBPZ 2.5V
VPFS VREF VPFS 1LSB 4.999924V 4.999848V 1LSB 2.5V VREF 2.5V
Unipolar Analog Input Voltage
Bipolar Input, Binary Two's Complement Output: (BTC) Negative Full-Scale Code VNFS 8000H, Vcode VREF Bipolar Zero Code VBPZ 0000H, Vcode Positive Full-Scale Code VPFS 7FFFH, Vcode (VCM VREF) 1LSB
Figure Ideal Conversion Characteristics (Condition: Single-Ended, chXX- 2.5V, VREF 2.5V)
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Step
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LAYOUT
optimum performance, care should taken with physical layout ADS8365 circuitry. This recommendation particularly true input approaching maximum throughput rate. basic architecture sensitive glitches sudden changes power supply, reference, ground connections, digital inputs that occur just prior latching output analog comparator. Thus, driving single conversion n-bit converter, there windows which large external transient voltages affect conversion result. Such glitches might originate from switching power supplies, nearby digital logic, high-power devices. degree error digital output depends reference voltage, layout, exact timing external event. Their error change external event changes time with respect input. With this information mind, power ADS8365 should clean well-bypassed. 0.1µF ceramic bypass capacitor should placed close device possible. addition, 10µF capacitor recommended. needed, even larger
capacitor series resistor used low-pass filter noisy supply. average, ADS8365 draws very little current from external reference because reference voltage internally buffered. bypass capacitor 0.1µF 10µF suggested when using internal reference (tie directly 62).
GROUNDING
AGND pins should connected clean ground point. cases, this point should analog ground. Avoid connections that close grounding point microcontroller digital signal processor. required, ground trace directly from converter power-supply entry point. ideal layout includes analog ground plane dedicated converter associated analog circuitry. Three signal ground pins (SGND) input signal grounds that same potential analog ground.
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APPLICATION INFORMATION
Different connection diagrams DSPs microcontrollers shown Figure through Figure
2.048V REF3220 100nF 100kW 20kW SENSE OPA343 REFOUT REFIN AVDD
100W 100kW 40kW VREF 100W 0.5V 4.5V ±10V INA159 ADS8365 A02.5V
40kW
100W INA159 100W A1CH B0CH B1CH C0100W INA159 100W C1SGND AGND
Figure ±10V Input Range Using INA159
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ADS8365 BVDD BVDD HOLDA HOLDB BYTE HOLDC
3.3V DVDD PWM1 PWM2 PWM3
C28xx
EXT_INT1 MCLKX ADC_RST (MFSX)
RESET DATA DATA [15] BGND
Figure Typical C28xx Connection (Hardware Control)
BVDD
ADS8365 HOLDA HOLDB HOLDC BYTE BVDD
3.3V DVDD
C28xx
EXT_INT1 MCLKX
DATA DATA [15] BGND
Figure Typical C28xx Connection (Software Control)
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ADS8365 BVDD BYTE RESET DATA DATA [15] BGND BVDD HOLDA HOLDB HOLDC
3.3V DVDD TOUT1 INT0 TOUT0
C67xx
DB_CNTL0 (ED27)
Figure Typical C67xx Connection (Cycle Mode-Hardware Control)
BVDD
ADS8365 HOLDA HOLDB HOLDC BYTE BVDD
3.3V DVDD
C67xx
INT0 TOUT0
DATA DATA [15] BGND
Figure Typical C67xx Connection (Software Control)
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ADS8365 BVDD BVDD HOLDA HOLDB BYTE RESET DATA DATA [15] BGND (1G32) HOLDC
3.3V DVDD TOUT0
C54xx
I/OSTRB INT0 BCLKX1
Figure Typical C54xx Connection (FIFO Mode-Hardware Control)
ADS8365 BVDD BVDD HOLDA BYTE HOLDB HOLDC RESET DATA DATA BGND
3.3V
MSP430x1xx DVDD TACLK (P1.0)
P1.1 P1.2 P1.3 (ADC_INT) SMCLK (P1.4) P2.0 P2.7
Figure Typical MSP430x1xx Connection (Cycle Mode-Hardware Control)
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Part Change Notification 20071210003
ADS8365 device underwent silicon change under Texas Instruments Part Change Notification (PCN) number 20071210003. Details this change obtained from Product Information Center Texas Instruments contacting your local sales/distribution office. Devices with date code higher covered this PCN.
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Revision History
NOTE: Page numbers previous revisions differ from page numbers current version.
Changes from Revision (November 2006) Revision Page Added Part Change Notification information.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device ADS8365IPAG ADS8365IPAGG4 ADS8365IPAGR ADS8365IPAGRG4
Status ACTIVE ACTIVE ACTIVE ACTIVE
Package Type TQFP TQFP TQFP TQFP
Package Drawing
Pins Package Plan Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-4-260C-72 Level-4-260C-72 Level-4-260C-72 Level-4-260C-72
1500 Green (RoHS Sb/Br) 1500 Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
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TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing TQFP
Reel Reel Diameter Width (mm) (mm) 330.0 24.8
(mm)
(mm)
(mm)
(mm) 16.0
Pin1 (mm) Quadrant 24.0
ADS8365IPAGR
1500
13.0
13.0
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
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*All dimensions nominal
Device ADS8365IPAGR
Package Type TQFP
Package Drawing
Pins
1500
Length (mm) 346.0
Width (mm) 346.0
Height (mm) 41.0
Pack Materials-Page
MECHANICAL DATA
MTQF006A JANUARY 1995 REVISED DECEMBER 1996
(S-PQFP-G64)
0,50 0,27 0,17
PLASTIC QUAD FLATPACK
0,08
0,13 7,50 10,20 9,80 12,20 11,80 1,05 0,95 Seating Plane Gage Plane 0,25 0,05 0,75 0,45
1,20
0,08 4040282 11/96
NOTES: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026
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DALLAS, TEXAS 7526
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