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ADS6149 / ADS6129 ADS6148 / ADS6128

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ADS6149 / ADS6129 ADS6148 / ADS6128
www.ti.com ........................................................................... SLWS211B - JULY 2008 - REVISED OCTOBER 2008
14 / 12-Bit, 250 / 210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs
FEATURES
DESCRIPTION
ADS614X (ADS612X) is a family of 14-bit (12-bit) A / D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48 QFN package. This makes it well-suited for multicarrier, wide band-width communications applications. ADS614X / 2X has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (-40°C to 85°C).
250 MSPS ADS614X 14-Bit Family ADS612X 12-Bit Family ADS6149 ADS6129 210 MSPS ADS6148 ADS6128
APPLICATIONS
Multicarrier, Wide Band-Width Communications Wireless Multi-carrier Communications Infrastructure Software Defined Radio Power Amplifier Linearization 802.16d / e Test and Measurement Instrumentation High Definition Video Medical Imaging Radar Systems
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
ADS6149 / ADS6129 ADS6148 / ADS6128
SLWS211B - JULY 2008 - REVISED OCTOBER 2008 ........................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ADS614X BLOCK DIAGRAM
DRGND DRVDD AGND AVDD
DDR LVDS Interface CLKP CLKM CLOCKGEN CLKOUTP CLKOUTM
RESET
SDATA
B0095-06
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ADS612X BLOCK DIAGRAM
DRGND DRVDD AGND AVDD
DDR LVDS Interface CLKP CLKM CLOCKGEN CLKOUTP CLKOUTM
ADS6129 / 28
RESET
SDATA
B0095-07
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PACKAGE / ORDERING INFORMATION (1) (2)
PRODUCT ADS614x ADS6149 QFN-48 ADS6148 ADS612x ADS6129 QFN-48 ADS6128 RGZ -40°C to 85°C Cu NiPdAu AZ6128 AZ6129 ADS6129IRGZR ADS6129IRGZT ADS6128IRGZR ADS6128IRGZT Tape and reel RGZ -40°C to 85°C Cu NiPdAu AZ6148 AZ6149 ADS6149IRGZR ADS6149IRGZT ADS6148IRGZR ADS6148IRGZT Tape and reel PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE LEAD / BALL FINISH PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY
ABSOLUTE MAXIMUM RATINGS (1)
VALUE Supply voltage range, AVDD Supply voltage range, DRVDD Voltage between AGND and DRGND Voltage between AVDD to DRVDD (when AVDD leads DRVDD) VI Voltage between DRVDD to AVDD (when DRVDD leads AVDD) Voltage applied to external pin, VCM (in external reference mode) Voltage applied to analog input pins - INP, INM Voltage applied to input pins - CLKP, CLKM (2), RESET, SCLK, SDATA, SEN, DFS and MODE TA TJ Tstg (1) (2) Operating free-air temperature range Operating junction temperature range Storage temperature range -0.3 V to 3.9 -0.3 V to 2.2 -0.3 to 0.3 0 to 3.3 -1.5 to 1.8 -0.3 to 2.0 -0.3V to minimum ( 3.6, AVDD + 0.3V ) -0.3V to AVDD + 0.3V -40 to 85 125 -65 to 150 UNIT V V V V V V V V °C °C °C
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
ANALOG INPUTS
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ELECTRICAL CHARACTERISTICS - ADS614X and ADS612X
IDRVDD
In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency and the supply voltage (see Figure 91 and CMOS interface power dissipation in application section). The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance on each digital output line is 10 pF.
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ELECTRICAL CHARACTERISTICS - ADS6149 and ADS6148
ELECTRICAL CHARACTERISTICS - ADS6129 and ADS6128
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ELECTRICAL CHARACTERISTICS - ADS614x and ADS612x
Input overload recovery PSRR AC power supply rejection ratio
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DIGITAL CHARACTERISTICS - ADS614x and ADS612x
TEST CONDITIONS
ADS6149 / ADS6148 / ADS6129 / ADS6128 MIN 1.3 0.4 16 10 0 -20 4 DRVDD 0 2 275 -425 1 350 -350 1.2 2 425 -275 1.3 TYP MAX
VOCM, Output common-mode voltage Output capacitance (1) (2) (3) (4) (5) Capacitance inside the device, from either output to ground
GND GND
T0399-01
Figure 1. LVDS Voltage Levels
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TIMING REQUIREMENTS - LVDS AND CMOS MODES (1)
PARAMETER ta tj Aperture delay Aperture jitter Time to valid data after coming out of STANDBY mode Wake-up time Time to valid data after coming out of PDN GLOBAL mode Time to valid data after stopping and restarting the input clock ADC Latency (4) DDR LVDS MODE tsu th tPDI
TEST CONDITIONS The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs
MIN 0.7
TYP 1.2 170 0.3 25 10 18
MAX 1.7
UNIT ns fs rms
µs clock cycles clock cycles
Default, after reset
Data setup time Data hold time Clock propagation delay tdelay LVDS bit clock duty cycle
Data valid
to zero-crossing of CLKOUTP
ns ns ns 7.5 ns
tRISE, tFALL tCLKRISE, tCLKFALL tOE tSTART tDV tPDI
Data rise time, Data fall time Output clock rise time, Output clock fall time Output enable (OE) to data delay
PARALLEL CMOS MODE (7) Input clock to data delay Data valid time Clock propagation delay tdelay Output clock duty cycle tRISE, tFALL tCLKRISE, tCLKFALL tOE Data rise time, Data fall time Output clock rise time, Output clock fall time Output enable (OE) to data delay 3.2 0.7 1.5 ns ns
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LVDS Timings at Lower Sampling Frequencies
HOLD TIME, ns TYP 0.8 0.9 1.1 1.2 1.4 MAX
CMOS Timings at Lower Sampling Frequencies
Timings specified with respect to input clock SAMPLING FREQUENCY, MSPS MIN 210 190 170 150 tSTART, ns TYP MAX 1.7 0.4 5.1 4.8 DATA VALID TIME, ns MIN 1.6 2.2 2.4 3.0 TYP 2.4 3.0 3.6 4.3 MAX
HOLD TIME, ns TYP 2.2 2.7 MAX
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N+3 N+4 N+18 N+20
N+2 Sample N Input Signal ta N+1
Input Clock
CLKP CLKM
CLKOU CLKOUTP tsu DDR LVDS Output Data DXP, DXM E O E O E O 18 Clock Cycles th tPDI
E - Even Bits D0, D2, D4, .. O - Odd Bits D1, D3, D5, ..
tPDI CLKOUT tsu 18 Clock Cycles th N-14 N-1 N N+1 N+2
Parallel CMOS
Output Data
T0105-09
Figure 2. Latency Diagram
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Input Clock
CLKP CLKM tPDI
Output Clock
CLKOUTP CLKOU th tsu tsu th
Output Data Pair
- Bits D0, D2, D4, ..
T0106-07
Dn+1 - Bits D1, D3, D5, ..
Figure 3. LVDS Mode Timing
CLKM CLKP tPDI Output Clock
Input Clock
CLKOUT th tsu
Output Data
Input Clock
CLKM CLKP tSTART tDV
Output Data
Dn - Bits D0, D1, D2, ..
T0107-05
Figure 4. CMOS Mode Timing
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DEVICE CONFIGURATION
ADS614X / 2X can be configured independently using either parallel interface control or serial interface programming.
PARALLEL CONFIGURATION ONLY
PIN DFS MODE (1) SEN SDATA (1) TYPE OF CONTROL Analog Analog Analog Digital CONTROLS MODES Data format and LVDS / CMOS output interface. Internal or external reference, low speed mode enable CLKOUT edge programmability. Global power-down (ADC, internal references and output buffers are powered down)
In the next generation pin-compatible ADC family, MODE will be converted to a digital control pin for certain reserved functions. So, the selection of internal or external reference and low speed functions will not be supported using MODE. In the system board using ADS61x9 / x8, the MODE pin can be routed to a digital controller. This will avoid board modification while migrating to the next generation ADC.
SERIAL INTERFACE CONFIGURATION ONLY
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CONFIGURATION USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
DESCRIPTION OF PARALLEL PINS
Table 3. SDATA - DIGITAL CONTROL PIN
SDATA 0 AVDD Normal operation (default) Global power-down. ADC, internal references and the output buffers are powered down. DESCRIPTION
Table 4. SEN - ANALOG CONTROL PIN (1)
SEN 0 (3 / 8)AVDD (5 / 8)AVDD AVDD (1) DESCRIPTION - Output Clock Edge Programmability LVDS: Data and output clock transitions are aligned CMOS: Setup time increases by (6xTs / 26), Hold time reduces by (6xTs / 26) LVDS: Setup time decreases by (4xTs / 26), Hold time increases by (4xTs / 26) CMOS: Setup time increases by (9xTs / 26), Hold time reduces by (9xTs / 26) LVDS: Setup time increases by (4xTs / 26), Hold time reduces by (4xTs / 26) CMOS: Setup time increases by (3xTs / 26), Hold time reduces by (3xTs / 26) Default output clock position (Setup / hold timings of output data with respect to this clock position is specified in the timing characteristics table).
Table 5. DFS - ANALOG CONTROL PIN
DFS 0 (3 / 8)AVDD (5 / 8)AVDD AVDD 2s complement data and DDR LVDS output 2s complement data and parallel CMOS output Offset binary data and parallel CMOS output Offset binary data and DDR LVDS output DESCRIPTION
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Table 6. MODE - ANALOG CONTROL PIN
AVDD (5 / 8) AVDD 3R (5 / 8) AVDD
2R (3 / 8) AVDD
(3 / 8) AVDD To Parallel Pin
S0321-01
Figure 5. Simple Scheme to Configure Parallel Pins SEN and SCLK
SERIAL INTERFACE
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Register Address
Register Data
SDATA
D2 t(DH)
t(SCLK)
t(DSU)
t(SLOADS)
t(SLOADH)
RESET
T0109-01
Figure 6. Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
SERIAL REGISTER READOUT
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SDATA
B) Read contents of register 0x3F. This register has been initialized with 0x04 (device is put in global power down mode)
SDATA
T0386-01
Figure 7. Serial Readout
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RESET TIMING
PARAMETER t1 t2 t3 Power-on delay Reset pulse width TEST CONDITIONS Delay from power-up of AVDD and DRVDD to RESET pulse active Pulse width of active RESET signal that will reset the serial registers Delay from RESET disable to SEN active
Power Supply AVDD, DRVDD t1
MIN 10
UNIT ms ns
RESET t2 t3
T0108-01
Figure 8. Reset Timing Diagram
SERIAL REGISTER MAP
Table 7. Summary of Functions Supported by Serial Interface (1)
Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
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D7-D0
D5-D0
D3-D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 D7-D4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100
1100 to 1111 RESERVED
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Outputs digital ramp ADS6149 / 8: Output data increments by one LSB (14-bit) every clock cycle from code 0 to code 16383 ADS6129 / 8: Output data increments by one LSB (124-bit) every 4th clock cycle from code 0 to code 4095
Outputs custom pattern as specified in registers 0x51 and 0x52. Unused Unused
Mid-code + 31 LSB Mid-code + 30 LSB Mid-code + 29 LSB Mid-code Mid-code - 1 LSB Mid-code - 2 LSB Mid-code - 32 LSB
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DEVICE INFORMATION
Pad is connected to DRGND
Thermal Pad
P0023-12
Figure 9. PIN CONFIGURATION (LVDS MODE) - ADS6149 / 48
DRGND DRVDD NC NC NC NC RESET SCLK SDATA SEN AVDD AGND
Pad is connected to DRGND
Thermal Pad
P0023-13
Figure 10. PIN CONFIGURATION (LVDS MODE) - ADS6129 / 28
24 Submit Documentation Feedback
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Table 8. PIN ASSIGNMENTS (LVDS MODE) - ADS6149 / 48 and ADS6129 / 28
PIN NAME AVDD AGND CLKP, CLKM INP, INM VCM NO. 8, 18, 20, 22, 24, 26 9, 12, 14, 17, 19, 25 10, 11 15, 16 13 I / O NO. of PINS 6 6 2 2 1 3.3-V Analog power supply Analog ground Differential clock input Differential analog input Internal reference mode - Common-mode voltage output. IO DESCRIPTION
External reference mode - Reference input. The voltage forced on this pin sets the internal references
Serial interface RESET input.
RESET
When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset option. Refer to SERIAL INTERFACE section. In parallel interface mode, the user has to tie RESET pin permanently HIGH. (SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100 k pull-down resistor.
Serial interface clock input. The pin has an internal 100 k pull-down resistor. This pin functions as serial interface data input when RESET is LOW. It functions as power down control pin when RESET is tied high.
SDATA
See Table 3 for detailed information. The pin has an internal 100 k pull-down resistor.
This pin functions as serial interface enable input when RESET is low.
It functions as output clock edge control when RESET is tied high. See Table 4 for detailed information. The pin has an internal 100 k pull-up resistor to AVDD.
Output buffer enable input, active high. The pin has an internal 100 k pull-up resistor to AVDD. Data Format Select input. This pin sets the DATA FORMAT (2s complement or Offset binary) and the LVDS / CMOS output interface type.
OE DFS
See Table 5 for detailed information.
See Figure 9 and Figure 10
In the next generation pin-compatible ADC family, MODE will be converted to a digital control pin for certain reserved functions. So, the selection of internal or external reference and low speed functions will not be supported using MODE. In the system board using ADS61x9 / x8, the MODE pin can be routed to a digital controller. This will avoid board modification while migrating to the next generation ADC. Submit Documentation Feedback 25
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Table 8. PIN ASSIGNMENTS (LVDS MODE) - ADS6149 / 48 and ADS6129 / 28 (continued)
PIN NAME DRVDD DRGND NO. 2, 35 1, 36, PAD See Figure 9 and Figure 10 I / O I I NO. of PINS 2 2 1.8 V Digital and output buffer supply Digital and output buffer ground DESCRIPTION
Do not connect
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DRGND DRVDD D1 D0 NC NC RESET SCLK SDATA SEN AVDD AGND
Pad is connected to DRGND
Thermal Pad
P0023-14
Figure 11. PIN CONFIGURATION (CMOS MODE) - ADS6149 / 48
D10 D11 D8 D3 D5 D7 D4 D0
DRGND DRVDD NC NC NC NC RESET SCLK SDATA SEN AVDD AGND
Pad is connected to DRGND
Thermal Pad
P0023-15
Figure 12. PIN CONFIGURATION (CMOS MODE) - ADS6129 / 28
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PIN ASSIGNMENTS (CMOS MODE) - ADS6149 / 48 and ADS6129 / 28
RESET
SDATA
MODE CLKOUT OE CLKOU D0-D13
23 5 7 4 See Figure 11 and Figure 12 3 2, 35 1, 36, PAD 4 See Figure 11 and Figure 12
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TYPICAL CHARACTERISTICS - ADS6149
FFT for 20 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
FFT for 60 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
f - Frequency - MHz
Figure 13. FFT for 170 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
Figure 14. FFT for 300 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
f - Frequency - MHz
Figure 15. FFT for 2-TONE INPUT SIGNAL (IMD)
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
Figure 16. FFT for 2-TONE INPUT SIGNAL (IMD)
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
f - Frequency - MHz
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS - ADS6149 (continued)
SFDR vs INPUT FREQUENCY
100 95 90 SFDR - dBc 85 80 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
SNR vs INPUT FREQUENCY
LVDS SNR - dBFS
72 71 70 69 68 67 66 65 64 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Figure 19. SFDR vs GAIN
100 95 90 SFDR - dBc 85 80 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Figure 20. SINAD vs GAIN
75 73 71 SINAD - dBFS 4 dB 5 dB 69 67 65 63 61 1 dB 0 dB 59 57 55 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Input adjusted to get -1dBFS input 3 dB
Input adjusted to get -1dBFS input
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS - ADS6149 (continued)
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
G012 G014
86 SNR
Input Amplitude - dBFS
VCM - Common-Mode Voltage of Analog Inputs - V
Figure 23. PERFORMANCE vs AVDD SUPPLY
96 94 92 SFDR - dBc 90 SFDR 88 86 SNR 84 82 80 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 72 71 70 3.7
Figure 24. PERFORMANCE vs DRVDD SUPPLY
AVDD - Supply Voltage - V
DRVDD - Supply Voltage - V
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS - ADS6149 (continued)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
77 76 75 74 73 94 92 90 SFDR SNR - dBFS 88 86 84 82 80 78 0.20 0.70 1.20 1.70 2.20 2.70
SFDR - dBc
T - Temperature - °C
Figure 27. PERFORMANCE vs INPUT CLOCK DUTY CYCLE
SFDR - dBc
Figure 28. PERFORMANCE vs VCM VOLTAGE
84 SNR 82
VVCM - VCM Voltage - V
Figure 29. OUTPUT NOISE HISTOGRAM
Figure 30.
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TYPICAL CHARACTERISTICS - ADS6148
FFT for 20 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 20 40 60 80 100
FFT for 60 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 20 40 60 80 100
f - Frequency - MHz
Figure 32. FFT for 170 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 20 40 60 80 100
Figure 33. FFT for 300 MHz INPUT SIGNAL
-20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0
f - Frequency - MHz
Figure 34. FFT for 2-TONE INPUT SIGNAL (IMD)
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 20 40 60 80 100
Figure 35. FFT for 2-TONE INPUT SIGNAL (IMD)
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 20 40 60 80 100
f - Frequency - MHz
Figure 36.
Figure 37.
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TYPICAL CHARACTERISTICS - ADS6148 (continued)
SFDR vs INPUT FREQUENCY
100 95 90 SFDR - dBc 85 80 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
SNR vs INPUT FREQUENCY
LVDS SNR - dBFS
72 71 70 69 68 67 66 65 64 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Figure 38. SFDR vs GAIN
100 95 90 SFDR - dBc 85 80 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Figure 39. SINAD vs GAIN
75 73 71 SINAD - dBFS 69 67 65 63 61 59 1 dB 0 dB 57 55 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Input adjusted to get -1dBFS input 3 dB 4 dB 5 dB 6 dB 2 dB
4 dB 5 dB 6 dB 1 dB Input adjusted to get -1dBFS input 0 dB
Figure 40.
Figure 41.
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TYPICAL CHARACTERISTICS - ADS6148 (continued)
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
SFDR (dBFS)
77 76 SNR - dBFS 75
94 SFDR 92 SNR SFDR - dBc
75 SNR - dBFS
SNR (dBFS)
Input Amplitude - dBFS
VCM - Common-Mode Voltage of Analog Inputs - V
Figure 42. PERFORMANCE vs AVDD SUPPLY
Figure 43. PERFORMANCE vs DRVDD SUPPLY
AVDD - Supply Voltage - V
DRVDD - Supply Voltage - V
Figure 44.
Figure 45.
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TYPICAL CHARACTERISTICS - ADS6148 (continued)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
T - Temperature - °C
Input Clock Amplitude - VPP
Figure 46. PERFORMANCE vs INPUT CLOCK DUTY CYCLE
Figure 47. PERFORMANCE vs VCM VOLTAGE
SNR - dBFS
75 SNR - dBFS
SFDR - dBc
SFDR 92 74
90 SNR
VVCM - VCM Voltage - V
Figure 48. OUTPUT NOISE HISTOGRAM
Figure 49.
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SFDR SFDR - dBc
SFDR - dBc
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TYPICAL CHARACTERISTICS - ADS6129
FFT for 20 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
FFT for 60 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
f - Frequency - MHz
Figure 51. FFT for 170 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
Figure 52. FFT for 300 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
f - Frequency - MHz
Figure 53. FFT for 2-TONE INPUT SIGNAL (IMD)
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
Figure 54. FFT for 2-TONE INPUT SIGNAL (IMD)
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 25 50 75 100 125
f - Frequency - MHz
Figure 55.
Figure 56.
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TYPICAL CHARACTERISTICS - ADS6129 (continued)
SFDR vs INPUT FREQUENCY
100 95 90 SFDR - dBc 85 80 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
SNR vs INPUT FREQUENCY
LVDS SNR - dBFS
72 71 70 69 68 67 66 65 64 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Figure 57. SFDR vs GAIN
100 95 90 SFDR - dBc 85 80 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Figure 58. SINAD vs GAIN
75 73 71 SINAD - dBFS 69 67 65 63 61 1 dB 0 dB 59 57 55 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Input adjusted to get -1dBFS input 3 dB 4 dB 5 dB 6 dB
3 dB 4 dB 5 dB 6 dB Input adjusted to get -1dBFS input
Figure 59.
Figure 60.
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TYPICAL CHARACTERISTICS - ADS6129 (continued)
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
G050 G052
SFDR (dBFS)
SNR (dBFS)
Input Amplitude - dBFS
VCM - Common-Mode Voltage of Analog Inputs - V
Figure 61. PERFORMANCE vs AVDD SUPPLY
96 94 92 SFDR - dBc 90 SFDR 88 86 84 82 80 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SNR 72 71 70 69 68 3.7
Figure 62. PERFORMANCE vs DRVDD SUPPLY
75 74 SNR - dBFS
SFDR - dBc
AVDD - Supply Voltage - V
DRVDD - Supply Voltage - V
Figure 63.
Figure 64.
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TYPICAL CHARACTERISTICS - ADS6129 (continued)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
74 94 92 90 SFDR SNR - dBFS 88 86 84 82 80 78 0.20 0.70 1.20 1.70 2.20 2.70
SFDR - dBc
T - Temperature - °C
Figure 65. PERFORMANCE vs INPUT CLOCK DUTY CYCLE
SFDR - dBc
Figure 66. PERFORMANCE vs VCM VOLTAGE
SFDR - dBc
VVCM - VCM Voltage - V
Figure 67. OUTPUT NOISE HISTOGRAM
Figure 68.
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TYPICAL CHARACTERISTICS - ADS6128
FFT for 20 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 20 40 60 80 100
FFT for 60 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 20 40 60 80 100
f - Frequency - MHz
Figure 70. FFT for 170 MHz INPUT SIGNAL
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 20 40 60 80 100
Figure 71. FFT for 300 MHz INPUT SIGNAL
-20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0
f - Frequency - MHz
Figure 72. FFT for 2-TONE INPUT SIGNAL (IMD)
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 20 40 60 80 100
Figure 73. FFT for 2-TONE INPUT SIGNAL (IMD)
0 -20 -40 Amplitude - dB -60 -80 -100 -120 -140 -160 0 20 40 60 80 100
f - Frequency - MHz
Figure 74.
Figure 75.
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TYPICAL CHARACTERISTICS - ADS6128 (continued)
SFDR vs INPUT FREQUENCY
100 95 90 SFDR - dBc 85 80 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
SNR vs INPUT FREQUENCY
LVDS SNR - dBFS
72 71 70 69 68 67 66 65 64 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Figure 76. SFDR vs GAIN
100 95 90 SFDR - dBc 85 80 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Figure 77. SINAD vs GAIN
75 73 71 SINAD - dBFS 69 67 65 63 61 1 dB 0 dB 59 57 55 0 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz
Input adjusted to get -1dBFS input 3 dB 4 dB 5 dB 6 dB 2 dB
Input adjusted to get -1dBFS input
Figure 78.
Figure 79.
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TYPICAL CHARACTERISTICS - ADS6128 (continued)
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
SFDR (dBFS)
SNR (dBFS)
90 SNR 88
Input Amplitude - dBFS
VCM - Common-Mode Voltage of Analog Inputs - V
Figure 80. PERFORMANCE vs AVDD SUPPLY
96 94 92 SFDR - dBc 90 88 SNR 86 84 82 80 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 71 70 69 68 3.7
Figure 81. PERFORMANCE vs DRVDD SUPPLY
SNR - dBFS
AVDD - Supply Voltage - V
DRVDD - Supply Voltage - V
Figure 82.
Figure 83.
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SFDR - dBc
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TYPICAL CHARACTERISTICS - ADS6128 (continued)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
75 96 94 92 SNR - dBFS SFDR SFDR - dBc 90 88 SNR 86 84 82 80 0.20 0.70 1.20 1.70 2.20
SFDR - dBc
T - Temperature - °C
Figure 84. PERFORMANCE vs INPUT CLOCK DUTY CYCLE
Figure 85. PERFORMANCE vs VCM VOLTAGE
SFDR - dBc
VVCM - VCM Voltage - V
Figure 86. OUTPUT NOISE HISTOGRAM
Figure 87.
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TYPICAL CHARACTERISTICS - COMMON PLOTS
CMRR vs INPUT FREQUENCY
0 -10 -20 P - Total Power - W -30 CMRR - dB -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 100
TOTAL POWER vs SAMPLING FREQUENCY
fIN - Input Frequency - MHz
fS - Sampling Frequency - MSPS
Figure 89. DRVDD CURRENT vs SAMPLING FREQUENCY
100 IDRVDD - DRVDD Current - mA 90 80 70 60 50 40 30 20 10 0 0 50 100 150 200 250
Figure 90.
CMOS OE Disabled
fS - Sampling Frequency - MSPS
Figure 91.
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CONTOUR PLOTS - ADS6149 / ADS6148 / ADS6129 / ADS6128
fS - Sampling Frequency - MSPS
fIN - Input Frequency - MHz 60 65 70 75 80 85 90 95
SFDR - dBc
M0049-17
Figure 92. SFDR Contour Plot (0 dB gain)
fS - Sampling Frequency - MSPS
fIN - Input Frequency - MHz 60 65 70 80 85 90 95
SFDR - dBc
M0049-18
Figure 93. SFDR Contour Plot (6 dB gain)
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CONTOUR PLOTS - ADS6149 / ADS6148
fS - Sampling Frequency - MSPS
fIN - Input Frequency - MHz 64 65 66 67 68 69 70 71 72 73 74 75
SNR - dBFS
M0048-19
Figure 94. SNR Contour Plot (0 dB gain)
fS - Sampling Frequency - MSPS
fIN - Input Frequency - MHz 60 61 62 63 64 65 66 67 68 69
SNR - dBFS
M0048-20
Figure 95. SNR Contour Plot (6 dB gain)
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APPLICATION INFORMATION THEORY OF OPERATION
ADS6149 / 48 and ADS6129 / 28 is a family of high performance, low power 14-bit and 12-bit pipeline A / D converters with maximum sampling rate up to 250 MSPS. At every rising edge of the input clock, the analog input signal is sampled and sequentially converted by a pipeline of low resolution stages. In each stage, the sampled and held signal is converted by a high speed, low resolution flash sub-ADC. The difference (residue) between the stage input and its quantized equivalent is gained and propagates to the next stage. At every clock, each succeeding stage resolves the sampled input with greater accuracy. The digital outputs from all stages are combined in a digital correction logic block to create the final 14 or 12 bit code, after a data latency of 18 clock cycles. The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight offset binary or binary 2s complement format. The dynamic offset of the first stage sub-ADC limits the maximum analog input frequency to about 500MHz (with 2VPP amplitude) and about 800MHz (with 1VPP amplitude).
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture. This differential topology results in a good AC performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5V, available on VCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5V and VCM - 0.5V, resulting in a 2Vpp differential input swing.
Sampling Switch Lpkg~1 nH INP Cbond ~ 1 pF Resr 200 W 100 W 3 pF Cpar1 0.25 pF Csamp 2 pF Ron 10 W Cpar2 0.5 pF Ron 15 W Csamp 2 pF Sampling Capacitor
RCR Filter
Lpkg~1 nH INM Cbond ~ 1 pF Resr 200 W
Ron 15 W Cpar2 0.5 pF Sampling Switch
Sampling Capacitor
Figure 96. Analog Input Equivalent Circuit The input sampling circuit has a high 3-dB bandwidth that extends up to 700 MHz (measured from the input pins to the sampled voltage).
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Resistance - kW
0.01 0 100 200 300 400 500 600 700 800 900 1000 f - Frequency - MHz
Figure 97. ADC Analog Input Resistance (Rin) Across Frequency
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Capacitance - pF
1 0 100 200 300 400 500 600 700 800 900 1000 f - Frequency - MHz
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39 nH 0.1 mF 0.1 mF 50 W 0.1 mF 25 W 15 W INP 50 W 22 pF 25 W 50 W 1:1 1:1 0.1 mF 39 nH 50 W INM 15 W VCM
Figure 99. Drive Circuit with Low Bandwidth (for low input frequencies) The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back to back helps minimize this mismatch and good performance is obtained for high frequency input signals. An additional termination resistor pair may be required between the two transformers as shown in the figures. The center point of this termination is connected to ground to improve the balance between the P and M sides. The values of the terminations between the transformers and on the secondary side have to be chosen to get an effective 50 (in the case of 50 source impedance).
0.1 mF 0.1 mF 0.1 mF 25 W 50 W 3.3 pF 25 W 5W 1:1 1:1 0.1 mF VCM 50 W INM 5W INP
REFERENCE
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INTREF VCM Internal Reference
INTREF
EXTREF REFM
S0165-09
Figure 101. Reference Section Internal Reference When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5V nominal) is output on VCM pin, which can be used to externally bias the analog input pins. External Reference When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential input voltage corresponding to full-scale is given by Equation 2.
In this mode, the 1.5V common-mode voltage to bias the input pins has to be generated externally.
CLOCK INPUT
ADS614X / 2X clock inputs can be driven differentially (sine, LVPECL or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-k resistors. This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS clock sources.
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Clock buffer
Lpkg ~1 nH CLKP Cbond ~1 pF
20 W Ceq Resr ~100 W 2 pF 5 kW 5 kW VCM Ceq
Lpkg ~1 nH CLKM Cbond ~1 pF
Resr ~100 W Ceq ~ 1 to 3 pF, equivalent input capacitance of clock buffer
0.1 mF CLKP
CMOS Clock Input 0.1 mF CLKP
Differential Sine-Wave or PECL or LVDS Clock Input 0.1 mF CLKM
0.1 mF
S0167-10
S0168-14
Figure 103. Differential Clock Driving Circuit
Figure 104. Single-Ended Clock Driving Circuit
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FINE GAIN CONTROL
ADS614X / 2X includes gain settings that can be used to get improved SFDR performance (compared to no gain). The gain is programmable from 0dB to 6dB (in 0.5 dB steps). For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 9. The SFDR improvement is achieved at the expense of SNR for each gain setting, the SNR degrades about 0.5-1dB. The SNR degradation is less at high input frequencies. As a result, the gain is useful at high input frequencies as the SFDR improvement is significant with marginal degradation in SNR. So, the gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB. Table 9. Full-Scale Range Across Gains
Gain, dB 0 1 2 3 4 5 6 Fine, programmable Type Default after reset Full-Scale, VPP 2V 1.78 1.59 1.42 1.26 1.12 1.00
OFFSET CORRECTION
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8204 8200 8196 8192 8188 8184 Code - LSB 8180 8176 8172 8168 8164 8160 8156 8152 8148 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56
Offset Correction Disabled
Offset Correction Enabled
Output Data With Offset Corrected
Output Data With 36 LSB Offset
Figure 105. Output Code Time Response With Offset Correction Enabled
POWER DOWN
POWER SUPPLY SEQUENCE
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated in the device. Externally, they can be driven from separate supplies or from a single supply.
DIGITAL OUTPUT INFORMATION
ADS614X / 2X provides 14-bit / 12-bit data and an output clock synchronized with the data.
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LVDS Buffers
Pins CLKOUTP CLKOUTM
Output Clock
Data bits D0, D1
LVDS Buffers
12 bit ADC data
Data bits D0, D1
Data bits D2, D3 Data bits D4, D5
Data bits D2, D3
Data bits D4, D5
14 bit ADC data
Data bits D6, D7
Data bits D8, D9
Data bits D10, D11
Data bits D12, D13
ADS 614 X
ADS612X
Figure 106. 14-Bit ADC LVDS Outputs
Figure 107. 12-Bit ADC LVDS Outputs
Even data bits D0, D2, D4.. are output at the falling edge of CLKOUTP and the odd data bits D1, D3, D5.. are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to capture all of the data bits (see Figure 108).
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CLKOUTP CLKOUTM
Sample N
Sample N+1
T0110-01
Figure 108. DDR LVDS Interface LVDS Buffer The equivalent circuit of each LVDS output buffer is shown in Figure 109. The buffer is designed to present an output impedance of 100 (Rout). The differential outputs can be terminated at the receive end by a 100 termination. The buffer output impedance behaves like a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity. Note that this internal termination cannot be disabled and its value cannot be changed.
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ADS6149 / 48 / 29 / 28
0.35 V
External 100-W Load
-0.35 V
S0374-01
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