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User's Manual
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ZiLOG Worldwide Headquarters Race Street Jose, 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
Document Disclaimer
ZiLOG registered trademark ZiLOG Inc. United States other countries. other products and/or service names mentioned herein trademarks companies with which they associated. ©2004 ZiLOG, Inc. rights reserved. Information this publication concerning devices, applications, technology described intended suggest possible uses superseded. ZiLOG, INC. DOES ASSUME LIABILITY PROVIDE REPRESENTATION ACCURACY INFORMATION, DEVICES, TECHNOLOGY DESCRIBED THIS DOCUMENT. ZiLOG ALSO DOES ASSUME LIABILITY INTELLECTUAL PROPERTY INFRINGEMENT RELATED MANNER INFORMATION, DEVICES, TECHNOLOGY DESCRIBED HEREIN OTHERWISE. Except with express written approval ZiLOG, information, devices, technology critical components life support systems authorized. licenses conveyed, implicitly otherwise, this document under intellectual property rights.
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Revision History
Each instance Table reflects change this document from previous revision. more detail, click appropriate link table.
Table Revision History this Document Revision Level Section
Date
Description
Page 176,177,
December 2004
Instruction Corrected discrepancies patterns instructions. Instruction Set, Instruction Description Corrected illustration Rotate Shift Group RLCA instruction. Also corrected code RLCA instruction page
February 2005
190,
Chapter Title
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PRELIMINARY DRAFT v1.0
Chapter Title
User's Manual
Table Contents
Revision History
Overview
Architecture Registers Arithmetic Logic Unit (ALU) Instruction Register Control Description Overview Functions Timing Overview Instruction Fetch Memory Read Write Input Output Cycles. Request/Acknowledge Cycle Interrupt Request/Acknowledge Cycle Non-Maskable Interrupt Response HALT Exit Power-Down Acknowledge Cycle. Power-Down Release Cycle Interrupt Response Overview Interrupt Enable/Disable Response
Hardware Software Implementation Examples
Hardware Minimum System
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Adding Memory Speed Control Interfacing Dynamic Memories Software Implementation Examples Overview Software Features Examples Specific Instructions Examples Programming Tasks
Instruction Description
Overview Instruction Types Addressing Modes Instruction Codes
Instruction
Assembly Language Status Indicator Flags Add/Subtract Flag Instruction Description 8-Bit Load Group 16-Bit Load Group .102 Exchange, Block Transfer, Search Group .122 8-Bit Arithmetic Group .140 General-Purpose Arithmetic Control Groups .166 16-Bit Arithmetic Group .179 Rotate Shift Group .190 Set, Reset, Test Group .224 Jump Group Call Return Group .255 Input Output Group .269
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List Instructions
.146 .180 (HL) .143 .144 .145 .142 .140 .179 .182 .183 (HL) .226 (IX+d) .228 (IY+d) .230 .224 CALL .257 CALL .255 .170 .158 .137 CPDR .138 .134 CPIR .135 .168 .166 .188 .189 .164 .187 .174 DJNZ, .253
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(SP), (SP), (SP), HALT (HL) (IX+d) (IY+d) INDR INIR (HL) (IX) (IY)
List Instructions
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(BC), (DE), (HL), (HL), (IX+d), (IX+d), (IY+d), (IY+d), (nn), (nn), .110 (nn), .109 (nn), (nn), (BC) (DE) (nn) (nn) .106 .102 (nn) .105 .100 (nn) .107 (nn) .104 (HL) (IX+d). (IY+d) .101 .113
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LDDR LDIR OTDR OTIR (C), (n), OUTD OUTI PUSH PUSH PUSH RETI RETN (HL) (IX+d) (IY+d) RLCA
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.193 .205 RRCA .192 .222 .267 .150 .181 .171 (HL) .233 (IX+d) .234 (IY+d) .232 .211 .217 .148 .156
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List Figures
Figure Block Diagram Figure Register Configuration Figure Configuration Figure Basic Timing Example Figure Instruction Code Fetch Figure Memory Read Write Cycle Figure Input Output Cycles Figure Request/Acknowledge Cycle Figure Interrupt Request/Acknowledge Cycle Figure Non-Maskable Interrupt Request Operation Figure HALT Exit Figure Power-Down Acknowledge Figure Power-Down Release Cycle Figure Power-Down Release Cycle Figure Power-Down Release Cycle Figure Mode Interrupt Response Mode Figure Minimum Computer System Figure Implementation Figure Adding Wait State Cycle Figure Adding Wait State Memory Cycle Figure Interfacing Dynamic RAMs Figure Shifting Digits/Bytes
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List Tables
Table Revision History this Document Table Interrupt Enable/Disable, Flip-Flops Table Bubble Listing Table Multiply Listing Table Hex, Binary, Decimal Conversion Table Table 8-Bit Load Group Table 16-Bit Load Group PUSH POP. Table Exchanges Table Block Transfer Group Table Block Search Group Table 8-Bit Arithmetic Logic Table General-Purpose Operation Table 16-Bit Arithmetic Table Rotates Shifts Table Manipulation Group Table Jump, Call, Return Group Table Restart Group Table Input Group Table 8-Bit Arithmetic Logic Table Miscellaneous Control
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List Tables
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Manual Objectives
This user manual describes architecture instruction CPU.
About This Manual
ZiLOG recommends that user read understand everything this manual before setting using product. However, recognize that users have different styles learning: some will want their evaluation while they read about others will open these pages only check particular specification. Therefore, have designed this manual used either procedural manual reference guide important data.
Intended Audience
This document written ZiLOG customers experienced working with microprocessors writing assembly code compilers.
Manual Organization
User's Manual divided into four chapters. Overview Presents overview User's Manual Architecture, descriptions, timing Interrupt Response. Hardware Software Implementation Presents examples User's Manual hardware software.
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Instruction Description Presents User's Manual instruction types, addressing modes instruction Codes. Instruction Presents overview User's Manual assenbly language, status indicator flags instructions. Related Documents
Part Number Part Number Part Number Title Title Title number number number
Manual Conventions
following assumptions conventions adopted provide clarity ease use: Words Clear words clear imply that register condition contains values logical logical respectively. When either these terms followed number, word logical included, implied. Notation Bits Similar Registers field bits within register designated Register (n-n). example: PWM_CR (31-20). field bits within designated Busn-n. example: PCntl7-4. range similar (whole) registers designated Registern-Registern. example: OPBCS5-OPBCS0.
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Terms this document, terms MSB, when appearing upper case, mean least significant byte most significant byte, respectively. lowercase forms, lsb, mean least significant most significant bit, respectively. Courier Font Commands, code lines fragments, register (and other) mnemonics, values, equations, various executable items distinguished from general text Courier font. This convention used within tables. example: CNTR register must Where font possible, Index, name entity presented upper case. Hexadecimal Values Designated Hexadecimal values designated uppercase appear Courier typeface. example: STAT F8H. Uppercase Letters uppercase letters designates names states commands. example: receiver force line force transmitter into WAIT state. considered BUSY after Start condition. START command triggers processing initialization sequence. Initial Uppercase Letters Initial uppercase letters designate settings, modes, conditions general text. example: Slave receiver leaves data line High. Transmit mode, byte sent most significant first. Master generate Stop condition abort transfer.
Manual Objectives
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Register Access Abbreviations Register access designated following abbreviations:
Designation Description Read Only Read/Write Write Only Unspecified indeterminate
Trademarks
Z80, Z180, Z380 Z80382 trademarks ZiLOG, Inc.
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Overview
ARCHITECTURE
ZiLOG family components fourth-generation enhanced microprocessors with exceptional computational power. They offer higher system throughput more efficient memory utilization than comparable second- third-generation microprocessors. speed offerings from suit wide range applications which migrate software. internal registers contain bits read/write memory that accessible programmer. These registers include sets general purpose registers which used individually either 8-bit registers 16-bit register pairs. addition, there sets accumulator flag registers. also contains Stack Pointer, Program Counter, index registers, REFRESH register, INTERRUPT register. easy incorporate into system since requires only single power source. output signals fully decoded timed control standard memory peripheral circuits; supported extensive family peripheral controllers. Figure illustrates internal architecture major elements CPU.
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Data Control
System Control Signals
Inst. Register
Internal Data
Control
Registers
Address Control
16-Bit Address
Figure
Block Diagram
Registers
contains bits memory that available programmer. Figure illustrates this memory configured eighteen 8-bit registers four 16-bit registers. registers implemented using static RAM. registers include sets general-purpose registers that used individually 8-bit registers pairs 16-bit registers. There also sets accumulator flag registers special-purpose registers.
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Main Register Accumulator Interrupt Vector Index Register Index Register Stack Pointer Program Counter Flags
Alternate Register Accumulator Flags
General Purpose Registers
Memory Refresh
Special Purpose Registers
Figure
Register Configuration
Special-Purpose Registers
Program Counter (PC) program counter holds 16-bit address current instruction being fetched from memory. automatically incremented after contents have been transferred address lines. When program jump occurs, value automatically placed overriding incrementer. Stack Pointer (SP) stack pointer holds 16-bit address current stack located anywhere external system memory. external stack memory organized last-in first-out (LIFO) file. Data pushed onto stack from specific registers popped stack specific registers through execution PUSH instructions. data popped from stack always last data pushed onto stack allows simple implementation multiple level interrupts,
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unlimited subroutine nesting simplification many types data manipulation. Index Registers independent index registers hold 16-bit base address that used indexed addressing modes. this mode, index register used base point region memory from which data stored retrieved. additional byte included indexed instructions specify displacement from this base. This displacement specified two's complement signed integer. This mode addressing greatly simplifies many types programs, especially where tables data used. Interrupt Page Address Register operated mode where indirect call memory location achieved response interrupt. register used this purpose stores high order eight bits indirect address while interrupting device provides lower eight bits address. This feature allows interrupt routines dynamically located anywhere memory with minimal access time routine. Memory Refresh Register contains memory refresh counter, enabling dynamic memories used with same ease static memories. Seven bits this 8-bit register automatically incremented after each instruction fetch. eighth remains programmed, resulting from instruction. data refresh counter sent lower portion address along with refresh control signal while decoding executing fetched instruction. This mode refresh transparent programmer does slow operation. programmer load register testing purposes, this register normally used programmer. During refresh, contents register placed upper eight bits address bus.
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Accumulator Flag Registers
includes independent 8-bit accumulators associated 8-bit flag registers. accumulator holds results 8-bit arithmetic logical operations while FLAG register indicates specific conditions 8-bit 16-bit operations, such indicating whether result operation equal zero. programmer selects accumulator flag pair with single exchange instruction that possible work with either pair.
General Purpose Registers
matched sets general-purpose registers, each containing 8-bit registers, used individually 8-bit registers 16-bit register pairs. called while complementary called BC', DE', HL'. time, programmer select either registers work through single exchange command entire set. systems that require fast interrupt response, generalpurpose registers ACCUMULATOR/FLAG register reserved handling this fast routine. exchange command executed switch routines. This greatly reduces interrupt service time eliminating requirement saving retrieving register contents external stack during interrupt subroutine processing. These general-purpose registers used wide range applications. They also simplify programing, specifically ROM-based systems where little external read/write memory available.
Arithmetic Logic Unit (ALU)
8-bit arithmetic logical instructions executed ALU. Internally, communicates with registers external data using internal data bus. Functions performed include:
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Subtract Logical Logical Logical Exclusive Compare Left Right Shifts Rotates (Arithmetic Logical) Increment Decrement Reset Test
Instruction Register Control
each instruction fetched from memory, placed INSTRUCTION register decoded. control sections performs this function then generates supplies control signals necessary read write data from registers, control ALU, provide required external control signals.
DESCRIPTION Overview
pins illustrated Figure function each described following paragraphs.
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MREQ IORQ RFSH HALT WAIT Control RESET Control BUSRQ BUSACK
System Control
Address
Data
Figure
Configuration
Functions
A15-A0 Address (output, active High, tristate). A15-A0 form 16-bit address bus. Address provides address memory data exchanges Kbytes) device exchanges.
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BUSACK Acknowledge (output, active Low). Acknowledge indicates requesting device that address bus, data bus, control signals MREQ, IORQ have entered their high-impedance states. external circuitry control these lines. BUSREQ Request (input, active Low). Request higher priority than always recognized current machine cycle. BUSREQ forces address bus, data bus, control signals MREQ IORQ, high-impedance state that other devices control these lines. BUSREQ normally wired-OR requires external pull-up these applications. Extended BUSREQ periods extensive operations prevent from properly refreshing dynamic RAMS. D7-D0 Data (input/output, active High, tristate). D7-D0 constitute 8-bit bidirectional data bus, used data exchanges with memory I/O. HALT HALT State (output, active Low). HALT indicates that executed HALT instruction waiting either non-maskable maskable interrupt (with mask enabled) before operation resume. During HALT, executes NOPs maintain memory refresh. Interrupt Request (input, active Low). Interrupt Request generated devices. honors request current instruction internal software-controlled interrupt enable flip-flop (IFF) enabled. normally wired-OR requires external pull-up these applications.
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IORQ Input/Output Request (output, active Low, tristate). IORQ indicates that lower half address holds valid address read write operation. IORQ also generated concurrently with during interrupt acknowledge cycle indicate that interrupt response vector placed data bus. Machine Cycle (output, active Low). together with MREQ, indicates that current machine cycle opcode fetch cycle instruction execution. together with IORQ, indicates interrupt acknowledge cycle. MREQ Memory Request (output, active Low, tristate). MREQ indicates that address holds valid address memory read memory write operation. Non-Maskable Interrupt (input, negative edge-triggered). higher priority than INT. always recognized current instruction, independent status interrupt enable flip-flop, automatically forces restart location 0066H. Read (output, active Low, tristate). indicates that wants read data from memory device. addressed device memory should this signal gate data onto data bus. RESET Reset (input, active Low). RESET initializes follows: resets interrupt enable flip-flop, clears registers sets
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interrupt status Mode During reset time, address data high-impedance state, control output signals inactive state. Notice that RESET must active minimum three full clock cycles before reset operation complete. RFSH Refresh (output, active Low). RFSH, together with MREQ indicates that lower seven bits system's address used refresh address system's dynamic memories. WAIT WAIT (input, active Low). WAIT communicates that addressed memory devices ready data transfer. continues enter WAIT state long this signal active. Extended WAIT periods prevent from properly refreshing dynamic memory. Write (output, active Low, tristate). indicates that data holds valid data stored addressed memory location. Clock (input). Single-phase MOS-level clock.
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TIMING Overview
executes instructions stepping through precise basic operations. These include:
Memory Read Write Device Read Write Interrupt Acknowledge
instructions series basic operations. Each these operations take from three clock periods complete they lengthened synchronize speed external devices. clock periods referred (time) cycles operations referred (machine) cycles. Figure illustrates typical instruction series specific cycles. Notice that this instruction consists three machine cycles (M1, M3). first machine cycle instruction fetch cycle which four, five, cycles long (unless lengthened WAIT signal, which described next section). fetch cycle (M1) used fetch opcode next instruction executed. Subsequent machine cycles move data between memory devices, they have anywhere from three five cycles (again, they lengthened wait states synchronize external devices CPU). following paragraphs describe timing which occurs within basic machine cycles. During every subsequent samples WAIT line with falling edge Clock. WAIT line active this time, another WAIT state entered during following cycle. Using this technique, read lengthened match access time type memory device.
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Cycle
Machine Cycle (Opcode Fetch) (Memory Read) Instruction Cycle (Memory Write)
Figure
Basic Timing Example
Instruction Fetch
Figure depicts timing during (opcode fetch) cycle. placed address beginning cycle. half clock cycle later MREQ signal goes active. this time address memory time stabilize that falling edge MREQ used directly chip enable clock dynamic memories. line also goes active indicate that memory read data should enabled onto data bus. samples data from memory data with rising edge clock state this same edge used turn MREQ signals. Thus, data already been sampled before signal becomes inactive. Clock state fetch cycle used refresh dynamic memories. uses this time decode execute fetched instruction that other operation could performed this time. During lower seven bits address contain memory refresh address RFSH signal becomes active tindicating that refresh read dynamic memories must accomplished. signal generated during refresh time prevent data from different memory
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segments from being gated onto data bus. MREQ signal during refresh time should used perform refresh read memory elements. refresh signal used itself because refresh address only guaranteed stable during MREQ time.
Cycle
MREQ
Refresh Address
WAIT RFSH
Figure
Instruction Code Fetch
Memory Read Write
Figure illustrates timing memory read write cycles other than Code fetch cycle. These cycles generally three clock periods long unless wait states requested memory through WAIT signal. MREQ signal signal used same fetch cycle. memory write cycle, MREQ also becomes active when address stable that used directly chip enable dynamic memories. line active when data data stable that
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used directly pulse virtually type semiconductor memory. Furthermore, signal goes inactive one-half state before address data contents changed that overlap requirements almost type semiconductor memory type met.
Memory Read Cycle MREQ WAIT Data Memory Address Memory Address Memory Write Cycle
Figure
Memory Read Write Cycle
Input Output Cycles
Figure illustrates read write operation. During operations single wait state automatically inserted. reason that during operations, time from when IORQ signal goes active until must sample WAIT line very short. Without this extra state, sufficient time does exist port decode address activate WAIT line wait required. Also, without this wait state, difficult design devices that operate full speed. During this wait state time, WAIT request signal sampled. During read operation, line used enable addressed port onto data just case memory read. write operations, line used clock port.
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IORQ WAIT
Port Address
Read Cycle
Write Cycle
*Automatically inserted WAIT state
Figure
Input Output Cycles
Request/Acknowledge Cycle
Figure illustrates timing Request/Acknowledge cycle. BUSREQ signal sampled with rising edge last clock period machine cycle. BUSREQ signal active, sets address, data, tristate control signals high-impedance state with rising edge next clock pulse. that time, external device control buses transfer data between memory devices. (This operation generally known Direct Memory Access [DMA] using cycle stealing.) maximum time respond request length machine cycle external controller maintain control many clock cycles required. very long cycles used, dynamic memories used, external controller also performs refresh function. This situation only occurs very large blocks data
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transferred under control. During request cycle, cannot interrupted either signal.
Cycle Last State BUSREQ Sample BUSACK MREQ, IORQ, RFSH Sample Available Status
Floating
Figure
Request/Acknowledge Cycle
Interrupt Request/Acknowledge Cycle
Figure illustrates timing associated with interrupt cycle. samples interrupt signal (INT) with rising edge last clock instruction. signal accepted internal software controlled interrupt enable flip-flop BUSREQ signal active. When signal accepted, special cycle generated. During this special cycle, IORQ signal becomes active (instead normal MREQ) indicate that interrupting device place 8-bit vector data bus. wait states automatically added this cycle. These states added that ripple priority interrupt scheme easily implemented. wait states allow sufficient time ripple signals stabilize identify which device must insert response vector. Refer Chapter details interrupt response vector utilized CPU.
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Last Cycle Instruction Last State MREQ IORQ WAIT
Refresh
Figure
Interrupt Request/Acknowledge Cycle
Non-Maskable Interrupt Response
Figure illustrates request/acknowledge cycle non-maskable interrupt. This signal sampled same time interrupt line, this line takes priority over normal interrupt disabled under software control. usual function provide immediate response important signals such impending power failure. response non-maskable interrupt similar normal memory read operation. only difference that content data ignored while processor automatically stores external stack jumps location 0066H. service routine non-maskable interrupt must begin this location this interrupt used.
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Last Cycle Last State MREQ RFSH
Refresh
Figure Non-Maskable Interrupt Request Operation
HALT Exit
Whenever software HALT instruction executed, executes NOPs until interrupt received (either non-maskable maskable interrupt while interrupt flip-flop enabled). interrupt lines sampled with rising clock edge during each state depicted Figure non-maskable interrupt been received maskable interrupt been received interrupt enable flip-flop set, then HALT state exited next rising clock edge. following cycle interrupt acknowledge cycle corresponding type interrupt that received. both received this time, then non-maskable acknowledged since highest priority. purpose executing instructions while HALT state keep memory refresh signals active. Each cycle HALT state normal (fetch) cycle except that data received from memory ignored instruction forced internally CPU. HALT acknowledge signal active during this time indicating that processor HALT state.
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HALT HALT Instruction repeated during this Memory Cycle
Figure HALT Exit
Power-Down Acknowledge Cycle
When clock input CMOS stopped either High level, CMOS stops operation maintains registers control signals. However, ICC2 (standby supply current) guaranteed only when system clock stopped level during machine cycle following execution HALT instruction. timing diagram power-down function, when implemented with HALT instruction, shown Figure
HALT
Figure Power-Down Acknowledge
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Power-Down Release Cycle
system clock must supplied CMOS release power-down state. When system clock supplied input, CMOS restarts operations from point which powerdown state implemented. timing diagrams release from power-down mode featured Figure When HALT instruction executed enter power-down state, CMOS also enters HALT state. interrupt signal (either ANT) RESET signal must applied after system clock supplied order release power-down state.
HALT
Figure Power-Down Release Cycle
RESET
HALT
Figure Power-Down Release Cycle
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HALT
Figure Power-Down Release Cycle
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INTERRUPT RESPONSE Overview
interrupt allows peripheral devices suspend operation force start peripheral service routine. This service routine usually involves exchange data, status, control information between peripheral. When service routine completed, returns operation from which interrupted.
Interrupt Enable/Disable
interrupt inputs, software maskable interrupt (INT) non-maskable interrupt (NMI). non-maskable interrupt cannot disabled programmer accepted whenever peripheral device requests This interrupt generally reserved very important functions that enabled disabled selectively programmer. This routine allows programmer disable interrupt during periods when program timing constraints that allow interrupt. CPU, there interrupt enable flip-flop (IFF) that reset programmer using Enable Interrupt (EI) Disable Interrupt (DI) instructions. When reset, interrupt cannot accepted CPU. enable flip-flops IFF1 IFF2.
IFF1 Disables interrupts from being accepted IFF2 Temporary storage location IFF1
state IFF1 used inhibit interrupts while IFF2 used temporary storage location IFF1.
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reset forces both IFF1 IFF2 reset state, which disables interrupts. Interrupts enabled time instruction from programmer. When instruction executed, pending interrupt request accepted until after instruction following executed. This single instruction delay necessary when next instruction return instruction. Interrupts allowed until return completed. instruction sets both IFF1 IFF2 enable state. When accepts maskable interrupt, both IFF1 IFF2 automatically reset, inhibiting further interrupts until programmer issues instruction. Note that previous cases, IFF1 IFF2 always equal. purpose IFF2 save status IFF1 when non-maskable interrupt occurs. When non-maskable interrupt accepted, IFF1 resets prevent further interrupts until reenabled programmer. Thus, after non-maskable interrupt accepted, maskable interrupts disabled previous state IFF1 been saved that complete state just prior non-maskable interrupt restored time. When Load Register with Register instruction Load Register with Register instruction executed, state IFF2 copied parity flag where tested stored. second method restoring status IFF1 through execution Return From Non-Maskable Interrupt (RETN) instruction. This instruction indicates that non-maskable interrupt service routine complete contents IFF2 copied back into IFF1 that status IFF1 just prior acceptance non-maskable interrupt restored automatically. Table summary effect different instructions enable flip-flops.
Table Interrupt Enable/Disable, Flip-Flops Action Reset IFF1 IFF2 Comments Maskable Interrupt, Disabled
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Table Interrupt Enable/Disable, Flip-Flops Action Instruction Execution Instruction Execution IFF1 IFF2 Comments Maskable Disabled Maskable, Enabled IFF2 Parity Flag IFF2 Parity Flag Maskable Interrupt IFF2 indicates completion nonmaskable interrupt service routine.
Instruction Execution instruction Execution Accept
RETN Instruction Execution IFF2
Response
Non-Maskable
always accepts non-maskable interrupt. When this occurs, ignores next instruction that fetches instead performs restart location 0066H. functions recycled restart instruction, location other than eight software restart locations. restart merely call specific address page memory. programmed respond maskable interrupt three possible modes.
Mode
This mode similar 8080A interrupt response mode. With this mode, interrupting device place instruction data executes Thus, interrupting device provides next instruction executed. Often this restart instruction because interrupting device only need supply single byte instruction. Alternatively, other
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instruction such 3-byte call location memory could executed. number clock cycles necessary execute this instruction more than normal number instruction. This occurs because automatically adds wait states Interrupt response cycle allow sufficient time implement external daisy-chain priority control. Figure Figure illustrate detailed timing interrupt response. After application RESET, automatically enters interrupt Mode
Mode
When this mode selected programmer, responds interrupt executing restart location 0038H. Thus, response identical that non-maskable interrupt except that call location 0038H instead 0066H. number cycles required complete restart instruction more than normal added wait states.
Mode
This mode most powerful interrupt response mode. With single 8-bit byte from user, indirect call made memory location. this mode, programmer maintains table 16-bit starting addresses every interrupt service routine. This table located anywhere memory. When interrupt accepted, 16-bit pointer must formed obtain desired interrupt service routine starting address from table. upper eight bits this pointer formed from contents register. register must loaded with applicable value programmer, such reset clears register that initialized zero. lower eight bits pointer must supplied interrupting device. Only seven bits required from interrupting device because least-significant must zero. This required
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because pointer used adjacent bytes form complete 16bit service routine starting address addresses must always start even locations.
Starting Address Pointed Interrupt Service Routine Starting Address Table
Order High Order
Register Contents
Seven Bits From Peripheral
Figure Mode Interrupt Response Mode
first byte table least-significant (low order portion address). programmer must complete this table with correct addresses before interrupts accepted. programmer change this table storing Read/Write Memory, which also allows individual peripherals serviced different service routines. When interrupting device supplies lower portion pointer, automatically pushes program counter onto stack, obtains starting address from table, performs jump this address. This mode response requires clock periods complete (seven fetch lower eight bits from interrupting device, save program counter, obtain jump address). peripheral devices include daisy-chain priority interrupt structure that automatically supplies programmed vector during interrupt acknowledge. Refer Peripherals User Manual more complete information.
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Hardware Software Implementation Examples
HARDWARE Minimum System
This chapter introduction implementing systems that CPU. Figure illustrates simple system. system must include following elements:
Power Supply Oscillator Memory Devices Circuits
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A9-A0
Power Supply
Address
MREQ Data IORQ
Data
RESET
Z80-PIO IORQ Port Port
Output Data
Input Data
Figure Minimum Computer System
Because requires only single power supply, most small systems implemented using only this single supply. external memory mixture standard RAM, ROM, PROM. Figure single Kbytes) comprises entire memory system. internal register configuration contains sufficient Read/Write storage, requiring external memory. circuits allow computer systems interface with external devices. Figure output 8-bit control vector input 8-bit status word. input data gated data using standard three-state driver while output data latched with type standard latch. serves circuit. This single circuit attaches data indicated provides required bits compatible I/O. (Refer Peripherals User's Manual details operation this circuit.) This powerful computer built with only three circuits, simple oscillator, single power supply.
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Adding
Most computer systems require some external Read/Write memory data storage stack implementation. Figure illustrates bytes static memory added previous example Figure memory space assumed organized follows:
Address: 0000H Kbyte Bytes 03FFH 0400H 04FFFH
this diagram address space described hexadecimal notation. Address separates space from space, allowing this address used chip select function. larger amounts external RAM, simple decoder required form chip selects.
Address A7-A0 A7-A0 A7-A0
MREQ
D7-D0
D3-D0 Data
D7-D4
Figure Implementation
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Memory Speed Control
Slow memories reduce costs many applications. WAIT line allows operate with speed memory. Memory access time requirements, which covered Chapter most severe during cycle instruction fetch. other memory access cycles complete additional half clock cycle. Hence, sometimes appropriate wait state cycle slower memories used. Figure example simple circuit that accomplishes this objective. This circuit changed single wait state memory access indicated Figure
WAIT
7474 7474 WAIT
Figure Adding Wait State Cycle
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7400
WAIT
MREQ 7474
7474 WAIT MREQ
Figure Adding Wait State Memory Cycle
Interfacing Dynamic Memories
Each individual dynamic it's specifications that require minor modifications examples given here. ZiLOG Application Notes available describing interfaced with most popular dynamic RAM. Figure illustrates logic necessary interface Kbytes dynamic using 18-pin dynamic memories. This logic assumes that RAMs only memory system that used select between pages memory. During refresh time, memories system must read. provides correct refresh address lines through When adding more memory system, necessary replace only gates that operate with decoder that operates required address bits. Address buffers data buffers generally required larger systems.
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RFSH MREQ
A11-A0 Array D7-D0
Data
Page (1000 1FFFF)
Array Page (0000 0FFFF)
Figure Interfacing Dynamic RAMs
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SOFTWARE IMPLEMENTATION EXAMPLES Overview Software Features
instruction provides user with large number operations control CPU. main alternate index registers hold arithmetic logical operations, form memory addresses, fastaccess storage frequently used data. Information moved directly from register register, from memory memory, from memory registers, from registers memory. addition, register contents register/memory contents exchanged without using temporary storage. particular, contents main alternate registers completely exchanged executing only instructions, EXX. This register exchange procedure used separate working registers from different logical procedures expand available registers single procedure. Storage retrieval data between pairs registers memory controlled last-in first-out basis through PUSH instructions that utilize special STACK POINTER register (SP). This stack register available both manipulate data automatically store retrieve addresses subroutine linkage. When subroutine called, example, address following CALL instruction placed pushdown stack pointed When subroutine returns calling routine, address stack used program counter address next instruction. stack pointer adjusted automatically reflect current stack position during PUSH, POP, CALL, instructions. This stack mechanism allows pushdown data stacks subroutine calls nested practical depth because stack area potentially large memory space. sequence instruction execution controlled different flags (carry, zero, sign, parity/overflow, add/subtract, half-carry), which reflect results arithmetic, logical, shift, compare instructions.
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After execution instruction that sets flag, that flag used control conditional jump return instruction. These instructions provide logical control following manipulation single bit, 8-bit byte, 18-bit data quantities. full logical operations, including AND, (exclusive-OR), (NOR), (two's complement) available Boolean operations between accumulator other 8-bit registers, memory locations, immediate operands. addition, full arithmetic logical shifts both directions available which operate contents 8-bit primary registers directly memory location. carry flag included these shift instructions provide both testing shift results link register/register register/memory shift operations.
Examples Specific Instructions
Example One:
When 737-byte data string memory location DATA must moved location BUFFER, operation programmed follows:
DATA ;START ADDRESS DATA STRING BUFFER;START ADDRESS TARGET BUFFER ;LENGTH DATA STRING LDIR ;MOVE STRING TRANSFER MEMORY POINTED INTO MEMORY LOCATION POINTED INCREMENT ;DECREMENT PROCESS UNTIL
Eleven bytes required this operation each byte data moved clock cycles.
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Example Two:
string memory (limited maximum length characters) starting location DATA moved another memory location starting location BUFFER until ASCII (used string delimitor) found. This operation performed follows:
DATA ;STARTING ADDRESS DATA STRING BUFFER;STARTING ADDRESS TARGET BUFFER ;MAXIMUM STRING LENGTH ;STRING DELIMITER CODE (HL) ;COMPARE MEMORY CONTENTS WITH ;DELIMITER END-$ CHARACTERS EQUAL ;MOVE CHARACTER (HL) (DE) ;INCREMENT DECREMENT LOOP "LOOP" MORE CHARACTERS END: ;OTHERWISE, FALL THROUGH ;NOTE: FLAG USED INDICATE THAT REGISTER ;DECREMENTED ZERO. LOOP:CP
Nineteen bytes required this operation.
Example Three:
16-digit decimal number shifted depicted Figure This shift performed mechanize multiplication division. 16-digit decimal number represented packed format (two digits/ byte) operation programmed follows:
DATA;ADDRESS FIRST BYTE COUNT;SHIFT COUNT ;CLEAR ACCUMULATOR ROTAT:RLD ;ROTATE LEFT ORDER DIGIT ;WITH DIGITS (HL) ;ADVANCE MEMORY POINTER. DJNZ ROTAT-$ ;DECREMENT ROTAT
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ZERO, OTHERWISE FALL ;THROUGH.
Eleven bytes required this operation.
Figure Shifting Digits/Bytes
Example Four:
number subtracted from another number, both which packed format equal varying length. result stored location minuend. operation programmed follows:
SUBDEC:LD ARG1 ARG2 LENGTH (DE) (HL) ;ADDRESS MINUEND ;ADDRESS SUBTRAHEND ;LENGTH ARGUMENTS ;CLEAR CARRY FLAG ;SUBTRAHEND ;SUBTRACT (HL) FROM
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VALUE DJNZ
;ADJUST RESULT DECIMAL CODED (HL), ;STORE RESULT ;ADVANCE MEMORY POINTERS SUBDEC $;DECREMENT "SUBDEC" ;NOT ZERO, OTHERWISE FALL ;THROUGH
Seventeen bytes required this operation.
Examples Programming Tasks
depicted Table this example program sorts array numbers ascending order, using standard exchange sorting algorithm. These numbers range from 255.
Table Bubble Listing Code Stmt Source Statement UM008005-0205 temporary storage calculations counter data array Hardware Software Implementation Examples register contents registers exit data sorted ascending order entry: contains address data contains number elements sorted <c<256) standard exchange (bubble) sort routine
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Table Bubble Listing (Continued) Code Stmt Source Statement 0000 0003 0005 0006 0007 000b 000e goof 0012 0013 0015 0018 001b 0010 001f 0021 0023 0025 222600 cb84 dd2a2600 dd7e00 dd5e01 3008 dd7300 dd7201 cbc4 dd23 10ea cb44 20de UM008005-0205 Hardware Software Implementation Examples flag, loop-$ sort: loop: next: noex: djnz (data), flag, (data) (ix) (ix+1) (ix), (ix+i), flag, next-$ record exchange occurred point next data element count number comparisons repeat more data pairs determine exchange occurred continue data unsorted otherwise, exit save data address initialize exchange flag initialize length counter adjust testing initialize array pointer first element comparison temporary storage element second element comparison comparison first second exchange array elements length data array first element comparison second element comparison flag indicate exchange unused pointer into data array unused
noex-$ first second, jump
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Table Bubble Listing (Continued) 0026 0026 Code Stmt Source Statement flag: data: defs designation flag storage data address
following program (see Table multiplies unsigned 16-bit integers, leaving result register pair.
Table Multiply Listing Code 0000 Stmt Source Statement mult:; unsigned sixteen integer multiply. high order partial result order partial result high order multiplicand order multiplicand counter number shifts high order bits multiplier register uses: exit result entrance: multiplier multiplicand
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Table Multiply Listing (Continued) Code Stmt Source Statement 0000 0610 0002 0003 0004 0005 210000 0008 cb39 000a 000b 3001 good 000e goof 0010 0011 10f5 0013 noadd: djnz ret; end; mloop-$; repeat until more bits. mloop: move multiplicand clear partial result shift multiplier right least significant carry. noadd-$; carry, skip add. else multiplicand partial result. shift multiplicand left multiplying two. number bits-initialize move multiplier order bits multiplier
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Instruction Description
Overview
execute different instruction types including 8080A CPU. instructions fall into these major groups:
Load Exchange Block Transfer Search Arithmetic Logical Rotate Shift Manipulation (Set, Reset, Test) Jump, Call, Return Input/Output Basic Control
Instruction Types
load instructions move data internally among registers between registers external memory. these instructions specify source location from which data moved destination location. source location altered load instruction. Examples load group instructions include moves between general-purpose registers such move data register from register This group also includes load-immediate register external memory location. Other types load instructions allow transfer between registers memory locations. exchange instructions trade contents registers.
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unique block transfer instructions provided Z80. With single instruction, block memory size moved other location memory. This block moves extremely valuable when processing large strings data. With single instruction, block external memory desired length searched 8-bit character. When character found block reached, instruction automatically terminates. Both block transfer block search instructions interrupted during their execution they occupy long periods time. arithmetic logical instructions operate data stored accumulator other general-purpose registers external memory locations. results operations placed accumulator appropriate flags according result operation. example arithmetic operation adding accumulator contents external memory location. results addition placed accumulator. This group also includes 16-bit addition subtraction between 16-bit registers. rotate shift group allows register memory location rotated right left, with without carry either arithmetic logical. Also, digit accumulator rotated right left with digits memory location. manipulation instructions allow accumulator, general-purpose register, external memory location set, reset, tested with single instruction. example, most-significant register reset. This group especially useful control applications controlling software flags general-purpose programming. JUMP, CALL, RETURN instructions used transfer between various locations user's program. This group uses several different techniques obtaining program counter address from specific external memory locations. unique type call RESTART instruction. This instruction actually contains address part
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8-bit Code. This possible because only eight separate addresses located page zero external memory specified. Program jumps also achieved loading register directly into thus allowing jump address complex function routine being executed. input/output group instructions allow wide range transfers between external memory locations general-purpose registers, external devices. each case, port number provided lower eight bits address during transaction. instruction allows this port number specified second byte instruction while other instructions allow specified content register. major advantage using register pointer device that allows multiple ports share common software driver routines. This advantage possible when address part Code routines stored ROM. Another feature these input instructions automatic setting flag register, making additional operations unnecessary determine state input data. parity state example. includes single instructions that move blocks data bytes) automatically from port directly memory location. conjunction with dual general-purpose registers, these instructions provide fast block transfer rates. power this instruction demonstrated providing required floppy disk formatting double-density floppy disk drives interrupt-driven basis. example, provides preamble, address, data, enables codes. Finally, basic control instructions allow various options modes. This group includes instructions such setting resetting interrupt enable flip-flop setting mode interrupt response.
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Addressing Modes
Most instructions operate data stored internal registers, external memory, ports. Addressing refers address this data generated each instruction. This section brief summary types addressing used while subsequent sections detail type addressing available each instruction group. Immediate this mode addressing, byte following Code memory contains actual operand.
Code Code Bytes
Examples this type instruction loading accumulator with constant, where constant byte immediately following Code. Immediate Extended This mode extension immediate addressing that bytes following Codes operand.
Code Code Code Bytes Order High Order
Examples this type instruction loading register pair (16-bit register) with bits (two bytes) data.
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Modified Page Zero Addressing special single byte CALL instruction eight locations page zero memory. This instruction, which referred restart, sets effective address page zero. value this instruction that allows single byte specify complete 16-bit address where commonly called subroutines located, thus saving memory space.
Code Byte
Effective Address 000)2
Relative Addressing Relative addressing uses byte data following Code specify displacement from existing program which program jump occur. This displacement signed two's complement number that added address Code following instruction.
Code Code Jump Relative (One Byte Code) 8-Bit Two's Complement Displacement Added Address (A+2)
value relative addressing that allows jumps nearby locations while only requiring bytes memory space. most programs, relative jumps most prevalent type jump proximity related program segments. Thus, these instructions Significantly reduce memory space requirements. signed displacement range between +127 -128 from A+2. This allows total displacement +129 -126 from jump relative Code address. Another major advantage that allows relocatable code.
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Extended Addressing Extended Addressing provides bytes bits) address included instruction. This data address which program jump address where operand located.
Code Order Address Order Operand High Order Address Order Operand Bytes
Extended addressing required program jump from location memory other location, load store data memory location. During extended addressing use, specify source destination address operand. This notation (nn) used indicate content memory where 16-bit address specified instruction. bytes address used pointer memory location. parentheses always means that value enclosed within them used pointer memory location. example, (3200) refers contents memory location 1200. Indexed Addressing this type addressing, byte data following Code contains displacement that added index registers (the Code specifies which index register used) form pointer memory. contents index register altered this operation.
Code Byte Code Code Displacement Operand added index register form pointer memory
example indexed instruction load contents memory location (Index Register Displacement) into accumulator.
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displacement signed two's complement number. Indexed addressing greatly simplifies programs using tables data because index register point start table. index registers provided because very often operations require more tables. Indexed addressing also allows relocatable code. index registers referred indicate indexed addressing notation use: (IX+d) (IY+d) Here displacement specified after Code. parentheses indicate that this value used pointer external memory. Register Addressing Many Codes contain bits information that specify which register used operation. example register addressing load data register into register Implied Addressing Implied addressing refers operations where Code automatically implies more registers containing operands. example arithmetic operations where accumulator always implied destination results. Register Indirect Addressing This type addressing specifies 16-bit register pair (such used pointer location memory. This type instruction very powerful used wide range applications.
Code Bytes
example this type instruction load accumulator with data memory location pointed register contents. Indexed addressing actually form register indirect addressing
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except that displacement added with indexed addressing. Register indirect addressing allows very powerful simple implement memory accesses. block move search commands extensions this type addressing where automatic register incrementing, decrementing, comparing been added. notation indicating register indirect addressing parentheses around name register that used pointer. example, symbol (HL) specifies that contents register used pointer memory location. Often register indirect addressing used specify 16-bit operands. this case, register contents point lower order portion operand while register contents automatically incremented obtain upper portion operand. Addressing contains large number set, reset, test instructions. These instructions allow memory location register specified operation through three previous addressing modes (register, register indirect, indexed) while three bits Code specify which eight bits manipulated.
Addressing Mode Combinations
Many instructions include more than operand (such arithmetic instructions loads). these cases, types addressing employed. example, load immediate addressing specify source register indirect indexed addressing specify destination.
Instruction Codes
This section describes each instructions provides tables listing Codes every instruction. each these tables, Codes shaded areas identical those offered 8080A CPU.
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Also depicted assembly language mnemonic that used each instruction. instruction Codes listed hexadecimal notation. Single byte Codes require characters while double byte Codes require four characters. convenience, conversion from binary repeated Table
Table Hex, Binary, Decimal Conversion Table
Binary
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Decimal
instruction mnemonics consist Code zero, one, operands. Instructions where operand implied contains operand. Instructions that contain only logical operand, where operand invariant (such Logical instruction), represented operand mnemonic. Instructions that contain varying operands represented operand mnemonics.
Load Exchange
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Table defines Code 8-bit load instructions implemented CPU. Also described this table type addressing used each instruction. source data found horizontal destination specified left column. example, load register from register uses Code 48H. figures, Code specified hexadecimal notation (0100 1000 binary) code fetched from external memory during time, decoded, then register transfer automatically performed CPU. assembly language mnemonic this entire group followed destination, followed source DEST, SOURCE). Note that several combinations addressing modes possible. example, source register addressing destination register indirect; such load memory location pointed register with contents register Code this operation mnemonic this load instruction (HL), parentheses around indicates that contents used pointer memory location. load instruction mnemonics, destination always listed first, with source following. assembly language defined ease programming. Every instruction self documenting programs written language easy maintain. Table some Codes that available bytes. This feature efficient method memory utilization because 18-, 24-, 32-bit instructions implemented Z80. Often utilized instructions such arithmetic logical operations only eight bits, which results better memory utilization than achieved with fixed instruction sizes such bits.
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Table 8-Bit Load Group
Source Implied Destination Register Register Indirect 11indexed Addr. Imme.
(HL) (BC) (DE) (IX+d) (lY+d) Inn)
Indirect
(HL)
(BC) (DE) INDEXED (IX+d)
(IY+d)
EXT, ADDR IMPLIED
(nn)
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load instructions using indexed addressing either source destination location actually three bytes memory with third byte being displacement example, load register with operand pointed with offset written:
instruction sequence this memory
Address Code Displacement Operand
extended addressing instructions also three byte instructions. example, instruction load accumulator with operand memory location 6F32H written:
32H)
instruction sequence
Address Code Order Address High Order Address
Notice that order portion address always first operand. load immediate instructions general-purpose 8-bit registers two-byte instructions. instruction load register with value written:
sequence
Address Code Operand
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Loading memory location using indexed addressing destination immediate addressing source requires four bytes. example,
15),
appears
Address Code Bytes Displacement (-15 Signed Two's Complement Operand Load
Notice that with indexed addressing displacement always follows directly after Code. Table specifies 16-bit load operations. extended addressing feature covers register pairs. Register indirect operations specifying stack pointer PUSH instructions. mnemonic these instructions PUSH POP. These differ from other 16-bit loads that stack pointer automatically decremented incremented each byte pushed onto popped from stack respectively. example, instruction PUSH single byte instruction with Code F5H. During execution, this sequence generated:
Decrement (SP), Decrement (SP),
external stack appears
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(SP) (SP+1)
stack
instruction exact reverse PUSH. PUSH instructions utilize 16-bit operand high order byte always pushed first popped last.
PUSH PUSH PUSH PUSH then PUSH then PUSH then then
instruction using extended immediate addressing source requires bytes data following Code. example,
0659H
appears
Address Code Operand
extended immediate extended addressing modes, order byte always appears first after Code. Table lists 16-bit exchange instructions implemented Z80. Code allows programmer switch between pairs accumulator flag registers while allows programmer switch between duplicate general-purpose registers. These Codes only byte length minimize time necessary perform exchange that duplicate banks used make very fast interrupt response times.
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Table 16-Bit Load Group PUSH
Source Register Register Instructions Imm. Ext. Ext. Addr. (nn) Reg. Indir. (SP)
ADDR.
(nn)
PUSH REG. Instructions IND.
(SP)
NOTE: Push instruction adjust after every execution.
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Table Exchanges Implied Addressing
IMPLIED REG. IND. (SP)
BC', DE',
Block Transfer Search
Table lists extremely powerful block transfer instructions. These instructions operate with three registers.
points source location points destination location byte counter
After programmer initializes these three registers, these four instructions used. (Load Increment) instruction moves byte from location pointed location pointed Register pairs then automatically incremented ready point following locations. byte counter (register pair also decremented this time. This instruction valuable when blocks data must moved other types processing required between each move. LDIR (Load, Increment Repeat) instruction extension instruction. same load increment operation repeated until byte counter reaches count zero. Thus, this single instruction move block data from location other.
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Because 16-bit registers used, size block Kbytes 1024) long moved from location memory other location. Furthermore, blocks overlapping because there constraints data used three register pairs. LDDR instructions very similar LDIR. only difference that register pairs decremented after every move that block transfer starts from highest address designated block rather than lowest. Table specifies Codes four block search instructions. first, (Compare Increment) compares data accumulator with contents memory location pointed register result compare stored flag bits register pair then incremented byte counter (register pair decremented. instruction CPIR merely extension instruction which compare repeated until either match found byte counter (register pair becomes zero. Thus, this single instruction search entire memory 8-bit character. (Compare Decrement) CPDR (Compare, Decrement, Repeat) similar instructions, their only difference that they decrement after every compare that they search memory opposite direction. search started highest location memory block. These block transfer compare instructions extremely powerful string manipulation applications.
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Table Block Transfer Group Destination
Reg. Indir. (DE)
Source
Reg. Indir. (HL) (ED) (ED) (ED) (ED) Load (DE) (HL) LDIR, Load (DE) (HL) Repeat until Load (DE) (HL) LDDR Load (DE) (HL) Repeat until
Note: points source points destination byte counter
Table Block Search Group Search Location
Reg. Indir. (HL) (ED) (ED) (ED) (ED) CPRI. Repeat until) find match CPDR Repeat until find match
Note: points location memory compared with accumulator contents byte counter
Arithmetic Logical
Table lists 8-bit arithmetic operations that performed with accumulator, also listed increment (INC) decrement
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(DEC) instructions. these instructions, except DEC, specified 8-bit operation performed between data accumulator source data. result operation placed accumulator with exception compare (CP) that leaves accumulator unchanged. these operations effect flag register result specified operation. instructions specify register memory location both source destination result. When source operand addressed using index registers, displacement must follow directly. With immediate addressing, actual operand follows directly. example, instruction
Address Code Operand
Assuming that accumulator contained value F3H, result placed accumulator: Accumulator before operation1111 0011 Operand
0000 0111
Result Accumulator0000 0011 instruction (ADD) performs binary between data source location data accumulator. Subtract (SUB) performs binary subtraction. When with Carry specified, (ADC) Subtract with Carry (SBC), then Carry flag also added subtracted respectively. flags decimal adjust instruction (DAA) allow arithmetic operations for:
Multiprecision packed numbers Multiprecision signed unsigned binary numbers Multiprecision two's complement signed numbers
Other instructions this group logical (AND), logical (OR), exclusive (XOR), compare (CP).
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Five general-purpose arithmetic instructions operate accumulator carry flag. These five listed Table decimal adjust instruction adjust subtraction well addition, making arithmetic operations simple. Note that allow this operation flag used. This flag last arithmetic operation subtract. negate accumulator (NEG) instruction forms two's complement number accumulator. Finally, notice that reset carry instruction included because this operation easily achieved through other instructions such logical accumulator with itself. Table lists 16-bit arithmetic operations between 16-bit registers. There five groups instructions including with carry subtract with carry. affect flags. These groups simplify address calculation operations other 16-bit arithmetic operations.
Table 8-Bit Arithmetic Logic
Source Register Addressing Indir. (HL) Indexed (IX+d) (lY+d) Immed.
CARRY SUBTRACT CARR
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Table 8-Bit Arithmetic Logic (Continued)
Source Register Addressing Indir. Indexed Immed.
COMPARE INCREMENT DECREMENT
Table General-Purpose Operation
Decimal Adjust Acc, Complement Acc, Negate Acc, (2's complement Complement Carry Flag, Carry Flag,
Table 16-Bit Arithmetic Source
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Table 16-Bit Arithmetic (Continued) Source
Destination with carry flags with carry flags Increment Decrement
Rotate Shift
major feature rotate shift data accumulator, general-purpose register, memory location. rotate shift Codes depicted Figure Also included arithmetic logical shift operations. These operations useful wide range applications including integer multiplication division. digit rotate instructions (RRD RLD) allow digit accumulator rotated with digits memory location pointed register pair (See Figure 14). These instructions allow efficient arithmetic.
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Table Rotates Shifts
Source Type Rotate Shift (HL) (IX+d) (lY+d)
Rotate Left Circular
RLCA
Rotate Right Circular
RRCA
Rotate Left
Rotate Right
Shift Left Arithmetic
Shift Right Arithmetic
Shift Right Logical b3-b0 Rotate b7-b4 b3-b0 (HL) Digit Left
(HL)
Rotate Digit Right
Manipulation
ability set, reset, test individual bits register memory location needed almost every program. These bits flags general-purpose software routine, indications external control
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conditions, data packed into memory locations, making memory utilization more efficient. set, reset, test accumulator, generalpurpose register memory location with single instruction. Table lists instructions that available this purpose. Register addressing specify accumulator general-purpose register which operation performed. Register indirect indexed addressing available operate external memory locations. test operations Zero flag tested zero.
Jump, Call, Return
Table lists jump, call, return instructions implemented CPU. jump branch program where program counter loaded with 16-bit value specified three available addressing modes (Immediate Extended, Relative, Register Indirect). Notice that jump group several conditions that specified before jump made. these conditions met, program merely continues with next sequential instruction. conditions dependent data flag register. immediate extended addressing used jump location memory. This instruction requires three bytes (two specify 16-bit address) with order address byte first, followed high order address byte. example, unconditional jump memory location 3E32H
Address Code Order Address High Order Address
relative jump instruction uses only bytes, second byte signed two's complement displacement from existing This displacement range +129 -126 measured from address instruction Code.
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Three types register indirect jumps also included. These instructions implemented loading register pair index registers directly into This feature allows program jumps function previous calculations. call special form jump where address byte following call instruction pushed onto stack before jump made. return instruction reverse call because data stack popped directly into form jump address. call return instructions allow simple subroutine interrupt handling. special return instruction included family components. return from interrupt instruction (RETI) return from nonmaskable interrupt (RETN) treated unconditional return identical Code C9H. difference that (RETI) used interrupt routine peripheral chips recognize execution this instruction proper control nested priority interrupt handling. This instruction, coupled with peripheral devices implementation, simplifies normal return from nested interrupt. Without this feature, following software sequence necessary inform interrupting device that interrupt routine completed:
Disable Interrupt Enable Interrupt Return Prevent interrupt before routine exited. Notify peripheral that service routine complete.
This seven byte sequence replaced with byte instruction byte RETI instruction Z80. This important because interrupt service time often must minimized.
Table Manipulation Group
Register Addressing Reg. Indir. (HL) Indexed (IX+d) (IY+d)
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Table Manipulation Group (Continued)
Register Addressing Test Reg. Indir. Indexed
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Table Manipulation Group (Continued)
Register Addressing Rest Reg. Indir. Indexed
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Table Manipulation Group (Continued)
Register Addressing Reg. Indir. Indexed
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Table Jump, Call, Return Group
Condition UnCarry Cond. JUMP IMMED. EXT. RELATIVE Register INDIR. Carry Zero Zero Parity Parity Sign Even Sign
JUMP JUMP
PC+e (HL) (IX) (IY)
CALL
IMMED. EXT.
Decrement Jump RELATIVE Zero DJNZ Return Return From RETI Return From Maskable RETN REGISTER INDIR.
PC+e (SP) (SP+1)
instruction DJNZ used facilitate program loop control. This byte, relative jump instruction decrements register jump occurs register been decremented zero. relative displacement expressed signed two's complement number. simple example
Address
N+10,N+11
Instruction
(Perform sequence instructions) DJNZ (Next Instruction)
Comments
register count loop performed times jump from N+12
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Table lists eight Codes restart instruction. This instruction single byte call eight addresses listed. simple mnemonic these eight calls also listed. This instruction useful frequently-used routines because memory consumption minimized.
Table Restart Group Code
CALL Address 0000H 0008H 0010H 0018H 0020H 0028H 0030H 0038H
Input/Output
extensive input output instructions shown Table Table addressing input output device either absolute register indirect, using register. register indirect addressing mode, data transferred between devices internal registers. addition, eight block transfer instructions have been implemented. These instructions similar memory block transfers except that they register pair pointer memory source (output commands) destination (input commands) while register used byte counter. Register holds address port which input output command required. Because register eight bits length, block transfer command handles bytes. instructions device address appears lower half address (A7-A0) while accumulator content
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transferred upper half address bus. register indirect input output instructions, including block transfers, content register transferred lower half address (device address) while content register transferred upper half address bus.
Control Group
Table illustrates general-purpose control instructions. do-nothing instruction. HALT instruction suspends operation until subsequent interrupt received, while used lock enable interrupts. three interrupt mode commands three available interrupt response modes follows. Mode set, interrupting device insert instruction data allow execute Mode simplified mode where automatically executes restart (RST) location 0038H that external hardware required (the content pushed onto stack). Mode most powerful because allows indirect call location memory. With this mode, forms 16-bit memory address where upper eight bits content register lower eight bits supplied interrupting device. This address points first sequential bytes table where address service routine located. automatically obtains starting address performs CALL instruction this address.
Pointer Interrupt Table, Register Upper Address, Peripheral Supplies Lower Address
Address Interrupt Service Routine
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Table Input Group Register Immed. Indir.
Input Destination Input Register Address input INIR INP, repeat input INDR input, repeat Register Indir (HL) Block Input Commands
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Table 8-Bit Arithmetic Logic Source
Register Register Indir. (HL)
11OUT
Immed. Ind.
Block Output Command
11OUT output 11OUT output repeat 11OUT output 11OUTDR output, repeat Port Destination Address
Table Miscellaneous Control
HALT Disable (EI) Enable (EI) mode mode mode
8080A mode Call location 0038H indirect call using register bits from INTER device pointer
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Instruction
Assembly Language
assembly language allows user write program without concern memory addresses machine instruction formats. uses symbolic addresses identify memory locations mnemonic codes Codes operands) represent instructions. Labels (symbols) assigned particular instruction step source program identify that step entry point subsequent instructions. Operands following each instruction represent storage locations, registers, constant values. assembly language also includes assembler directives that supplement machine instruction. pseudo-op, example, statement that translated machine instruction, rather interpreted directive that controls assembly process. program written assembly language called source program, which consists symbolic commands called statements. Each statement written single line consist from four entries: label field, operation field, operand field, comment field. source program processed assembler obtain machine language program (object program) that executed directly CPU. ZiLOG provides several assemblers that differ features offered. Both absolute relocatable assemblers available with Development Micro-computer Systems. absolute assembler contained base level software operating memory space, while relocating assembler part environment operating memory space.
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Status Indicator Flags
flag registers supply information user about status given time. positions each flag listed below:
Symbol
Field Name Carry Flag Add/Subtract Parity/Overflow Flag Half Carry Flag Zero Flag Sign Flag Used
Each flag registers contains bits status information that cleared operations. (Bits used.) Four these bits P/V, tested with conditional JUMP, CALL, RETURN instructions. flags tested used arithmetic.
Carry Flag
Carry Flag cleared depending operation performed. instructions that generate Carry, instructions that generate Borrow, Carry Flag sets. Carry Flag reset instruction that does generate Carry, instruction that does generate Borrow. This saved Carry facilitates software routines
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extended precision arithmetic. Also, instruction sets Carry Flag conditions making decimal adjustment met. instructions RLA, RRA, RLS, RRS, Carry used link between least significant byte (LSB) most significant byte (MSB) register memory location. During instructions RLCA, RLC, SLA, Carry contains last value shifted register memory location. During instructions RRCA, RRC, SRA, SRL, Carry contains last value shifted register memory location. logical instructions AND, XOR, Carry reset. Carry Flag also Carry Flag (SCF) complemented Compliment Carry Flag (CCF) instructions.
Add/Subtract Flag
Add/Subtract Flag used Decimal Adjust Accumulator instruction (DAA) distinguish between instructions. instructions, cleared instructions,
Add/Subtract Flag
Decimal Adjust Accumulator instruction (DAA) uses this flag distinguish between SUBTRACT instructions. instructions, sets SUBTRACT instructions, sets
Parity/Overflow Flag (P/V)
This flag specific state depending operation performed. arithmetic operations, this flag indicates Overflow condition when result Accumulator greater than maximum possible number
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User's Manual
(+127) less than minimum possible number (-128). This Overflow condition determined examining sign bits operands. addition, operands with different signs never cause Overflow. When adding operands with like signs result different sign, Overflow Flag set, example:
+120 +105 +225 0111 0110 1110 1000 1001 0001 ADDEND AUGEND (-95)
numbers added together resulted number that exceeds +127 positive operands have resulted negative number (-95), which incorrect. Overflow Flag therefore set. subtraction, Overflow occur operands unlike signs. Operands like signs never cause Overflow. example:
+127 +191 0111 1100 1011 1111 0000 1111 MINUEND SUBTRAHEND DIFFERENCE
minuend sign changed from Positive negative, giving incorrect difference. Overflow set. Another method identifying Overflow observe Carry sign bit. there Carry Carry out, there Carry Carry out, then Overflow occurred. This flag also used with logical operations rotate instructions indicate resulting parity Even. number bits byte counted. total Odd, parity flagged total Even, EVEN parity flagged During search instructions (CPI, CPIR, CPD, CPDR) block transfer instructions (LDI, LDIR, LDD, LDDR), Flag monitors state
UM008005-0205
Instruction
User's Manual
Byte Count Register (BC). When decrementing, byte counter decrements flag cleared otherwise flag to1. During instructions, Flag with value interrupt enable flip-flop (IFF2) storage testing. When inputting byte from device with (C), instruction, Flag adjusted indicate data parity.
Half Carry Flag
Half-Carry Flag cleared depending Carry Borrow status between Bits 8-bit arithmetic operation. This flag used Decimal Adjust Accumulator instruction (DAA) correct result packed subtract operation. Flag cleared according following table:
Flag Subtract
Carry occurs from Borrow from occurs Carry occurs from Borrow from occurs
Zero Flag
Zero Flag cleared result generated execution certain instructions 8-bit arithmetic logical operations, flag resulting byte Accumulator byte flag reset compare (Search) instructions, flag value Accumulator equal value memory location indicated value Register pair When testing register memory location, flag contains complemented state indicated (see "Bit s").
UM008005-0205
Instruction
User's Manual
When inputting outputting byte between memory location device (INI, IND, OUTI, OUTD), result decrementing Register flag otherwise flag Also byte inputs from devices using (C), flag indicate 0-byte input.
Sign Flag
Sign Flag stores state most-significant Accumulator (bit When performs arithmetic operations signed numbers, binary twos-complement notation used represent process numeric information. positive number identified negative number identified binary equivalent magnitude positive number stored bits total range from 127. negative number represented twos complement equivalent positive number. total range negative numbers from -128. When inputting byte from device register using instruction, Flag indicates either positive negative data.
Instruction Description
Execution time (E.T.) each instruction given microseconds assumed clock. Total machine cycles indicated with total clock periods States). Also indicated number States each cycle. example: Cycles: States: 7(4,3) MHzE.T.: 1.75 indicates that instruction consists machine cycles. first cycle contains clock periods States). second cycle contains clock periods total clock periods States. instruction executes 1.75 microseconds. Register format indicated each instruction with most-significant left least-significant right.
UM008005-0205 Instruction
User's Manual
8-Bit Load Group
Operation: Code: Operands:
Description: contents register loaded other register identifies registers assembled follows object code: Register Cycles Condition Bits Affected: None Example: register contains number 8AH, register contains 10H, instruction results both registers containing 10H.
States
E.T.
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: 8-bit integer loaded register where identifies register assembled follows object code: Register Cycles Condition Bits Affected: None Example: execution contents register A5H.
States
E.T. 1.75
UM008005-0205
Instruction
User's Manual
(HL)
Operation: Code: Operands: (HL) (HL)
Description: 8-bit contents memory location (HL) loaded register where identifies register assembled follows object code: Register Cycles Condition Bits Affected: None Example: register pair contains number 75A1H, memory address 75A1H contains byte 58H, execution (HL) results register
States
E.T. 1.75
UM008005-0205
Instruction
User's Manual
(IX+d)
Operation: Code: Operands: (IX+d) (IX+d)
Description: operand (IX+d), (the contents Index Register summed with two's complement displacement integer loaded register where identifies register assembled follows object code: Register Cycles Condition Bits Affected: None Example: Index Register contains number 25AFH, instruction (IX+19H) causes calculation 25AFH 19H, which points memory location 25C8H. this address contains byte 39H, instruction results register also containing 39H.
States
E.T. 2.50
UM008005-0205
Instruction
User's Manual
(IY+d)
Operation: Code: Operands: (IY+D) (lY+d)
Description: operand (lY+d) (the contents Index Register summed with two's complement displacement integer loaded register where identifies register assembled follows object code: Register Cycles Condition Bits Affected: None Example: Index Register contains number 25AFH, instruction (IY+19H) causes calculation 25AFH 19H, which points memory location 25C8H. this address contains byte 39H, instruction results register also containing 39H.
States
E.T. 4.75
UM008005-0205
Instruction
User's Manual
(HL),
Operation: Code: Operands: (HL) (HL),
Description: contents register loaded memory location specified contents register pair. symbol identifies register assembled follows object code: Register Cycles Condition Bits Affected: None Example: contents register pair specifies memory location 2146H, register contains byte 29H, execution (HL), memory address 2146H also contains 29H.
States
E.T. 1.75
UM008005-0205
Instruction
User's Manual
(IX+d),
Operation: Code: Operands: (IX+d) (IX+d),
Description: contents register loaded memory address specified contents Index Register summed with two's complement displacement integer. symbol identifies register assembled follows object code: Register Cycles Condition Bits Affected: None Example: register contains byte 1CH, Index Register contains 3100H, then instruction (IX+6H), performs 3100H loads memory location 3106H.
States
E.T. 4.75
UM008005-0205
Instruction
User's Manual
(IY+d),
Operation: Code: Operands: (lY+d) (lY+d),
Description: contents resister loaded memory address specified contents Index Register two's complement displacement integer. symbol specified according following table. Register Cycles Condition Bits Affected: None Example: register contains byte 48H, Index Register contains 2A11H, then instruction (IY+4H), performs 2A11H loads memory location 2A15.
States
E.T. 4.75
UM008005-0205
Instruction
User's Manual
(HL),
Operation: Code: Operands: (HL) (HL),
Description: Integer loaded memory address specified contents register pair. Cycles Condition Bits Affected: None Example: register pair contains 4444H, instruction (HL), results memory location 4444H containing byte 28H. States E.T. 2.50
UM008005-0205
Instruction
User's Manual
(IX+d),
Operation: Code: Operands: (IX+d) (IX+d),
Description: operand loaded memory address specified Index Register two's complement displacement operand Cycles Condition Bits Affected: None Example: Index Register contains number 219AH, instruction (IX+5H), results byte memory address 219FH. States 3,5,3) E.T. 4.75
UM008005-0205
Instruction
User's Manual
(IY+d),
Operation: Code: Operands: (lY+d) (lY+d),
Description: Integer loaded memory location specified contents Index Register summed with two's complement displacement integer Cycles Condition Bits Affected: None Example: Index Register contains number A940H, instruction (IY+10H), results byte memory location A950H. States E.T. 2.50
UM008005-0205
Instruction
User's Manual
(BC)
Operation: Code: Operands: (BC) (BC)
Description: contents memory location specified contents register pair loaded Accumulator. Cycles Condition Bits Affected: None Example: register pair contains number 4747H, memory address 4747H contains byte 12H, then instruction (BC) results byte register States E.T. 1.75
UM008005-0205
Instruction
User's Manual
(DE)
Operation: Code: Operands: (DE) (DE)
Description: contents memory location specified register pair loaded Accumulator. Cycles Condition Bits Affected: None Example: register pair contains number 30A2H memory address 30A2H contains byte 22H, then instruction (DE) results byte register States E.T. 1.75
UM008005-0205
Instruction
User's Manual
(nn)
Operation: Code: Operands: (nn) (nn)
Description: contents memory location specified operands loaded Accumulator. first operand after Code order byte 2-byte memory address. Cycles Condition Bits Affected: None Example: contents number 8832H, content memory address 8832H byte 04H, instruction (nn) byte Accumulator. States E.T. 3.25
UM008005-0205
Instruction
User's Manual
(BC),
Operation: Code: Operands: (BC) (BC),
Description: contents Accumulator loaded memory location specified contents register pair Cycles Condition Bits Affected: None Example: Accumulator contains register pair contains 1212H instruction (BC), results memory location 1212H. States E.T. 1.75
UM008005-0205
Instruction
User's Manual
(DE),
Operation: Code: Operands: (DE) (DE),
Description: contents Accumulator loaded memory location specified contents register pair. cycles Condition Bits Affected: None Example: contents register pair 1128H, Accumulator contains byte A0H, instruction (DE), results memory location 1128H. States E.T. 1.75
UM008005-0205
Instruction
User's Manual
(nn),
Operation: Code: Operands: (nn) (nn),
Description: contents Accumulator loaded memory address specified operand first operand after Code order byte Cycles Condition Bits Affected: None Example: contents Accumulator byte D7H, execution (3141 AD7H results memory location 3141H. States E.T. 3.25
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: contents Interrupt Vector Register loaded Accumulator. Cycles Condition Bits Affected: I-Register negative; reset otherwise I-Register zero; reset otherwise reset contains contents IFF2 reset affected interrupt occurs during execution this instruction, Parity flag contains States E.T. 2.25
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: contents Memory Refresh Register loaded Accumulator. Cycles Condition Bits Affected: R-Register negative; reset otherwise R-Register zero; reset otherwise reset contains contents IFF2 reset affected interrupt occurs during execution this instruction, parity flag contains States E.T. 2.25
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: contents Accumulator loaded Interrupt Control Vector Register, Cycles Condition Bits Affected: None States E.T. 2.25
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: contents Accumulator loaded Memory Refresh register Cycles Condition Bits Affected: None States E.T. 2.25
UM008005-0205
Instruction
User's Manual
16-Bit Load Group
Operation: Code: Operands:
Description: 2-byte integer loaded register pair, where defines register pairs, assembled follows object code: Pair
first operand after Code order byte. Cycles Condition Bits Affected: None Example: execution 5000H contents register pair 5000H. States E.T. 2.50
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: Integer loaded Index Register first operand after Code order byte. Cycles Condition Bits Affected: None Example: instruction 45A2H Index Register contains integer 45A2H. States E.T. 3.50
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: Integer loaded Index Register first operand after Code order byte. Cycles Condition Bits Affected: None Example: instruction 7733H Index Register contains integer 7733H. States E.T. 3.50
UM008005-0205
Instruction
User's Manual
(nn)
Operation: Code: Operands: (nn+1), (nn) (nn)
Description: contents memory address (nn) loaded order portion register pair (register contents next highest memory address (nn+1) loaded high order portion (register first operand after Code order byte Cycles Condition Bits Affected: None Example: address 4545H contains 37H, address 4546H contains A1H, instruction (4545H) register pair contains A137H. States E.T. 4.00
UM008005-0205
Instruction
User's Manual
(nn)
Operation: Code: Operands: (nn+1) (nn) (nn)
Description: contents address (nn) loaded order portion register pair contents next highest memory address (nn+1) loaded high order portion Register pair defines register pairs, assembled follows object code: Pair
first operand after Code order byte (nn). Cycles Condition Bits Affected: None Example: Address 2130H contains 65H, address 2131M contains 78H, instruction (2130H) register pair contains 7865H. States E.T. 5.00
UM008005-0205
Instruction
User's Manual
(nn)
Operation: Code: Operands: (nn+1), (nn) (nn)
Description: contents address (nn) loaded order portion Index Register contents next highest memory address (nn+1) loaded high order portion first operand after Code order byte Cycles Condition Bits Affected: None Example: address 6666H contains 92H, address 6667H contains DAH, instruction (6666H) Index Register contains DA92H. States E.T. 5.00
UM008005-0205
Instruction
User's Manual
(nn)
Operation: Code: Operands: (nn+1), (nn)
Description: contents address (nn) loaded order portion Index Register contents next highest memory address (nn+1) loaded high order portion first operand after Code order byte Cycles Condition Bits Affected: None Example: address 6666H contains 92H, address 6667H contains DAH, instruction (6666H) Index Register contains DA92H. States E.T. 5.00
UM008005-0205
Instruction
User's Manual
(nn),
Operation: Code: Operands: (nn+1) (nn) (nn),
Description: contents order portion register pair (register loaded memory address (nn), contents high order portion (register loaded next highest memory address (nn+1). first operand after Code order byte Cycles Condition Bits Affected: None Example: content register pair 483AH, instruction (B2291-1), address B229H contains 3AH, address B22AH contains 48H. States E.T. 4.00
UM008005-0205
Instruction
User's Manual
(nn),
Operation: Code: Operands: (nn+1) ddh, (nn) (nn),
Description: order byte register pair loaded memory address (nn); upper byte loaded memory address (nn+1). Register pair defines either assembled follows object code: Pair
first operand after Code order byte byte memory address. Cycles Condition Bits Affected: None Example: register pair contains number 4644H, instruction (1000H), results memory location 1000H, memory location 1001H. States E.T. 5.00
UM008005-0205
Instruction
User's Manual
(nn),
Operation: Code: Operands: (nn+1) IXh, (nn) (nn),
Description: order byte Index Register loaded memory address (nn); upper order byte loaded next highest address (nn+1). first operand after Code order byte Cycles Condition Bits Affected: None Example: Index Register contains 5A30H, instruction (4392H), memory location 4392H contains number 30H, location 4393H contains 5AH. States E.T. 5.00
UM008005-0205
Instruction
User's Manual
(nn),
Operation: Code: Operands: (nn+1) IYh, (nn) (nn),
Description: order byte Index Register loaded memory address (nn); upper order byte loaded memory location (nn+1). first operand after Code order byte Cycles Condition Bits Affected: None Example: Index Register contains 4174H instruction (8838H), memory location 8838H contains number 74H, memory location 8839H contains 41H. States E.T. 5.00
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: contents register pair loaded Stack Pointer (SP). Cycles Condition Bits Affected: None Example: register pair contains 442EH, instruction Stack Pointer also contains 442EH. States E.T.
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: 2-byte contents Index Register loaded Stack Pointer (SP). Cycles Condition Bits Affected: None Example: contents Index Register 98DAH, instruction contents Stack Pointer also 98DAH. States E.T. 2.50
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: 2-byte contents Index Register loaded Stack Pointer Cycles Condition Bits Affected: None Example: Index Register contains integer A227H, instruction Stack Pointer also contains A227H. States E.T. 2.50
UM008005-0205
Instruction
User's Manual
PUSH
Operation: Code: Operands: (SP-2) qqL, (SP-1) PUSH
Description: contents register pair pushed external memory LIFO (last-in, first-out) Stack. Stack Pointer (SP) register pair holds 16-bit address current Stack. This instruction first decrements loads high order byte register pair memory address specified decremented again loads order byte memory location corresponding this address operand identifies register pair assembled follows object code: Pair Cycles Condition Bits Affected: None Example: register pair contains 2233H Stack Pointer contains 1007H, instruction PUSH memory address 1006H contains 22H, memory address 1005H contains 33H, Stack Pointer contains 1005H.
States
E.T. 2.75
UM008005-0205
Instruction
User's Manual
PUSH
Operation: Code: Operands: (SP-2) IXL, (SP-1) PUSH
Description: contents Index Register pushed external memory LIFO (last-in, first-out) Stack. Stack Pointer (SP) register pair holds 16-bit address current Stack. This instruction first decrements loads high order byte memory address specified then decrements again loads order byte memory location corresponding this address Cycles Condition Bits Affected: None Example: Index Register contains 2233H Stack Pointer contains 1007H, instruction PUSH memory address 1006H contains 22H, memory address 1005H contains 33H, Stack Pointer contains 1005H. States E.T. 3.75
UM008005-0205
Instruction
User's Manual
PUSH
Operation: Code: Operands: (SP-2) IYL, (SP-1) PUSH
Description: contents Index Register pushed external memory LIFO (last-in, first-out) Stack. Stack Pointer (SP) register pair holds 16-bit address current Stack. This instruction first decrements loads high order byte memory address specified then decrements again loads order byte memory location corresponding this address Cycles Condition Bits Affected: None Example: Index Register contains 2233H Stack Pointer Contains 1007H, instruction PUSH memory address 1006H contains 22H, memory address 1005H contains 33H, Stack Pointer contains 1005H. States E.T. 3.75
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands: (SP+1), (SP)
Description: bytes external memory LIFO (last-in, first-out) Stack popped register pair Stack Pointer (SP) register pair holds 16-bit address current Stack. This instruction first loads order portion byte memory location corresponding contents then incriminated contents corresponding adjacent memory location loaded high order portion incriminated again. operand identifies register pair assembled follows object code: Pair Cycles Condition Bits Affected: None Example: Stack Pointer contains 1000H, memory location 1000H contains 55H, location 1001H contains 33H, instruction results register pair containing 3355H, Stack Pointer containing 1002H.
States
E.T. 2.50
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands: (SP+1), (SP)
Description: bytes external memory LIFO (last-in, first-out) Stack popped Index Register Stack Pointer (SP) register pair holds 16-bit address current Stack. This instruction first loads order portion byte memory location corresponding contents then incremented contents corresponding adjacent memory location loaded high order portion incremented again. Cycles Condition Bits Affected: None Example: Stack Pointer contains 1000H, memory location 1000H contains 55H, location 1001H contains 33H, instruction results Index Register containing 3355H, Stack Pointer containing 1002H. States E.T. 3.50
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands: (SP-X1), (SP)
Description: bytes external memory LIFO (last-in, first-out) Stack popped Index Register Stack Pointer (SP) register pair holds 16-bit address current Stack. This instruction first loads order portion byte memory location corresponding contents then incremented contents corresponding adjacent memory location loaded high order portion incremented again. Cycles Condition Bits Affected: None Example: Stack Pointer Contains 1000H, memory location 1000H contains 55H, location 1001H contains 33H, instruction results Index Register containing 3355H, Stack Pointer containing 1002H. States E.T. 3.50
UM008005-0205
Instruction
User's Manual
Exchange, Block Transfer, Search Group
Operation: Code: Operands:
Description: 2-byte contents register pairs exchanged. Cycles Condition Bits Affected: None Example: content register pair number 2822H, content register pair number 499AH, instruction content register pair 499AH, content register pair 2822H. States E.T. 1.00
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands:
Description: 2-byte contents register pairs exchanged. Register pair consists registers Cycles Condition Bits Affected: None Example: content register pair number 9900H, content register pair number 5944H, instruction contents 5944H, contents 9900H. States E.T. 1.00
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands: (BC) (BC'), (DE) (DE'), (HL) (HL')
Description: Each 2-byte value register pairs exchanged with 2-byte value BC', DE', HL', respectively. Cycles Condition Bits Affected: None Example: contents register pairs numbers 445AH, 3DA2H, 8859H, respectively, contents register pairs BC', DE', 0988H, 9300H, 00E7H, respectively, instruction contents register pairs follows: contains 0988H; contains 9300H; contains 00E7H; contains 445AH; contains 3DA2H; contains 8859H. States E.T. 1.00
UM008005-0205
Instruction
User's Manual
(SP),
Operation: Code: Operands: (SP+1), (SP) (SP),
Description: order byte contained register pair exchanged with contents memory address specified contents register pair (Stack Pointer), high order byte exchanged with next highest memory address (SP+1). Cycles Condition Bits Affected: None Example: register pair contains 7012H, register pair contains 8856H, memory location 8856H contains byte 11H, memory location 8857H contains byte 22H, then instruction (SP), results register pair containing number 2211H, memory location 8856H containing byte 12H, memory location 8857H containing byte Stack Pointer containing 8856H. States E.T. 4.75
UM008005-0205
Instruction
User's Manual
(SP),
Operation: Code: Operands: (SP+1), (SP) (SP),
Description: order byte Index Register exchanged with contents memory address specified contents register pair (Stack Pointer), high order byte exchanged with next highest memory address (SP+1). cycles Condition Bits Affected: None Example: Index Register contains 3988H, register pair Contains 0100H, memory location 0100H contains byte 90H, memory location 0101H contains byte 48H, then instruction (SP), results register pair containing number 4890H, memory location 0100H containing 88H, memory location 0101H containing 39H, Stack Pointer containing 0100H. States E.T. 5.75
UM008005-0205
Instruction
User's Manual
(SP),
Operation: Code: Operands: (SP+1), (SP) (SP),
Description: order byte Index Register exchanged with contents memory address specified contents register pair (Stack Pointer), high order byte exchanged with next highest memory address (SP+1). Cycles Condition Bits Affected: None Example: Index Register contains 3988H, register pair contains 0100H, memory location 0100H contains byte 90H, memory location 0101H contains byte 48H, then instruction (SP), results register pair containing number 4890H, memory location 0100H containing 88H, memory location 0101H containing 39H, Stack Pointer containing 0100H. States E.T. 5.75
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands: (DE) (HL), (SP),
Description: byte data transferred from memory location addressed, contents register pair memory location addressed contents register pair. Then both these register pairs incremented (Byte Counter) register pair decremented. Cycles Condition Bits Affected: affected affected reset reset otherwise reset affected Example: register pair contains 1111H, memory location 1111H contains byte 88H, register pair contains 2222H, memory location 2222H contains byte 66H, register pair contains then instruction results following contents register pairs memory addresses: (1111H) (2222H)
UM008005-0205
States
E.T. 4.00
contains 1112H contains contains 2223H contains contains
Instruction
User's Manual
LDIR
Operation: Code: Operands: (DE) (HL), LDIR
Description: This 2-byte instruction transfers byte data from memory location addressed contents register pair memory location addressed register pair. Both these register pairs incremented (Byte Counter) register pair decremented. decrementing causes zero, instruction terminated. zero, program counter decremented instruction repeated. Interrupts recognized refresh cycles executed after each data transfer. When zero prior instruction execution, instruction loops through Kbytes. Cycles Cycles Condition Bits Affected: affected affected reset reset reset affected States E.T. 4.00 States E.T. 5.25
UM008005-0205
Instruction
User's Manual
Example:
register pair contains 11111H, register pair contains 2222H, register pair contains 0003H, memory locations have these contents: (1111H) contains (1112H) contains (1113H) contains (2222H) contains (2223H) contains (2224H) contains
then execution LDIR contents register pairs memory locations are: (1111H) (1112H) (1113H) contains contains contains contains contains contains
1114H 2225H 0000H
(2222H) (2223H) (2224H)
contains contains contains
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands: (DE) (HL), HL-1, BC-1
Description: This 2-byte instruction transfers byte data from memory location addressed contents register pair memory location addressed contents register pair. Then both these register pairs including (Byte Counter) register pair decremented. Cycles Condition Bits Affected: affected affected reset reset otherwise reset affected Example: register pair contains 1111H, memory location 1111H contains byte 88H, register pair contains 2222H, memory location 2222H contains byte 66H, register pair contains then instruction results following contents register pairs memory addresses: (1111H) (2222H)
UM008005-0205
States
E.T. 4.00
contains 1110H contains contains 2221H contains contains
Instruction
User's Manual
LDDR
Operation: Code: Operands: (DE) (HL), HL-1, BC-1 LDDR
Description: This 2-byte instruction transfers byte data from memory location addressed contents register pair memory location addressed contents register pair. Then both these registers, well (Byte Counter), decremented. decrementing causes zero, instruction terminated. zero, program counter decremented instruction repeated. Interrupts recognized refresh cycles execute after each data transfer. When zero, prior instruction execution, instruction loops through Kbytes. Cycles Cycles Condition Bits Affected: affected affected reset reset reset
UM008005-0205 Instruction
States
E.T. 5.25
States
E.T. 4.00
User's Manual
Example:
register pair contains 1114H, register pair contains 2225H, register pair contains 0003H, memory locations have these contents: (1114H) contains (1113H) contains (1112H) contains (2225H) contains (2224H) contains (2223H) contains
Then execution LDDR contents register pairs memory locations are: (1114H) (1113H) (1112H) contains contains contains contains contains contains
1111H 2222H 0000H
(2225H) contains (2224H) contains (2223H) contains
UM008005-0205
Instruction
User's Manual
Operation: Code: Operands: (HL),
Description: contents memory location addressed register compared with contents Accumulator. case true compare, condition set. Then incremented Byte Counter (register pair decremented. Cycles Condition Bits Affected: result negative; reset otherwise (HL); reset otherwise borrow from reset otherwise reset otherwise affected Example: register pair contains 1111H, memory location 1111H contains 3BH, Accumulator contains 3BH, Byte Counter contains 0001H. execution Byte Counter contains 0000H, register pair contains 1112H, flag register sets, flag register resets. There effect contents Accumulator address 1111H. States E.T. 4.00
UM008005-020
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