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UG112 (v3.2) March 2009 [optional]
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UG112 (v3.2) March 2009
Revision History
following table shows revision history this document.
Date 01/31/04 02/04/05 05/31/06 05/18/07
Version Initial release Added Pb-free packaging information.
Revision
Extensive updates material added. Updated "Material Data Declaration Sheet (MDDS)" Chapter revised link "Xilinx Packaging Material Content Data Standard PB-Free Packages". Revised "Part Marking" Chapter added "Ordering Information", "Marking Template", Table 1-1: "Example Part Numbers (FPGA, CPLD, PROM)", Table 1-2: "Xilinx Device Marking Definition-Example". Updated "Flip-Chip Packages" Chapter added content "Package Construction" clarify Type Type usage. Updated "Thermal Management Thermal Characterization Methods Conditions" Chapter removed "Junction-to-Board Measurement JB", added link "Data Acquisition Package Thermal Database", added Figure 3-5, page "Package Thermal Data Query Device-Specific Data" (query tool replaces Table 3-1: "Summary Thermal Resistance Packages", which removed). Updated "Recommended Design Rules BGA, CSP, CCGA Packages," page added missing values CP56 CP132 packages corrected SF363 package specification value Table 5-3, page Added CS48 Table 5-4, page Updated Table 6-2, page include ratings Pb-free packages. Updated "Package Peak Reflow Temperature" Chapter correction peak reflow temperature. Added post-wash bake details "Post Reflow Washing" section.
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Device Package User Guide
Date 12/18/08
Version
Revision Added link Package Thermal Data Query Tool xilinx.com. Updated remaining external links. Added Spartan®-3A information Table 1-1, page Added these packages Table 2-3, page FG484 FGG484. Added these packages Table 5-3, page SFG363, FF676, FGG484, FFG676, FT64 FTG64. Removed these packages from Table 5-3, page FF896, FFG896, FF1704, FFG1704, FF1696 FFG1696. Added these packages Table 5-4, page CS484 CSG484.
03/17/09
Revised "Small Form Factor Packages," page include description third template used marking small form factor packages. Revised "Package Construction," page describe flip-chip package vent hole locations. Added missing Pb-free packages Table 1-3, page Revised mass FG676 FGG676 packages Table 1-3, page Added CS484 CSG484 information Table 1-3, page Table 2-3, page Added FF1136 FFG1136 tray information Table 2-3, page Changed link from DS529 UG331 third paragraph "Data Acquisition Package Thermal Database," page Added CS484 electrical data Table 4-1, page Added note Table 5-3, page referring UG195. Revised humidity value third paragraph "Dry Bake Recommendation Policy," page 105. Revised humidity value first fourth paragraph "Expiration Date," page 105. Updated links Table A-1, page 119.
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UG112 (v3.2) March 2009
Table Contents
Revision History
Chapter Package Information
Package Overview
Introduction Xilinx Packaging Packaging Technology Xilinx. Package Drawings Material Data Declaration Sheet (MDDS)
Package Samples Specifications Definitions
Inches Millimeters Pressure Handling Capacity Clockwise Counterclockwise Cavity-Up Cavity-Down
Part Marking
Ordering Information Marking Template
Package Technology Descriptions
Pb-Free Packaging Cavity-Up Plastic Packages. Cavity-Down Thermally Enhanced Packages Flip-Chip Packages Assembling Flip-Chip BGAs Chip Scale Packages Quad Flat No-Lead (QFN) Packages Ceramic Column Grid Array (CCGA) Packages Thermally Enhanced Lead Frame Packaging
Package Mass Table
Chapter Pack Ship
Introduction Tape Reel
Benefits Cover Tape Reel Code Label Shipping Standard Code Label Locations
Tubes Trays
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Chapter Thermal Management Thermal Characterization Methods Conditions
Introduction Thermal Management Package Thermal Characterization Methods Conditions
Characterization Methods Calibration Isolated Diode Simulation Methods. Measurement Standards Definition Terms Junction-to-Reference General Setup Junction-to-Case Measurement Junction-to-Top Measurement Junction-to-Ambient Measurement Thermal Resistance: Junction-to-Board Data Acquisition Package Thermal Database
Support Compact Thermal Models (CTM) Application Thermal Resistance Data Thermal Data Usage
Example Example Heatsink Calculation
Thermal Data Comparison Some Power Management Options System Simulation Support
Chapter Package Electrical Characteristics
Introduction Terminology Definitions Reviews
Resistance Inductance Capacitance (C). Conductance (G). Impedance (Z). Time Delay (Td) Crosstalk Ground Bounce Signal Integrity Package Performance Review Practical Measurements Package Sample Fixture Preparation. Software-Based Simulations Extractions Package Electrical Data Delivery Formats Data Examples Models Xilinx Electrical Data Delivery Models Further Explanations Model Data Terminology
Electrical Data Generation Measurement Methods
References
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Device Package User Guide UG112 (v3.2) March 2009
Chapter Recommended Design Rules
Recommended Design Rules Packages Recommended Design Rules TSOP/TSSOP Packages Recommended Design Rules BGA, CSP, CCGA Packages Board Routability Guidelines with Xilinx Fine-Pitch Packages
Board Level Routing Challenges Board Routing Strategy Board Routing Examples Pattern Design Surface-Mount Considerations Packages Patterns Thermal Design Solder Masking Considerations Stencil Design Perimeter Pads Stencil Design Thermal Types Solder Voiding Stencil Thickness Solder Paste References
Recommended Design Rules Packages
Chapter Moisture Sensitivity PSMCs
Moisture-Induced Cracking During Solder Reflow Factory Floor Life Bake Recommendation Policy Handling Parts Sealed Bags
Inspection Storage Expiration Date Other Conditions
Assigned Package MSL.
Chapter Reflow Soldering Process Guidelines
Solder Reflow Process
Package Peak Reflow Temperature
Soldering Problems Summary
Typical Conditions Reflow Soldering
Implementing Optimizing Solder Reflow Process Packages
Reflow Ovens Reflow Process Methods Measuring Profiles Reflow Profiling Post Reflow Washing Reworking Flip-Chip BGAs Reballing Conformal Coating Post Assembly Handling Heat Sink Removal Procedure Package Pressure Handling Capacity
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References
Reflow Profile
Appendix: Additional Information
Table Socket Manufacturers Sites Heatsink Sources Sites Interface Material Sources Related Xilinx Sites Links Xilinx Packaging Application Notes
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Device Package User Guide UG112 (v3.2) March 2009
Chapter
Package Information
Package Overview
Introduction Xilinx Packaging
Electronic packages interconnectable housings semiconductor devices. major functions electronic packages provide electrical interconnections between board efficiently remove heat generated device. Feature sizes constantly shrinking, resulting increased number transistors being packed into device. Today's submicron technology also enabling large-scale functional integration system-on-a-chip solutions. order keep pace with these advancements silicon technologies, semiconductor packages have also evolved provide improved device functionality performance. Feature size device level driving package feature sizes down design rules early transistors. meet these demands, electronic packages must flexible address high counts, reduced pitch form factor requirements. same time, packages must reliable cost effective.
Packaging Technology Xilinx
Xilinx provides wide range leaded array packaging solutions advanced silicon products. Xilinx® advanced packaging solutions include overmolded plastic ball grid arrays (PBGA), small form factor Chip Scale Packages, "Cavity-Down" BGAs, flip-chip BGAs, flip-chip ceramic column grid arrays (CCGA), well newer lead frame packages such Quad Flat No-Lead (QFN) packages meet various counts density requirements. Packages from Xilinx designed, optimized, characterized support long-term mechanical reliability requirements well support cutting-edge electrical thermal performance requirements highspeed advanced FPGA products.
Pb-free Packaging Solutions from Xilinx
Xilinx also develops packaging solutions that safer environment. Today, standard packages from Xilinx contain substances that identified harmful environment including cadmium, hexavalent chromium, mercury, PBB, PBDE. Pbfree solutions take that step further also contain lead (Pb). This makes Pbfree solutions from Xilinx RoHS (Reduction Hazardous Substances) compliant. Pb-free packages from Xilinx also JEDEC J-STD-020 compliant, meaning that packages made more robust they capable withstanding higher reflow temperatures. Xilinx ready support industry requirements Pb-free packaging solutions.
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Package Drawings
Package drawings mechanical specifications that include exact dimensions placement pins, height package, related information. Package drawings available online
Material Data Declaration Sheet (MDDS)
MDDS template used Xilinx based Electronic Industries Alliance (EIA) September Material Composition Declaration Guide dated September 2003 Level Level materials interest. EIA, "Level List composed materials substances subject currently enacted legislation that: Prohibits their and/or marketing Restricts their and/or marketing Requires reporting results other regulatory effect.
EIA, "Level List composed materials substances that industry determined relevant disclosure because they meet more following criteria: Precious materials/substances that provide economic value end-of-life management purposes Materials/substances that significant environmental, health, safety interest Materials/substances that would trigger hazardous waste management requirements
Materials/substances that could have negative impact end-of-life management. standard more specific information. Xilinx Packaging Material Content Data Standard (non Pb-free) Pb-Free/RoHS packages found
Package Samples
Xilinx offers types non-product-specific package samples that help develop custom processes perform board-level tests. These samples ordered with ordering codes detailed below. Mechanical Samples XCMECH-XXXXX (where XXXXX package code interest) This part type used mechanical evaluations, process setup, etc. Most packages based JEDEC outline, these parts times referred "dummy" parts since mechanical samples contain die. Example: order FG676 package mechanical sample (without die), part number would XCMECH-FG676. Daisy Chain Samples XCDAISY-XXXXX (where XXXXX package code interest)
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Device Package User Guide UG112 (v3.2) March 2009
this part type perform board-based evaluations (such vibrations temperature cycles) well solder balls withstand these mechanical conditions. Xilinx daisy chain parts (XCDAISY-XXXXX), specific ball assignment chain available. have board already made, default chain. purchase these parts from Xilinx through standard sales outlets. Xilinx does support unique chains because these parts have volume justify development effort. Example: order FG676 package daisy-chained configuration, part number would XCDAISY-FG676.
Specifications Definitions
Inches Millimeters
JEDEC standards PLCC, CQFP, packages define package dimensions inches. lead spacing specified mils, mils, mils (0.025 in., 0.050 0.100 in.). JEDEC standards PQFP, HQFP, TQFP, VQFP, CSP, packages define package dimensions millimeters. lead frame packages have lead spacings 0.65 packages have ball pitches 1.00 1.27 Because potential measurement discrepancies, this Data Book provides measurements controlling standard only, either inches millimeters.
Pressure Handling Capacity
mounted packages, including flip chips, direct compressive (non-varying) force applied normally package with tool head that coincides with slightly bigger) will induce mechanical damage device including external balls, provided force over grams external ball, device board supported prevent flexing bowing. These components tested sockets with loads gm/ball range short durations. Analysis using 10g/ball (e.g., FF1148) showed little impact shortterm some creep over time. gm/ball gm/ball loads over week period shown beginning bridging some outer balls; these were static load tests. component survive forces greater than limit while short-term situations. However, sustained higher loads should avoided (particularly they overlaid with thermal power cycle loads). Within recommended limits, circuit board needs properly supported prevent flexing resulting from force application. flexing bowing resulting from such force likely damage package-to-board connections. Besides damage that occur from bending, only major concern long-term creep bulging solder balls compression cause bridging. life part, staying below recommended limit will ensure against that remote possibility.
Clockwise Counterclockwise
orientation package orientation package board affect board layout. PLCC PQFP packages specify pins counterclockwise direction, when viewed from package (the surface with
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Xilinx logo). PLCCs have center beveled edge while other packages have corner, with exception: 100-pin 165-pin CQFPs (CB100 CB164) XC3000 devices have center edge. CQFP packages specify pins clockwise direction, when viewed from package. user make pins counterclockwise forming leads such that logo mounts against board. However, heat flow surrounding impaired logo mounted down.
Cavity-Up Cavity-Down
Most Xilinx devices attach against inside bottom package (the side that does carry Xilinx logo). Called "Cavity-Up," this been standard assembly method over years. This method does provide best thermal characteristics. Grid Arrays (greater than pins), copper based packages, Ceramic Quad Flat Packs assembled "Cavity-Down," with attached inside package, optimal heat transfer ambient air. More information Xilinx's "Cavity-Up" packages "Cavity-Down" packages found "Package Technology Descriptions" section. most packages this information does affect package used because user choice package mounted board. Ceramic Quad Flat Pack (CQFP) packages however, leads formed either side. Therefore, best heat transfer surrounding air, CQFP packages should mounted with logo facing away from board.
Part Marking
Ordering Information
example ordering code Xilinx FPGA XC4VLX60-10FFG668CS2. ordering code stands for: XC4VLX Family (Virtex®-4 Number system gates logic cells (60,000 logic cells) Speed grade (-10 speed) Package type (Pb-free flip-chip BGA) number pins (668 pins) Temperature grade (Commercial) Step Other examples shown Table 1-1. Table 1-1: Example Part Numbers (FPGA, CPLD, PROM)
Family Virtex-5 Virtex-5 Virtex-5 Virtex-4 Part Number XC5VLX## XC5VLX##T XC5VSX##T XC4VLX## Sample Ordering Code XC5VLX110 FFG676C XC5VLX330T-1FF1738I XC5VSX35T-2FF665C XC4VLX25 FF668C
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Device Package User Guide UG112 (v3.2) March 2009
Table 1-1:
Example Part Numbers (FPGA, CPLD, PROM) (Cont'd)
Family Part Number XC4VSX## XC2VP## XC2V## XCV##E XCV## XC3S## XC3S##A XC3S##E XC2S## XC2S##E XC3Sx###AN XC3SD####A XCS## XCS##XL XC4##E XC4##XL XC2C## XCR##XL XC95##XV XC95##XL XC95## Sample Ordering Code XC4VSX55 FF1148C XC2VP7 FG456C XC2V1000 FG456C XCV300E PQ240C XCV300 PQ240C XC3S1000 FG676C XC3S50A FTG256C XC3S250E FT256C XC2S50 PQ208C XC2S50E PQ208C XC3S400AN-4FG400I XC3SD1800A-4CS484LI XCS20 PQ208C XCS20XL PQ208C XC4013E HQ240C XC4013XL PQ208C XC2C256 PQ208C XCR3512XL PQ208C XC9536XV VQ44I XC9572XL TQ100C XC95216 HQ208C
Virtex-4 Virtex-II Virtex-II Virtex-E Virtex Spartan®-3 Spartan-3A Spartan-3E Spartan-II Spartan-IIE Spartan-3AN Spartan-3A Spartan Spartan-XL 4000E 4000XL CoolRunnerTM-II CoolRunner (XPLA3) 9500XV 9500XL 9500
Notes:
Automotive parts "XA" instead "XC". QML-certified parts "XQ" instead "XC". Aerospace parts have after "XQ" instead "XC".
Examples
CPLD Ordering Information
example ordering number Xilinx CPLD XC2C256-7PQ108I, defined follows: XC2C Family (CoolRunner-II) Number macrocells (256 macrocells) Speed grade speed) Package type (Plastic Quad Flat Pack) Number pins (208 pins)
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Temperature grade (Industrial)
PROM Ordering Information
example ordering number Xilinx PROM XC18V04VQ44C, defined follows: XC18V Family 1800 (ISP) PROM PROM size (18V00, 17V00, 1700E/L) equivalent Spartan-II Spartan-IIE device (17S00A/XL/L), storage capacity Package type (Plastic Quad Flat Pack) Number pins pins) Temperature grade (commercial) determine valid ordering combinations given device, consult device data sheet. Data sheets available
Marking Template
Large Form Factor Packages
December 1995, Product Change Notice (PCN) 95013 issued acknowledge change Xilinx standard package marking. view this notice Xilinx part marking follows generalized marking templates that different small large packages. Within each group, some minor variations exist device family branding. large package template (Figure 1-1) consists Xilinx Logo, family brand logo, lines information.
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Device Package User Guide UG112 (v3.2) March 2009
X-Ref Target Figure
Device Type Package
XC5VLX50T
FFG1136xxxXXXX DxxxxxxxA
Date Code Code Engineering Sample
Speed Grade
Operating Range
ug112_c1_01_021909
Figure 1-1: Table 1-2:
Marking (for large device packages)
Xilinx Device Marking Definition-Example
Description Xilinx logo, Xilinx name with trademark, trademark-registered status. Product family name with trademark trademark-registered status. This line optional could appear blank. Device type. Package type count, circuit design revision, location code wafer fab, geometry code, date code.
Item Corporate Logo Family Brand Logo Line
Line
third letter package type indicates Pb-free RoHS compliant package. more details Xilinx Pb-Free RoHS Compliant Products, see: alphanumeric characters assembly, lot, step information. last digit usually stepping version does exist. Device speed grade temperature range. grade marked package, product considered commercial grade. Other variations line:
Line
Line
1C-xxxx 1C-ES
xxxx indicates device. special ordering code that always marked device mark. indicates Engineering Sample.
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Small Form Factor Packages
second template used smaller packages that have enough room lines marking. This marking used mainly PROMs, found some mediumsize packages well. Line Product name code, eight characters. Five characters (for example, 1765D) designate product name representation (usually name without "XC"). name followed PROM package designator (usually single character). last letter represents temperature range (for example, Line numeric characters preceded Xilinx logo. first numeric character after designates last digit year which product assembled. This digit will same every years. next numeric characters identify assembly work week. last three characters final three digits Assembly number lot. Line This line usually left blank customer PROM designator marking. third template used CPLD Spartan FPGA small form factor packages. Information provided four lines. Line Product name code (without XC). example, 9536XL 3S250E preceded Xilinx logo. Line Consists alphanumeric characters. first character letter that represents manufacturing location. next five numeric characters number. last four numeric characters four digit date code YYWW format. Line Indicates country origin. Line Consists about seven alphanumeric characters. first characters CPLD Spartan FPGA package designator followed three letter mask code. last characters speed temperature range.
Package Technology Descriptions
Pb-Free Packaging
Recent legislative directives corporate driven initiatives around world have called elimination other hazardous substances electronics used many sectors electronics industry. Pb-free program Xilinx established 1999 proactive effort develop qualify suitable material sets processes Pb-free applications. Xilinx taken leadership position quickly forming partnerships with customers, suppliers, participating industry consortiums provide technical solutions that aligned with industry requirements.
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Device Package User Guide UG112 (v3.2) March 2009
Pb-free Material
Xilinx researched alternatives compounds selected matte lead finish lead-frame packages SnAgCu solder balls packages. addition, suitable material sets chosen qualified higher reflow temperatures (245oC 260oC) that required Pb-free soldering processes. Pb-free products from Xilinx designated with additional package designator portion part number. example, FGG1152 Pb-free version FG1152.
Features
RoHS compliant Compliant JEDEC-J-STD-020 standard peak reflow temperature (245oC 260oC) Packages marked with Pb-free identifier
Backward Compatibility
Backward compatibility, described this chapter, refers only soldering process. Pb-free devices from Xilinx have same form, function standard Pb-based products. changes required board design when using Pb-free products from Xilinx. However, finish materials boards need adjusted. Lead frame packages (PQG, TQG, VQG, PCG, QFG, etc.) from Xilinx backward compatible, meaning that component soldered with Sn/Pb solder using Sn/Pb soldering process. Lead-frame packages from Xilinx matte plating leads which compatible with both Pb-free soldering alloys Sn/Pb soldering alloy. packages (CPG, FTG, FGG, BGG, etc.), however, recommended soldered with SnPb solder using Sn/Pb soldering process. traditional Sn/Pb soldering process usually peak reflow temperature 205oC 220oC. this temperature range, SnAgCu solder balls properly melt soldering surfaces. result, reliability assembly yields compromised. more information Xilinx Pb-free solutions, refer more information Pb-free reflow process, refer XAPP427.
Whisker Mitigation
Following some efforts Xilinx making mitigate whiskering Pb-free lead-frame packages (non-BGA): whisker growth mitigation practices are: Annealing matte hour 150°C within hours after plating Minimum thicker plating thickness micro inches micro meter)
Xilinx assembly subcontractors comply with JEDEC standards whisker test conditions outlined JESD22A121.01 (May 2005) JESD201 (March 2006) 100% matte plating over bare lead frame
lead finish method Xilinx Pb-Free lead-frame product
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Cavity-Up Plastic Packages
plastic package technology that utilizes area array solder balls bottom package make electrical contact with system circuit board. area array format solder balls reduces package size considerably when compared leaded products. also results improved electrical performance well having higher manufacturing yields. substrate made mutilayer (bismaleimide triazene) epoxy-based material. Power ground pins grouped together signal pins assigned perimeter format ease routing board. package offered format contains wirebonded device that covered with mold compound.
Package Construction
X-Ref Target Figure
Plastic Mold
Plated Copper Conductor
Soldermask
Thermal Vias
(PCB Laminate)
Solder Ball
UG112_c1_02_111508
Figure 1-2:
Cavity-Up Ball Grid Array Package
shown cross section Figure 1-2, package contains wire bonded single-core printed circuit board with overmold. Beneath thermal vias which dissipate heat through portion solder ball array ultimately into power ground planes system circuit board. This thermal management technique provides better thermal dissipation than standard PQFP package. Metal planes also distribute heat across entire package, enabling 15-20% decrease thermal resistance case.
Features/Advantages Xilinx Cavity-Up Packages
High board assembly yield since board attachment process self-centering compatible, resulting minimum capital investment Extendable multichip modules profile small footprint Improved electrical performance (short wire length) Enhanced thermal performance Excellent board level reliability
Cavity-Down Thermally Enhanced Packages
Copper-based cavity-down BGAs high-performance, low-profile packages that offer superior electrical thermal characteristics. This technology especially applicable high-speed, high-power semiconductors such Xilinx's Virtex device family.
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Package Construction
Figure depicts cross-section cavity-down package. should noted that this solid construction without internal cavity. backside attached directly copper heat spreader conducts heat package through epoxy attach adhesive. larger size package body size, better thermal performance. incorporation copper heat spreader also results thermal resistance values that lowest among packages offered Xilinx. Attached heatspreader copper stiffener with cavity accommodate die. Along with heatspreader, this stiffener provides mechanical flexural strength warpage control package. exposed surface stiffener laminate build-up structure that contains circuit traces, power ground planes any, sites connecting solder balls. laminate made either glass-reinforced high-glass transition temperature (Tg) bismaleimide triazine (BT) build-up structure. Xilinx uses laminate with four layers, including planes.
Features/Advantages Xilinx Cavity-Down BGAs
Lowest thermal resistance 13°C/W) Superior electrical performance profile light weight construction Excellent board-level reliability
Heatspreader Attach Adhesive
X-Ref Target Figure
Ring
Substrate
Gold Wire
Encapsulant
Solder Ball
UG112_c1_03_111508
Figure 1-3:
Cavity-Down Package
Flip-Chip Packages
Flip chip packaging interconnect technology that replaces peripheral bond pads traditional wirebond interconnect technology with area array interconnect technology die/substrate interface. bond pads either redistributed surface some very limited cases, they directly dropped from core surface. Because this inherent distribution bond pads surface device, more bond pads I/Os packed into device.
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X-Ref Target Figure
UG112_c1_04_111508
Figure 1-4:
Eutectic Bumps
Xilinx flip-chip package offered Xilinx high-performance FPGA products. Unlike traditional packaging which attached substrate face connection made using wire, solder bumped flip-chip flipped over placed face down, with conductive bumps connecting directly matching metal pads laminate substrate. Unlike traditional packaging technology which interconnection between substrate made possible using wire, flip chip utilizes conductive bumps that placed directly area array pads surface. area array pads contain wettable metallization solders (either eutectic high lead) where controlled amount solder deposited either plating screen-printing. These parts then reflowed yield bumped dies with relatively uniform solder bumps over surface device. device then flipped over reflowed ceramic organic laminate substrate. solder material molten stage self-aligning produces good joints even chips placed offset substrates. After soldered substrate, (standoff) formed between chip substrate filled with organic compound called underfill. underfill type epoxy that helps distribute stresses from these solder joints surface whole hence improve reliability fatigue performance these solder joints. This interconnect technology emerged applications related high performance communications, networking computer applications well consumer applications where miniaturization, high count, good thermal performance attributes.
Package Construction
Flip-chip packages high-performance applications built high-density multi-layer organic laminate substrates. Because flip-chip bump pads area array configuration, requires very fine lines geometry substrates able successfully route signals from periphery substrates. Multilayer build-up structures offer this layout flexibility flip-chip packages. Figure Figure show cross-section views package constructions. Note that types lids used assemble flip-chip packages; type lids shown with flat top) type lids shown Figure with hat-type top), depending package type. package drawing specification determine type used specific packages,
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X-Ref Target Figure
Underfill Epoxy
Flip Chip Solder Bump
Thermal Interface Material
Copper Heatspreader
Adhesive Epoxy*
Silicon
Solder Ball
Organic Build-up Substrate
UG112_c1_05_111508
Figure 1-5:
X-Ref Target Figure
Flip-Chip Package with Type
Copper Heatspreader
Flip Chip Solder Bump
Thermal Interface Underfill Material Epoxy
Adhesive Epoxy*
Silicon
Solder Ball
Organic Build-up Substrate
UG112_c1_06_111508
Figure 1-6:
Flip-Chip Package With Type
Xilinx flip-chip packages hermetically sealed, exposure cleaning solvents excessive moisture during board assembly pose serious package reliability concerns. Small vents placed design between heatspreader (lid) organic substrate allow outgassing moisture evaporation. These vent holes located middle four sides flip-chip packages. only exception would flipchip packages which vent holes dictated chip-cap placement, which varies based device. Solvents other corrosive chemicals seep through these vents attack organic materials components inside package strongly discouraged during board assembly Xilinx flip-chip packages.
Features/Advantages Flip-Chip Packages
Easy access core power/ground, resulting better electrical performance Excellent thermal performance (direct heatsinking backside die) Higher density since bond pads area array format Higher frequency switching with better noise control
Assembling Flip-Chip BGAs
Xilinx flip-chip BGAs conform JEDEC body sizes footprint standards. These packages follow moisture level classification plastic surface mount components
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(PSMC). Standard surface mount assembly process should used with consideration slightly higher thermal mass these packages. Like other components, flip-chip assembly involves following process: screen printing, solder reflow, post reflow washing. following will serve guideline assemble flip-chip BGAs onto PCBs.
Screen Printing Machine Parameters
Below example parameters that were used screen printing process. Note that these optimized parameters. Optimized parameters depend user's applications setup. Equipment: Ultraprint 2000 Squeegee Type: Metal Squeegee Angle: Squeegee Pressure: lbs/sq. Squeegee Speed: in/second Print Cycle: pass Stencil Snap Off: 0.10 inches Stencil Lift Speed: Slow
Screen Printing Process Parameters
Solder paste: Alpha Metals WS609 (water soluble) Stencil aperture: 0.0177 inches diameter Stencil thickness: 0.006 inches Aperture creation: Laser
highly recommended either no-clean solder paste water soluble solder paste. cleaning required, then water soluble solder paste should used.
Chip Scale Packages
Chip Scale Packages have emerged dominant packaging option meeting demands miniaturization while offering improved performance. Applications Chip Scale Packages targeted portable consumer products where real estate utmost importance, miniaturization key, power consumption/dissipation must low. Chip Scale Package defined package that fits definition being between times area that package contains while having pitch less than employing Xilinx's packages, system designers dramatically reduce board real estate increase counts.
Package Construction
Although there currently more than different types CSPs available market, Xilinx packages fall into categories, shown Figure 1-7: Flex-based substrates Rigid BT-based substrates. Although, both types meet reliability requirement component board level, BT-based substrate chosen newer devices because large vendor base producing/supporting BT-based substrates.
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Features/Advantages Packages
extremely small form factor which significantly reduces board real estate such applications PCMCIA cards, portable wireless designs, add-in cards Lower inductance lower capacitance absence thin, fragile leads found other packages very thin, light-weight package
X-Ref Target Figure
Attach
Molding Compond
Attach
Molding Compond
Resin
Solder Ball
Solder Mask
Plated
Polyimide Tape
Copper Plating
UG112_c1_07_112508
Figure 1-7:
Rigid BT-Based Substrate Chip Scale Packages, left; Flex-Based Tape Substrate, right
Quad Flat No-Lead (QFN) Packages
Quad Flat No-Lead (QFN) package robust low-profile lead frame-based plastic package that several advantages over traditional lead frame packages. exposed die-attach paddle enables efficient thermal dissipation when directly soldered PCB. Additionally, this near chip scale package offers improved electrical performance, smaller package size, absence external leads. Since package external leads, coplanarity bent leads longer concern. Xilinx Quad Flat No-Lead packages ideal portable applications where size, weight, performance matter.
Package Construction
molded leadless package with land pads bottom package. Electrical contact made soldering land pads PCB. backside attached exposed paddle through attach material which electrically conductive. exposed therefore represents weak ground should left floating connected ground net.
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X-Ref Target Figure
Gold Wire
Mold Compound
Attach Epoxy
Silicon
Copper Leadframe
Down Bond
Exposed Paddle
Ground Bond
UG112_c1_08_112508
Figure 1-8:
Left Cross-Section. Right Bottom View.
Features/Advantages Packages
Small size light weight Excellent thermal electrical performance Compatible with conventional processes
Ceramic Column Grid Array (CCGA) Packages
Ceramic Column Grid Array (CCGA) packages surface-mount-compatible packages that high-temperature solder columns interconnections board. Compared solder spheres, columns have lower stiffness provide higher stand-off. These features significantly increase reliability solder joints. When combined with high-density, multilayer ceramic substrate, this packaging technology offers high density, reliable packaging solution. Ceramic offers following benefits:
Features/Advantages CCGA Packages
High planarity excellent thermal stability high temperature matches well with silicon moisture absorption
Xilinx offers different formats CCGA: "Cavity-Down" wire-bonded CCGA, "CavityUp" wire-bonded CCGA, flip-chip CCGA.
Cavity-Down Wire-Bonded CCGA CG560 Package Construction
CG560 offered with Xilinx XQV1000 XQVR1000 devices. pin-compatible with plastic BG560 package. Below additional attributes CG560. Interconnect: 90Pb/10Sn hard solder column interposer, attached with 63Sn/37Pb soft solder. Hermetically sealed with eutectic Sn/Au
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Device Package User Guide UG112 (v3.2) March 2009
X-Ref Target Figure
Copper/Tungsten Heatsink
Solder Column
Kovar (Plated with
Ceramic Substrate
UG112_c1_09_111608
Figure 1-9:
CG560 Package
Cavity-Up Wire-Bonded CG717 Package Construction
CG717 offered with Xilinx XQ2V3000 XQR2V3000 devices. pin-compatible with plastic BG728 package. Below additional attributes CG717. Interconnect: 80Pb/20Sn hard solder column, attached with 63Sn/37Pb soft solder. Hermetically sealed with eutectic Sn/Au
Kovar (Plated with
X-Ref Target Figure 1-10
Solder Column
Ceramic Substrate
UG112_c1_10_111608
Figure 1-10: CG717 Package
Flip-Chip CCGA CF1144 Package Construction
Flip-Chip CCGA targeted applications that require high performance, density, high reliability. CF1144 offered with Xilinx XQ2V6000 XQR2V6000 devices. CF1144 package pin-compatible with plastic flip-chip FF1152 package. Below additional attributes CF1144: 95Pb/5Sn flip-chip solder bumps 90Pb/10Sn hard solder column
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X-Ref Target Figure 1-11
Underfill Epoxy
Flip-chip Solder Bump
Thermal Adhesive
Aluminum Heatspreader
Silicon
Solder Column
Ceramic Multi-layer Substrate
UG112_c1_11_120908
Figure 1-11:
CF1144 Package
Thermally Enhanced Lead Frame Packaging
Xilinx offers thermally enhanced quad flat pack packages XC4000 Series devices some earlier Virtex devices. This section discusses performance usage these packages (designated HQ).
Features/Advantages Thermally Enhanced Lead Frame Packages
HQ-series regular packages conform same JEDEC drawings. packages same land patterns. packages have more mass Thermal performance better packages
Applications Packages
packages offered thermally enhanced equivalents packages. They used high gate count high count devices packages, where heat dissipation without enhancement handicap device performance. Such devices include XC4013E, XC4020E, XC4025E, XC5215. series 240-pin count level below offered with heatsink bottom package. This done ensure compatibility with existing packages. 304-pin count level, offered with heatsink This arrangement offers better potential further thermal enhancement designer.
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X-Ref Target Figure 1-12
Heatsink Down
Down Heatsink
Heatsink Down Orientation Heatsink Orientation
UG112_C1_12_111208
Figure 1-12:
Heatsink Orientation
die-up/heatsink-down configuration, heatsink surface insulated.
Package Mass Table
numbers provided Table represent average values typical devices used package. size variation from device device, slight changes moisture content, number specific layers used specific substrate etc., will provide some variation. some cases data accuracy ±10%. More precise numbers specific devices obtained from insitu weighing. this critical, specific information requested. Table 1-3: Package Mass (Weight) Package Type
Description ball flip-chip body (1.27 pitch) Molded Full Matrix Molded Peripheral SuperBGA Peripheral (1.27 pitch) SuperBGA Peripheral Molded (1.27 pitch) Mass 18.5
Package BF957, BFG957 BG225, BGG225 BG256, BGG256 BG352, BGG352 BG388 BG432, BGG432 BG492, BGG492
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Table 1-3:
Package Mass (Weight) Package Type (Cont'd)
Description SuperBGA 42.5 42.5 body (1.27 pitch) body (1.27 pitch) NCTB Brazed XC3000/XC4000 NCTB Brazed XC3000/XC4000 NCTB Brazed XC4000 NCTB Brazed XC4000 Ceramic Leaded Chip Carrier Ceramic Leaded Chip Carrier Ceramic Side Brazed Ceramic Side Brazed Ceramic Column flip chip, pitch Ceramic SPGA 42.5 42.5 Ceramic Column Grid Array, 1.27 pitch (0.5 pitch) ball pitch (0.8 pitch) (0.8 pitch) (0.8 pitch) (0.8 pitch) Cerdip Package (.300" Spacing) Flip-chip pitch ball Ceramic Column flip-chip BGA, ball pitch ball flip-chip BGA, ball pitch ball flip-chip BGA, pitch Full ball flip-chip body (1.0 pitch) Flip-chip BGA, 1148 ball flip-chip body (1.0 pitch) Mass 12.3 10.8 11.5 15.3 17.6 44.0 44.0 13.3 11.2 14.0 14.0
Package BG560, BGG560 BG575, BGG575 BG728, BGG728 CB100 CB164 CB196 CB228 CC20 CC44 CD48 CF1144 CG560 CG717 CP56, CPG56 CP132, CPG132 CS48, CSG48 CS144, CSG144 CS280, CSG280 CS484, CSG484 FF665, FFG665 FF668, FFG668 FF672, FFG672 FF676, FFG676 FF896, FFG896 FF1136, FFG1136 FF1148, FFG1148
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Table 1-3:
Package Mass (Weight) Package Type (Cont'd)
Description 1152 ball flip-chip body (1.0 pitch) Flip-chip 1513 ball flip-chip body (1.0 pitch) 1517 ball flip-chip body (1.0 pitch) 1696 ball flip-chip 42.5 42.5 body (1.0 pitch) 1704 ball flip-chip 42.5 42.5 body (1.0 pitch) Flip-chip 42.5 42.5 pitch Flip-chip 42.5 42.5 pitch Fine pitch ball pitch Fine pitch ball pitch Molded pitch Fine pitch ball pitch Fine pitch ball pitch Molded pitch Fine pitch ball pitch SuperBGA pitch Fine pitch ball pitch Fine pitch ball pitch Fine pitch 42.5 42.57 ball pitch Fine pitch ball pitch Fine pitch ball pitch 48BGA, ball pitch Thin PBGA body (1.0 pitch) Metric 0.65 1.6H/S Metric Metric Metric Down Thin (HQ) Mass 14.0 14.0 17.0 17.2 20.5 21.1 22.0 22.0 3.06 10.6 13.8 10.8 10.8 15.0 26.2
Package FF1152, FFG1152 FF1153, FFG1153 FF1513, FFG1513 FF1517, FFG1517 FF1696, FFG1696 FF1704, FFG1704 FF1738, FFG1738 FF1760, FFG1760 FG256, FGG256 FG320, FGG320 FG324, FGG324 FG456, FGG456 FG400, FGG400 FG484, FGG484 FG556, FGG556 FG580 FG676, FGG676 FG680, FGG680 FG860, FGG860 FG900, FGG900 FG1156, FGG1156 FS48, FSG48 FT256, FTG256 HQ160, HQG160 HQ208, HQG208 HQ240, HQG240 HQ304, HQG304 HT144
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Table 1-3:
Package Mass (Weight) Package Type (Cont'd)
Description Thin (HQ) PLCC JEDEC MO-047 PLCC JEDEC MO-047 PLCC JEDEC MO-047 PLCC JEDEC MO-047 PLCC JEDEC MO-047 .300 Standard .600 Standard Ceramic "Cavity Ceramic "Cavity Windowed CPGA "Cavity Ceramic Matrix Ceramic Matrix Ceramic Cavity Ceramic Matrix Ceramic Standard Version Ceramic Standard (All) Ceramic Type Ceramic Heatsink Ceramic Matrix Ceramic Stagger Ceramic Stagger Ceramic EIAJ EIAJ 1.60 (default) EIAJ 1.80 (not used) EIAJ 1.95 (old version) EIAJ 0.65 1.60 EIAJ 1.30 EIAJ Flip-chip pitch Version 0.150/50 SOIC Mass 11.5 11.8 16.9 17.1 17.7 21.8 26.0 37.5 29.8 36.7 39.5 44.5
Package HT176 PC20, PCG20 PC28, PCG28 PC44, PCG44 PC68, PCG68 PC84, PCG84 PD8, PDG8 PD48 PG68 PG84 PG84 PG120 PG132 PG144 PG156 PG175 PG191 PG223 PG299 PG299 PG411 PG475 PG559 PQ44, PQG44 PQ100, PQG100 PQ100, PQG100 PQ100, PQG100 PQ160, PQG160 PQ208, PQG208 PQ240, PQG240 SF363, SFG363 SO8, SOG8 SO20, SOG20
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Table 1-3:
Package Mass (Weight) Package Type (Cont'd)
Description SOIC Thin thick Thin thick RECT Thin thick Thin thick Thin SOIC Thin SSOP, Thin Thin thick THIN thick Thin thick Mass
Package SO24 TQ100, TQG100 TQ128, TQG128 TQ144, TQG144 TQ176, TQG176 VO8, VOG8 VO20, VOG20 VO48, VOG48 VQ44, VQG44 VQ64, VQG64 VQ100, VQG100
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Chapter
Pack Ship
Introduction
Xilinx offers several packing options through-hole surface-mount products. devices packed either tubes, trays, tape reel.
Tape Reel
Xilinx offers tape reel packing PLCC, BGA, QFP, packages. packing material made black conductive polystyrene protects packages from mechanical electrical damage. reel material provides suitable medium pick place equipment. tape reel packaging consists pocketed carrier tape, sealed with protective cover. device sits pedestals (for PLCC, packages) protect leads from mechanical damage. devices loaded into tape carriers baked, lead scanned before cover tape attached sealed carrier. In-line mark inspection mark quality package orientation used ensure shipping quality.
Benefits
Increased quantity devices reel versus tubes improves cycle time reduces amount time index spent tubes. Tape reel packaging enables automated pick place board assembly. Reels uniform size enabling equipment flexibility. Transparent cover tape allows device verification orientation. Antistatic reel materials provides protection. Carrier design include pedestal protect package leads during shipment. code labels each reel facilitate automated inventory control component traceability. tape reel shipments include desiccant pouches humidity indicators ensure products safe from moisture. Compliant Electronic Industries Association (EIA) 481. Material Construction Carrier Tape. pocketed carrier tape made conductive polystyrene material, equivalent, with surface resistivity level less than ohms square inch. Devices loaded "live bug" leads down, into device pocket. Each carrier pocket hole center automated sensing whether unit pocket not.
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Sprocket holes along edge carrier tape enable direct feeding into automated board assembly equipment.
Cover Tape
anti-static, transparent, polyester cover tape, with heat activated adhesive coating, sealed carrier edges hold devices carrier pockets. Surface resistivity both sides less than 1011 ohms square inch.
Reel
reel made anti-static polystyrene material. loaded carrier tape wound onto this conductive plastic reel. protective strip made conductive polystyrene material placed outer part reel protect devices from external pressure shipment. Surface resistivity less than 1011 ohms square inch. Device loading orientation compliance with Standard 481.
Code Label
code label each reel provides customer identification, device part number, date code product quantity reel. Print quality accordance with ANSI X3.182-1990 Code Print Quality Guidelines. Presentation Data labels EIA-556-A compliant. label alphanumeric, medium density Code labels. This machine-readable label enhances inventory management data input accuracy.
Shipping
shipping container reels C-flute, corrugated, white "pizza box," rated test.
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Device Package User Guide UG112 (v3.2) March 2009
Table 2-1:
Tape Reel Packaging
Qty. Reel 4000 1500 2000 1000 1000 1000 1000 2500 2000 2000 1000 Reel Size (inches) Carrier Width (mm) Cover Width (mm) 37.5 37.5 37.5 13.3 21.0 21.0 37.5 37.5 13.3 25.5 37.5 37.5 37.5 37.5 49.5 49.5 49.5 21.0 21.0 37.5 13.3 21.0 21.0 21.0 Pitch (mm) 20.0 12.0
Package Code BG225(1), BGG225(1) BG256(1), BGG256(1) BG272(1), BGG272(1) CP56(1), CPG56(1) CS48(1), CSG48(1)
CS144(1), CSG144(1) FG256(1), FGG256(1) FG456(1), FGG456(1) FG676(1), FGG676(1) FT256, FTG256 PC20(1), PCG20(1) PC44(1), PCG44(1) PC68(1), PCG68(1) PC84(1), PCG84(1) PQ100, PQG100 PQ160, PQG160 BG352(1), BGG352(1) BG432(1), BGG432(1) BG560(1), BGG560(1) SO20 TQ100, TQG100 TQ144, TQG144 VO8, VOG8 VO20, VOG20 VQ44, VQG44 VQ64, VQG64 VQ100, VQG100
Note:
In-house capability.
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Standard Code Label Locations
X-Ref Target Figure
Desiccant
Antistatic Tape
Label
Code Label
Antistatic Tape
Desiccant
UG112_C2_01_111208
Figure 2-1:
Standard Code Label Locations
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X-Ref Target Figure
Desiccant Included Label
Code Label Label
Vacuum Sealed
UG112_C2_02_111208
Figure 2-2:
Standard Code Label Locations
Tubes
Tubes used unit carriers most Xilinx smaller packages. tubes coated with antistatic material protect product from damage. Table 2-2: Standard Device Quantities Tube
Package PC84, PCG84, WC84 PC68, PCG68, WC68 PC44, PCG44, CC44, WC44 PC28, PCG28 PC20, PCG20, CC20 CD48 PD48 SO24 Full Tube Quantity Max. Tube Qty. (8.5" 27") Max. Tube Qty. (12" 27")
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Table 2-2:
SO20
Standard Device Quantities Tube
VO20, VOG20 VO24 VO8, VOG8
Trays
Trays used pack most Xilinx surface-mount devices since they provide excellent protection from mechanical damage. addition, they coated with antistatic material provide protection against damage withstand operation temperature 150o Table 2-3: Standard Device Counts Tray
Number Devices Tray Number Units Internal
Package BF957/BFG957 BG225/BGG225 BG256/BGG256 BG352/BGG352 BG492/BGG492 BG728/BGG728 BG432/BGG432 BG560/BGG560 BG575/BGG575 CB100, CB164, CB196, CB228 CP56/CPG56 CP132/CPG132 CS48/CSG48 CS144/CSG144 CS280/CSG280 CS484, CSG484 FG256/FGG256 FG320/FGG320 FG324/FGG324 FG456/FGG456, FG484/FGG484 FG676/FGG676
1800 1800 2080
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Device Package User Guide UG112 (v3.2) March 2009
Table 2-3:
Standard Device Counts Tray (Cont'd)
Number Devices Tray Number Units Internal
Package FG860 FG900/FGG900 FG680/FGG680 FG1156/FGG1156 FF668 FFG668 FF672/FFG672 FF896/FFG896 FF1136/FFG1136 FF1148/FFG1148 FF1152/FFG1152 FF1513/FFG1513 FF1517/FFG1517 FF1696/FFG1696 FF1704/FFG1704 FS48/FSG48 FT256/FTG256 HQ160/HQG160 HQ208/HQG208 HQ240/HQG240 HQ304 HT144 HT176 PG68, PG84 PG120 PG132/PP132 PG144 PG156/PP156 PG175/PP175 PG191, PG223 PG299 PG411, PG475, PG559 PQ44/PQG44 PQ100/PQG100 PQ160/PQG160 PQ208/PQG208
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Table 2-3:
Standard Device Counts Tray (Cont'd)
Number Devices Tray Number Units Internal 2450 1300
Package PQ240/PQG240 QFG32 QFG48 SF363/SFG363 TQ144, TQG144 TQ160, TQ176 TQ100/TQG100 TQ128 VO48/VOG48 VQ44/VQG44 VQ64/VQG64 VQ100/VQG100
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Chapter
Thermal Management Thermal Characterization Methods Conditions
Introduction
This chapter addresses need manage heat generated CMOS logic devices, industry wide pursuit, describes measures Xilinx uses recommends customers quantify manage potential thermal problems FPGAs.
Thermal Management
Modern high-speed logic devices consume appreciable amount electrical energy. This energy invariably turns into heat. Higher device integration drives technologies produce smaller device geometry interconnections. With chip sizes getting smaller circuit densities their highest levels, amount heat generated these fastswitching CMOS circuits very significant. example, Xilinx Virtex®-II FPGA devices incorporate multiple processors, multiple-gigabit transceivers, digitalcontrolled impedance I/Os, I/Os capable supporting various high current standards. Special attention must paid addressing heat removal needs these devices. need manage heat generated modern CMOS logic device unique Xilinx. This general industry pursuit. However, unlike power needs typical industry application-specific integrated circuit (ASIC) gate array, field-programmable device's power requirement determined factory. Customers' designs vary power well physical needs. This challenge predicting FPGA thermal management needs. There sure anticipating accurate power dissipation FPGA device short actual measurement. Xilinx developed several software-based power-estimator tools help user predict power consumption. tools useful first step. Like most tools, however, predicted output depends work into predicting effort. assigning packages devices, effort been made tailor packages power needs typical users. each device, suitable packages typically chosen handle "typical" designs gate utilization device. most part, choice package primary internal heat removal casing works well without external heat management. Increasingly, with highly integrated devices, need arises customers utilize FPGA device beyond "typical" design parameters. these situations, primary package without external enhancement adequate address heat removal needs device. these cases that need manage heat removal through external means becomes essential.
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Heat removed from device ensure that device maintained within functional maximum design temperature limits. heat buildup becomes excessive, device's temperature exceed temperature limits. consequence this that device fail meet speed-files performance specifications. addition performance considerations, there also need satisfy system reliability objectives operating lower temperature. Failure mechanisms failure rate devices have exponential dependence device's operating temperatures. Thus, control package, extension device temperature, essential ensure product reliability.
Package Thermal Characterization Methods Conditions
Characterization Methods
Xilinx uses several methods obtain thermal performance characteristics integrated circuit packages. methods include thermal simulation using finite element software tools, indirect electrical method utilizing isolated diode special thermal test even Xilinx FPGA housed package interest. majority data reported Xilinx based indirect diode method. Simulation tools, calibrated with actual measurement data, used supplement thermal collateral data generation. Most published compact thermal model data based such effort.
Calibration Isolated Diode
direct electrical method, forward-voltage drop isolated diode residing special test temperature diode Xilinx FGPA calibrated applying constant forcing current (from 0.100 0.500 over temperature range 125°C (degrees Celsius). calibrated packaged device then mounted appropriate board placed testing environment e.g., still forced convection. Power (PD) applied device through diffused resistors same thermal die. FPGA case, known self-heating program loaded clocked generate monitored power. Usually, between watts watts applied. Higher power watts) possible, depending package. resulting rise junction temperature monitored with forward-voltage drop precalibrated diode.
Simulation Methods
simulation effort, finite element (FEA) methodology used represent packages interest. package geometrical details (based data), well board stack-up details captured. Published material properties used input derive thermal characteristics based JEDEC environment boundary conditions. Using sample test data, inputs assumptions optimized minimize variation between measurement simulation.
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X-Ref Target Figure
UG112_C3_01_111208
Figure 3-1: Simulation Tool Outputs: Quarter Model Package, JEDEC Enclosure Once simulation inputs assumptions refined, method used obtain thermal characteristics including thermal models devices family using same material construction details.
Measurement Standards
Previously, Xilinx Thermal used SEMI thermal test methods (#G38-87) associated SEMI-based boards (#G42-87) perform thermal characterization. Most recent measurements simulations based provision JEDEC Standard JESD51-n series specifications. assessment that latter standard offers some options that available SEMI method. will continue quote SEMI-based data (designated SEMI comment column) older packages measured earlier era, when quote data, they will designated JESD comment section. also essential note that these standard-based measurements give characterization results that allow packages conditions compared. Like miles gallon (MPG) figures quoted cars, numbers should used with caution. specific user environments will identical conditions used characterization, numbers quoted precisely predict performance package application-specific environment. better in-system prediction, Xilinx provides compact thermal models devices. Some these available model libraries download Download Center Models older products requested from ctm_team@xilinx.com.
Definition Terms
Junction Temperature, defined maximum temperature die, expressed (degrees Celsius). Ambient Temperature, defined temperature surrounding environment, expressed (degrees Celsius). Temperature package taken defined location body. most situations, taken primary heat flow path package will represent hottest part package, expressed next item when taken top.
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Temperature package body taken location package. This special case This board temperature taken predefined location board near component under test, expressed This isothermal fluid temperature when junction case temperature taken, expressed total device power dissipation, expressed watts.
Junction-to-Reference General Setup
X-Ref Target Figure
Environment Const Current Source
Resistor Supply
Environment Still Forced Circulated FC-40 Sensing Diode Diffused Resistors
Data Acquisition Control Computer
UG112_C3_02 _111208
Figure 3-2:
Thermal Measurement Setup (Schematic Junction Reference)
Junction-to-Case Measurement
Theta-JC measures heat flow resistance between surface surface package (case). This data relevant packages used with external heatsinks. assumes that heat flowing through exclusion others. ideal case, heat forced escape package path where taken. lateral heat flow allowed minimized that source temperature differential will attributable total known heat input.
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UG112_C3_03_111208
Figure 3-3:
Measurement Setup
copper heatsink plate package used methods achieve forced preferred directional flow. Prior 1999, junction-to-case characterization some heatsink packages accomplished Flourinert (FC-40) isothermal circulating fluid stabilized 25°C. Current Xilinx data simulated using cold plate approach. With applied power (PD) under stabilized conditions, case temperature (TC) measured with gauge thermocouple (36-40 AWG) primary heat-flow path particular package. Junction temperature (TJ) calculated from diode forwardvoltage drop from initial stable condition before power applied: TC)/PD where terms defined above. poorly defined condition usually leads lower numbers being reported. such cases, recorded temperature difference (TJ-TC) result having fraction power going through path. However, calculation, full power used.
Junction-to-Top Measurement
Psi-JT (JT) junction thermal parameter (not thermal resistance), defined JEDEC specification that shadows real-world situation. This parameter provides correlation between chip junction temperature temperature package top. measured defined FR4-based board described under reference temperature temperature monitored component, Though cause temperature rise caused power applied, full power used calculation: Tt)/PD where full applied power. parameter value depends airflow conditions. heatsink type packages (some most packages) where primary heat flow almost dimensional heat flux confined top, taken same point approaches molded packages like Xilinx FG676, FG900 FG1156, one-dimensional condition difficult meet. best, fraction heat flux (about 60%) goes
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standardized setup. end-user application, heat flux division follow similar pattern. Under such cases, psi-jt (JT) theta-JC tend diverge from each other. total power known, temperature carefully measured, used predict application environment. Xilinx does provide numbers they strongly depend application conditions.
Junction-to-Ambient Measurement
X-Ref Target Figure
UG112_C3_04_111208
Figure 3-4:
Measurement Setup
SEMI method: Some data reported based SEMI standard methods associated board standards. data reported based SEMI were measured FR4-based boards measuring .0625 (114.3 152.4 with edge connectors. Several versions available handle various surface mount (SMT) devices. They are, however, grouped into main types. Type board (the equivalent JEDEC low-conductivity board) single layer with signal planes (one each surface) internal Power/GND planes. This 2L/0P 2S/0P board trace density this board less than side. type board (the equivalent JEDEC 2S/2P board) internal copper planes power ground. These planes addition signal trace layers both surfaces. This 4L/2P (four-layer, also referred 2S/2P) board. JEDEC measurements: Packages measured foot-cube enclosure based JEDS51-2. Test boards fashioned test board specification JESD51-3 JESD51-7. board sizes depend package typically 76.2 114.3 101.6 114.3 These come low-conductivity well highconductivity versions. Thermal resistance data taken with package mounted socket with package mounted directly traces board. Socket measurements typically 2S/0P low-conductivity boards. devices, other hand, either board. Published data always reflect board mount conditions used (ref 2S/0P 4L/2P). board with device under test (DUT) mounted test enclosure data taken prevailing temperature pressure conditions between 20°C 30°C ambient (TA). Appropriate power used, depending anticipated thermal resistance package. Applied power, signal monitoring including enclosure (ambient) temperatures noted. junction ambient thermal resistance calculated follows:
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TA)/PD case airflow measurement, this done special airflow enclosure section suction-type low-velocity wind tunnel. Airflow velocities from 0-1000 linear feet minute (LFM), i.e., 0-5.08 m/s, used with very turbulence. controlling specification JESD51-6. Airflow measurements similar boards with conditions noted with wire anemometer.
Thermal Resistance: Junction-to-Board
This defined TB)/PD where board temperature steady state measured specified location board. actual power watts that produces change temperature. monitored board with 40-gauge thermocouple specific location proximity package leads balls. example, package, thermocouple attached trace midway along side package with attachment point within package body. Like depends constrained flow preferred direction. actual measurement simulations heat flow forced preferably through board excluding other paths with insulation. measurement conditions likely reproduced real application.
Data Acquisition Package Thermal Database
Data package type gathered various sizes, power levels, cooling modes (air flow sometimes heatsink effects) with Data Acquisition Control System (DAS). system controls conditions power supplies other ancillary equipment hands-free data taking. package completely characterized with respect major variables that influence thermal resistance. database generated package. From database, thermal resistance data interpolated typical values individual Xilinx devices that assembled characterized package. Figure screen shot Package Thermal Data Query Xilinx components. This tool located Xilinx.com Device-specific data from thermal database obtained from this site. data from this query specific devices individual packages.
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X-Ref Target Figure
UG112_C3_05_111208
Figure 3-5:
Package Thermal Data Query Device-Specific Data
Thermal data consistent with above query results also found product-specific user guides newer device families. Below three examples: UG075, Virtex-4 FPGA Packaging Pinout Specification UG195, Virtex-5 FPGA Packaging Pinout Specification UG331, Spartan-3 FPGA Generation User Guide
linked query provides thermal data released active Xilinx products. supporting data table updated periodically include newer products prune inactive products. Data from Query replaces generic package based (summarized package type) thermal data that used tabulated previous versions this user guide.
Support Compact Thermal Models (CTM)
Table provides traditional thermal resistance data Xilinx packages. This resistance data measured using prescribed JEDEC standard that might necessarily reflect actual user environment. quoted numbers environmentally dependent, JEDEC traditionally recommended that these used with that awareness. more accurate junction temperature prediction, these might enough, system level thermal simulation might required.
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X-Ref Target Figure
DELPHI BCI-CTopology FCBGA
Resistor Model
Junction
Side
Junction
UG112_C3_06 _111208
Figure 3-6:
Compact Thermal Model Topologies
Though Xilinx will continue support these figure merit data, newer high performance devices such Virtex-4, boundary condition independent compact thermal models (BCI-CTM) available assist users their thermal simulations. resistor models, well resistor network models, offered these devices. These compact models seek capture thermal behavior packages more accurately pre-determined critical points (junction, case, top, leads, etc.) with reduced nodes. Unlike full model, these computationally efficient work well integrated system simulation environment. Delphi CTMs newer high performance devices available Xilinx Support Download Center: Models older products requested from: ctm_team@xilinx.com.
Application Thermal Resistance Data
Thermal resistance data used gauge package thermal performance. There several ways express thermal resistance between points. following them: Junction ambient thermal resistance (°C/W). Junction case thermal resistance (°C/W) Junction board thermal resistance (°C/W) Case ambient thermal resistance (°C/W) Case heatsink thermal resistance (°C/W) Heatsink ambient thermal resistance (°C/W)
Other thermal parameters include
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Junction board thermal characteristic parameter (°C/W) Junction package thermal characteristic parameter (°C/W)
measures internal package resistance heat conduction from surface, through mount material package exterior. strongly depends package material's heat conductivity geometrical considerations. measures total package thermal resistance including depends package material properties such external conditions convective efficiency board mount conditions. example, package mounted socket have value higher than same package mounted four-layer board with power ground planes. general, expresses thermal resistance between points above expression, source points indicated. situations where heatsink used with heatsink compound, thermal resistance heatsink referenced (sink-to-ambient) attached material (caseto-heatsink). These thermal resistances added. example, expression used heatsink situations with interface material resistance
Thermal Data Usage
Note: Actual thermal resistance system impacted several user conditions. examples that follow, should noted that unique user conditions will impact predictions estimates. Such user conditions have been taken into consideration examples. main influences thermal resistance board conditions. Table shows table that illustrates thermal resistance flip-chip package (FF1148) influenced board characteristics. package with high-conductivity JEDEC board-based measured JAof 10.1°C/watt exhibit almost reduction square board with copper layers used. Other user boundary conditions also affect effective thermal resistance system. Figure depicts impact when airflow applied packages. general, users work their through these examples, external influences have been taken into account estimates. following some data requirements using thermal resistance application. Xilinx-supplied data:
Thermal data JCis available Thermal data provided heatsink supplier. TJmax This high absolute maximum temperature package typically 125°C 135°C plastic Note that components tested meet speed file specifications temperatures associated with them 85°C grade, higher grades. Running parts higher than specified meet specifications. user will have pick TJmax reliability considerations, plan thermal budget around that This also another variable that user control. Typically, this approximately 45°C 55°C.
Items that user need supply.
Ambient temperature system
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Items usually estimated:
Power dissipation. thermal equation used determine power range that satisfy some given conditions Also, power known, TJmax calculated from equations temperature bare part well monitored system (not measured), thermal parameter used junction temperature Similarly, well monitored board temperature used predict junction with parameter
non-heatsink situations, following inequality formula should hold: TJmax examples below illustrate above inequality formula. Specific packages used examples, package-Quad, BGA, FGs, even flip-chip based BGs-are applicable.
Example
manufacturer's goal achieve TJmax 85°C module designed 45°C max. XCV300 FG456 16.5°C/watt. 2.0°C/watt. Given XCV300 with logic design with rated power watts. With this information, maximum temperature calculated (16.5 2.0) 78°C. system manufacturer's goal 85°C this case.
Example
module 55°C max. Xilinx FPGA XCV400E PQ240 package. logic design XCV400E determined 2.70 watts. module manufacturer's goal achieve (max.) 100°C. Table shows package thermal enhancement combinations required meet goal 100°C. Table 3-1: Thermal Resistance XC4013E PQ240 HQ240 Packages
Package PQ240 still 17.9 (250 LFM) 13.2 (500 LFM) 11.7 (750 LFM) 10.8 Comments 2L/0P
Device Name XCV400E
solutions, junction temperature calculated Power solutions meet module requirement less than 100°C, with exception PQ240 package still air. general, depending ambient board temperatures conditions, most importantly total power dissipation, thermal enhancements such forced cooling, heat sinking, etc., necessary meet (max) conditions set.
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Possible solutions meet module requirements 100°C: Using standard PQ240: (17.9 2.70) 103.33°C. Using standard PQ240 with forced air: (13.2 2.70) 90.64°C.
Heatsink Calculation
Example illustrating heatsink: Device XCV1000E-FG680 There need external thermal enhancements. Data supplied from Xilinx XCV1000E-FG680 shown Table Table 3-2: Data supplied from Xilinx XCV1000E-FG680
still 10.6 °C/W (250 LFM) (500 LFM) (750 LFM)
Package Code FG680
Customer requirements
50°C Power watts (user's estimate) User does want exceed TJmax 100°C 10.6 134.8°C Unacceptable! still will work because 134.8°C beyond stated goal 100°C less. Determine what will required stay below 100°C with watts power? Thermal budget 50°C. (50)/8 6.25°C/watt. package enhancement need have effective thermal resistance from junction ambient less than 6.25°C/watt. That becomes goal thermal solution ought meet. bare package with (2.54 meters/s) will give 6.1°C/watt. (from data table above). That will workable option, that much airflow will tolerable. Heatsink calculation. With heatsink, heat will pass through package then through interface material CS), from heatsink ambient SA). This expressed follows: 6.25 0.9+0.1+ 6.25°C/watt condition
Determination with base Still data:
Calculating acceptable thermal resistance:
Solution Options:
where
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0.9°C/watt from data 0.1°C/watt from interface material data
From above, 5.25°C/watt objective will look heatsink with 5.25°C/watt that meets physical constraints system Passive heatsink with some flow (1.25 m/s) selected Active heatsinks possible small low-profile heatsinks with fans
Thermal Data Comparison
X-Ref Target Figure
40.0 35.0 30.0 FG456 FG484 FG556 FT256 FG676
Figure 3-7:
25.0 20.0 15.0 10.0
Size (mils)
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Effect Size Thermal Resistance (JA) PBGA Packages
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X-Ref Target Figure
Figure 3-8:
Table 3-3:
Impact Mounted Board Characteristics Flip-Chip FF1148
Xilinx FF1148-4VLX100 Board 10.1 (100%) (88%) (82%) (79%) Board Size Board (91%) (60%) (51%) (50%) (47%) Board (54%) (48%) (46%) (44%)
Flow (linear ft/min)
XC4010E-HQ208 XC4010E-PQ208
XC4013E-HQ240 XC4013E-PQ240
XC4025E-HQ304
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Effect Flow Thermal Resistance HQ/PQ Packages
Layer Count Mounted Board
JEDEC mount conditions.
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X-Ref Target Figure
Figure 3-9:
X-Ref Target Figure 3-10
PG299 Various Enhancements
Standard Pkg+Finned (Passive) Pkg+Active (V=0) Pkg+Active (V=12) +250LFM Pkg+Finned 250LFM
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Effect Active Passive Heat Sinks Thermal Resistance (JA) PG299 Packages
35.0 30.0 25.0
10.0
Figure 3-10:
20.0 15.0
Flow (linear ft/min)
XC2S300E-FT256 XCV1000E-FG680
XC3S1500-FG456 XC2V6000-FF1152
XC2VP40-FG676
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Effect Flow Thermal Resistance (JA) Packages
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Some Power Management Options
variety applications that FPGA devices used makes challenge anticipate power requirements thus thermal management needs particular user have. While Xilinx programmable devices dominating power consumers some systems, conceivable that high-gate-count FPGA devices will exercised sufficiently generate considerable heat.
X-Ref Target Figure 3-11
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Figure 3-11:
Enhanced with Profile Retainer Type Passive Heatsinks
general, high-I/O high-gate-count Virtex family devices have potential being clocked produce high wattage. Being aware this potential power needs, package offering these devices includes medium- high-power-capable package options. This allows system designer further enhance these high-end packages handle more power. When actual estimated power dissipation appears more than specification bare package, some thermal management options considered. accompanying Thermal management chart illustrates incremental nature recommendations ranging from simple airflow schemes that include passive heatsinks active heatsinks.
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X-Ref Target Figure 3-12
Figure 3-12:
Thermal Management Incremental Options
heat pipes, even liquid-cooled heat plates, considered extreme some these packages. Details engineering designs analysis some these suggested considerations require help thermal management consultants. references listed this section provide heatsink solutions industry-standard packages. Some options available thermal management include following: Most high-gate-count Xilinx devices come more than package types. Explore thermally enhanced package options available devices. quad packages some packages have heat enhancement options. Typically, improvement thermal performance expected from these heatsink-embedded packages. system design, natural convection enhanced with venting system enclosure. This will effectively lower increase available thermal budget moderate power dissipation. forced-air fans next step beyond natural convection, effective improve thermal performance. seen graphs calculations above, forced (200-300 LFM) reduce junction-to-ambient thermal resistance 30%. moderate power dissipation watts), passive heatsinks heat spreaders attached with thermally conductive double-sided tapes retainers offer quick solutions. lightweight finned external passive heatsinks effective dissipating watts some packages. implemented with forced well, benefit reduction illustrated XCV1000E-FG680 example. more efficient external heatsinks tend tall heavy. When using bulky heatsink, advisable spring-loaded pins clips reduce heatsinkinduced stress solder joints component these pins clips help transfer mounting stress circuit board. diagonals some these heatsinks designed with extensions allow direct connection board (see Figure 3-13).
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X-Ref Target Figure 3-13
UG112_C3_13_111208
Figure 3-13:
Heatsink with Clips
Exposed metal heatsink packages: thermally enhanced BGAs with dies facing down (including these package codes BG352, BG432, BG560, FG680, FG860, flip-chip BGAs) offered with exposed metal heatsink top. These considered high-end thermal packages they lend themselves application external heatsinks (passive active) further heat removal efficiency. Again, precautions should taken prevent component damage when bulky heatsink attached. Active heatsinks include simple heatsink incorporating mini even Peltier Thermoelectric Coolers (TECs) with carry away heat generated. consideration applying heat management should include consultation with experts using devices, these devices reversed this damage components. Also, condensation issue. Molded packages (FG456, FG676, FG1156, PQs, etc.) without exposed metal also these heatsinks further heat reduction. These packages similar construction those used graphic cards applications, heatsinks used those applications easily used these packages well. this case, resistance will limiting consideration.
X-Ref Target Figure 3-14
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Figure 3-14:
Example Active Heatsink (Malico)
Outside package itself, board which package sits have significant impact thermal performance. Board designs implemented take advantage board's ability spread heat. Heat flows outside package sunk into board conducted away through heatpipes normal convection. effect board will dependent size conducts heat. Board size, level copper traces number buried copper planes lower thermal resistance package mounted Some heatsink packages like with exposed heatsink board side glued board with thermal compound enhance heat removal into board. packages with full matrix balls cooled with this scheme. Users need aware that direct heat path board from component also exposes component
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effect other heat sources, particularly board cooled effectively. otherwise cooler component heated other heat-contributing components board. Xilinx lower voltage version equivalent circuit same similar package. With product speed grade choice, power reduction anticipated 5.0V 3.3V version. products have equivalent lower voltage versions.
"Web Sites Heatsink Sources" lists sites that offer more information heat management sources interface material.
System Simulation Support
more accurate in-system prediction, Xilinx provide Compact Thermal Models (CTMs) used system thermal simulations. figure merit thermal data Xilinx provides used select packages perform comparative thermal analysis some preliminary predictions. However, when thermal margins very tight, component integrated with other heat sources system, full system thermal analysis might required. These CTMs provided reduce computational complexity. CTMs based Delphi approach that JEDEC proposed. Since JEDEC neutral (XML) format proposal been adopted yet, Delphi approach used generate these files data saved native proprietary file formats targeted tools, rather than follow neutral file. closely following JC15-1 developments hope offer neutral file format when ready adopted tool vendors. meantime, these CTMs based Delphi (dotcomp optimization) approach specific tools. These tools occupied first places pre-introduction customer survey. libraries available Flotherm (pdml) format; V5.1 above Icepack (ver. above) format. Virtex-4 device, newer products supported. Cdata downloaded from Xilinx Support Download Center Models older products requested from: ctm_team@xilinx.com. plan support models other tools through neutral format approach. Before neutral file format adopted, there might limited support Xilinx formatted ASCII-based file defining nodes listing associated resistances between notes manual entry into various other tools that support Cusage; requests this type should directed ctm_team@xilinx.com.
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Chapter
Package Electrical Characteristics
Introduction
data rates increase signal rise times become shorter, effects package parasitics becoming increasingly significant hardware engineers model their circuits. Discontinuities that have minimal impact circuit performance past generations components paramount importance designers strive achieve higher performance their systems. package forms interconnect system just like traces printed circuit board (PCB) conductors connectors. When designer simulates signaling performance from driver receiver, interconnect parasitics path, including package, must considered order achieve simulation results that represent entire system's performance. Current Xilinx packages constructed with either wirebond flip chip interconnect technology. Some components simpler leadframe-based packages, while others laminate-based packages with multilayer construction. choice package matches performance marketing objectives sought device family. multilayer packages, innovative pin-out selections creative design techniques used codesign effort optimize package performance prevent package from being limiting factor device. these high performance FPGA packages, Xilinx also provides package models that allow user take package parasites into account accurately model component's performance prior committing hardware. This chapter focuses defining certain critical concepts associated with electrical characterization packages. also intended provide relevant theoretical review electrical issues concepts they relate characterization effort. document provides descriptions methods utilized generate parasitic data derive appropriate models their use. Some data examples, ranging from simple tabulated s-parameter models, given illustrate range electrical data that available packages.
Terminology Definitions Reviews
There number concepts that should understood order appreciate packages affect signals transiting through them, well package parasitics modeled measured lab. conductor system characterized some basic electrical parameters which dependent physical design system, package exception. basic electrical parameters associated with packages resistance, inductance, conductance, capacitance. These commonly referred RLGC parameters. parameters will defined following subsections. section also explains several other metrics
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which derived from RLGC parameter values. Finally, more advanced concepts such s-parameters, crosstalk, will covered.
Resistance
Resistance basic electrical parameters that commonly defines series loss conductor. Electrically, Ohm's defines resistance ratio voltage current conductor:
Where: electrical resistance voltage current Physically, resistance defined
Equation
Where: resistance
Equation
resistivity conductor material
length conductor cross-sectional area conductor physical equation above valid where current flows through whole cross sectional area conductor. higher frequencies, where skin effect becomes important, cross sectional area decreased consequently resistance increases higher frequencies. amount that cross sectional area decreased highly geometry-dependent also function proximity conductor other nearby current carrying conductors. Typically, reported component package resistances given nets intended operate below about GHz. Higher frequency nets, such those associated with transceivers (MGTs GTPs), characterized with frequency-dependent losses. These frequency-dependent losses best determined with extractor software. skin depth (which depth electric magnetic field penetration) conductor given
Equation
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Where:
skin depth microns conductor resistivity frequency (MHz) point reference, about microns frequency conductor copper. Note that decreases with frequency skin depth would
half value that frequency
Inductance
Inductance fundamental properties electrical conductor. current carrying conductor surrounded lines magnetic flux. These lines circular loops which encircle current carrying conductor. number loops instance concentrated near conductor with density lines decreasing distance from conductor increases. basic relationship inductance
Where: inductance number magnetic lines encircling conductor (Wb) current Inductance geometry-dependent.
Equation
Whether conductor Amps flowing through inductance same since ratio remains constant. presence dielectric material near conductor will alter inductance. presence ferro-magnetic material with permeability greater than will affect inductance. When discuss inductance, terms loop inductance, partial inductance, self inductance, mutual inductance some items that come These explained below: Loop inductance inductance complete current carrying loop. unique value dependent loop geometry. larger area encompassed loop, larger loop inductance will partial inductance inductance contributed portion loop. unique value. Self Inductance When refers inductance conductor reference usually meant imply self inductance. This ratio lines magnetic flux current where lines encircle their conductor. concept mutual inductance comes into play when considers lines magnetic flux generated current carrying conductor that also encircle couple another conductor. These lines flux will cause voltage generated into coupled conductor.
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Some Inductance Expressions
Closed form analytical equations calculate inductance exist simple geometries. complex system like package, such simplified closed form expressions hard come approximations abound with varying degrees accuracy. accurately determine partial inductance conductor geometry package, good electromagnetic extractor program recommended. Below some closed-form formulas that reasonably accurate geometries commonly found packages. Partial self inductance round wire (with ground infinity):
wire
Where: Lwire inductance (nH) wire length (inches) wire radius (inches) Partial self inductance round wire over metal plane:
Equation
wire
Where: Lwire inductance (nH) wire length (inches)
Equation
height wire above plane (inches) wire radius (inches) Partial self inductance rectangular conductor (with ground infinity):
Where: inductance (nH) conductor length (inches) conductor width (inches)
Equation
thickness conductor (inches) Partial self inductance rectangular conductor like trace perhaps leadframe lead over metal plane:
8hw+t
Equation
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Where: Inductance (nH) conductor length (inches) height conductor above plane (inches) conductor width (inches) thickness conductor (inches) These relationships compiled from publications several authors(1,2,3) including Eric Bogatin, Brian Young Grover.
Capacitance
capacitance conductor dependent area conductor, distance conductor placed from some reference conductor dielectric constant dielectric material. expression simple parallel plate capacitance commonly expressed
Where: capacitance
Equation
permittivity free space
conductor area dielectric thickness dielectric material between conductors some material other than vacuum equation modified include relative dielectric constant follows:
Where: capacitance
Equation 4-10
permittivity free space
conductor area dielectric thickness
equal 0.0885 pF/cm equivalently 0.225 pF/inch. seen that
capacitance conductor will increase size conductor increases, thickness dielectric decreases dielectric constant dielectric material increased. While this expression directly applicable geometries package transmission lines planes, does illustrate basic relationships between capacitance dielectric constant, conductor area dielectric thickness.
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Other ways expressing capacitance: Capacitance also defined ratio charge voltage that stored between pair conductors:
Where: capacitance (Farads) charge (Coulombs) voltage (volts)
Equation 4-11
Transmission lines commonly have their capacitance specified per-unit-length (PUL) value such that total length Self capacitance capacitance conductor ground would capacitance conductor ground). Mutual capacitance capacitance between conductors (C12 would capacitance between conductor conductor
Examples closed form expressions capacitance: complex structure field solver preferred method determining capacitance conductor, however couple simple structures following equations provide answers accurate within about Wire over ground:
(pF/inch)
Equation 4-12
Where:
Equation 4-13
relative dielectric constant dielectric
distance from ground plane center wire (inches) radius wire (inches) Capacitance between parallel wires:
(pF/inch)
Equation 4-14
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where: distance between wire centers diameter first wire diameter second wire
Conductance
conductance parameter related losses insulating substrate material. This frequency dependent parameter that scales directly with frequency. Most substrate materials utilized package construction have very losses frequencies (less than GHz). result, conductance parallel loss) very usually ignored when modeling SelectIOlines. dielectric loss does become significant higher frequencies where high speed nets utilized. These lines typically characterized s-parameters opposed RLGC parameters.
Impedance
impedance transmission line calculated readily know line's inductance capacitance. relevant equation
Where: impedance line's per-unit-length inductance line's per-unit-length capacitance
Equation 4-15
When circuit elements interface with each other (for example, package trace trace, trace termination), mismatch their impedances their boundaries will result reflections. higher mismatched magnitude, greater associated reflection, hence distortion signal traversing mismatched interface. this reason, makes sense minimize impedance mismatches system.
Time Delay (Td)
time delay transmission line (i.e., conductor) package calculated equation where delay seconds, capacitance Farads inductance Henrys. Knowledge line's delay contribution needed determining timing closure. Time delay also determined knows relative dielectric constant substrate material associated with transmission line. transmission line with dielectric propagates signals speed light 1010 cm/second) about inches/psec. material with relative dielectric velocity propagation given expression:
Equation 4-16
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Where: velocity material speed light
relative dielectric constant dielectric material
example, typical material dielectric constant about velocity propagation transmission line utilizing dielectric material will (one half speed light) 2.95 inches/psec. time delay transmission line simply reciprocal velocity. case FR4, about 169.5 inches/psec. Additionally, time flight (Tof) transmission line simply line's length times This number what would used timing closure calculations. large size laminate ceramic-based packages where likely over delay data provided. This derived from data per-pin data available. some cases, derived directly from trace length data relevant package design.
Crosstalk
Coupling (usually unwanted) from conductor another termed "Crosstalk". line generating signal called "aggressor" line into which signal coupled termed "victim." Generally, this coupled signal considered noise undesired. There mechanisms involved this unwanted coupling between circuits; capacitive inductive. Capacitive coupling occurs when victim affected electric-field lines generated aggressor. Inductive coupling caused magnetic-field lines generated aggressor inducing voltage victim circuit. Physically, items that affect coupling distance between circuits length coupling regions. most effective minimize crosstalk increase spacing between aggressor victim nets. Crosstalk broadly divided into "near-end" "far-end" crosstalk. Near-end crosstalk always positive since currents generated inductive capacitive coupling components near end. Far-end crosstalk either negative positive. magnitude inductively coupled component larger than capacitive coupled component then difference currents positive, however, capacitive component predominates then effect will negative voltage. Also note, that magnitude near-end crosstalk insensitive coupled length aggressor victim nets. However, far-end crosstalk will increase with increasing coupled length until saturation point reached. exact mathematical relationships calculating crosstalk complex vary detail depending whether nets terminated open circuited whether near-end far-end crosstalk considered. following expressions, taken from High Speed Digital System Design4, illustrate couple cases where both aggressor victim nets terminated both near far-end (quite often case): above reference reviews other terminated cases well. Far-end Crosstalk
Equation 4-17
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Near-end Crosstalk
Equation 4-18
Where: self capacitance inductances victim lines, respectively. mutual capacitances inductances respectively between nets
Ground Bounce
Ground bounce voltage difference between grounds (typically between circuit board ground) induced simultaneously switching current through bond wire, lead, other interconnect inductance. When outputs change state, large current spikes result from charging discharging load capacitance. larger load capacitance faster rise/fall times, larger current spikes are: dv/dt. Current spikes through bondwire induce voltage drop across leads bondwires: di/dt. result momentary voltage difference between internal ground system ground, which show voltage spikes unswitched outputs. Factors that affect ground bounce include: rise fall times load capacitance package inductance number output drivers sharing same ground path device type
Signal Integrity Package Performance
Resistance, Capacitance Inductance (defined "Terminology Definitions Reviews" section) three major electrical parameters used format another describe package electrical performance. These metrics used describe I/O, well power networks packages. parameters, also known interconnect parasitics, source many serious issues digital systems. example, large resistance cause off-chip delays, power dissipation, edge-rate degradation. Large capacitance nets cause delays, crosstalk, edge-rate degradation, signal distortion. Lead inductance, perhaps most damaging parasitic digital circuitry, cause such problems ground bounce (also known simultaneous switching noise delta-I noise), delays, crosstalk, edge-rate degradation, signal distortion. design Xilinx packages, challenge seek appropriate balance these parameters that signal integrity issues minimized. Package characterization geared assist package designers co-design effort make appropriate choices backed simulation measurements optimizing package design layout performance. further goal effort gather parasitics data seek appropriate data representation these parameters help end-users deploy these packages. this end, Xilinx offers tabulated package parasitic data, summaries data, various models part deliverable. Representative samples will shown appropriate sections.
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measurement extraction capability, well models support, will described subsequent sections.
Electrical Data Generation Measurement Methods
With regards experimental measurements, Xilinx uses both Time-Domain Reflectometry (TDR) method parasitic inductance capacitance measurements, well frequency domain measurements performed with 4-port Vector Network Analyzer (VNA). practical measurement capability augmented range analytical calculators, full wave tools that utilized through simulations extract various signal integrity-based parameters about packages.
Review Practical Measurements
main components setup includes digitizing sampling oscilloscope, fast rise-time step generator (<17 ps), device-under-test (DUT) interface, impedanceprofile analysis software extract parasitic models from reflection waveforms. this method, voltage step propagated down package under test, incident reflected voltage waves monitored oscilloscope particular point line. resulting characteristic impedance package interconnect shows nature (resistive, inductive, capacitive) each discontinuity. measurement setup composed 4-port VNA, probing station, microprobes. Using VNA, s-parameter measurements various package nets made over wide bandwidths. injects swept frequency signal into DUT. instrument then measures both reflected transmitted voltages various package nodes which being probed.
Package Sample Fixture Preparation
Prior performing package measurements utilizing either VNA, package interface must fixtured. Proper fixturing ensures accurate repeatable measurements.
X-Ref Target Figure
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Figure 4-1:
Altair Fixture Used Measurement
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Figure depicts Altair test fixture that used some measurements packages. measurements, DUTs inductance (self mutual) specially assembled components with leads shorted internal package ground. packages without internal ground (i.e., QFP, PLCC, etc.), die-paddle used instead (i.e., bonds made paddle). Measurement includes wire parasitics. samples capacitance (self mutual) measurements special assembled package units with internal leads floating (un-bonded). actual testing, lead/ball under test isolated other package leads connected common potential (ground) conductor grounded (OCG) mode. interface provides physical connection between oscilloscope with minimum crosstalk probe/DUT reflection. also provides small ground loop minimize ground inductance fixture.
X-Ref Target Figure
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Figure 4-2:
Fixture
measurements, either single-sided two-sided measurements made. most cases, package measured attached test fixture board that facilitates holding sample package during measurement procedure. Two-sided measurements allow characterization package from bumps sites balls. package held right angles probing station table. Single-side measurements sometimes made when difficult impossible achieve two-sided probing package. this case, package held parallel probe station table. both cases, measured waveforms usually downloaded integrated running analysis software package parasitic model extraction. software uses method called Z-profile algorithm, impedance-profile algorithm, parasitic analysis. This method translates downloaded reflection waveforms into true impedance waveforms, from which package models inductance capacitance extracted.
Software-Based Simulations Extractions
Xilinx data generation approach consists electrical models based Full Wave package simulations/extraction that calibrated with time frequency domain measurements. Once simulation assumptions optimized calibrated with data, deploy extraction tools generate data other full package
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models that impossible deal with directly. simulation tools used make determinations provide design guidelines pre-layout feasibility, assignment review, layout design rule generation. post-layout/fabout stage, these software tools deployed among other things, extract parasitics whole package. addition parasitic extraction, tools also provide voltage drops current densities power ground nets. These same tools used generate data models internal well external use. Some tools used this effort listed below.
Modeling Simulation Tools
Ansoft Maxwell Ansoft HFSS (High Frequency Structure Simulator) Optimal Corp. PakSi-E High Speed Field Solver Optimal Corp. O-wave/PowerGrid Cadence Advance Package Engineer (APE)/SpectraQuest Sigrity; Power Systems I-Connect
Package Electrical Data Delivery Formats
tables below show some typical electrical data summaries. general, generated electrical data tabulated product used appropriate IBIS models component. specific products data, packages listed, additional information (such mutual power plane data), obtain them through model download area contact Xilinx Support with specifics. Summary data tables: most leadframe type packages (TQ, PQs, etc.) smaller laminate packages, Xilinx typically acquires electrical parasitic data longest shortest lead/traces package based design data. This provides best worst case each package type (defined package design, lead/ball count, size, etc.). Table below shows some typical data some laminate-based FPGA packages. Similar data depicted Table leadframe-based packages. specific product-based data, review [Package] section IBIS file work through your field engineer. IBIS header file [Package]. Most electrical data generated recent device families will summarized [Package] section device IBIS file.The [Package] section data will formatted Typical, format file. completed IBIS file, packages should represented. need uncomment specific package interest. [Package] section Spartan-3E file shown Figure illustrate this method conveying package-specific electrical data device family. Note that this example, FG320 uncommented use. device IBIS files downloaded from data tabulation: electrical data available packages most high FPGA devices. data available legacy products leadframe devices. Xilinx keeps database this data type will make them available end-users Excel format request. header typical Excel formatted data tabulation found Figure 4-5.
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IBIS .pkg type file format: next section models Xilinx description IBIS format. This method conveys data both coupled uncoupled .pkg format. This usually long data file that parsed data.
Data Examples
Table contains typical measured electrical data some common laminate packages. Table 4-1:
Package Type
Electrical Data Common Laminate Packages
Xilinx PkgCode BG225 BG256 Lself-Max (nH) 11.5 10.7 10.3 Lself-Min (nH) C-Max (pF) 2.20 1.30 1.50 1.30 2.70 3.20 C-Min (pF) 0.67 0.68 0.80 0.80 0.30 0.20 R-Max R-Min
1.27 pitch
BG352 BG432 BG560 BG728
Small Form Factor
CP132 CP56 CS144 CS280 CS48 CS484
0.30 0.40 0.30 0.80 0.30 1.55
0.10 0.14 0.20 0.20 0.20 0.63
Device Package User Guide UG112 (v3.2) March 2009
www.xilinx.com
Table 4-1:
Package Type
Electrical Data Common Laminate Packages (Cont'd)
Xilinx PkgCode FT256 FG256 FG320 FG324 Lself-Max (nH) 10.1 11.8 12.3 Lself-Min (nH) C-Max (pF) 1.30 1.20 1.70 1.90 3.60 2.30 5.40 2.30 2.20 2.20 C-Min (pF) 0.40 0.50 0.60 0.80 0.50 0.70 0.40 0.20 0.40 0.50 R-Max R-Min
Fine pitch
FG456 FG484 FG676 FG680 FG900 FG1156
Notes:
Wirebond parasitics were part consideration. data depicted table summary measured data typical laminate packages used FPGAs. They summarized without reference specific device families larger range cover devices. more recent devices, specific device-based parasitic limits, well typical values, found [Package] section appropriate downloadable device IBIS file. These ranges also apply lead-free equivalent packages. lead-free version packages letter appended before numeric portions package code (e.g., lead-free version FT256 will become FTG256). same data applies both packages.
Table contains summary parasitics some leadframe-based packages. data includes wirebond parasitics. Table 4-2: Parasitics Leadframe-based Packages
Lself-Max (nH) 10.2 13.0 Lself-Min (nH) C-Max (pF) C-Min (pF) R-Max R-Min
Xilinx PkgCode(1) SO20 PC20 PC44 PC68 PC84 VQ44 VQ64 VQ100 TQ44
www.xilinx.com
Device Package User Guide UG112 (v3.2) March 2009
Table 4-2:
Parasitics Leadframe-based Packages (Cont'd)
Lself-Max (nH) 10.1 15.2 15.9 15.2 12.7 12.1 12.2 Lself-Min (nH) C-Max (pF) C-Min (pF) R-Max R-Min
Xilinx PkgCode(1) TQ100 TQ144 TQ176 PQ100 PQ160 PQ208 PQ240 HQ208 HQ240 HQ304
Notes:
This same data applies lead-free versions packages. lead-free version these packages letter appended before numeric portions package code (for example, lead-free version TQ144 will TQG144). same data applies both packages. This compilation measured data leadframe packages without regard specific device family. Most product data will fall within these limits. These limits used components listed these products. Recent family products will have specific limits [Package] section device IBIS file. This table will updated periodically reflect addition newer packages updates existing package data with newer limits, should those devices expand range.
Table contains summary select parasitics some flip-chip packages. Table 4-3: Select Parasitics Flip-Chip Packages
Lself-Max (nH) 12.2 14.5 11.8 14.1 Lself-Min (nH) 3.88 3.34 3.11 3.93 7.50 1.90 4.62 5.30 4.66 9.70 10.20 C-Max (pF) 0.47 0.84 0.40 1.00 0.90 0.60 0.60 0.77 0.48 0.75 1.20 C-Min (pF) 1854 1466 1837 1962 2076 2450 1848 R-Max R-Min
Xilinx PkgCode(1) SF363 FF668 FF672 FF676 FF896 BF957 FF1148 FF1152 FF1513 FF1517 FF1704
Device Package User Guide UG112 (v3.2) March 2009
www.xilinx.com
Table 4-3:
Select Parasitics Flip-Chip Packages (Cont'd)
Lself-Max (nH) Lself-Min (nH) 3.66 C-Max (pF) 0.94 C-Min (pF) R-Max 1884 R-Min
Xilinx PkgCode(1) FF1760
Notes:
These ranges also apply lead-free equivalent packages. lead-free version packages letter appended before numeric portions package code (for example, lead-free version FF1148 will become FFG1148). same data applies both packages. bump, vias, traces, external balls depicted Figure 4-3. data reflects full interconnect chain- data presented Figure compilation SelectIO-based data devices used these flip-chip packages across couple generations Virtex devices. range encompasses known devices time publication. This table will updated periodically include newer packages updates older packages with newer data, should those devices expand range. Specific device family data obtained from IBIS file (see example Figure 4-4), they requested through your field engineer.
X-Ref Target Figure
UG112_C4_03_111208
Figure 4-3:
Flip Chip Interconnect Chain
Figure representation electrical parasitics data embedded component family IBIS file.
www.xilinx.com
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