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VMIVME-4512 16-Channels 12-Bit Analog Board
Product Manual
(256) 880-0444
12090 South Memorial Parkway Huntsville, Alabama 35803-3308, (800) 322-3616 Fax: (256) 882-0859 500-004512-000 Rev.
(256) 880-0444
12090 South Memorial Parkway Huntsville, Alabama 35803-3308, (800) 322-3616 Fax: (256) 882-0859
COPYRIGHT TRADEMARKS
Copyright 2001. information this document been carefully checked believed entirely reliable. While reasonable efforts ensure accuracy have been taken preparation this manual, VMIC assumes responsibility resulting from omissions errors this manual, from information contained herein. VMIC reserves right make changes, without notice, this VMIC's products improve reliability, performance, function, design. VMIC does assume liability arising application product circuit described herein; does VMIC convey license under patent rights rights others. warranty repair policies, refer VMIC's Standard Conditions Sale. AMXbus, BITMODULE, COSMODULE, DMAbus, IOMax, IOWorks Foundation, IOWorks Manager, IOWorks Server, MAGICWARE, MEGAMODULE, ACCELERATOR (ACCELERATION), Quick Link, RTnet, Soft Logic Link, SRTbus, TESTCAL, "The Next Generation PLC", Connection, TURBOMODULE, UCLIO, UIOD, UPLC, Visual Soft Logic Control(ler), VMEaccess, VMEbus Access, VMEmanager, VMEmonitor, VMEnet, VMEnet VMEprobe trademarks Experts, Systems Experts, Soft Logic Experts, Total Solutions Provider service marks VMIC.
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(256) 880-0444
12090 South Memorial Parkway Huntsville, Alabama 35803-3308, (800) 322-3616 Fax: (256) 882-0859
Table Contents
List Figures List Tables Overview Features Functional Description Reference Material List. Chapter Theory Operation Internal Functional Organization. VMEbus Control Interface Control Timing. Converter Controls Status Flags Throughput (Sample Rate) Factors Interleaved (Pipelined) Operation Analog Inputs Pass Filters Input Multiplexer Single-Ended Operation. Analog Outputs Digital-to-Analog Converter (DAC). Analog Distributor. Output Buffers Switches Data Refresh Control Built-In-Test (BIT) Self-Test Multiplexers. Loopback Testing Inputs Outputs Built-In Power Converter
VMIVME-4512 16-Channel 12-Bit Analog Board
Chapter Configuration Installation Unpacking Procedures Physical Installation Before Applying Power: Checklist Operational Configuration Factory-Installed Jumpers. Board Address Address Modifier Selection Analog Input Modes Differential Single-Ended Operation. Input Voltage Range. Bipolar Unipolar Operation Analog Output Mode Output Voltage Range Bipolar Unipolar Operation Calibration Equipment Required Analog Inputs Calibration Procedure Analog Outputs Calibration Procedure Connector Descriptions Chapter Programming Control Status Register Descriptions Control Register Data Format Status Register Flags Controlling Reading Analog-to-Digital Converter (ADC). Timing. Controls Flags Controls (Control Register) Flags (Status Register) Converter Data Register (CDR) Reading Codes. Data Format Coding Accessing Analog Input Channels. Controlling Analog Outputs Writing Outputs Data Format Coding "FAST REFRESH" Off-line Operation
Table Contents
Self-Testing VMIVME-4512 Board Loopback Testing Inputs Outputs Testing Correcting Analog Input Zero Offsets. Maintenance Maintenance Maintenance Prints
VMIVME-4512 16-Channel 12-Bit Analog Board
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 3-10
VMIVME-4512 Functional Block Diagram VMEbus Control Signals Interface Logic Timing Logic Control Signals Single-Ended Differential Input Configurations Analog Inputs Signal Routing Analog Output Channels Analog Outputs Refresh Logic; Flow Diagram Power Converter Programmable Jumper Resistor Network Locations P1/P2 Connector Assignments Program Flowchart Basic Control Sequence Program Example Conversion Program Flowchart Pipelined Control Sequence Program Example Pipelined Control Sequence Program Flowchart Loopback Self-Test
VMIVME-4512 Calibration Adjustments Test Points
Program Example Self-Test Program Example Program Flowchart Self-Testing Input Multiplexer Self-Test Input Multiplexer Example Program Flowchart Input Multiplexer Zero Correction
Example Conversion with Input Multiplexer Zero Correction
VMIVME-4512 16-Channel 12-Bit Analog Board
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table
Programmable Jumpers Configuration Typical Board Address (NNNN8840 Hex) Selection Connector Signal Assignments Communication Register Control Register Status Register Data Format/Coding Coding Analog Input Channel Selection. Data Format Coding Coding Self-Test Control Modes
VMIVME-4512 16-Channel 12-Bit Analog Board
OvervieContents
Features Functional Description Reference Material List
Introduction
VMIVME-4512 16-Channel 12-Bit Analog Input/Output (AIO) Board provides both stimulus response functions encountered closed-loop analog systems. Self contained, with resident 12-bit Analog-to-Digital Converter (ADC) Digital-to-Analog Converter (DAC), VMIVME-4512 represents single board solution analog input/output requirements such applications process control, simulators, trainers supervisory control. Analog inputs configured either differential channels single-ended channels, available with pass filters noise elimination anti-aliasing. resident smart controller permits "pipelined" operation, automatically inserts necessary settling delays. This feature reduces program control simple handshake sequence. analog outputs supply milliampere drive current over full output range operated off-line self-test. Built-in-Test (BIT) features permit off-line verification active components routing analog outputs through analog input multiplexers.
VMIVME-4512 16-Channel 12-Bit Analog Board
Features
VMIVME-4512 does rely upon additional supporting analog boards Analog-to-Digital (AD) Digital-to-Analog (DA) conversion, which simplifies task designing system which requires both analog inputs outputs. brief overview principal features illustrates flexibility performance that available with VMIVME-4512 board: differential single-ended analog input channels analog output channels with 10-milliamperes drive capability Resident 12-bit ADCs DACs Input output ranges jumper-selectable ±2.5 Optional pass filters available analog input noise elimination anti-aliasing Program-controlled off-line operation analog outputs data coding program-selectable either binary, offset binary two's complement format Total acquisition conversion time resulting maximum throughput non-pipelined mode On-board smart controller permits interleaved (pipelined) operation maximum conversion throughput inputs outputs protected against line transients short circuits Front-panel Fail indicator Double Eurocard form factor Individually coded/keyed connectors
Overvie
Functional Description
VMIVME-4512 (Figure page self-contained, 16-channel, 12-bit Board. Analog inputs user-selectable either single-ended pseudo-differential channels, differential-pair channels. Each analog outputs will supply milliamperes drive current, operated off-line both loopback self-testing single-point analog input/output applications. Built-in-test active components provided loopback testing analog input multiplexers with either on-line off-line analog outputs. Interleaved (pipelined) conversion capability provided standard feature, high throughput applications, permits acquisition settling time each channel begin while conversion (digitizing) preceding channel still progress. This analog "pipelining" provides highest possible throughput, sample rate, without degrading accuracy.
Conn Analog Inputs Pass Filters Analog (2/32) DIFF Data 12-Bit Pair CH00 Pairs) Pair Selt-Test Multiplexers Test Address Control VMEbus Conn Timing Pair (DIFF) (SE) Track/Hold Amplifier Hold Conv Conv Compl
VMIVME-4512 16-Channel 12-Bit Analog Board
Figure VMIVME-4512 Functional Block Diagram
Input Address
VMEbus Interface On-Line/Off-Line Output Switches Protection
Conn
Analog Outputs
Analog Outputs Refresh Logic
12-Bit Analog Distributor
Output Buffers
*Analog Outputs Monitor *Monitors board outputs "on-line" mode, buffer outputs "off-line" mode. DC-to-DC Power Converter
Overvie
Reference Material List
detailed explanation VMEbus characteristics, refer "The VMEbus Specification" available from: VMEbus Specification Rev. VMEbus Handbook VMEbus International Trade Association 7825 Gelding Suite Scottsdale, 85620-3415 (602) 951-8866 Fax: (602) 951-0720 e-mail: info@vita.com Internet: www.vita.com Refer VMIC Specification 800-004512-000 detailed explanation physical description specifications 16-Channel 12-Bit Analog Board. following application configuration guides available from VMIC assist selection, specification implementation systems based upon VMIC's products:
Title Digital Input Board Application Guide Change-of-State Application Guide Digital (with Built-in-Test) Product Line Description Synchro/Resolver (Built-in-Test) Subsystem Analog product (with Built-in-Test) Connector Cable Application Guide Document 825-000000-000 825-000000-002 825-000000-003 825-000000-004 825-000000-005 825-000000-006
VMIVME-4512 16-Channel 12-Bit Analog Board
CHAPTER
Theory Operation
Contents
Internal Functional Organization VMEbus Control Interface Control Timing Analog Inputs Analog Outputs Built-In-Test (BIT) Built-In Power Converter
Introduction
VMIVME-4512 16-channel, 12-bit Analog Input/Output (AIO) Board designed operate standard VMEbus. board self-contained with resident 12-bit Analog-to-Digital Converter (ADC) Digital-to-Analog Converter (DAC) with loopback self-test features. VMIVME-4512 does require additional boards provide high quality analog input output functions. VMIVME-4512 flexible system element which offers Built-In-Test off-line operational features found many other products.
VMIVME-4512 16-Channel 12-Bit Analog Board
Internal Functional Organization
board divided into following functional categories, illustrated Figure page VMIVME-4512 functions discussed detail this section. Below diagram VMEbus control signals interface logic (Figure 1-1). VMEbus Interface Analog-to-Digital Converter (ADC) Analog Input Filters Multiplexer Analog Distributor Analog Output Buffers Switches Analog Outputs Refresh Logic Self-Test Multiplexers Power Converter
Selection Jumpers VMEbus (P1) Address Address Modifier Board-Selection Comparation (Selection Comparison)
DTACK
DTACK Generator
Controls
Control Decoder
Decoded Read/Write Controls Control Status Register (CSR) Control Register Registered Controls
Write Reset
Status Register Data Transceiver
Status Flags Internal Data
Figure VMEbus Control Signals Interface Logic
VMEbus Control Interface
VMEbus Control Interface
VMIVME-4512 communications registers memory mapped (decimal) 16-bit words. registers contiguous, user-located 64-byte boundary within short address space VMEbus. board user-configured respond either short supervisory non-privileged communications. During each read write operation, VMEbus control signals ignored unless board-selection comparator detects match between on-board selection jumpers shown Figure page address address-modifier lines from backplane. appropriate board response occurs valid match detected, after which open-collector DTACK interface signal asserted (driven LOW). Subsequent removal Central Processing Unit (CPU) read write command
causes board-generated DTACK signal return state.
After board selection occurred, following three groups VMEbus signals control communications with board: Data lines Address lines A01, A02, A03, A04, Control Signals: WRITE DS0,* DS1* RESET* Data lines bidirectional move data from board through 16-bit data transceiver response control signals from control decoder. data transceiver serves buffer internal data which interconnects data devices board. Address lines through communication registers onto 64-byte range within VMEbus address space (see Chapter "Programming" page 45). control signals determine whether data moved board (write) from board (read), provide necessary data strobes (DS0, DS1), supply clock (SYS CLK) on-board timers. RESET* input resets timers flags. Static controls latched into Control Register used primarily establish operational mode board. Status flags, necessary monitoring controlling analog input multiplexer ADC, read through Status Register. Control Status Registers referred collectively Control Status Register (CSR), since they same address. WRITE signal determines which accessed. Most control register outputs monitored directly through status register. Each analog output channels controlled writing 12-bit right-justified data into dedicated 16-bit read/write register. analog output control registers constitute VMEbus port 16-word dual port memory. other memory port controlled analog output refresh logic.
VMIVME-4512 16-Channel 12-Bit Analog Board
Control Timing
Control commands status flags associated with controlling illustrated Figure below, described following paragraphs Chapter "Programming".
Registered Control From
Software Reset Reset Converter Control Logic Settling Busy Conv Busy Data Status Flags
Decoded Read/Write Controls
Start Settling Start Conv
From
Conv Compl
MHz) Microsecond Timer Timer Converter Timing Decoder
Tracking Conv Track/Hold
Timer Registered Control From Short Settling
Figure Timing Logic Control Signals
Converter Controls Status Flags
conversion sequence initiated writing START SETTLING START CONV controls bits, composed following consecutive time intervals: Settling Delay Tracking Interval Analog-to-Digital (AD) Conversion timing intervals discussed this section performed automatically on-board smart controller. Program control converter consists basic handshake sequences. settling delay occurs directly after state change occurred analog networks (such selecting input channel), represents settling time networks. After settling delay been completed, Track-and-Hold (T&H) amplifier (Figure page enters tracking mode, tracking interval begins.
Control Timing
During tracking interval, output amplifier settles value which equal input voltage. SETTLING BUSY flag HIGH beginning settling delay, cleared tracking interval. CONV BUSY flag HIGH START CONV control bit, remains HIGH until conversion sequence been completed. tracking interval, amplifier enters HOLD MODE, which output amplifier held constant level, CONV from timing decoder causes conversion begin. conversion digitizes output amplifier into 12-bit data word, then terminates conversion sequence. CONV COMPL flag from HIGH during conversion, otherwise. Completion conversion causes DATA flag HIGH, indicating that valid data present Converter Data Register (CDR). action reading resets DATA CONV BUSY flags state zero (0). output coding program-selected either binary two's complement. read non-destructive. microsecond timer uses system clock generate TRACKING CONV control signals converter, also provides settling delay. Setting SHORT SETTLING control HIGH provides increased throughput reducing both settling delay tracking interval.
Throughput (Sample Rate) Factors
Total system throughput (sample rate) expressed generally 1/[N +T4)], where: Throughput (samples second, channel) Number channels 4512 settling delay 4512 tracking interval 4512 conversion time (controlling processor) time invested channel typical situation, example, which overhead (T4) microseconds, expression maximum throughput (default), (SHORT SETTLING) (default), (SHORT SETTLING) FT(max) Maximum throughput then, (37,000 samples second) single input channel. Setting SHORT SETTLING control HIGH increases throughput kHz.
VMIVME-4512 16-Channel 12-Bit Analog Board
Interleaved (Pipelined) Operation
allowing channel settle before conversion previously selected channel been completed, will eliminated (maximum). VMIVME-4512 control logic permits this take place board operated interleaved (pipelined) mode. Operating requirements interleaved mode discussed Chapter "Programming". eliminating ignoring overhead, maximum throughput this mode (maximum) (default), (SHORT SETTLING)
Analog Inputs
Analog Inputs
Sixteen differential single-ended analog input channels available rear panel through connector. connecting analog return remote device INPUT GROUND SENSE input connector shown Figure below, single-ended lines operated pseudo-differential inputs. recommended that differential mode used increased noise common mode rejection.
Alternate Locations LO-Input Resistors
Connector Input R-FILT
(DIFF)
(S.E.)
C-FILT R-FILT R-FILT Diff
(Channels
Analog Input Self-Test Multiplexers
Input
R-FILT
C-FILT R-FILT R-FILT
(Channels through
Input Sense
Figure Single-Ended Differential Input Configurations
Differential Pass Filter (16)
Pass Filters Input Multiplexer
VMIVME-4512 16-Channel 12-Bit Analog Board
analog input channels provided with individual, single-pole, pass filters shown Figure below. Input channels user-configured operate either single-ended differentially. document number 800-004512-000 input filter specifications.
CH00 HI/LO CH01 Pairs Analog Inputs From Conn Pairs) CH07
FILT FILT DIFF DIFF Inputs
Pairs FILT
2/16
DIFF
Figure Analog Inputs Signal Routing
CH08 HI/LO
FILT
CH09
FILT Pairs
CH15
FILT
2/16
From Analog Output Buffers Lines)
Test FILT 1/16 Output Monitor Test Self-Test Multiplexers
Test Address From Control Logic Lines)
Address
Analog Inputs
achieve maximum system accuracy with filtered analog inputs, sample rate should limited 1,000 less channel channels). Higher sample rates will produce reflected "pumpback" currents inputs which induce error voltages across filter input resistors. Each analog inputs selectable through multiplexer sections. Each multiplexer accepts eight differential input pairs, which first routed through self-test multiplexer. Both multiplexer sections controlled same four address lines (INP ADDRESS), which derived from control bits "MUX A00" through "MUX A03" from Control Register. ADDRESS inverted CH00 CH07 multiplexer permit both multiplexers operate common differential node.
Single-Ended Operation
Differential single-ended operation analog inputs selected location Single-In-Line-Package (SIP) resistors, illustrated Figure page input multiplexers always operated differential mode; single-ended (pseudo-differential) operation obtained connecting input resistor common INPUT GROUND SENSE input instead individual signal inputs. VMIVME-4512 input channels over voltage protected current-limiting input resistors. document number 800-004512-000 input over voltage specifications.
VMIVME-4512 16-Channel 12-Bit Analog Board
Analog Outputs
addition analog inputs, analog outputs available connector. analog outputs updated (refreshed) periodically from dual port memory REFRESH control logic, illustrated Figure below. Each output receives update once every milliseconds default refresh mode. program-controlled FAST REFRESH control used reduce refresh cycle time approximately milliseconds, thereby raising maximum output sampling rate from kHz.
Connector
Output Online
Output Buffer Switches 12-Bit Refresh Port Port Analog Distributor (Analog)
Analog Outputs
Internal Data
Dual Port Memory
Fast Refresh Busy (Inhibit DTACK)
Refresh Control Arbitration Logic
Address
Figure Analog Output Channels
Digital-to-Analog Converter (DAC)
analog outputs serviced single 12-bit DAC. controlled REFRESH control logic, which periodically transfers data from dual-port memory's REFRESH port DAC, simultaneously connects appropriate section analog distributor. Analog output data dual port memory placed there through port controlling processor.
Analog Outputs
Analog Distributor
analog distributor consists following elements: decoder charge injection analog de-multiplexer Sixteen capacitive storage elements updated with data each channel output REFRESH sequence, decoder receives same four address lines that used select dual port memory data location. this manner, converted analog level always routed distributor section which corresponds dual port memory location same channel. After allowing settle, REFRESH logic enables (turns demultiplexer, converted voltage level transferred corresponding storage capacitor. settling interval approximately provided REFRESH logic, after which demultiplexer disabled next channel REFRESH sequence accessed.
Output Buffers Switches
Voltage levels stored analog distributor buffered then switched connector routing through system cables. output buffers leakage, precision operational amplifiers which supply milliamperes drive current over full available output voltage range which withstand sustained short circuits ground without damage. Output switches permit analog outputs disconnected from "off-line" self-testing impedance, single-point analog input/output system applications. eliminate effect switch resistance output impedance, inverting (sense) input each output buffer switched between load line side output switch on-line off-line operations. Clamping diodes protect buffers switches from line transients preventing voltage excursions beyond supply rails. outputs monitored through self-test multiplexer. deriving output monitor multiplexer inputs from sense inputs output buffers, measured output signals correct both on-line off-line operational modes.
Data Refresh Control
dual port memory which services analog outputs organized 16-bit wide, 16-location array, which each location accessed from either ports. random access port used host load analog output digital codes into memory. digital codes then transferred sequentially through port DAC, where they converted into voltage levels subsequently distributed appropriate analog output channels. REFRESH logic control sequence shown flow diagram form Figure page Operation dual port memory controlled REFRESH control logic which derives timing from system clock. REFRESH control logic supervises data transfers between memory DAC, controls distribution analog voltage levels analog outputs. Because dual port memory must accessed through both ports, arbitration logic employed during transfer data ensure that only port active time.
VMIVME-4512 16-Channel 12-Bit Analog Board
(Reset)
Begin Sequence Refresh Analog Outputs
Board Selected?
*Set "RAM Busy" Flag (Enables Input Latch) *Switch Address Refresh Center Outputs
Access
*Clear "RAM Busy" Flag *Switch Address A01-A04 Lines
Settling
*Set Output Strobe
Distributor Settling
*Clear Output Strobe
Distributor Release
*Increment Address Counter
Address Center Settling
Figure Analog Outputs Refresh Logic; Flow Diagram
Built-In-Test (BIT)
Built-In-Test (BIT)
Self-test provisions VMIVME-4512 design permit program-controlled verification active components board.
Self-Test Multiplexers
signal routing paths multiplexers involved board level self-test shown Figure page analog outputs switched output monitor multiplexer onto single line which turn, connected self-test multiplexer channel input either analog input multiplexer. This arrangement permits analog outputs sampled ADC. also verifies operation analog input multiplexers exercising them with known signal levels. addition accepting selected analog output signal, self-test multiplexer permits HIGH inputs differential amplifier switched simultaneously signal return. This feature provides precision "zero" signal software-correcting common "zero" offsets analog input channels. Because channel inputs input multiplexers shared both analog inputs output-monitor signal, analog inputs corresponding input channels routed through self-test multiplexer.
Loopback Testing Inputs Outputs
routing analog outputs through analog input multiplexers (see previous section), active components exercised "loopback" arrangement. controlling processor perform loopback test either on-line off-line mode sending voltage-level code specific output channel then verifying that produces same code after sampling signal. This technique described detail Chapter "Programming".
VMIVME-4512 16-Channel 12-Bit Analog Board
Built-In Power Converter
Electrical power VMIVME-4512 analog network supplied DC-to-DC converter shown Figure below. converter transforms logic power into regulated isolated power, with load capacity approximately milliamperes each bus.
CONN
Power Board
DC-to-DC Converter
Figure Power Converter
CHAPTER
Configuration Installation
Contents
Unpacking Procedures Physical Installation Operational Configuration Calibration Connector Descriptions
Introduction
This chapter leads through configuration installation VMIVME-4512 16-Channel 12-Bit Analog Board.
VMIVME-4512 16-Channel 12-Bit Analog Board
Unpacking Procedures
CAUTION: Some components assembled VMIC products sensitive electrostatic discharge damage occur boards that subjected highenergy electrostatic field. When board placed bench configuring, etc., suggested that conductive material placed under board provide conductive shunt. Unused boards should stored same protective boxes which they were shipped. Upon receipt, precautions found shipping container should observed. items should carefully unpacked thoroughly inspected damage that have occurred during shipment. board(s) should checked broken components, damaged printed circuit board(s), heat damage, other visible contamination. claims arising from shipping damage should filed with carrier complete report sent VMIC together with request advice concerning disposition damaged item(s).
Physical Installation
Physical Installation
Disconnect power from equipment insert board into appropriate slot chassis. While ensuring that board properly aligned oriented supporting board guides, slide board smoothly forward against mating connector until firmly seated. VMIVME-4512 installed slot position, with exception slot which reserved system controller. WARNING: install remove board while power applied.
Before Applying Power: Checklist
Before installing board VMEbus system, check following items ensure that board ready intended application. Have sections pertaining theory programming, Sections been reviewed applied system requirements? Review "Factory-Installed Jumpers" page Table page verify that factory-installed jumpers place. change board address address modifier response, refer "Board Address Address Modifier Selection" page Have cables, with proper mating connectors, been connected input/output connector Refer "Connector Descriptions" page description connector. Calibration been performed factory. re-calibration should required, refer "Calibration" page WARNING: install remove this board with power applied system, unless board equipped with power-on option (Extended Ground Pins).
VMIVME-4512 16-Channel 12-Bit Analog Board
Operational Configuration
Control VMIVME-4512 Board address access mode determined field replaceable, on-board jumpers. This section describes these jumpers, their effects board performance. locations functions VMIVME-4512 jumpers shown Figure page Table below.
Factory-Installed Jumpers
Each VMIVME-4512 Board configured factory with specific jumper arrangement shown Table below. factory configuration establishes following functional baseline VMIVME-4512 Board, ensures that essential jumpers installed. Board short address 0000 access mode short non-privileged Analog input output ranges full scale range
Table Programmable Jumpers Configuration Jumper Function (Installed) Board Address Board Address Board Address Board Address Board Address Board Address Board Address Board Address Board Address Board Address Short Supervisory Access Inputs, Full Scale Range Inputs, Full Scale Range Inputs, Full Scale Range Inputs, Bipolar Operation Inputs, Unipolar Operation Outputs, Unipolar Operation Outputs, Bipolar Operation Outputs, Full Scale Range Outputs, Full Scale Range Outputs Ground Connector Single-Ended Input Ground Sense Connector Factory Conf Installed Installed Installed Installed Installed Installed Installed Installed Installed Installed Omitted Omitted** Installed** Omitted** Installed** Omitted** Omitted** Installed** Omitted** Omitted** Installed Omitted
NOTES: jumper omitted FSR. Factory configuration these jumpers FSR.
Figure Programmable Jumper Resistor Network Locations
Power Converter
Operational Configuration
VMIVME-4512 16-Channel 12-Bit Analog Board
Board Address Address Modifier Selection
Jumper header jumpers permit VMIVME-4512 Board located 64-byte boundary within short address space. short address space consists addresses between NNNN0000 HEX* NNNNFFFF HEX, requires that (word) address lines decoded order account locations. Since five lines used decoding on-board functions, VMIVME-4512 Board address defined lines; address bits through A15. NOTE: *The value NNNN depends make model board used. board address programmed installing shorting plugs zero address jumper positions, omitting shorting plugs HIGH positions. Address weight byte-locations. example, typical jumper arrangement shown Table below would produce board address NNNN8840 HEX. access mode programmed selecting address modifier using jumper Short supervisory access selected omitting jumper. Short nonprivileged access selected installing jumper.
Table Typical Board Address (NNNN8840 Hex) Selection Jumper Address State* Open Shorted Shorted Shorted Shorted Open Shorted Shorted Shorted Open
NOTE: *Shorted zero (jumper installed). Open (jumper omitted).
Operational Configuration
Analog Input Modes Differential Single-Ended Operation
VMIVME-4512 Board shipped with analog inputs configured differential operation. select single-ended operation, move resistor networks located RP13, locations RP10, single-ended mode, external ground sense input used compensate potential differences between equipment signal returns. jumper position, ground sense input/output connector grounded VMIVME-4512 Board. jumper position, P2-C16 becomes external ground sense input.
Input Voltage Range
Input voltage range controlled jumpers maximum full scale range modify full scale range range, configure jumpers indicated Table page
Bipolar Unipolar Operation
Bipolar Unipolar operation analog inputs selected with jumper indicated Table page NOTE: value NNNN depends make model board used.
Analog Output Mode Output Voltage Range
Output voltage range controlled jumper block maximum full scale range modify full scale range configure jumper block indicated Table page full scale range selected omitting jumper entirely.
Bipolar Unipolar Operation
Bipolar Unipolar operation analog outputs selected with jumper block indicated Table page
VMIVME-4512 16-Channel 12-Bit Analog Board
Calibration
Before delivery from factory, VMIVME-4512 Board fully calibrated conforms specifications listed (See "Reference Material List" page 17). Should re-calibration required, perform ""Analog Inputs Calibration Procedure"" below "Analog Outputs Calibration Procedure" page with equipment listed "Equipment Required" below. locations adjustments test points shown Figure page delivered from factory, calibration adjustments sealed against accidental movement. seals easily broken re-calibration, however. adjustments should re-sealed with suitable fast-cure sealing compound after re-calibration been completed. CAUTION: install remove this board with power applied system unless board equipped with extended ground pins option.
Equipment Required
Digital Voltmeter (DVM): ±1.0000 ±10.000 ranges; more digits; ±0.005 percent reading voltage measurement accuracy; minimum input impedance. Digital Voltage Source: ±10.000 Range; resolution 0.0005 VDC; Accuracy, ±0.005 percent expected value; 0.10 maximum output impedance. Cardcage: VMEbus backplane equivalent, connectors, VMEbus master controller, ±0.1 VDC, power supply. slot allocated testing VMIVME-4512 Board. Extender card: VMEbus extender card. Test cables: Test cables equipment listed above.
Analog Inputs Calibration Procedure
Install VMIVME-4512 Board extender board VMEbus backplane. Configure analog inputs outputs Volts full scale range bipolar operation. Apply power backplane. Allow minimum warm-up interval minutes after power been applied before proceeding. Connect digital voltage source between connector pins P2-A17 P2-C17 (-). Write 16-bit value 7840 (HEX) Control Status Register (CSR) board relative address 0002. Adjust digital voltage source output 0.0000 VDC. While reading (16-bit word board relative address 0004), adjust (BIPOLAR OFFSET) indication 0800 (HEX). Adjust digital voltage source output +9.9975 VDC.
Calibration
While reading ADC, adjust (GAIN ADJ) indication that alternates between 0FFE 0FFF (HEX). Repeat steps until further adjustments required. Move JC-A, jumper JC-B, position. Adjust digital voltage source output +5.0000 VDC. While reading ADC, adjust (UNIPOLAR ZERO ADJUST) indication 0800 (HEX). Calibration analog inputs completed. Remove test connections, restore board original configuration.
Analog Outputs Calibration Procedure
Perform steps analog Inputs Calibration Procedure. necessary perform this step Analog Inputs Calibration Procedure performed within hour beginning this procedure). Connect digital voltmeter connector pins P2-A1 P2-C1 (-). Move jumper JD-1, position. Remove jumper. Write 16-bit value 7840 (HEX) board relative address 0002. Write 16-bit value 0000 (HEX) analog output channel register board relative address 0020 (HEX). Adjust digital voltmeter indication 0.0000 ±0.0010 VDC. Move jumper JD-2 position. Write 16-bit value 0800 (HEX) analog output channel register board relative address 0020 (HEX). Adjust digital voltmeter indication 0.0000 ±0.0010 VDC. Write 16-bit value 0FFF (HEX) analog output channel register board relative address 0020 (HEX). Adjust digital voltmeter indication +9.9951 ±0.0010 VDC. Calibration analog outputs completed. Remove power test connections. Restore board original configuration.
VMIVME-4512 16-Channel 12-Bit Analog Board
Power Converter
Figure VMIVME-4512 Calibration Adjustments Test Points
Connector Descriptions
Connector Descriptions
96-pin connectors, provide connections VMIVME-4512 board. contains address, data control lines, additional signals necessary control VMEbus functions related board. provides connections analog input channels analog output channels. Orientation P1/P2 connector shown Figure below, signal assignments listed Table page mating connector (Panduit Model 120-964-455E equivalent) designed used with standard 64-wire ribbon cable with conductor spacing 0.050 inches. twisted-pair ribbon cable with overall shield recommended applications involving level signals high electrical noise environments.
Connector
Connector
ISOMETRIC VIEW
Front
ISOMETRIC VIEW
Front
Figure P1/P2 Connector Assignments
VMIVME-4512 16-Channel 12-Bit Analog Board
Table Connector Signal Assignments Output Signals Analog Output Signal Return Analog Input Sense Input Signals Signal Return
CHAPTER
Programming
Contents
Control Status Register Descriptions Controlling Reading Analog-to-Digital Converter (ADC) Accessing Analog Input Channels Controlling Analog Outputs Self-Testing VMIVME-4512 Board
Introduction
Communication with VMIVME-4512 Analog (AIO) Board takes place through contiguous 16-bit register locations which mapped into short address space. short address space consists locations within address range from NNNN0000 NNNNFFFF HEX*. Functions communication registers, which discussed detail within this section, summarized Table page NOTE: *The value NNNN depends make model board used.
VMIVME-4512 16-Channel 12-Bit Analog Board
Control Status Register Descriptions
communication register located relative address Control Status Register (CSR), contains flags necessary control monitor following board operations: Analog input channel selection Analog-to-Digital (AD) conversion Built-in-Test (BIT) Analog outputs on-line/off-line Analog outputs refresh rate Front panel Fail indicator Board RESET bits length, detailed Table page Table page function each control status flag described detail subsequently associated programming discussions.
Control Status Register Descriptions
Table Communication Register Relative Address Register Name Board Identification Control Status Register (CSR) Converter Data Register Reserved Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Analog Output Channel Access Mode Read (03XX Hex) Read/Write Read -Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
*Register address relative address board address.
VMIVME-4512 16-Channel 12-Bit Analog Board
Control Register Data Format
Table Control Register Control Register: Offset (Hex), (Dec), Read/Write
Short Settling (MSB)
Fail
Start Conv
Two's Compl
Output On-line
Test Mode
Test Mode
Fast Refresh
Reserved
Start Settling
Software Reset
Reserved
(LSB)
Control Register Definitions
D15*: Short Settling controls selection distinct input settling (acquisition) times. zero state selects default settling time that ensures that full accuracy converter utilized. Settling reduces settling time accommodate situations which small degradation accuracy acceptable order increase overall throughput. Fail Fail this (1), zero (0). Start Conv single conversion enabled each time written this control bit. will ignored Converter Data Register (CDR) contains unread data from previous conversion. current settling sequence will sustained until READ command occurs. Two's Compl coding format offset binary high when (1), two's complement when zero (0). Output On-Line high, analog outputs connected connector. analog outputs disabled disconnected from zero low. Test Mode 1100 Normal Operation Reserved Test Input Offset Test Analog Outputs
D14: D13*:
D12: D11:
D10:
Test Mode
1010
Control Status Register Descriptions
Control Register Definitions (Continued)
Fast Refresh analog output refresh nominal interval milliseconds zero low, milliseconds high. Reserved Start Settling When (1), analog input settling (acquisition) interval initiated. Software Reset When high on-board timing networks cleared. Reserved through through select analog input channels. NOTE: *Each control mapped directly into corresponding Status register unless indicated with (*).
D6*: through
VMIVME-4512 16-Channel 12-Bit Analog Board
Status Register Flags
Table Status Register Status Register: Offset (Hex), (Dec), Read/Write
Data (MSB)
Fail
Conv Busy
Two's Compl
Output Online
Test Mode
Test Mode
Fast Refresh
Reserved
Settling Busy
Software Reset
Reserved
Input Channel Select
Input Channel Select
Input Channel Select
Input Channel Select (LSB)
Status Register Definitions
D15: Data When this flag indicates that conversion been completed that data available CDR. Reading clears this flag. Fail Conv Busy Writing Start control causes flag (1). flag will remain until next conversion been completed data available CDR. settling sequence will completion this flag set. Two's Compl Output On-Line Test Mode Test Mode Fast Refresh Reserved Settling Busy When this flag indicates that input settling sequence progress, that Start Settling command will ignored. Start Settling command will recognized this flag zero low. Software Reset Reserved Input Channel Select Input Channel Select Input Channel Select Input Channel Select NOTE: *The corresponding control register mapped directly this flag.
D14*: D13:
D12*: D11*: D10*: D9*: D8*: D7*:
D5*: D4*: D3*: D2*: D1*: D0*:
Controlling Reading Analog-to-Digital Converter (ADC)
Controlling Reading Analog-to-Digital Converter (ADC)
principal methods available controlling VMIVME-4512 Board. applications which conversion speed critical factor, basic method usually will provide suitable performance. This simpler methods implement, will produce maximum throughput approximately (40,000 samples second). higher throughput essential, interleaved (pipelined) method used. interleaved control approach permits settling interval channel begin while conversion progress. This technique eliminates settling interval from throughput equation, raises throughput approximately kHz. Short-settling conversions used those situations which small degradation accuracy tolerated order obtain higher throughput. Setting SHORT SETTLING control decreases major contributors settling time, increases maximum throughput pipelined).
Timing
timing operations performed on-board controller. Control converter consists "handshake" programming sequences described following paragraphs.
Controls Flags
following controls, flags registers available controlling (controls flags summarized Table page Table page 50):
Controls (Control Register)
START SETTLING D06* TWO's COMPL START CONV H.D13 SHORT SETTLING H.D15 NOTE: *Effective only upon writing. ("strobed").
Flags (Status Register)
SETTLING BUSY H.D06 CONV BUSY H.D13 DATA H.D15 NOTE: when data available data register.
VMIVME-4512 16-Channel 12-Bit Analog Board
Converter Data Register (CDR)
Converter Data Register 16-bit read only register relative address (HEX). Data this register bits, right-justified. through always zero binary data mode, sign extensions two's complement data mode (Table page 57). START SETTLING START CONV controls essentially strobes, effective only moment writing Control Register. Although supplied separate control bits flexibility, these controls usually written register simultaneously along with operational mode channel selections. measurement sequence which uses basic conversion control method illustrated Figure page Figure page sequence simple because only DATA flag must monitored determine when each conversion been completed. interleaved (pipelined) control method presented Figure page Figure page higher throughput achieved using somewhat more complex control sequence. With this method, both SETTLING BUSY DATA flags must monitored.
Reading Codes
data format which applies when reading shown Table page Coding straight binary, offset binary two's complement, depending upon configuration input range selection jumpers state TWO's COMPL control bit. Converter output codes that produced major points within full scale ranges shown summarized Table page offset binary converter output code (BIPOLAR RANGE), associated input voltage obtained with expressions:
INPUT (Volts) EFSR/2 EFSR [Decimal Output Code]/4096, where EFSR full scale range voltage. (EG: EFSR Volts range.) input voltage straight binary code (Unipolar Range) INPUT (Volts) +EFSR [Decimal Output Code]/4096.
Controlling Reading Analog-to-Digital Converter (ADC)
Begin Sequence Converter Basic Control
Initialize Table Pointers
Select Input Channel Start Conversion Sequence
Read Status Register
Data Ready?
Last Channel Been Read? Sequence
Figure Program Flowchart Basic Control Sequence
VMIVME-4512 16-Channel 12-Bit Analog Board
68020 *this program written 68020 later processor $1000 *this first line FORCE lea.l $FBFF0000, load address (CPU board specific) bsr.s setup preparation example bsr.s example example written subroutine dc.w $A002 (depends debug software) setup move.w move.w cmp.w lea.l #$20, #$5000, A0), $2000, reset 4512 (optional) un-reset 4512 dummy read register (must after reset) pointer beginning data buffer
*the following example uses normal (non-pipelined) mode read analog *input channels, stores them buffer RAM. example moveq.l #15, loop cycles, init counter move.w #$7040, init settle, convert control word loop convwait move.w btst.b beq.s move.w addq.l convwait A0), (A1) loop select input start settling convert check conversion complete loop until conversion complete read conversion into data buffer command word next channel take next readings
Figure Program Example Conversion
Controlling Reading Analog-to-Digital Converter (ADC)
Begin Sequence Converter Interleaved Control
Initialize Table Pointers
Select First Input Channel; Start Conversion Sequence
Read Status Register
Settling Busy?
Select Next Input Channel; Start Conversion Sequence
Read Status Register
Data Ready?
Read Data Register; Store Data Memory
Last Channel
Read Data Register; Store Data Memory
Sequence
Figure Program Flowchart Pipelined Control Sequence
VMIVME-4512 16-Channel 12-Bit Analog Board
68020 *this program written 68020 later processor $1000 *these first four lines FORCE with FORCEBUG: lea.l $FBFF0000, load address (CPU board specific) bsr.s setup preparation example bsr.s example example written subroutine dc.w $A002 (depends debug software) setup move.w move.w move.w cmp.w lea.l move.l moveq.l move.w move.l sub.w lea.l #$20, #$5800, #$FFFF, A0), $2000, #$F08, #15, ($20,A0,D1.W*2) (A1)+ #$100,D0 filloop $2000,A1 reset 4512 (optional) un-reset 4512 dummy read (must after reset) pointer beginning data buffer first fill value count fills fill location clear reading array change fill value pointer beginning data buffer
filloop
*the following example uses pipelined mode read analog input *channels, stores them buffer RAM. example move.w #$7640, init command word (output read input) moveq.l #14, loop cycles, init counter setlwait loop convwait move.w move.w btst.b bne.s addq.l move.w btst.b beq.s move.w move.w #$7640, setlwait convwait A0), (A1)+ loop A0), (A1)+ command: settle, convert (nonpipeline) command: settle, convert (nonpipeline) check settling complete loop until settling complete settling command word next chan. select next input start settling check conversion complete loop until conversion complete read conversion into data buffer take next pipelined readings make 16th reading data buffer
Figure Program Example Pipelined Control Sequence
Controlling Reading Analog-to-Digital Converter (ADC)
Data Format Coding
Table Data Format/Coding Data Format/Coding (Converter Data Register): Offset (Hex), (Dec), Read-Only
(MSB)
(LSB)
NOTE: zero (offset binary, straight binary) extended sign (two's complement).
Table Coding Unipolar Ranges Input +FS-1 +1/2 +9.9975 +5.0000 +0.0024 Bipolar Ranges Input +FS-1 +1/2 Zero -FS+1 +9.9951 +5.0000 +0.0049 0.0000 -9.9951 -10.0000 Bipolar Ranges Input +FS-1 +1/2 Zero -FS+1 +9.9951 +5.0000 +0.0049 0.0000 -9.9951 -10.0000 +4.9976 +2.5000 +0.0024 0.0000 -4.9976 -5.0000 0000 0000 0000 0000 1111 1111 0111 0100 0000 0000 1000 1000 1111 0000 0000 0000 0000 0000 +4.9976 +2.5000 +0.0024 0.0000 -4.9976 -5.0000 0000 0000 0000 0000 0000 0000 1111 1100 1000 1000 0000 0000 1111 0000 0000 0000 0000 0000 +4.9988 +2.5000 +0.0012 0000 0000 0000 1111 1000 0000 1111 0000 0000 Straight Binary 1111 0000 0001
Offset Binary 1111 0000 0001 0000 0001 0000
Two's Complement 1111 0000 0001 0000 0001 0000
VMIVME-4512 16-Channel 12-Bit Analog Board
Accessing Analog Input Channels
Selection analog input channels connector controlled four least significant control bits (D00 through D03) Control Register. control code each input channel listed Table below.
Table Analog Input Channel Selection Control Register
Selected Input Channel
Controlling Analog Outputs
Controlling Analog Outputs
analog output channels appear controlling processor consecutive 16-bit words address space assigned VMIVME-4512 board. communication register shown Table page lists board-relative address each output channel. Each analog output register supports both read write operations, eliminating need corresponding "shadow" latches processor Random Access Memory (RAM) space.
Writing Outputs
Digital codes recognized Analog Output Registers right-justified 12-bit binary data. Data written upper four Most Significant Bits (MSBs) (D12 D15) will ignored, will retained read back. Digital-to-Analog coding conventions used Digital-to-Analog Converter (DAC) shown Table page Each output will respond code within milliseconds after code written output register (0.4 milliseconds FAST REFRESH MODE).
Data Format Coding
Table Data Format Coding Data Register (Converter Data Register): Offset (Hex), (Dec), Read-Only
(MSB)
(LSB)
VMIVME-4512 16-Channel 12-Bit Analog Board
Table Coding Unipolar Ranges Output +FS-1 +1/2 +9.9975 +5.0000 +0.0024 Bipolar Ranges Output +FS-1 +1/2 Zero -FS+1 +9.9951 +5.0000 +0.0049 0.0000 -9.9951 -10.0000 +4.9976 +2.5000 +0.0024 0.0000 -4.9976 -5.0000 XXXX XXXX XXXX XXXX XXXX XXXX 1111 1100 0000 1000 0000 0000 1111 0000 0000 0000 0000 0000 +4.9988 +2.5000 +0.0012 XXXX XXXX XXXX 1111 1000 0000 1111 0000 0000 Straight Binary 1111 0000 0001
Offset Binary 1111 0000 0001 0000 0001 0000
NOTE: don't care.
"FAST REFRESH"
Settling FAST REFRESH control (Table page HIGH will reduce analog output REFRESH time from default value milliseconds milliseconds. FAST REFRESH MODE raises output Nyquist frequency (maximum output signal frequency) from approximately kHz.
Off-line Operation
Settling OUTPUT ON-LINE control HIGH (Table page connects analog outputs connector normal system operation. Clearing disconnects analog outputs from However, output buffers still monitored through self-test multiplexers. This operating mode normally used loopback testing.
Self-Testing VMIVME-4512 Board
Self-Testing VMIVME-4512 Board
Built-in-Test (BIT) provisions include loopback testing measurement analog input offset voltages. These capabilities permit self-contained, board level verification performance. control VMIVME-4512 self-test modes summarized Table below.
Table Self-Test Control Modes Control Bits Self-Test Mode Normal Operation Reserved Test Input Offset Test Analog Outputs
Selected Analog Input Channel
Selected Analog Output Channel
NOTE: zero test input Channels multiplexer, test Channels multiplexer.
Loopback Testing Inputs Outputs
routing analog outputs through input multiplexers, operation active components VMIVME-4512 Board verified. This loopback test performed selecting analog output channels. selected output channel then exercised controlling processor, monitored verify that components loopback signal path operating correctly. This technique illustrated Figure page Figure page Output Channels routed through input multiplexer input Channels through Outputs through routed through multiplexer inputs through
Testing Correcting Analog Input Zero Offsets
Zero offset errors which present analog input signal path corrected first performing input offset self-test procedure shown Figure page Figure page applying results test input multiplexer zero correction procedure illustrated Figure page Figure 3-10 page This offset normally small most cases does affect accuracy.
VMIVME-4512 16-Channel 12-Bit Analog Board
Begin Sequence Loopback Self-Test
Clear "Output On-Line" Control Select "Test Analog Outputs" Mode Point First Output Channel
Write Output Test Voltage Output Channels
Delay
Start/Read
Compare Reading with Output Test Voltage
Note Failed Channel
Compare within Test Limits Last Output Channel Sequence
Select Next Output Channel
Figure Program Flowchart Loopback Self-Test
Self-Testing VMIVME-4512 Board
68020 *this program written 68020 later processor $1000 *these first four lines FORCE with FORCEBUG: lea.l $FBFF0000, load 4512 address (CPU board specific) bsr.s setup 4512 some prior self-test bsr.s example self-test example written subroutine dc.w $A002 (depends debug software) *"setup" loads analog outputs with typical values self-test example setup move.w #$20, reset 4512 move.w #$5600, un-reset 4512 cmp.w A0), dummy read output moveq.l #15, fill different. moveq.l analog output registers. load move.w D7,($20,A0,D0.W*2) with different values add.w #$111, compute next fill value load move.w #$F000, load delay constant (varies with system) delay delay delay least milliseconds. *this subroutine uses 4512 self-test ability read analog outputs *compare them expected outputs. counts channels which deviate *much from expected value D2). entry, assumed that outputs *have time stabilize, ready. **The 4512 inputs outputs must same voltage range (e.g., example moveq.l moveq.l moveq.w move.w btst.b beq.s move.w #15, #$764F, wait A0), initialize counter channels clear out-of-tolerance channel counter load control word ($7E4F outputs command analog-to-digital conversion check conversion complete branch conversion finished read conversion value
loop wait
move.w ($20,A0,D1.W*2),D5 read expected value from *the above addressing mode translates "word (word D1)" andi.w #$FFF, bits 12-15 (unused) zero sub.w find difference bpl.s posdiff take absolute value difference neg.w (negate negative difference) posdiff cmpi.w difference within tolerance? bmi.s nocount branch difference tolerance addq.I count possibly channel nocount subq.I make control word read next channel loop next channel Figure Program Example Self-Test Program Example
VMIVME-4512 16-Channel 12-Bit Analog Board
Begin Sequence: Input Multiplexer Self-Test
Initialize Table Pointers Select "Test Input Offset" Mode
Select Input Channel
Start/Read Converter (Zero Offset)
Save Zero Offset Correction Table
Offset Acceptance Range Last Channel
Multiplexer Offset Fail Flag
Sequence
Figure Program Flowchart Self-Testing Input Multiplexer
Self-Testing VMIVME-4512 Board
68020 *this program written 68020 later processor $1000 *these first four lines FORCE with FORCEBUG: lea.l $FBFF0000, load address (CPU board specific) bsr.s setup preparation example bsr.s example example written subroutine dc.w $A002 (depends debug software) setup move.w #$20, reset 4512 (optional) move.w #$5000, un-reset 4512 cmp.w A0), dummy read register (must after reset) lea.l $2000, pointer beginning offset data clr.b clear "mux offset fail" flag *the following example uses normal (non-pipelined) mode read analog *input channels, stores them buffer RAM. example moveq.l #15, loop cycles, init counter move.w #$7440, init settle, convert control word loop move.w select input start settling convert convwait btst.b check conversion complete beq.s convwait loop until conversion complete move.w A0), read conversion into register cmp2.w ofsrange, Carry offset bcc.s ofsok branch offset acceptable moveq.l "mux offsets fail" flag ofsok sub.w #$800, convert offset two's complement move.w (A1) store conversion data buffer addq.l command word next channel loop take next readings ofsrange dc.w $7F8, $808 acceptable input offset limits Figure Self-Test Input Multiplexer Example
VMIVME-4512 16-Channel 12-Bit Analog Board
Begin Sequence: Input Multiplexer Zero Correction
Execute Sequence: Input Multiplexer Self-Test (Generates Zero-Correction Table)
Initialize Table Pointer
Select/Convert/Read Input Multiplexer Channel
Subtract Stored Zero-Offset From Digitized Channel Value
Store Corrected Channel Value Memory
Last Input Channel Sequence
Figure Program Flowchart Input Multiplexer Zero Correction
Self-Testing VMIVME-4512 Board
68020 *this program written 68020 later processor $1200 *these first four lines FORCE with FORCEBUG: lea.l $FBFF0000, load address (CPU board specific) bsr.s setup preparation example bsr.s example example written subroutine dc.w $A002 (depends debug software) setup move.w move.w cmp.w lea.l lea.l #$20, #$5000, A0), $2000, $2020, reset 4512 (optional) un-reset 4512 dummy read register (must after reset) pointer beginning offset data pointer beginning corrected readings
*the following example uses normal (non-pipelined) mode read analog *inputs; then corrects input offset stores result RAM. example loop convwait moveq.l move.w move.w btst.b beq.s move.w sub.w move.w addq.l Figure 3-10 Example Conversion with Input Multiplexer Zero Correction #15, #$7040, convwait A0), (A1) (A1) loop loop cycles, init counter init init settle, convert control word select input start settling convert check conversion complete loop until conversion complete read conversion into register subtract offset store conversion data buffer command word next channel take next readings
VMIVME-4512 16-Channel 12-Bit Analog Board
Maintenance
Maintenance
This section provides information relative care maintenance VMIC's products. product malfunctions, verify following: System power Software System configuration Electrical connections Jumper configuration options Boards fully inserted into their proper connector location Connector pins clean free from contamination components adjacent boards disturbed when inserting removing board from chassis Quality cables connections products must returned, contact VMIC Return Material Authorization (RMA) Number. This Number must obtained prior return. Contact VMIC Customer Service 1-800-240-7782, E-mail: customer.service@vmic.com
VMIVME-4512 16-Channel 12-Bit Analog Board
Maintenance Prints
User level repairs recommended. drawings tables this manual reference purposes only.
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