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VMIVME-2120 64-bit High-Voltage Digital Output Megamodule

Product Manual

VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Product Manual
12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA (800) 322-3616 w Fax: (256) 882-0859 500-002120-000 Rev. AC
12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA (800) 322-3616 w Fax: (256) 882-0859
COPYRIGHT AND TRADEMARKS
(I / O man figure)
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VMIC All Rights Reserved
This document shall not be duplicated, nor its contents used for any purpose, unless granted express written permission from VMIC.
12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA (800) 322-3616 w Fax: (256) 882-0859
Table of Contents
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
List of Figures
Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 1-6 Figure 1-7 Figure 1-8 Figure 1-9 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 3-1 Figure 3-2
Functional Block Diagram .................................................... Address Selection Block Diagram ............................................... Address Section Block Diagram ................................................ ........................................
Control Section Block Diagram ................................................. 21 Data Transfer Block Diagram .................................................. I / O Register Control Logic Block Diagram CSR Control Logic Block Diagram .............................................. I / O Registers Block Diagram ................................................... I / O Registers Bank B Block Diagram ............................................ Switch and Jumper Locations ................................................. Connection for Inductive Loads or Long Cable Length ............................... Jumper Installation for Pull-Up Voltage ........................................... Data Register Base Address Select Switches, S1 and S3 P3 / P4 Front Panel Connectors ............................ CSR Base Address Select Switches, S4 and S2 ................................... P2 Connector .............................................................. Programming Flowchart (Built-in-Test Active) ..................................... ..................................
Cable Connector Configuration ................................................. 42 Programming Flowchart (Built-in-Test not Active)
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
List of Tables
Table 2-1 Table 2-2 Table 3-1 Table 3-2 Table 3-3 Table 3-4
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Overview
Introduction
Features
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Functional Description
has been designed with specific hardware to support Built-in-Test functions. These functions support both off-line and on-line fault detection and isolation.
Reference Material List
The reader should refer to "The VMEbus Specification" for a detailed explanation of the VMEbus. "The VMEbus Specification" is available from the following source:
VMEbus Specification Rev. C. and the VMEbus Handbook
VMEbus International Trade Assoc. (VITA) 7825 East Gelding Dr. Suite 104 Scottsdale, AZ 85260 (602) 951-8866 (602) 951-0720 (FAX) www.vita.com
Physical Description and Specification
Title Digital Input Board Application Guide Digital I / O (with Built-in-Test) Product Line Description Connector and I / O Cable Application Guide
Document No. 825-000000-000 825-000000-003 825-000000-006
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Safety Summary
Ground the System
To minimize shock hazard, the chassis and system cabinet must be connected to an electrical ground. A three-conductor AC power cable should be used. The power cable must either be plugged into an approved three-contact electrical outlet or used with a three-contact to two-contact adapter with the grounding wire (green) firmly connected to an electrical ground (safety ground) at the power outlet.
Do Not Operate in an Explosive Atmosphere
Do not operate the system in the presence of flammable gases or fumes. Operation of any electrical system in such an environment constitutes a definite safety hazard.
Keep Away from Live Circuits
Operating personnel must not remove product covers. Component replacement and internal adjustments must be made by qualified maintenance personnel. Do not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, always disconnect power and discharge circuits before touching them.
Do Not Service or Adjust Alone
Do not attempt internal service or adjustment unless another person, capable of rendering first aid and resuscitation, is present.
Do Not Substitute Parts or Modify System
Because of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modification to the product. Return the product to VMIC for service and repair to ensure that safety features are maintained.
Dangerous Procedure Warnings
Warnings, such as the example below, precede only potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed. STOP: Dangerous voltages, capable of causing death, are present in this system. Use extreme caution when handling, testing and adjusting.
Safety Symbols Used in This Manual
STOP: informs the operator the that a practice or procedure should not be performed. Actions could result in injury or death to personnel, or could result in damage to or destruction of part or all of the system.
WARNING: denotes a hazard. It calls attention to a procedure, a practice, a condition, which, if not correctly performed or adhered to, could result in injury or death to personnel.
CAUTION: denotes a hazard. It calls attention to an operating procedure, a practice, or a condition, which, if not correctly performed or adhered to, could result in damage to or destruction of part or all of the system.
NOTE: denotes important information. It calls attention to a procedure, a practice, a condition or the like, which is essential to highlight.
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
CHAPTER
Theory of Operation
Contents
Introduction
Operational Overview
The VMIVME-2120 is designed for a variety of applications such as: · Relay drivers · Lamp drivers · Solenoid drivers · Hammer drivers · Stepping motor drivers · Triac drivers · LED drivers · High current, high-voltage drivers, and · Fiber-optic LED drivers
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
The design of the VMIVME-2120 board as shown in the functional block diagram in Figure 1-1 on page 19 consists primarily of four sections which are: · VMEbus Foundation Logic · Device Addressing · Output Drivers · Built-in-Test Logic The VMIVME-2120 board is designed using eight 8-bit bidirectional registers, a Control Status Register (CSR), high-performance output drivers, typical VMEbus foundation logic, and two device address switch banks. The two switch banks provide the user with the capability and flexibility to map I / O registers and CSRs into separate contiguous memory locations.
Device Addressing
The VMIVME-2120 is designed to support data transfers in supervisory or nonprivileged short I / O memory space. A jumper is provided as shown in Figure 1-1 (Address Selection Block Diagram) to allow user selection of either I / O access type. The jumper (JA) is shown on logic diagram 141-002120-000 in Appendix A. The VMIVME-2120 is factory configured (jumper JA not installed) to respond to short supervisory I / O access.
OPTIONAL PULL-UP RESISTORS
DATA I / O REG INTERNAL DATA BUS
OUTPUT DRIVERS 64-PIN OUTPUT CONN
VMEbus FOUNDATION LOGIC
OUTPUT DRIVERS
ADDRESS BUS
OUTPUT DRIVERS
64-PIN OUTPUT CONN DATA I / O REG DATA REG. ADDRESS SWITCHES DATA REG ADDRESS LOGIC CSR FAIL LED 16 OUTPUT DRIVERS
TEST MODE
CSR REG. ADDRESS SWITCHES
CSR ADDRESS LOGIC
M2120 / F3.1-1
Figure 1-1 Functional Block Diagram
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
The VMIVME-2120 is designed with two sets of board select switches and decode logic as shown in Figure 1-2 to provide an efficient memory address map for CSR and I / O addresses. This feature allows the user to map CSR and I / O addresses into separate contiguous memory locations when configuring subsystems that require more than one board.
AM0-AM5
(SUPERVISORY OR NON-PRIVILEGED SHORT I / O ACCESS JUMPER)
A15-A8
A7-A1
BOARD SELECT
Figure 1-2 Address Selection Block Diagram
VMEbus Foundation Logic
Typical VMEbus drivers, receivers, and control logic are shown in Figure 1-3 and Figure 1-4. The DTACK generator shown in Figure 1-4 is designed with a jumper installed at the factory to provide the maximum data transfer rate.
DATA STROBE 1 P1 DATA STROBE 2 R E C E I V E R
LONG LONG WORD WORD
READ / WRITE
ADDRESS STROBE
SYSTEM RESET
SYSTEM CLOCK
BOARD SELECT
DELAY STROBE
DTACK
DATA STROBE 1
DATA STROBE 2
Figure 1-3 Control Section Block Diagram
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
U12 P1
A01-A07
BA01-BA07
BA11-BA15
M2120 / F3.3-2
Figure 1-4 Address Section Block Diagram
Data Transfers
Data transfer transceivers are shown in Figure 1-5. The data transceivers are designed to support write and read operations on 8-, 16-, and 32-bit boundaries.
WRITE / READ U16 P1 D00-D07 8
DATA STROBE
IDB00-IDB07
IDB08-IDB15
LWORD
IDB16-IDB23 WDMUXL U4 U3
D16-D23 8
IDB00-IDB07
LWORD
U2 D24-D31 8
IDB08-IDB15
IDB24-IDB31
Figure 1-5 Data Transfer Block Diagram
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Register Control Logic
The VMIVME-2120 board register control logic is designed to support write and read operations to and from eight 8-bit bi-directional dual port latches and write transfers to a CSR register that controls the test mode and front panel LED. The control logic shown in Figure 1-6 is separated into read and write control signals and provides the capability to read or write 8, 16, or 32 bits of data. To perform output data transfers, data is transferred via transceivers, which are selected by address bits A2, A1, and the data strobes. The 64 bits of high voltage outputs are addressable as two 32-bit longwords, four 16-bit words, or as eight 8-bit bytes.
U6 U22 READ DATA TRANSFER SELECT READ REGISTER WORD SELECT READ R0 R1 R2 R3 L O N G W O R D O R W O R D
REG. 0 REG. 1 REG. 2 REG. 3 READ
SELECT S READ LONGWORD
WRITE W O R D O R WRITE REGISTER WORD SELECT R3 R2 R1 R0 WRITE SELECT S U21 WRITE LONGWORD L O N G W O R D REG. 3 REG. 2 REG. 1 REG. 0 WRITE
Figure 1-6 I / O Register Control Logic Block Diagram 24
Control and Status Register (CSR)
The CSR is a write only register that controls the Test Mode (TM) bit (bit 7) and the front panel Fail LED (bit 6) as shown in Figure 1-7. The bit disables the output drivers to perform Built-in-Test functions. Both bits of the CSR are initialized active upon system reset such that the register outputs are disabled and the front panel LED is illuminated. Writing a "zero" to these bits will turn the LED OFF and enable the output drivers.
TEST MODE
UDB06
FAIL LED
CSR SELECT WRITE DATA STROBE 1 CLK
SYSTEM RESET
M2120 / F3.6-1
Figure 1-7 CSR Control Logic Block Diagram
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Built-in-Test
The Built-in-Test feature of the VMIVME-2120 is enabled by asserting the test mode bit in the CSR. While in test mode, test data may be written to any Output Data Register (ODR), and read back on a read operation. While in test mode, accessing an ODR does not affect the user equipment since the output drivers are disabled by the test mode bit. The Built-in-Test features of this product provide the user with the capability of performing real-time loopback testing with the output drivers connected, and off-line diagnostic testing with the output drivers disconnected from the field devices. A front panel Fail LED is provided for quick fault isolation to the board level. The Fail LED is illuminated at power-up or system reset and may be extinguished by the user upon successful diagnostic execution.
Octal Registers and Output Drivers
A block diagram of the eight 8-bit I / O registers is shown in Figure 1-8 and Figure 1-9 on page 29. The AM295X I / O registers were selected as the primary building block because of their read back features, which allow the design to perform the Built-in-Test functions. An AM2952 is used for positive true boards, while the AM2953 is used on negative true boards. The VMIVME-2120 is designed to support a wide range of output options. A jumper selectable option is provided that allows the selection of the 5 volt VMEbus power or an external power source for the open collector output drivers. If an external connection is required, it is supplied on pin A1 of connector P2. The VMIVME-2120 is factory configured with the pull-up voltage jumpered to the 5 volt VMEbus power.
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
OCTAL REGISTERS
REGISTER SELECT 7
8 IDB00-IDB07
8 DB00-DB07
REGISTER SELECT 6
8 IDB08-IDB15
8 DB08-DB15
TO OUTPUT DRIVERS
REGISTER SELECT 5
8 IDB16-IDB23
8 DB16-DB23
REGISTER SELECT 4
8 IDB24-IDB31
8 DB24-DB31
M2120 / F3.8-1
Figure 1-8 I / O Registers Block Diagram
Octal Registers and Output Drivers
OCTAL REGISTERS
REGISTER SELECT 3
8 IDB32-IDB39
8 DB32-DB39
REGISTER SELECT 2
8 IDB40-IDB47
8 DB40-DB47
TO OUTPUT DRIVERS
REGISTER SELECT 1
8 IDB48-IDB55
8 DB48-DB55
REGISTER SELECT 0
8 IDB56-IDB63
8 DB56-DB63
Figure 1-9 I / O Registers Bank B Block Diagram
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Signal Function Description
The following paragraphs describe some of the key signals used on the VMIVME-2120. 1. DTBSL: DATA TRANSFER - Board Select, active low. This signal is active when an I / O data register address matches the VMEbus address. 2. CSRBSL: CONTROL STATUS REGISTER - BOARD SELECT, active low. This signal is active when the CSR address matches the VMEbus address. 3. BSL: BOARD SELECT, active low. The signal is active when either DTBSL or CSRBSL is active, and is used to gate control signals onto the board. 4. GDS0L: GATED DS0, active low. This is the gated data strobe 0. 5. GDS1L: GATED DS1, active low. This is the gated data strobe 1. 6. GLWORDL: GATED LWORD, active low. This signal is used for transceiver control and I / O data register selection. 7. GDS0DL: GATED DS0 DELAYED, active low. 8. GDS1DL: GATED DS1 DELAYED, active low. These delayed signals allow setup time through the data transceivers before clocking the data into the I / O data registers. 9. TML: TEST MODE, active low. 10. FAILH: FAIL MODE, active high. 11. WDMUXL: WORD MULTIPLEXER, active low. This signal allows the IDB16-IDB31 data bits to be transferred onto data lines D00 to D15 of the VMEbus or vise-versa.
CHAPTER
Configuration and Installation
Contents
Introduction
This chapter describes the installation and configuration of the board. Cable configuration and board layout are illustrated in this chapter.
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Unpacking Procedures
Physical Installation
NOTE: Do not install or remove board while power is applied. De-energize the equipment and insert the board into an appropriate slot of the chassis. While ensuring that the board is properly aligned and oriented in the supporting board guides, slide the board smoothly forward against the mating connector until firmly seated.
Jumper and Switch Locations
The physical locations of the jumpers and switches described in this section are shown in Figure 2-1.
Figure 2-1 Switch and Jumper Locations
COMPONENT SIDE
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
External Pull-Up Voltage / Suppressor Diode Connections
The output drivers of the VMIVME-2120 have built-in suppressor diodes for protection while driving inductive loads. If the user requires operation for a relay driver or a similar application, the coil voltage must be connected to the VMIVME-2120 External Voltage (EXTV) signal via connector P2 pin A1. User ground should be connected to P3 / P4 Row C pins. The configuration and the required external voltage connection are shown in Figure 2-2 below and Figure 2-3 on page 35. The EXTV signal is routed to all 64 output channel circuits. In addition to suppressing inductive flyback the EXTV signal supplies a voltage to the optional pull-up resistors for electronic switch applications. The on-board 5 VDC power can be jumpered to the EXTV signal if +5 VDC is to be used for the pull-up voltage or the relay coil voltage as shown in Figure 2-3 on page 35. WARNING: When driving INDUCTIVE LOADS or long cables, Jumper JC MUST BE connected to EXTV and P2-A1 MUST BE connected to the USERS relay coil voltage. If this is not done SEVERE DAMAGE may result from Inductive flyback voltage spikes that exceed maximum allowable levels. User ground must be connected to P3 / P4 Row C pins. Failure to connect user ground may result in excess currents on the VME Backplane.
Jumper JC
User V POS. (Relay Coil Voltage) Optional Pull-Up Resistor
P3 XX DBXX
User Relay Coil User Ground P3 / P4 Row C
1 of 64 Typical Output Driver Stage
Figure 2-2 Connection for Inductive Loads or Long Cable Length
NOTE: The Zener diode is supported on assembled board No. 332-002120-K and later. For support on assembled board No. 332-002120-000-J and earlier, refer to Document No. 132-002120-000 (Assembly Drawing).
External Pull-Up Voltage / Suppressor Diode Connections
Install Jumper here for +5 V reference voltage (Factory Installed) JC
+5 Install jumper here for user supplied reference voltage applied to P2 pin A01 (Not Factory Installed)
Figure 2-3 Jumper Installation for Pull-Up Voltage
Address Modifiers
The VMIVME-2120 is configured at the factory to respond to short supervisory I / O access. This configuration can be changed, by installing the jumper "JA". This will make the board respond to short non-privileged I / O access.
DTACK Delay Jumper
The VMIVME-2120 DTACK delay jumper is configured at the factory and should not be changed. It is set for the maximum data transfer rate.
Address Selection Switches
The VMIVME-2120 is designed with two banks of address select switches that specify the beginning board address for data transfers and the address of the Control Status Register (CSR). The address selection switches are shown in Figure 2-2 on page 34 and Figure 2-3 above. The VMIVME-2120 is factory configured to respond to FF00 HEX for the data registers and to FFF0 HEX for the CSR.
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
OFF A15
OFF A14
OFF A13
OFF A12 0
OFF A11 0 ON
OFF A10
OFF A09
OFF A08
X NOT USED
Figure 2-4 Data Register Base Address Select Switches, S1 and S3
OFF A15
OFF A14
OFF A13
OFF A12 0
OFF A11 0 ON
OFF A10
OFF A09
OFF A08
OFF A07
OFF A06
OFF A05
OFF A04 A03 A02 A01
Figure 2-5 CSR Base Address Select Switches, S4 and S2
I / O Cable and Card-Edge Connector Configuration
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
P3 Front Panel Connector ROW
Front Panel P4 Connector ROW
Pin No. 32
VM IV 212ME 0
Isometric View
Front View
Figure 2-6 P3 / P4 Front Panel Connectors
I / O Cable and Card-Edge Connector Configuration
Table 2-1 P3 / P4 Connector Pin Assignments P3 Pin 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Row A Row C GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 P4 Row A Row C GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
P2 Connector
ROW Pin No. 1
C32 B32 A32
ISOMETRIC VIEW
Rear View of Board
Figure 2-7 P2 Connector
I / O Cable and Card-Edge Connector Configuration
Table 2-2 P2 Connector Pin Assignments Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND +5V GND GND +5V Row B2 +5 V GND Row C EXTV1
NOTES: 1 External reference voltage is supplied by the user. 2 Inputs to the board - not required.
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Connector
VM IV 212ME 0
Conductor No. 1
Conductor No. 1 Connector
Figure 2-8 Cable Connector Configuration
CHAPTER
Programming
Contents
Register Map
The VMIVME-2120 contains eight 8-bit Output Data Registers (ODR) and a 16-bit Control Status Register (CSR). Register address maps are shown in Table 3-1 below and Table 3-2 on page 44. The ODR allows control of 64 high voltage, digital output channels and are addressable as two 32-bit longwords, four 16-bit words, or as eight 8-bit bytes. The ODR can be read under program control for data validation or diagnostic testing. The CSR is a write only register addressable as a 16-bit word or as two 8-bit bytes.
Table 3-1 Data Register Address Map RELATIVE ADDRESS
MNEMONIC
DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7
NAME / FUNCTION
DATA REGISTER 0 DATA REGISTER 1 DATA REGISTER 2 DATA REGISTER 3 DATA REGISTER 4 DATA REGISTER 5 DATA REGISTER 6 DATA REGISTER 7
NOTE: DR0-DR7 are read / write registers. XXX of address is determined by data register address select switches S3 and S1 as shown in Chapter 2.
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Table 3-2 CSR Address Map RELATIVE ADDRESS
MNEMONIC
CSRU CSRL
NAME / FUNCTION
CSR UPPER BYTE CSR LOWER BYTE
NOTE: The CSR is a write only register.
YYY of address is determined by CSR address select switches S4 and S2 as shown in Chapter 2.
Output Data Registers Bit Maps
The ODR bit map is shown in Table 3-3 below, and the CSR bit definitions are shown in Table 3-4 on page 46.
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 09
Bit 08
Bit 06
Bit 05
Bit 04
Bit 03
Bit 02
Bit 01
Bit 00
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 09
Bit 08
Bit 06
Bit 05
Bit 04
Bit 03
Bit 02
Bit 01
Bit 00
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Control and Status Register Bit Definitions
Not Used
Bit 11
Bit 10
Bit 09
Bit 08
Bit 06
Bit 05
Bit 04
Bit 03
Bit 02
Bit 01
Bit 00
Not Used
Detailed Programming
Output Data Transfers
The register bit map in Output Data Registers Bit Maps on page 45 shows the correspondence between the ODRs (DR0 to DR7) and the output data channels 63 to 0.
Built-in-Test
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Start
System Reset
NOTE: FAIL LED is ON and Output Drivers are Disconnected.
Write Data to Data Registers
Read Back Data From Data Registers
(Leave) Fail LED on
Turn Test Bit and Fail LED OFF
Figure 3-1 Programming Flowchart (Built-in-Test Active)
Detailed Programming
Start
System Reset
NOTE: At system reset, output drivers are disconnected and the Fail LED is illuminated
Set CSR Bits to Zero
Write Output Data to Output Registers
Figure 3-2 Programming Flowchart (Built-in-Test not Active)
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Maintenance
VMIVME-2120 64-bit High-Voltage Digital Output Megamodule
Maintenance Prints
User level repairs are not recommended. The drawings and tables in this manual are for reference purposes only.